Technical Data 4083
Effective June 2017
Supersedes May 2010
Product features
PS04LTVA1
ESD suppressor
•Low trigger voltage and clamping voltage delivers
enhanced ESD protection of very sensitive ICs
•Ultra-low capacitance (0.05pF typ.) ideal for high speed
data applications
•Provides ESD protection with fast response time
(<1ns) allowing equipment to pass IEC 61000-4-2 level
4 test
•Single line, bidirectional device for placement flexibility
•Low profile 0402/1005 design for board space savings
•Low leakage current (<0.1nA typ.) reduces power
consumption
•RoHS compliant, halogen free and lead free for global
acceptance
•Tested to meet automotive specifications (AEC-Q200)
Pb
HALOGEN
HF
FREE
Applications
•Satellite / digital radio
•Mobile phones
•GSM Modules
•HDTV Equipment
•A/V Equipment
•DMB Modules
•Test and measurement
equipment
•Portable game systems
•Personal media players
Packaging
•10,000 pieces in paper tape on 7 inch diameter
(178mm) reel.
Surface Mount Device
•Security equipment
•Broadband network
equipment
•Other RF applications
•High speed data ports
oUSB 2.0/3.0
oIEEE 1394
oDVI
oHigh speed
ethernet
PS04LTVA1 Specifications
Performance Characteristics Value
Rated voltage 5Vdc typical, 12Vdc maximum
Clamping voltage
125V typical
Trigger voltage
2150V typical
Capacitance @ 1MHz 0.05pF typical, 0.15pF maximum
Attenuation change (0-20GHz) -0.2dB typical
Leakage current @ 12Vdc <0.1nA typical
ESD Capability
8kV typical
15kV typical
ESD pulse withstand
1
- IEC 61000-4-2 Direct Discharge
- IEC 61000-4-2 Air Discharge
>1000 pulses typical
1. Per IEC61000-4-2, Level 4 waveform (8kV direct, 30A) measured 30nS after initiation of pulse.
2. Trigger measurement made using Transmission Line Pulse (TLP) method.
3. Minor shifting in characteristics may be observed over multiple ESD pulses at very rapid rate.
Device Marking
PS04LTVA1 ESD Suppressors are marked on the tape and reel
packages, not individually. Since the product is bi-directional and
symmetrical, no orientation marking is required.
Design Consideration
The location in the circuit for the PS04LTVA has to be carefully
determined. For better performance, the device should be placed
as close to the signal input as possible and ahead of any other
component. Due to the high current associated with an ESD
event, it is recommended to use a “0-stub” pad design (pad
directly on the signal/data line and second pad directly on
common ground).