HEWLETT PACKARD GD High CMR Isolation Amplifiers Technical Data Features 15 kV/Lls Common-Mode Rejection at Voy = 1000 V* Compact, Auto-Insertable Standard 8-pin DIP Package 4.6 uV/C Offset Drift vs. Temperature 0.9 mV Input Offset Voltage 85 kHz Bandwidth 0.1% Nonlinearity * Worldwide Safety Approval: UL 1577 (8750 V rms/1 min), VDE 0884 and CSA Advanced Sigma-Delta (XA) A/D Converter Technology Fully Differential Circuit Topology 1 um CMOS IC Technology Applications Motor Phase Current Sensing General Purpose Current Sensing * High-Voltage Power Source Voltage Monitoring *The terms common-mode rejection (CMR) and isolation-mode rejection IMR) are used interchangeably throughout this data sheet. Switch-Mode Power Supply Signal Isolation General Purpose Analog Signal Isolation Transducer Isolation Description The HCPL-7800 high CMR isolation amplifier provides a unique combination of features ideally suited for motor control circuit designers. The product provides the precision and stability needed to accurately monitor motor current in high- noise motor control environ- ments, providing for smoother control (less torque ripple) in various types of motor control applications. This product paves the way for a smaller, lighter, easier to produce, high noise rejection, low cost solution to motor current sensing. The product can also be used for general analog signal isolation applications requiring high accuracy, stability and linearity under similarly severe noise conditions. For general HCPL-7800 HCPL-7800A HCPL-7800B applications, we recommend the HCPL-7800 which exhibits a part-to-part gain tolerance of + 5%. For precision applications, HP offers the HCPL-7800A and HCPL-7800B, each with part-to- part gain tolerances of + 1%. The HCPL-7800 utilizes sigma- delta (ZA) analog-to-digital converter technology, chopper stabilized amplifiers, and a fully differential circuit topology fabricated using HPs 1 um CMOS IC process. The part also couples our high-efficiency, high- speed AlGaAs LED to a high- speed, noise-shielded detector Functional Diagram I I 1 |pp1 pp2 8 Vpp1 Vpp2 4 GND1 CMR SHIELD CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1-216 5965-3592Eusing our patented light-pipe optocoupler packaging technology. Together, these features deliver unequaled isolation-mode noise Ordering Information: HCPL-7800x rejection, as well as excellent offset and gain accuracy and stability over time and tempera- ture. This performance is delivered in a compact, auto- insertable, industry standard 8- pin DIP package that meets worldwide regulatory safety standards (gull-wing surface mount option #300 also available). No Specifier = + 5% Gain Tol.; Mean Gain Value = 8.00 A =+1% Gain Tol.; Mean Gain Value = 7.93 B = + 1% Gain Tol.; Mean Gain Value = 8.07 Option yyy 300 = Gull Wing Surface Mount Lead Option 500 = Tape/Reel Package Option (1 k min.) Option datasheets available. Contact your Hewlett-Packard sales representative or authorized distributor for information. Package Outline Drawings Standard DIP Package 9.40 (0.370) 9.90 (0.390) hm@amenmcl HP 7800 YYWW ees TYPE NUMBER* 020.008 a 6.10 (0.240 0.33 (0.013) DATE CODE 10 (0.240) -_ 6.60 (0.260) 7.36 (0.290) 7.88 (0.310) 5 TYP. PIN ONE p (2) (3) VY] 119 0.047, Max. + _+ 1.78 0.070) MAX. PIN ONE 0.76 (0.030) 1.24 (0.049) p DIMENSIONS IN MILLIMETERS AND (INCHES). * TYPE NUMBER FOR: ee as 4.70 (0.185) MAX. PIN DIAGRAM | Li}vpp1 Ye [2 ] t Fost (0.020) MIN. 21Vin. V 7 2.92 (0.115) MIN. [2}in. Yours 17] [3]Yin- Vour-[6 ] ~ 0.65 (0.025) MAX. ca 4]Gnp1 Gnp2[5 | |< _2.28 (0.090) 9:80 (0.110) HCPL-7800 = 7800 HCPL-7800A = 7800A HCPL-7800B = 7800B 1-217Gull Wing Surface Mount Option 300* PIN LOCATION (FOR REFERENCE ONLY) 1.02 (0.040 * | 1.19 (0.047) CL] C] C1] OCI 9.65 + 0.25 (0.380 + 0.010) MOLDED OOO CoO Oo +| ~~ 0.380 (0.015) 1.19 (0.047) 0.635 (0.025) 1.78 (0.070) 1.780 9.65 + 0.25 , (0.070) (0.380 + 0.010) 1.19 MAX. (0.047) 7.62 + 0.25 MAX. (0.300 + 0.010) 0.20 (0.008) 4.19 0.33 (0.013) (0.165)MAX. | ' J 1,080 40.320, | | | 0.635 + 0.25 A (0.043 + 0.013) *) (0.025 + 0.010) 0.51 + 0.130 : +/2.540 (0.020 + 0.005) 12 NOM. (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 LEAD COPLANARITY XX.XXX = 0.005 MAXIMUM: 0.102 (0.004) * REFER TO OPTION 300 DATA SHEET FOR MORE INFORMATION. Maximum Solder Reflow Thermal Profile 260 240 220 200 180 160 140 120 100 80 60 40 20 TEMPERATURE - C 1.5C/SEC 0 1 2 3 4 5 6 AT = 145C, 1 7 8 9 10 TIME MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.) 1-218Regulatory Information The HCPL-7800 has been approved by the following organizations: UL CSA VDE Recognized under UL 1577, Approved under CSA Component Approved according to VDE Component Recognition Acceptance Notice #5, File CA 0884/06.92. Program, File E55361. 88324. Insulation and Safety Related Specifications Parameter Symbol | Value | Units Conditions Min. External Air Gap Ld01) 7.4 | mm _ | Measured from input terminals to output terminals, (External Clearance) shortest distance through air Min. External Tracking Ld02) 8.0 | mm _ | Measured from input terminals to output terminals, Path (External Creepage) shortest distance path along body Min. Internal Plastic Gap 0.5 mm_ | Through insulation distance, conductor to conductor, (Internal Clearance) usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity Tracking Resistance CTI 175 V DIN IEC 112/VDE 0308 Part 1 (Comparative Tracking Index) Isolation Group Illa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 surface mount classification is Class A in accordance with CECC 00802. VDE 0884 (06.92) Insulation Characteristics Description Symbol Characteristic Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage < 300 V rms I-IV for rated mains voltage < 600 V rms I-III Climatic Classification 40/100/21 Pollution Degree (DIN VDE 0110, Table 1)* 2 Maximum Working Insulation Voltage ViorM 848 V peak Input to Output Test Voltage, Method b** VpR 1591 V peak Ver = 1.875 x Viorm, Production test with tp = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a** VR 1273 V peak Ver = 1.5 x Viorm, Type and sample test with tp = 60 sec, Partial discharge < 5 pC Highest Allowable Overvoltage** (Transient Overvoltage trp = 10 sec) Ver 6000 V peak Safety-limiting values (Maximum values allowed in the event of a failure, also see Figure 27) Case Temperature Ts 175 C Input Power Pg Input 80 mW Output Power Ps output 250 mW Insulation Resistance at Ts, Vio = 500 V Rs > 1x1012 Q *This part may also be used in Pollution Degree 3 environments where the rated mains voltage is < 300 V rms (per DIN VDE 0110). **Refer to the front of the optocoupler section of the current catalog for a more detailed description of VDE 0884 and other product safety requirements. Note: Optocouplers providing safe electrical separation per VDE 0884 do so only within the safety-limiting values to which they are qualified. Protective cut-out switches must be used to ensure that the safety limits are not exceeded. 1-219Absolute Maximum Ratings Parameter Symbol Min, Max. Unit | Note Storage Temperature Ts -55 125 C Ambient Operating Temperature Ta -40 100 C Supply Voltages Vop1, Vpp2 0.0 5.5 Vv Steady-State Input Voltage Vine, Vin. -2.0 Vopi +0.5 Vv Two Second Transient Input Voltage -6.0 Output Voltages Vour+, Vour-. -0.5 Vop2 +0.5 V Lead Solder Temperature Tis 260 C 1 (1.6 mm below seating plane, 10 sec.) Reflow Temperature Profile See Package Outline Drawings Section Recommended Operating Conditions Parameter Symbol Min Max. Unit Note Ambient Operating Temperature Ta -40 85 C 2 Supply Voltages Vop1, Vpp2 4.5 5.5 Vv 3 Input Voltage Ving Vin. -200 200 mV 4 Output Current IIo] 1 mA 5 1-220DC Electrical Specifications All specifications and figures are at the nominal operating condition of Vy. = 0 V, Vin. = 0 V, Ty = 25C, Von; = 5.0 V, and Vpps = 5.0 V, unless otherwise noted. Parameter Symbol Min. | Typ. | Max. Unit Test Conditions Fig. | Note Input Offset Voltage Vos -1.8 -0.9 0.0 mV 1 Input Offset Drift vs. Vo3/dT -2.1 pv/C 1,2 6 Temperature Abs. Value of Input | d\;/aT | 4.6 pV/C 1 7 Offset Drift vs. Temperature Input Offset Drift vs. Vpp; Vos/dVpp1 30 pv/V 1,3 8 Input Offset Drift vs. Vop AVos/dVpp2 -40 pv/V 1,4 9 Gain (+ 5% Tol.) G 7.61 8.00 | 8.40 -200 mV < Vix, < 200 mV} 1,5 10 Gain - A Version (+ 1% Tol.) Gy 7.85 7.93 | 8.01 Gain - B Version (+ 1% Tol.) Gp 7.99 8.07 | 8.15 Gain Drift vs. Temperature dG/dT 0.001 %/C 5,6 11 Abs. Value of Gain Drift vs. |dG/aT | 0.001 %/C 5 12 Temperature Gain Drift vs. Vpp; dG/dVpp; 0.21 %/V 5,7 13 Gain Drift vs. Vpps dG/dV pps -0.06 %/V 5, 8 14 200 mV Nonlinearity Nao 0.2 | 0.35 % 5,9 15 200 mV Nonlinearity Drift ANLoo/dT -0.001 % pts/C 5,10 16 vs. Temperature 200 mV Nonlinearity Drift AN 90/dVpp 1 -0.005 % pts/V 5,11 17 vs. Vpp1 200 mV Nonlinearity Drift AN 90/dVp po -0.007 % pts/V 5,12 18 vs. Vppo 100 mV Nonlinearity NLiog 0.1 | 0.25 % -100 mV< Vy, < 100 mV | 5, 13 19 Maximum Input Voltage [Vin | max 300 mV 14 Before Output Clipping Average Input Bias Current In -670 nA 15,16] 20 Input Bias Current dly/dT 3 nA/C Temperature Coefficient Average Input Resistance Rw 530 kQ 15 20 Input Resistance dRp/dT 0.38 %/C Temperature Coefficient Input DC Common-Mode CMRRyy 72 dB 21 Rejection Ratio Output Resistance Ro 11 Q 5 Output Resistance dR,/dT 0.6 %/C Temperature Coefficient Output Low Voltage Vo. 1.18 Vv [Ving] = 500 mV 14 22 Output High Voltage Vou 3.61 Vv Inurs = OA, Ipyp, = OA Output Common-Mode Vocm 2.20 | 2.39 | 2.60 Vv -40 < Ty < 85C 14 Voltage 4.5 V <Vpp, < 5.5 V Input Supply Current Ippi 10.7 | 15.5 mA 17 23 Output Supply Current Ippe 11.6 | 14.5 mA Vine = 200 mV, 18 24 -40C < Ty < 85C 4.5 V < Vpp, < 5.5 V Output Short-Circuit Hoscl 9.8 mA Vour = 0 V or Vopp 25 Current 1-221AC Electrical Specifications All specifications and figures are at the nominal operating condition of Viq4 = 0 V, Viv. = 0 V, Ty = 25C, Vppi = 5.0 V, and Vpps = 5.0 V, unless otherwise noted. Parameter Symbol | Min. | Typ. | Max. Unit Test Conditions Fig. Note Rising Edge Isolation IMR 10 25 kV/us | Viy = 1 kV 19,20 | 26 Mode Rejection Falling Edge Isolation IMRp 10 15 kV/us Mode Rejection Isolation Mode Rejection IMRR >140 dB 19 27 Ratio at 60 Hz Propagation Delay to 10% tppi0 2.0 3.3 ps -40C < Th < 85C 21, 22 Propagation Delay to 50% tppso 3.4 5.6 ps Propagation Delay to 90% tppso 6.3 9.9 ps Rise/Fall Time (10%-90%) ter 4.3 6.6 ys Bandwidth (-3 dB) fsap 50 85 kHz 23, 24 Bandwidth (-45) fase 35 kHz RMS Input-Referred Ww 300 uV rms | Bandwidth = 100 kHz | 25,26 | 28 Noise Power Supply Rejection PSR 5 mV,p 29 Package Characteristics All specifications and figures are at the nominal operating condition of Viy4. = 0 V, Viv. = 0 V, Ty = 25C, Vppi = 5.0 V, and Vppe = 5.0 V, unless otherwise noted. Parameter Symbol | Min. | Typ. | Max. | Unit Test Conditions Fig. | Note Input-Output Momentary Viso 3750 Vrms | t = 1 min., RH < 50% 30, 31 Withstand Voltage* Input-Output Resistance Rio 1ol2 | 1018 2 Ty = 25C | Vig = 500 Vde 30 1091! T, = 100C Input-Output Capacitance Cro 0.7 pF f= 1 MHz 30 Input IC Junction-to- Gigi 96 C/W 32 Case Thermal Resistance Output IC Junction-to-Case Vico 114 C/W Thermal Resistance *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification, or HP Application Note 1074, Optocoupler Input-Output Endurance Voltage. 1-222Notes: General Note: Typical values represent the mean value of all characterization units at the nominal operating conditions. Typical drift specifications are determined by calculating the rate of change of the speci- fied parameter versus the drift parameter (at nominal operating conditions) for each characterization unit, and then averaging the individual unit rates. The correspond- ing drift figures are normalized to the nominal operating conditions and show how much drift occurs as the particular drift parameter is varied from its nominal value, with all other parameters held at their nominal operating values. Figures show the mean drift of all characterization units as a group, as well as the + 2-sigma statistical limits. Note that the typical drift specifications in the tables below may differ from the slopes of the mean curves shown in the corresponding figures. 1. HP recommends the use of non- chlorine activated fluxes. 2. The HCPL-7800 will operate properly at ambient temperatures up to 100C but may not meet published specifi- cations under these conditions. 3. DC performance can be best maintained by keeping Vpp, and Vppe as close as possible to 5 V. See application section for circuit recommendations. 4. HP recommends operation with Vp. = 0 V (tied to GND1). Limiting Vins to 100 mV will improve DC nonlinearity and nonlinearity drift. If Vin. is brought above 800 mV with respect to GND1, an internal test mode may be activated. This test mode is not intended for customer use. 5. Although, statistically, the average difference in the output resistance of pins 6 and 7 is near zero, the standard deviation of the difference is 1.3 Q due to normal process variations. Consequently, keeping the output current below 1 mA will ensure the best offset performance. 6. Data sheet value is the average change in offset voltage versus temperature at T, = 25C, with all other parameters held constant. This value is expressed as the change in offset voltage per C change in temperature. 7. Data sheet value is the average magnitude of the change in offset voltage versus temperature at Ty = 25C, with all other parameters held constant. This value is expressed 10. 11. 12. 13. 14. 1d. as the change in magnitude per C change in temperature. . Data sheet value is the average change in offset voltage versus input supply voltage at Vpp; = 5 V, with all other parameters held constant. This value is expressed as the change in offset voltage per volt change of the input supply voltage. . Data sheet value is the average change in offset voltage versus output supply voltage at Vppe = 5 V, with all other parameters held constant. This value is expressed as the change in offset voltage per volt change of the output supply voltage. Gain is defined as the slope of the best-fit line of differential output voltage (Voyr+ - Vour.) versus differential input voltage (Vay. -Viy_) over the specified input range. Data sheet value is the average change in gain versus temperature at T, = 25C, with all other parameters held constant. This value is expressed as the percentage change in gain per C change in temperature. Data sheet value is the average magnitude of the change in gain versus temperature at T, = 25C, with all other parameters held constant. This value is expressed as the percentage change in magnitude per C change in temperature. Data sheet value is the average change in gain versus input supply voltage at Vppi = 5 V, with all other parameters held constant. This value is expressed as the percentage change in gain per volt change of the input supply voltage. Data sheet value is the average change in gain versus output supply voltage at Vpp2 = 5 V, with all other parameters held constant. This value is expressed as the percentage change in gain per volt change of the output supply voltage. Nonlinearity is defined as the maxi- mum deviation of the output voltage from the best-fit gain line (see Note 10), expressed as a percentage of the full-scale differential output voltage range. For example, an input range of + 200 mV generates a full-scale differ- ential output range of 3.2 V (+ 1.6 V); a maximum output deviation of 6.4 mV would therefore correspond to a nonlinearity of 0.2%. 16. 17. 18. 19. 20. 21. 22. 23. 24. Data sheet value is the average change in nonlinearity versus temperature at Ty = 25C, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per C change in temperature. For example, if the temperature is increased from 25C to 35C, the nonlinearity typically will decrease by 0.01 percentage points (10 times -0.001 % pts/C) from 0.2% to 0.19%. Data sheet value is the average change in nonlinearity versus input supply voltage at Vpp; = 5 V, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per volt change of the input supply voltage. Data sheet value is the average change in nonlinearity versus output supply voltage at Vpp = 5 V, with all other parameters held constant. This value is expressed as the number of percentage points that the nonlinearity will change per volt change of the output supply voltage. NL jp is the nonlinearity specified over an input voltage range of + 100 mV. Because of the switched-capacitor nature of the input sigma-delta converter, time-averaged values are shown. This parameter is defined as the ratio of the differential signal gain (signal applied differentially between pins 2 and 3) to the common-mode gain (input pins tied together and the signal applied to both inputs at the same time), expressed in dB. When the differential input signal exceeds approximately 300 mV, the outputs will limit at the typical values shown. The maximum specified input supply current occurs when the differential input voltage (Vy, - Vp.) = 0 V. The input supply current decreases approximately 1.3 mA per 1 V decrease in Vpp). The maximum specified output supply current occurs when the differential input voltage (Vix, - Viv.) = 200 mV, the maximum recommended operating input voltage. However, the output supply current will continue to rise for differential input voltages up to approximately 300 mV, beyond which the output supply current remains constant. 1-2230.1 pF Figure 1. 25. Short circuit current is the amount of output current generated when either output is shorted to Vpp2 or ground. 26. IMR (also known as CMR or Common Mode Rejection) specifies the mini- mum rate of rise of an isolation mode noise signal at which small output perturbations begin to appear. These output perturbations can occur with both the rising and falling edges of the isolation-mode wave form and may be of either polarity. When the perturba- tions first appear, they occur only occasionally and with relatively small peak amplitudes (typically 20-30 mV at the output of the recommended application circuit). As the magnitude of the isolation mode transients increase, the regularity and amplitude of the perturbations also increase. See applications section for more information. 2.7. IMRR is defined as the ratio of differential signal gain (signal applied differentially between pins 2 and 3) to 28. the isolation mode gain Gnput pins tied to pin 4 and the signal applied between the input and the output of the isolation amplifier) at 60 Hz, expressed in dB. Output noise comes from two primary sources: chopper noise and sigma- delta quantization noise. Chopper noise results from chopper stabiliza- tion of the output op-amps. It occurs at a specific frequency (typically 200 kHz at room temperature), and is not attenuated by the internal output filter. A filter circuit can be easily added to the external post-amplifier to reduce the total rms output noise. The internal output filter does eliminate most, but not all, of the sigma-delta quantization noise. The magnitude of the output quantization noise is very small at lower frequencies (below 10 kHz) and increases with increasing frequency. See applications section for more information. H15V Your AD624CD +5V +5V HCPL-7800 0.1 pF 1 ar 8 10K 2 Z WW 3 8 WW 4 5 10K = = 0.33 pF Input Offset Voltage Test Circuit. 1-224 GAIN = 1000 -15 V 29. 30. 31. 32. dVgg INPUT-REFERRED OFFSET DRIFT pV Data sheet value is the differential amplitude of the transient at the output of the HCPL-7800 when a 1 Vpi-px, 1 MHz square wave with 5 ns rise and fall times is applied to both Vpp1 and Vppe- This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together. In accordance with UL1577, for devices with minimum Vigo specified at 3750 Vins, each optocoupler is proof- tested by applying an insulation test voltage greater-than-or-equal-to 4500 Vims for one second (leak current detection limit, Ig < 5 yA). This test is performed before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table. Case temperature was measured with a thermocouple located in the center of the underside of the package. 1500 === MEAN wes + 2 SIGMA 1000 500 / a \ fo 6 Pee wt aA \ 500 \! [eran -1000 40 -20 0 20 40 60 80 100 Ta TEMPERATURE C Figure 2. Input-Referred Offset Drift vs. Temperature.600 = MEAN \ +2 SIGMA > a | i = 400 ~ 4 / iz 200 A 3 a == Pr * nn) TT} rr fe -200 NY 2 / Nese Zz = -400 Lf o > 7.600 44 46 48 5.0 5.2 54 5.6 Vpp1 INPUT SUPPLY VOLTAGE - V Figure 3. Input-Referred Offset Drift vs. Vpn (Vpp2 = 5 V). 400 === MEAN wee 6+ 2 SIGMA 300 200 100 -100 dVgg INPUT-REFERRED OFFSET DRIFT - pV -200 44 46 48 5.0 5.2 54 5.6 Vpp2 OUTPUT SUPPLY VOLTAGE V Figure 4. Input-Referred Offset Drift vs. Vop2 (Vpp1 = 5 V). == MEAN +5V +5V +15 V mes + O SIGMA x 0.1 pF HCPL-7800 0.1 pF 3 1 Ww sj) == E x V 2 7 10K c IN AV z 3 6 3 ANY | 0.01 pF 4 5 10K g = = 0.33 uF Figure 5. Gain and Nonlinearity Test Circuit. 05 dG - GAIN DRIFT- % === MEAN wees + 2 SIGMA -2.0 44 46 48 5.0 5.2 54 5.6 Vpp1 INPUT SUPPLY VOLTAGE V Figure 7. Gain Drift vs. Vpp1 (Vppz = 5 VY). 40 -20 0 20 40 60 80 100 Ta- TEMPERATURE - C Figure 6. Gain Drift vs. Temperature. 0.5 0.3 T T === MEAN 0.4 === MEAN o2 |_| mm #2SIGMA , mee + 2SIGMA Wy \ 8 \ e oO * o3| oA o i 4 4 Fa 5 / \) a NA Zz 02 uO 5 o -O4 NIZA o % . V/ 3 & VW 0 i 0.2 0.1 03 44 46 48 50 52 54 5.6 0.2 -0.4 0 0.1 0.2 Vpp2 - OUTPUT SUPPLY VOLTAGE V Vin INPUT VOLTAGE - V Figure 8. Gain Drift vs. Vppz (Vpp1 = 5 V). Figure 9. 200 mV Nonlinearity Error Plot. 1-2250.15 === MEAN wees + 2 SIGMA 0.10 0.05 -0.05 -0.10 ANL o99 200 mV NON-LINEARITY DRIFT % PTS 40 -20 0 20 8640 60 80 100 Ty TEMPERATURE - C Figure 10. 200 mV Nonlinearity Drift vs. Temperature. 0.15 0.10 0.05 -0.05 -0.10 ERROR - % OF FULL-SCALE 0.15 = = MEAN me + 2 SIGMA -0.20 -0.10 0.05 0 0.05 0.10 Vin INPUT VOLTAGE - V Figure 13. 100 mV Nonlinearity Error Plot. 0 I EB -2 =z Gi / e / 34 3 2D s / 7 J 2 / ly -10 6 -4 -2 0 2 4 6 Vin INPUT VOLTAGE V Figure 16. Typical Input Current vs. Input Voltage. 1-226 n EF 0.06 x | 0.04 z a = ey zc 0.02 N SN. o , * <= uw am z 3 (oy 4 ~ 5 a 5 902 {~~ , 8 0.04 g } 2 0.06 s 44 46 48 50 52 54 56 Vpp1 INPUT SUPPLY VOLTAGE - V Figure 11. 200 mV Nonlinearity Drift vs. Vppi (Vpp2 = 5 V). 4.0 _ 77 3.5 \ 7 3.0 \ 4 " 7 = POSITIVE / 2.5 H] ouTPUT (PIN 7) 4 2.0 | NEGATIVE 4 \ " OUTPUT 4 (PIN 6) y . . \ ye YL 1.0 Vg OUTPUT VOLTAGE -V 06 04 -02 0 0.2 0.4 0.6 Vin INPUT VOLTAGE - V Figure 14. Typical Output Voltages vs. Input Voltage. 10.5 10.0 \ | pp1 INPUT SUPPLY CURRENT mA N 95 \ N iy N 9.0 mee T, = -40C Ta = 25C = = T, = 85C 85 I I I 04 -03 -02 -01 0 01 O02 03 04 Vin INPUT VOLTAGE - V Figure 17. Typical Input Supply Current vs. Input Voltage. 0.06 === MEAN wes + 2 SIGMA 0.04 0.02 -0.02 -0.04 dNL 499 200 mV NON-LINEARITY DRIFT - % PTS 44 46 48 5.0 5.2 5.4 5.6 Vpp2 OUTPUT SUPPLY VOLTAGE V Figure 12. 200 mV Nonlinearity Drift vs. Vpp2 (Vppi = 5 V). -200 - c b -400 va a | 3-600 E a 2 2 800 ZO T L z ra 1000 [| -1200 -0.2 0.1 0 0.1 02 Vin INPUT VOLTAGE - V Figure 15. Typical Input Current vs. Input Voltage. 12.0 T T T < = =Ta= 85C Ta = 25C L = Ta = -40C i 115 =5 i 1. S / oO a 411.0 2 / bE - \ / a 4 5 105 \S Lf " Lf I a ca a NX 10.0 al 04 -03 -0.2 -0.1 0 #O1 02 O03 04 Vin INPUT VOLTAGE - V Figure 18. Typical Output Supply Current vs. Input Voltage.+5V 78L05 HCPL-7800 0.1 pF IN OUuThe SE 2 1 NRK 4 oy [OTHF ) O1HF |g 3 6 xo 4 5 1.00 K I} 541K 330 pF PULSE GEN. 5V 7 7 Vim Figure 19. Isolation Mode Rejection Test Circuit. 1000 V vim 0v 50 mV PERTURBATION (DEFINITION OF FAILURE) Vo WJ q Qa Figure 20. Typical IMR Failure Waveform. t TIME - ps 10 | | DELAY TO 90% == RISE/FALL TIME 9 |_ [nm DELAY TO 50% i mmm DELAY TO 10% va a La al . L oo lamers] oo - ao i = antl Leena 40 -20 0 20 40 60 80 100 Tyg TEMPERATURE - C Figure 21. Typical Propagation Delays and Rise/Fall Time vs. Temperature. 1-227VIN 50% tpp9o >| }-tpp50 tepi0 Vout 0.1 pF HCPL-7800 0.1 pF OS 3 | oS io o g = nn q & lo fro fo a Nn o oO x 10.0K Figure 22. Propagation Delay and Rise/Fall Time Test Circuit. 0 110 TT 8 8 NO BANDWIDTH LIMITING NO BANDWIDTH LIMITING 4 -! x N\ 5 N ee OEOnEE PHASE > 9g |_[ BANOWIDTH LIMITED TO 100 kHz 4 -10 x i 4 \ 2 400 BANDWIDTH Llu. = BANDWIDTH LIMITED TO 10 kHz o 4 15 x N\ = w a | a a w wt z= 2 5 2.0 a wl Qa z 5 z = 90 N 40 a a 5 Ww a a a 2 30 0 g a ec 15 S I =< x wi a w a a L a mo 80 36 Ww wi w 3 Ww oc 1.0 = = o E = 3 4507 tn \ a 2 | < - 8 = a 2 Fe AMPLITUDE 2 70 2 6 a (05 = PHASE \ ! z Foda-tr-f-4-77 4 | | | -60 60 N s 28 a 2 0 100 500 1000 5000 10000 50000 100000 40-20 0 20 40 60 80 100 > 0 50 100 150 200 250 f - FREQUENCY Hz T, TEMPERATURE - C Vy INPUT VOLTAGE - mv Figure 23. Typical Amplitude and Figure 24. Typical 3 dB and 45 Figure 25. Typical RMS Input-Referred Phase Response vs. Frequency. Bandwidths vs. Temperature. Noise vs. Input Voltage. 1-228FLOATING POSITIVE SUPPLY GATE DRIVE CIRCUIT J IN U1 OUT 78L05 I C1 C2 1 0.1 pF 70.1 HF lO WA* 2) 2 R5 cs 3 | HePt-7e00} MOTOR 390 OTHE eee 4 > oe 4 R SENSE ch Figure 26. Recommended Application Circuit. 400 So oo === OUTPUT POWER, Ps | =< INPUT POWER, Ps 300 200 Pg - POWER - mW 100 NC 0 N 0 20 40 60 80 100120 140 160 |180 175 Ta TEMPERATURE C Figure 27. Dependence of Safety- Limiting Parameters on Ambient Temperature. Applications Information Functional Description Figure 28 shows the primary functional blocks of the HCPL- 7800. In operation, the sigma- delta analog-to-digital converter converts the analog input signal into a high-speed serial bit stream, the time average of which is directly proportional to the input signal. This high speed stream of digital data is encoded and optically transmitted to the detector circuit. The detected signal is decoded and converted into accurate analog voltage levels, which are then filtered to produce the final output signal. To help maintain device accuracy over time and temperature, internal amplifiers are chopper- stabilized. Additionally, the encoder circuit eliminates the effects of pulse-width distortion of the optically transmitted data by generating one pulse for every edge (both rising and falling) of the converter data to be transmitted, essentially converting the widths of the sigma-delta output pulses into the positions of the encoder output pulses. A significant benefit of this coding scheme is that any non-ideal characteristics of the LED (such as non-linearity and drift over time and temperature) have little, if any, effect on the performance of the HCPL-7800. 1-229Circuit Information The recommended application circuit is shown in Figure 26. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple three-terminal voltage regulator. The input of the HCPL-7800 is connected directly to the current sensing resistor. The differential output of the isolation amplifier is converted to a ground-referenced single-ended output voltage with a simple differential amplifier circuit. Although the application circuit is relatively simple, a few general recommendations should be followed to ensure optimal performance. As shown in Figure 26, 0.1 uF bypass capacitors should be located as close as possible to the input and output power supply pins of the HCPL-7800. Notice that pin 2 (Vy) is bypassed with a 0.01 uF capacitor to reduce input offset voltage that can be caused by the combination of long input leads and the switched- capacitor nature of the input circuit. With pin 3 (V,.) tied directly to pin 4 (GND1), the power-supply return line also functions as the sense line for the negative side of the current-sensing resistor; this allows a single twisted pair of wire to connect the isolation amplifier to the sense resistor. In some applications, however, better performance may be obtained by connecting pins 2 and 3 (Vix, and Vj.) directly across the sense resistor with twisted pair wire and using a separate wire for the power supply return line. Both input pins should be bypassed with 0.01 1-230 uF capacitors close to the isolation amplifier. In either case, it is recommended that twisted- pair wire be used to connect the isolation amplifier to the current- sensing resistor to minimize electro-magnetic interference of the sense signal. To obtain optimal CMR perfor- mance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below the HCPL- 7800. An example single-sided PCB layout for the recommended application circuit is shown in Figure 29. The trace pattern is shown in X-ray view as it would be seen from the top of the PCB; a mirror image of this layout can be used to generate a PCB. An inexpensive 78L05 three- terminal regulator is shown in the recommended application circuit. Because the performance of the isolation amplifier can be affected by changes in the power supply voltages, using regulators with tighter output voltage tolerances will result in better overall circuit performance. Many different regulators that provide tighter output voltage tolerances than the 78L05 can be used, including: TL780-05 (Texas Instruments), LM340LAZ-5.0 and LP2950CZ- 5.0 (National Semiconductor). The op-amp used in the external post-amplifier circuit should be of sufficiently high precision so that it does not contribute a significant amount of offset or offset drift relative to the contribution from the isolation amplifier. Generally, op-amps with bipolar input stages exhibit better offset performance than op-amps with JFET or MOSFET input stages. In addition, the op-amp should also have enough bandwidth and slew rate so that it does not adversely affect the response speed of the overall circuit. The post-amplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter; these capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier. Many different op-amps could be used in the circuit, including: MC34082A (Motorola), TLO32A, TLO52A, and TLC277 (Texas Instruments), LF412A (National Semiconductor). The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and adequate gain tolerance for the overall circuit. Resistor networks can be used that have much better ratio tolerances than can be achieved using discrete resistors. A resistor network also reduces the total number of components for the circuit as well as the required board space. The current-sensing resistor should have a relatively low value of resistance to minimize power dissipation, a fairly low inductance to accurately reflect high-frequency signal compo- nents, and a reasonably tight tolerance to maintain overall circuit accuracy. Although decreasing the value of the sense resistor decreases power dissipation, it also decreases the full-scale input voltage making iso-amp offset voltage effects more significant. These twoconflicting considerations, therefore, must be weighed against each other in selecting an appropriate sense resistor for a particular application. To maintain circuit accuracy, it is recommended that the sense resistor and the isolation amplifier circuit be located as close as possible to one another. Although it is possible to buy current- sensing resistors from established vendors (e.g., the LVR-1, -3 and -5 resistors from Dale), it is also possible to make a sense resistor using a short piece of wire or even a trace on a PC board. VOLTAGE REGULATOR aL Figures 30 and 31 illustrate the response of the overall isolation amplifier circuit shown in Figure 26. Figure 30 shows the response of the circuit to a+ 200 mV 20 kHz sine wave input and Figure 31 the response of the circuit to a + 200 mV 20 kHz square wave input. Both figures demonstrate the fast, well-behaved response of the HCPL-7800. Figure 32 shows how quickly the isolation amplifier recovers from an overdrive condition generated by a 2 kHz square wave swinging between 0 and 500 mV (note that CLOCK GENERATOR ISOLATION BOUNDARY the time scale is different from the previous figures). The first wave form is the output of the application circuit with the filter capacitors removed to show the actual response of the isolation amplifier. The second wave form is the response of the same circuit with the capacitors installed. The recovery time and overshoot are relatively independent of the amplitude and polarity of the overdrive signal, as well as its duration. For more information, refer to Application Note 1059. VOLTAGE REGULATOR ISO-AMP ; LED DRIVE DETECTOR INPUT cin ENCODER CIRCUIT ja ( CIRCUIT Figure 28. HCPL-7800 Block Diagram. U1 HCPL78a0 + Rsense - Rsense @ + Supply @ ee a[CJle ec+e ecvee ee R2 N Des Oel"7le R1 e eo oe M+5 Volts afClje Ground e e @+1S volts USI, MBvout e @-15 volts @ R33 @ ecse Figure 29. PC Board Trace Pattern and Loading Diagram Example. DECODER ISO-AMP AND D/A oe rf FILTER 1s sever 1-231Soe e es MS ie ES BS. BuB Bho Figure 30. Application Circuit Sine Wave Response. DE Eee 2 eae Figure 31. Application Circuit Square Wave Response. By Lee Teac boa ear ee it Figure 32. Application Circuit Overload Recovery Waveform. 1-232