W25N01GV
Publication Release Date: December 13, 2014
Preliminary - Revision C
3V 1G-BIT
SERIAL SLC NAND FLASH MEMORY WITH
DUAL/QUAD SPI & CONTINUOUS READ
W25N01GV
- 1 -
Table of Contents
1.GENERAL DESCRIPTIONS ............................................................................................................. 6
2.FEATURES ....................................................................................................................................... 6
3.PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 7
3.1Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2Pad Description WSON 8x6-mm .......................................................................................... 7
3.3Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
3.4Ball Description TFBGA 8x6-mm ......................................................................................... 8
4.PIN DESCRIPTIONS ........................................................................................................................ 9
4.1Chip Select (/CS) .................................................................................................................. 9
4.2Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9
4.3Write Protect (/WP) .............................................................................................................. 9
4.4HOLD (/HOLD) ..................................................................................................................... 9
4.5Serial Clock (CLK) ................................................................................................................ 9
5.BLOCK DIAGRAM .......................................................................................................................... 10
6.FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1Device Operation Flow ....................................................................................................... 11
6.1.1Standard SPI Instructions ..................................................................................................... 11
6.1.2Dual SPI Instructions ............................................................................................................ 11
6.1.3Quad SPI Instructions ........................................................................................................... 12
6.1.4Hold Function ....................................................................................................................... 12
6.2Write Protection .................................................................................................................. 13
7.PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 14
7.1Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 14
7.1.1Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable ................. 14
7.1.2Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable ................................ 15
7.1.3Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable .................... 15
7.2Configuration Register / Status Register-2 (Volatile Writable) ........................................... 16
7.2.1One Time Program Lock Bit (OTP-L) – OTP lockable .......................................................... 16
7.2.2Enter OTP Access Mode Bit (OTP-E) – Volatile Writable ..................................................... 16
7.2.3Status Register-1 Lock Bit (SR1-L) – OTP lockable ............................................................. 16
7.2.4ECC Enable Bit (ECC-E) – Volatile Writable ........................................................................ 17
7.2.5Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable .................................... 17
7.3Status Register-3 (Status Only) .......................................................................................... 18
7.3.1Look-Up Table Full (LUT-F) – Status Only ........................................................................... 18
7.3.2Cumulative ECC Status (ECC-1 , ECC-0) – Status Only....................................................... 18
7.3.3Program/Erase Failure (P-FAIL, E-FAIL) – Status Only ....................................................... 19
W25N01GV
Publication Release Date: December 13, 2014
- 2 - Preliminary - Revision C
7.3.4Write Enable Latch (WEL) – Status Only ............................................................................. 19
7.3.5Erase/Program In Progress (BUSY) – Status Only .............................................................. 19
7.3.6Reserved Bits – Non Functional ........................................................................................... 19
7.4W25N01GV Status Register Memory Protection ............................................................... 20
8.INSTRUCTIONS ............................................................................................................................. 21
8.1Device ID and Instruction Set Tables ................................................................................. 21
8.1.1Manufacturer and Device Identification ................................................................................ 21
8.1.2Instruction Set Table 1 (Continuous Read Mode, BUF = 0) ................................................. 22
8.1.3Instruction Set Table 2 (Buffer Read Mode, BUF = 1, Default Mode after Power Up) .......... 23
8.2Instruction Descriptions ...................................................................................................... 25
8.2.1Device Reset (FFh) .............................................................................................................. 25
8.2.2Read JEDEC ID (9Fh) .......................................................................................................... 26
8.2.3Read Status Register (0Fh / 05h) ......................................................................................... 27
8.2.4Write Status Register (1Fh / 01h) ......................................................................................... 28
8.2.5Write Enable (06h) ............................................................................................................... 29
8.2.6Write Disable (04h) ............................................................................................................... 29
8.2.7Bad Block Management (A1h) .............................................................................................. 30
8.2.8Read BBM Look Up Table (A5h) .......................................................................................... 31
8.2.9Last ECC Failure Page Address (A9h) ................................................................................. 32
8.2.10128KB Block Erase (D8h) ................................................................................................... 33
8.2.11Load Program Data (02h) / Random Load Program Data (84h) ......................................... 34
8.2.12Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ..................... 35
8.2.13Program Execute (10h)....................................................................................................... 36
8.2.14Page Data Read (13h) ........................................................................................................ 37
8.2.15Read Data (03h) ................................................................................................................. 38
8.2.16Fast Read (0Bh) ................................................................................................................. 39
8.2.17Fast Read with 4-Byte Address (0Ch) ................................................................................ 40
8.2.18Fast Read Dual Output (3Bh) ............................................................................................. 41
8.2.19Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 42
8.2.20Fast Read Quad Output (6Bh) ............................................................................................ 43
8.2.21Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 44
8.2.22Fast Read Dual I/O (BBh) ................................................................................................... 45
8.2.23Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 46
8.2.24Fast Read Quad I/O (EBh) ................................................................................................. 47
8.2.25Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 49
8.2.26Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 51
8.2.27Parameter Page Data Definitions ....................................................................................... 52
9.ELECTRICAL CHARACTERISTICS ............................................................................................... 53
9.1Absolute Maximum Ratings ................................................................................................ 53
9.2Operating Ranges............................................................................................................... 53
W25N01GV
- 3 -
9.3Power-up Power-down Timing Requirements .................................................................... 54
9.4DC Electrical Characteristics .............................................................................................. 55
9.5AC Measurement Conditions .............................................................................................. 56
9.6AC Electrical Characteristics .............................................................................................. 57
9.7Serial Output Timing ........................................................................................................... 59
9.8Serial Input Timing .............................................................................................................. 59
9.9/HOLD Timing ..................................................................................................................... 59
9.10/WP Timing ......................................................................................................................... 59
10.PACKAGE SPECIFICATIONS ........................................................................................................ 60
10.18-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 60
10.224-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 61
10.324-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 62
11.ORDERING INFORMATION .......................................................................................................... 63
11.1Valid Part Numbers and Top Side Marking ........................................................................ 64
12.REVISION HISTORY ...................................................................................................................... 65
W25N01GV
Publication Release Date: December 13, 2014
- 4 - Preliminary - Revision C
Table of Figures
Figure 1a. W25N01GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) .............................. 7
Figure 1b. W25N01GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) ................... 8
Figure 2. W25N01GV Flash Memory Architecture and Addressing ............................................................ 10
Figure 3. W25N01GV Flash Memory Operation Diagram .......................................................................... 11
Figure 4a. Protection Register / Status Register-1 (Address Axh) .............................................................. 14
Figure 4b. Configuration Register / Status Register-2 (Address Bxh) ......................................................... 16
Figure 4c. Status Register-3 (Address Cxh) ............................................................................................... 18
Figure 5. Device Reset Instruction .............................................................................................................. 25
Figure 6. Read JEDEC ID Instruction.......................................................................................................... 26
Figure 7. Read Status Register Instruction ................................................................................................. 27
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 28
Figure 9. Write Enable Instruction ............................................................................................................... 29
Figure 10. Write Disable Instruction ............................................................................................................ 29
Figure 11. Bad Block Management Instruction ........................................................................................... 30
Figure 12. Read BBM Look Up Table Instruction ........................................................................................ 31
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 32
Figure 14. 128KB Block Erase Instruction .................................................................................................. 33
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 34
Figure 16. Quad Load / Quad Random Load Program Data Instruction ..................................................... 35
Figure 17. Program Execute Instruction ...................................................................................................... 36
Figure 18. Page Data Read Instruction ....................................................................................................... 37
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 38
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ........................................................ 38
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................. 39
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0) ........................................................ 39
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................................ 40
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ....................... 40
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................. 41
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) .................................... 41
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............ 42
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ... 42
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 43
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) ................................... 43
Figure 25a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) .......... 44
Figure 25b. Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 44
W25N01GV
- 5 -
Figure 26a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) ................................................... 45
Figure 26b. Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0) .......................................... 45
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) .................. 46
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ......... 46
Figure 28a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ................................................. 47
Figure 28b. Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ......................................... 48
Figure 29a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................ 49
Figure 29b. Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ........ 50
Figure 30a. Power-up Timing and Voltage Levels ...................................................................................... 54
Figure 30b. Power-up, Power-Down Requirement ...................................................................................... 54
Figure 31. AC Measurement I/O Waveform................................................................................................ 56
W25N01GV
Publication Release Date: December 13, 2014
- 6 - Preliminary - Revision C
1. GENERAL DESCRIPTIONS
The W25N01GV (1G-bit) Serial SLC NAND Flash Memory provides a storage solution for systems with
limited s pace, pins and power. The W25N SpiFlash f amily incorporates the popular SPI interface and the
traditional large NAND non-volatile m em ory space. They are ideal for c ode shadowing to RAM, executing
code direct ly f rom Dual/Quad SPI (XIP) and stor ing voice, text and data. T he device operates on a single
2.7V to 3.6V power supply with current consumption as low as 25mA active and 10µA for standby. All
W 25N SpiF lash fam ily devices are off ered in space- saving pack ages which were im possible to use in the
past for the typical NAND flash memory.
The W25N01GV 1G-bit mem ory array is organized into 65,536 program m able pages of 2,048-bytes each.
The entire page can be programmed at one time us ing the data f r om the 2,048-Byte internal buff er. Pages
can be erased in groups of 64 (128KB block erase). The W25N01GV has 1,024 erasable blocks.
The W25N01GV supports the standar d Serial Peripheral Interf ace ( SPI), Dual/Quad I/O SPI: Serial Clock ,
Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/W P), and I/O3 (/HOLD). SPI clock f requencies of up
to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and
416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions.
The W25N01GV provides a new Continuous Read Mode that allows for efficient access to the entire
memory array with a single Read command. This feature is ideal for code shadowing applications.
A Hold pin, Write Protect pin and programmable write protection, provide further control flexibility.
Additionally, the device suppor ts JEDEC s tandard m anufactur er and device ID, one 2,048-Byte Unique ID
page, one 2,048-Byte parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash
memory manageability, user configurable internal ECC, bad block management are also available in
W25N01GV.
2. FEATURES
• New W25N Family of SpiFlash Memories
– W25N01GV: 1G-bit / 128M-byte
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI serial flash commands
• Highest Performance Serial NAND Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– Fast Program/Erase performance
– More than 100,000 erase/program cycles
– More than 10-year data retention
• Efficient “Continuous Read Mode”(1)
– Alternative method to the Buffer Read Mode
– No need to issue “Page Data Read” between
Read commands
– Allows direct read access to the entire array
• Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 25mA active, 10µA standby current
– -40°C to +85°C operating range
• Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
• Advanced Features
– On chip 1-Bit ECC for memory array
– ECC status bits indicate ECC results
– bad block management and LUT(2) access
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– 2KB Unique ID and 2KB parameter pages
– Ten 2KB OTP pages(3)
• Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1. Only the Read com mand st ructures are different between
the “Continuous Read Mode” and the “Buf fer Read Mode”,
all other c omm ands are identical.
2. LUT stands f or Look-Up Table.
3. OTP pages c an onl y be programm ed.
W25N01GV
- 7 -
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W 25N01GV is offered in an 8-pad W SON 8x6-m m (package code ZE), and two 24-ball 8x6-m m T FBGA
(package code TB & TC) packages as shown in Figure 1a-b respectively. Package diagrams and
dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
1
2
3
4
/CS
DO (IO
1
)
/WP (IO
2
)
GND
VCC
/HOLD (IO
3
)
DI (IO
0
)
CLK
Top Vie w
8
7
6
5
Figure 1a. W25N01GV P ad Assignments , 8-pad WSON 8x6-mm (Package Code ZE)
3.2 Pad Description WSON 8x6-mm
PAD NO. PAD NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2)
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)(1)
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)
8 VCC Power Supply
Notes:
1. IO0 and I O1 are used for St andard and Dual S PI instructions
2. IO0 – I O3 are used for Quad SP I instructions , /WP & /HOLD func tions are only avai l abl e f or Standard/Dual SPI.
W25N01GV
Publication Release Date: December 13, 2014
- 8 - Preliminary - Revision C
3.3 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1b. W25N01GV Ball Assignments, 24-ball TFB GA 8x6-mm (P ackage Code TB & TC)
3.4 Ball Description TFBGA 8x6-mm
BALL NO. PIN NAME I/O FUNCTION
B2 CLK I Serial Clock Input
B3 GND Ground
B4 VCC Power Supply
C2 /CS I Chip Select Input
C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2)
D2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
D3 DI (IO0) I/O Data Input (Data Input Output 0)(1)
D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)
Multiple NC No Connect
Notes:
1. IO0 and I O1 are used for St andard and Dual S PI instructions
2. IO0 – I O3 are used for Quad SP I instructions , /WP & /HOLD func tions are only avai l abl e f or Standard/Dual SPI.
W25N01GV
- 9 -
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devic es power consum ption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
30b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25N01GV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instruc tions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read
data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and r ead data or s tatus f r om the devic e on the f alling edge of
CLK.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits
SRP[1:0], a portion as small as 256K-Byte (2x128KB blocks) or up to the entire memory array can be
hardware protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP pin.
W hen W P- E=0, the device is in the Software Protection m ode that only SR-1 can be protected. The /WP
pin functions as a data I/O pin f or the Q uad SPI operations , as well as an active low input pin for the Write
Protection function for SR-1. Refer to section 7.1.3 for detail information.
W hen W P-E=1, the device is in the Hardware Protection m ode that /W P becom es a dedicated active low
input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”
functions are disabled. The entire device (including all registers, mem ory array, OTP pages) will become
read-only. Quad SPI read operations are also disabled when WP-E is set to 1.
4.4 HOLD (/HOLD)
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is actively
selected. When /HOLD is br ought low, while /CS is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). W hen /HOLD is brought high, device operation can
resume. The /HOLD func tion can be useful when m ultiple devices are sharing the same SPI signals. The
/HOLD pin is active low.
When a Quad SPI Read/Buffer Load command is issued, /HOLD pin will become a data I/O pin for the
Quad operations and no HOLD function is available until the current Quad operation finishes.
4.5 Serial Clock (CLK)
The SPI Serial Cloc k Input (C LK) pin provides the tim ing for serial input and output operations . ("See SPI
Operations")
W25N01GV
Publication Release Date: December 13, 2014
- 10 - Preliminary - Revision C
5. BLOCK DIAGRAM
Figure 2. W25N01GV Fl as h Memory Architecture and A ddres sing
1,024 Blocks
(65,536 Pages)
AddressBits 313029282726252423222120191817161514131211109876543210
SpiFlash(upto128M‐Bit) XXXXXXXX
SpiFlash(upto32G‐Bit)
SerialNAND(1G‐Bit) XXXX Ext
128KBBlockAddr(1024Blocks) PageAddr(64Pages) ByteAddress(0‐2047Byte )
64KBBlockAddr(256Blocks) PageAddress(256Pages) ByteAddress(0‐255Byte)
64KBBlockAddress PageAddress(256Pages) ByteAddress(0‐255Byte)
Page
Structure
(2,112-Byte)
Sector 0
512-Byte Sect o r 1
512-Byte Sect o r 2
512-Byte Sect o r 3
512-Byte Spare 0
16-Byte Spare 1
16-Byte Spare 2
16-Byte Spare 3
16-Byte
Column
Address
000h -- 1FFh 200h - - 3FFh 400h - - 5FF h 600h - - 7FF h 800h -- 80Fh810h - - 81F h820h -- 82Fh830h -- 83F h
Byte
Definition Bad Block
Marker User D ata
II User Data
IECC for
Sect or 0 ECC for
Spare
Byte
Address
0123456789ABCDEF
M ain Memory Arra y (2 ,048-Byte)
ECC Protected Spare Area (64-Byte)
No E CC
Protection ECC
Protected ECC for
Byte 4 to Byte D
W25N01GV
- 11 -
6. FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
Power Up
(default BUF=1, ECC-E=1)
Initializ ation &
Default Page Load (00) ~500us
Load Page xx
tRD ~50us
Y
N
Start “Buffer Read” with column address
(Page 00 or Page x x )
Read
page 0 0 ?
Set BUF=0
Load Page yy
tRD ~50us
Start “Continuous Read” from column 0
(Page yy)
Figure 3. W25N01GV Fl ash Memory Operation Di agram
6.1.1 Standard SPI Instructions
The W25N01GV is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25N01GV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the
W25N01GV
Publication Release Date: December 13, 2014
- 12 - Preliminary - Revision C
device at two to three tim es the rate of ordinar y Serial Flash devices . The Dual SPI Read instruc tions are
ideal for quic kly downloading code to RAM upon power-up (code-shadowing) or for executing non-s peed-
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W 25N01GV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)” and “Quad Program Data Load (32h/34h)”. These instructions allow
data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad
Read instructions offer a significant im provement in c ontinuous and r andom acc es s trans f er rates allowing
fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instruct ions the DI and DO pins becom e bidirec tional IO0 and IO1, and the /WP and /HOLD pins bec ome
IO2 and IO3 respectively.
6.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N01GV operation to be
paused while it is actively selected (when /CS is low). The /HOLD f unction may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI. When a Quad SPI command is issued, /HOLD pin will act as a
dedicated IO pin (IO3).
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate af ter the next f alling edge of CLK. T he /HOLD c ondition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. T he Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
W25N01GV
- 13 -
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may comprom ise data integrity. T o address this conc ern, the W 25N01GV
provides several means to protect the data from inadvertent writes.
• Device resets when VCC is below threshold
• Write enable/disable instructions and automatic write disable after erase or program
• Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
• Lock Down write protection for Protection Register (SR-1) until the next power-up
• One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
• Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, the W 25N01GV will m aintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 30a). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled f or a tim e delay of tPUW. T his
includes the Write Enable, Program Execute, Block Erase and the Write Status Register instructions. Note
that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL
time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse
command sequence. If needed a pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register W rite
Enable Latch (W EL) set to a 0. A W rite Enable instruction must be issued before a Program Execute or
Block Erase instruct ion will be accepted. After c om pleting a program or erase ins truc tion the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software contr olled write pr otection is f ac ilitated us ing the Write Status Regis ter ins tr uc tion and setting the
Status Register Pr otec t (SRP0, SRP1) and Block Protec t (TB, BP[3:0]) bits . T hes e s ettings allow a por tion
or the entire mem ory array to be c onf igur ed as read only. Used in conjunc tion with the Write Protect (/WP)
pin, changes to the Status Register can be enabled or disabled under hardware control. See Protection
Register section for further information.
The WP-E bit in Protection Register (SR-1) is us ed to enable the hardware protection. When W P-E is set
to 1, bringing /WP low in the system will block any Wr ite/Progr am/Eras e command to the W25N01GV, the
device will become read-only. The Quad SPI operations are also disabled when WP-E is set to 1.
W25N01GV
Publication Release Date: December 13, 2014
- 14 - Preliminary - Revision C
7. PROTECTION, CONFIGURATION AND STATUS REGISTERS
Three Status Registers are provided for W 25N01GV: Protection Register (SR-1), Configuration Register
(SR-2) & Status Register (SR-3). Each register is accessed by Read Status Register and Write Status
Register commands combined with 1-Byte Register Address respectively.
The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the
flash memory array, whether the device is write enabled or disabled, the state of write protection, Read
modes, Protection Register/OTP area lock status, Erase/Program results, ECC usage/status. The Write
Status Register instruct ion can be us ed to configure the device write protec tion features, Sof tware/Hardware
write protection, Read m odes, enable/disable ECC, Protection Register/OTP area lock. W rite access to the
Status Register is controlled by the state of the non-vola tile Status Register Protect bits (SRP0, SRP1) , the
Write Enable instruction, and when WP-E is set to 1, the /WP pin.
7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable)
Figure 4a. Prot ection Regis ter / St at us Regist er-1 (A ddress Axh)
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable
The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status regis ter-1 (S6,
S5, S4, S3 & S2) that provide W rite Protection c ontrol and status. Block Protect bits can be s et using the
Write Status Register Instruction. All, none or a portion of the memory array can be protected from
Program and Eras e instruc tions (s ee Status Regis ter Mem ory Protection table). T he default values for the
Block Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the Configuration
Register (SR-2) is set to 1, the default values will the values that are OTP locked.
W25N01GV
- 15 -
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protec tion Enable bit ( WP-E) is a volatile read/write bits in the s tatus regis ter -1 (S1). The WP-E
bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection, /WP pin
functionality, and Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in
Software Protection mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read
functions are enabled all the tim e. W hen WP-E is s et to 1, the device is in Har dware Protection mode, all
Quad functions are disabled and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0
and S7). The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, Quad Program/Read is enabled)
SRP1 SRP0 WP-E /WP / IO2 Descriptions
0 0 0 X No /WP functionality
/WP pin will always function as IO2
0 1 0 0 SR-1 cannot be changed (/WP = 0 during Write Status)
/WP pin will function as IO2 for Quad operations
0 1 0 1 SR-1 can be changed (/WP = 1 during Write Status)
/WP pin will function as IO2 for Quad operations
1 0 0 X Power Lock Down(1) SR-1
/WP pin will always function as IO2
1 1 0 X Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will always function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1 SRP0 WP-E /WP only Descriptions
0 X 1 VCC SR-1 can be changed
1 0 1 VCC Power Lock-Down(1) SR-1
1 1 1 VCC Enter OTP mode to protect SR-1 (allow SR1-L=1)
X X 1 GND All "Write/Program/Erase" commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
W25N01GV
Publication Release Date: December 13, 2014
- 16 - Preliminary - Revision C
7.2 Configuration Register / Status Register-2 (Volatile Writable)
Figure 4b. Configuration Regist er / Stat us Register-2 (Address B xh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25N01GV also provides an OTP area for the system to store
critical data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,112-Byte
each. The default data in the OT P area are FF h. Only Program com m and can be issued to the O TP area
to change the data fr om “1” to “0 ”, and data is not revers ible (“ 0” to “1” ) by the Eras e c om m and. O nce the
correc t data is programmed in and verif ied, the system developer c an s et OTP-L bit to 1, s o that the entire
OTP area will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OT P- E bit must be set to 1 in order to use the standard Pr ogram/Read c omm ands to ac ces s the OTP
area as well as to read the Unique ID / Par ameter Page inf or mation. The default value af ter power up or a
RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the devic e c an be c onf igured to have a por tion of or up to the entire ar ray to be write-
protected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set to 1
perm anently when SRP1 & SRP0 are set to (1,1), and OTP Ac cess Mode m ust be entered (OT P-E=1) to
execute the programming. Please refer to 8.2.26 for detailed information.
W25N01GV
- 17 -
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable
W25N01GV has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction
status is indicated by the ECC Status Bits. ECC f unction is enabled by default when power on (ECC-E=1),
and it will not be reset to 0 by the Device Reset command.
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable
W25N01GV provides two different modes for read operations, Buffer Read Mode (BUF=1) and
Continuous Read Mode (BUF=0). Prior to any Read operation, a Page Data Read com mand is needed to
initiate the data transfer from a specified page in the memory array to the Data Buffer. By default, after
power up, the data in page 0 will be automatically loaded into the Data Buffer and the device is ready to
accept any read commands.
The Buff er Read Mode (BUF=1) requires a Column Address to start outputting the ex isting data inside the
Data Buffer, and onc e it reaches the end of the data buffer (Byte 2,111), DO (I O1) pin will becom e high-Z
state.
The Continuous Read Mode (BUF=0) does n’t requir e the s tarting Colum n Addres s. T he device will always
start output the data f rom the f irst colum n (Byte 0) of the Data buff er, and once the end of the data buf fer
(Byte 2,048) is reached, the data output will continue through the next memory page. With Continuous
Read Mode, it is possible to read out the entire m emor y array using a single read com m and. Please refer
to respective command descriptions for the dummy cycle requirements for each read commands under
different read modes.
The default value of BUF bit after power up is 1. BUF bit can be written to 0 in the Status Register-2 to
perform the Continuous Read operation.
BUF ECC-E Read Mode
(Starting from Buffer) ECC Status Data Output Structure
1 0 Buffer Read N/A 2,048 + 64
1 1 Buffer Read Page based 2,048 + 64
0 0 Continuous Read N/A 2,048
0 1 Continuous Read Operation based 2,048
W25N01GV
Publication Release Date: December 13, 2014
- 18 - Preliminary - Revision C
7.3 Status Register-3 (Status Only)
Figure 4c. S tatus Register-3 (Addres s Cxh)
7.3.1 Look-Up Table Full (LUT-F) – Status Only
To fac ilitate the NAND flash memory bad block management, the W25N01GV is equipped with an internal
Bad Block Management Look-Up-Table (BBM LUT). Up to 20 bad memory blocks may be replaced by a
good memor y block respec tively. The addresses of the bloc ks are stor ed in the internal Look -Up T able as
Logical Block Address (LBA, the bad bloc k) & Physical Block Address (PBA, the good block). The LUT -F
bit indicates whether the 20 m em ory block links have been fully utilized or not. T he default value of LUT -F
is 0, once all 20 links are used, LUT-F will become 1, and no more memory block links may be established.
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only
ECC function is us ed in NAND f lash memory to correct limited memory errors during r ead operations . The
ECC Status Bits (ECC-1, ECC-0) should be c hec k ed af ter the c ompletion of a Read oper ation to ver ify the
data integrity. The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared to 0 after a
power cycle or a RESET command.
W25N01GV
- 19 -
ECC Status Descriptions
ECC-1 ECC-0
0 0 Entire data output is successful, without any ECC correction.
0 1
Entire data output is successful, with 1~4 bit/page ECC corrections in either a
single page or multiple pages.
1 0
Entire data output contains more than 4 bits errors only in a single page
which cannot be repaired by ECC.
In the Continuous Read Mode, an additional command can be used to read out
the Page Address (PA) which had the errors.
1 1
Entire data output contains more than 4 bits errors/page in multiple pages.
In the Continuous Read Mode, the additional command can only provide the
last Page Address (PA) that had failures, the user cannot obtain the PAs for
other failure pages. Data is not suitable to use.
Notes:
1. ECC-1,ECC-0 = (1,1) is only applicable during Continuous Read operation (BUF=0).
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only
The Program/Erase Failure Bits are used to indicate whether the internally-controlled Program/Erase
operation was executed successfully or not. These bits will also be set respectively when the Program or
Erase com m and is issued to a lock ed or protected m em or y array or OT P area. Both bits will be clear ed at
the beginning of the Program Execute or Block Erase instructions as well as the device RESET
instruction.
7.3.4 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Program
Execute, Block Erase, Page Data Read and Program Execute for OTP pages.
7.3.5 Erase/Program In Progress (BUSY) – Status Only
BUSY is a read only bit in the s tatus regis ter (S0) that is s et to a 1 s tate when the device is powering up or
executing a Page Data Read, BBM Management, Program Execute, Block Erase, Program Execute for
OTP area, OTP Locking or after a Continuous Read instruction. During this time the device will ignore
further instructions except for the Read Status Register and Read JEDEC ID instructions. When the
program , erase or write s tatus regis ter inst ruction has com pleted, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
7.3.6 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
W25N01GV
Publication Release Date: December 13, 2014
- 20 - Preliminary - Revision C
7.4 W25N01GV Status Register Memory Protection
STATUS REGISTER(1) W25N01GV (1G-BIT / 128M-BYTE) MEMORY PROTECTION(2)
TB BP3 BP2 BP1 BP0 PROTECTED
BLOCK(S)
PROTECTED
PAGE ADDRESS
PA[15:0]
PROTECTED
DENSITY
PROTECTED
PORTION
X 0 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 1022 & 1023 FF80h - FFFFh 256K B Upper 1/512
0 0 0 1 0 1020 thru 1023 FF00h - FFFFh 512K B Upper 1/256
0 0 0 1 1 1016 thru 1023 FE00h - FFFFh 1MB Upper 1/128
0 0 1 0 0 1008 thru 1023 FC00h - FFFFh 2MB Upper 1/64
0 0 1 0 1 992 thru 1023 F800h - FFFFh 4MB Upper 1/32
0 0 1 1 0 960 thru 1023 F000h - FFFFh 8MB Upper 1/16
0 0 1 1 1 896 thru 1023 E000h - FFFFh 16MB Upper 1/8
0 1 0 0 0 768 thru 1023 C000h - FFFFh 32MB Upper 1/4
0 1 0 0 1 512 thru 1023 8000h - FFFFh 64MB Upper 1/2
1 0 0 0 1 0 & 1 0000h – 007Fh 256KB Lower 1/512
1 0 0 1 0 0 thru 3 0000h - 00FFh 512KB Lower 1/256
1 0 0 1 1 0 thru 7 0000h - 01FFh 1MB Lower 1/128
1 0 1 0 0 0 thru 15 0000h - 03FFh 2MB Lower 1/64
1 0 1 0 1 0 thru 31 0000h - 07FFh 4MB Lower 1/32
1 0 1 1 0 0 thru 63 0000h - 0FFFh 8MB Lower 1/16
1 0 1 1 1 0 thru 127 0000h - 1FFFh 16MB Lower 1/8
1 1 0 0 0 0 thru 255 0000h - 3FFFh 32MB Lower 1/4
1 1 0 0 1 0 thru 511 0000h - 7FFFh 64MB Lower 1/2
X 1 0 1 X 0 thru 1023 0000h - FFFFh 128MB ALL
X 1 1 X X 0 thru 1023 0000h - FFFFh 128MB ALL
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.
W25N01GV
- 21 -
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W 25N01GV consists of 27 basic instructions that are
fully controlled through the SPI bus (s ee Ins tr uction Set Table1, 2). Ins tr uctions ar e initiated with the f alling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instruc tions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5
through 29. All read instructions can be completed after any clocked bit. However, all instructions that
W rite, Program or Erase must c omplete on a byte boundary (/CS dr iven high after a full 8-bits have been
clock ed) otherwise the ins truct ion will be ignored. This feature f urther protects the devic e f rom inadvertent
writes. Additionally, while the device is perform ing Program or Erase operation, BBM managem ent, Page
Data Read or OTP locking operations, BUSY bit will be high, and all instructions except for Read Status
Register or Read JEDEC ID will be ignored until the current operation cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID (MF7 - MF0)
Winbond Serial Flash EFh
Device ID (ID15 - ID0)
W25N01GV AA21h
W25N01GV
Publication Release Date: December 13, 2014
- 22 - Preliminary - Revision C
8.1.2 Instruction Set Table 1 (Continuous Read Mode, BUF = 0)(11)
Commands OpCode Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte9
Device RESET FFh
JEDEC ID 9Fh Dummy EFh AAh 21h
Read Status Register 0Fh / 05h SR Addr S7-0 S7-0 S7-0 S7-0 S7-0 S7-0 S7-0
Write Status Register 1Fh / 01h SR Addr S7-0
Write Enable 06h
Write Disable 04h
BB Management
(Swap Blocks) A1h LBA LBA PBA PBA
Read BBM LUT A5h Dummy LBA0 LBA0 PBA0 PBA0 LBA1 LBA1 PBA1
Last ECC failure
Page Address A9h Dummy PA15-8 PA7-0
Block Erase D8h Dummy PA15-8 PA7-0
Program Data Load
(Reset Buffer) 02h CA15-8 CA7-0
Data-0 Data-1 Data-2 Data-3 Data-4 Data-5
Random Program
Data Load 84h CA15-8 CA7-0
Data-0 Data-1 Data-2 Data-3 Data-4 Data-5
Quad Program
Data Load (Reset Buffer) 32h CA15-8 CA7-0
Data-0 / 4 Data-1 / 4 Data-2 / 4 Data-3 / 4 Data-4 / 4 Data-5 / 4
Random Quad Program
Data Load 34h CA15-8 CA7-0
Data-0 / 4 Data-1 / 4 Data-2 / 4 Data-3 / 4 Data-4 / 4 Data-5 / 4
Program Execute 10h Dummy PA15-8 PA7-0
Page Data Read 13h Dummy PA15-8 PA7-0
Read 03h Dummy Dummy Dummy D7-0 D7-0 D7-0 D7-0 D7-0
Fast Read 0Bh Dummy Dummy Dummy Dummy D7-0 D7-0 D7-0 D7-0
Fast Read
with 4-Byte Address 0Ch Dummy Dummy Dummy Dummy Dummy D7-0 D7-0 D7-0
Fast Read Dual Output 3Bh Dummy Dummy Dummy Dummy D7-0 / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Dual Output
with 4-Byte Address 3Ch Dummy Dummy Dummy Dummy Dummy D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Quad Output 6Bh Dummy Dummy Dummy Dummy D7-0 / 4 D7-0 / 4 D7-0 / 4 D7-0 / 4
Fast Read Quad Output
with 4-Byte Address 6Ch Dummy Dummy Dummy Dummy Dummy D7-0 / 4 D7-0 / 4 D7-0 / 4
Fast Read Dual I/O BBh Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address BCh Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Quad I/O EBh Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 D7-0 / 4 D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address ECh Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 D7-0 / 4