NCV7341D20R2G - ON Semiconductor - Datasheet.Directory

May, 2009 − Rev. 4

1Publication Order Number:

NCV7341/D

NCV7341

High Speed Low Power CAN

Transceiver

The NCV7341 CAN transceiver is the interface between a

controller area network (CAN) protocol controller and the physical

bus and may be used in both 12 V and 24 V systems. The transceiver

provides differential transmit capability to the bus and differential

receive capability to the CAN controller.

Due to the wide common−mode voltage range of the receiver inputs,

the NCV7341 is able to reach outstanding levels of electromagnetic

susceptibility (EMS). Similarly, extremely low electromagnetic

emission (EME) is achieved by the excellent matching of the output

signals.

The NCV7341 is a new addition to the ON Semiconductor CAN

high−speed transceiver family and offers the following additional

features:

Features

•Ideal Passive Behavior when Supply Voltage is Removed

•Separate VIO Supply for Digital Interface Allowing Communication

to CAN Controllers and Microcontrollers with Different Supply

Levels

•Fully Compatible with the ISO 11898 Standard

•High Speed (up to 1 Mb)

•Very Low Electromagnetic Emission (EME)

•VSPLIT Voltage Source for Stabilizing the Recessive Bus Level if

Split Termination is Used (Further Improvement of EME)

•Differential Receiver with High Common−Mode Range for

Electromagnetic Immunity (EMI)

•Up to 110 Nodes can be Connected in Function of the Bus Topology

•Transmit Data (TxD) Dominant Time−out Function

•Bus Error Detection with Version NCV7341D20

•Bus Pins Protected Against Transients in Automotive Environments

•Bus Pins and Pin VSPLIT Short−Circuit Proof to Battery and Ground

•Thermally Protected

•NCV Prefix for Automotive and Other Applications Requiring Site

and Change Controls

•These are Pb−Free Devices*

Typical Applications

•Automotive

•Industrial Networks

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

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PIN ASSIGNMENT

(Top View)

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

141

TxD

GND

RxD

EN WAKE

CANH

CANL

VBAT

NCV7341

PC20060727.1

VCC

VIO

INH

STB

VSPLIT

ERR

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Table 1. TECHNICAL CHARACTERISTICS

Symbol Parameter Condition Max Max Unit

VCC Supply Voltage for the Core Circuitry 4.75 5.25 V

VIO Supply Voltage for the Digital Interface 2.8 5.25 V

VEN DC Voltage at Pin EN −0.3 VIO + 0.3 V

VSTB DC Voltage at Pin STB −0.3 VIO + 0.3 V

VTxD DC Voltage at Pin TxD −0.3 VIO + 0.3 V

VRxD DC Voltage at Pin RxD −0.3 VIO + 0.3 V

VERR DC Voltage at Pin ERR −0.3 VIO + 0.3 V

VCANH DC Voltage at Pin CANH 0 < VCC < 5.25 V; No Time Limit −58 +58 V

VCANL DC Voltage at Pin CANL 0 < VCC < 5.25 V; No Time Limit −58 +58 V

VSPLIT DC Voltage at Pin VSPLIT 0 < VCC < 5.25 V; No time Limit −58 +58 V

VO(dif)(bus_dom) Differential Bus Output Voltage in Dominant

State

42.5 W < RLT < 60 W1.5 3 V

CMrange Input Common−Mode Range for Comparator Guaranteed Differential Receiver

Threshold and Leakage Current

−35 +35 V

Cload Load Capacitance on IC Outputs 15 pF

tpd(rec−dom) Propagation Delay TxD to RxD See Figure 6 90 230 ns

tpd(dom−rec) Propagation Delay TxD to RxD See Figure 6 90 245 ns

TJJunction Temperature −40 150 °C

ESDHBM ESD Level, Human Body Model Pins CANH, CANL, VSPLIT

WAKE, VBAT other Pins

−4

−3

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BLOCK DIAGRAM

VSPLIT

Digital

Control

Block Wake −up

Filter

NCV7341

GND

RxD

VCC

Timer VCC

TxD

Driver

control

Thermal

shutdown

PC20060921.1

POR

ÏÏ

VIO

ÏÏ

VIO

Level

shifter

VIO

−

WAKE

Clock

VBATINH

VIO

STB

ERR

CANH

CANL

VSPLIT

”Active”

Low Power

Rec

VCC/2

”Active”

26 kW

Figure 1. Block Diagram

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TYPICAL APPLICATION SCHEMATICS

STB

RxD

TxD

CAN

controller

GND GND

PC20060921.4

ERR 8

VCC

5V−Reg

VBATINHVio

VCC

3710

100nF

100 nF

xmF*

NCV7341

Note (*): Value depending on regulator

OUT

CANH

CANL

VSPLIT

CAN

BUS

RLT =60W

9WAKE

180 kW

2.7 kW

1kW

RLT =60W

CLT= 4.7 nF

10 nF

VBAT

10 nF

Figure 2. Application Diagram with a 5V CAN Controller

NCV7341

STB

RxD

TxD

CAN

controller

GND GND

PC20060921.4

ERR 8

Vcc

VBAT

INH

Vio

Vcc

100 nF

xmF*

Note (*): Value depending on regulator

5V−reg

3V−reg

xmF*

OUT

OUT IN

CANH

CANL

VSPLIT

CAN

BUS

RLT =60W

WAKE

180 kW

2.7 kW

1kW

RLT =60W

CLT = 4.7 nF

10 nF

VBAT

10 nF

Figure 3. Application Diagram with a 3V CAN Controller

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PIN DESCRIPTION

Figure 4. NCV7340 Pin Assignment

141

TxD

GND

RxD

EN WAKE

CANH

CANL

VBAT

NCV7341

PC20060727.1

VCC

VIO

INH

STB

VSPLIT

ERR

Table 2. PIN DESCRIPTION

Pin Name Description

1 TxD Transmit data input; low level = dominant on the bus; internal pull−up current

2 GND Ground

3 VCC Supply voltage for the core circuitry and the transceiver

4 RxD Receive data output; dominant bus => low output

5 VIO Supply voltage for the CAN controller interface

6 EN Enable input; internal pull−down current

7 INH High voltage output for controlling external voltage regulators

8ERR Digital output indicating errors and power−up; active low

9 WAKE Local wake−up input

10 VBAT Battery supply connection

11 VSPLIT Common−mode stabilization output

12 CANL Low−level CAN bus line (low in dominant)

13 CANH High−level CAN bus line (high in dominant)

14 STB Stand−by mode control input; internal pull−down current

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FUNCTIONAL DESCRIPTION

OPERATING MODES

Operation modes of NCV7341 are shown in Figures 5 and in Table 3.

POWER

RECEIVE

ONLY

MODE

NORMAL

MODE

STANDBY

MODE

GOTO

SLEEP

MODE

SLEEP

MODE

STB = H

and

EN = L

STB = H

and

EN = H

STB = H

and

EN = L

STB = H

and

EN = H

STB = L

and

EN = H

STB = L and EN = H

and

flags reset

STB = L

and

(EN = L or flags set)

STB = L

and

(EN = L or flags set)

STB = H

and

EN = H

STB = H

and

EN = L

STB = L

and

EN = L

STB = L and EN = H

and

flags reset

and

t > t h(min)

STB = L

and

flags set

STB = H and EN = L

and

VCC/VIO undervoltage flag reset

STB = H and EN = H

and

VCC/VIO undervoltage flag reset

LEGEND

”Flags set” : wake−up or power−up

”Flags reset” : not (wake−up or power−up)

PC20060921.2

Figure 5. Operation Modes

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Table 3. OPERATION MODES

Conditions Transceiver Behavior

Pin STB Pin EN

VCC/VIO

Undervoltage

Flag

VBAT

Undervoltage

Flag

Power−up or

Wakeup Flag Operating Mode Pin INH

X X Set X X Sleep Floating

Reset Set Set Standby High

Reset If in sleep, then no change Floating

otherwise stand−by High

Low Low Reset Reset Set Stand−by High

Reset If in sleep, then no change Floating

otherwise stand−by High

Low High Reset Reset Set Stand−by High

Reset If in sleep, then no change Floating

otherwise go−to−sleep High

High Low Reset Reset X Receive−only High

High High Reset Reset X Normal High

Normal Mode

In Normal mode, the transceiver is able to communicate

via the bus lines. The CAN controller can transmit data to the

bus via TxD pin and receive data from the bus via Pin RxD.

The bus lines (CANH and CANL) are internally biased to

VCC/2 via the common−mode input resistance. Pin VSPLIT

is also providing voltage VCC/2 which can be further used

to externally stabilize the common mode voltage of the bus

– see Figure 2 and Figure 3. Pin INH is active (pulled high)

so that the external regulators controlled by INH Pin are

switched on.

Receive−Only Mode

In Receive−only mode, the CAN transmitter is disabled.

The CAN controller can still receive data from the bus via

RxD Pin as the receiver part remains active. Equally to

normal mode, the bus lines (CANH and CANL) are

internally biased to VCC/2 and Pin VSPLIT is providing

voltage VCC/2. Pin INH is also active (pulled high).

Standby Mode

Standby mode is a low−power mode. Both the transmitter

and the receiver are disabled and a very low−power

differential receiver monitors the CAN bus activity. Bus

lines are biased internally to ground via the common mode

input resistance and Pin VSPLIT is high−impedant (floating).

A wake−up event can be detected either on the CAN bus or

on the WAKE Pin. A valid wake−up is signaled on pins ERR

and RxD. Pin INH remains active (pulled high) so that the

external regulators controlled by INH Pin are switched on.

Go−To−Sleep Mode

Go−To −Sleep mode is an intermediate state used to put the

transceiver into sleep mode in a controlled way.

Go−To −Sleep mode is entered when the CAN controller

puts pin EN to High and STB Pin to Low. If the logical state

of Pins EN and STB is kept unchanged for minimum period

of th(min) and neither a wake−up nor a power−up event occur

during this time, the transceiver enters sleep mode. While in

go−to−sleep mode, the transceiver behaves identically to

stand−by mode.

Sleep Mode

Sleep mode is a low−power mode in which the

consumption is further reduced compared to stand−by

mode. Sleep mode can be entered via go−to−sleep mode or

in case an undervoltage on either VCC or VIO occurs for

longer than the under−voltage detection time. The

transceiver behaves identically to standby mode, but the

INH Pin is deactivated (left floating) and the external

regulators controlled by INH Pin are switched off. In this

way, the VBAT consumption is reduced to a minimum. The

device will leave sleep mode either by a wake−up event (in

case of a CAN bus wake−up or via Pin WAKE) or by putting

Pin STB high (as long as an under−voltage on VCC or VIO

is not detected).

Internal Flags

The transceiver keeps several internal flags reflecting

conditions and events encountered during its operation.

Some flags influence the operation mode of the transceiver

(see Figure 5 and Table 3). Beside the undervoltage and the

TxD dominant timeout flags, all others can be read by the

CAN controller on Pin ERR. Pin ERR signals internal flags

depending on the operation mode of the transceiver. An

overview of the flags and their visibility on Pin ERR is given

in Table 4. Because the ERR Pin uses negative logic, it will

be pulled low if the signaled flag is set and will be pulled

high if the signaled flag is reset.

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Table 4. INTERNAL FLAGS AND THEIR VISIBILITY

Internal Flag Set Condition Reset Condition Visibility on Pin ERR

VCC/VIO Undervoltage VCC < VCC(SLEEP) longer than tUV(VCC)

or VIO < VIO(SLEEP) longer than tUV(VIO)

At wake−up or power−up No

VBAT Undervoltage VBAT < VBAT(STB) When VBAT recovers No

Powerup VBAT rises above VBAT(PWUP)

(VBAT connection to the transceiver)

When normal mode is

entered

In receive−only mode. Not

going from normal mode

Wake−up When remote or local wake−up is

detected

At power−up or when normal

mode is entered or when

VCC/VIO undervoltage flag is

set

Both on ERR and RxD (both

pulled to low). In

go−to−sleep, standby and

sleep mode.

Local Wake−up When local wake−up is detected

(i.e.via pin WAKE)

At power−up or when leaving

normal mode

In normal mode before 4

consecutive dominant

symbols are sent. Then ERR

pin becomes High again

Failure Pin TxD clamped low or

overtemperature

When entering normal mode

or when RxD is Low while

TxD is high (provided all

failures disappeared)

Overtemperature condition

observable in receive−only

mode entered from normal

mode

Bus Failure

(NCV7341D20)

One of the bus lines shorted to ground

or supply during four consecutive

transmitted dominants

No bus line short (to ground

or supply) detected during

four consecutive dominant bit

transmissions

In normal mode

VCC/VIO Undervoltage Flag

The VCC/VIO undervoltage flag is set if VCC supply drops

below VCC(sleep) level for longer than tUV(VCC) or VIO

supply drops below VIO(sleep) level for longer than tUV(VIO).

If the flag is set, the transceiver enters sleep mode. After a

waiting time identical to the undervoltage detection times

tUV(VCC) and tUV(VIO), respectively, the flag can be reset

either by a valid wake−up request or when the powerup flag

is set. During this waiting time, the wakeup detection is

blocked.

VBAT Under−voltage Flag

The flag is set when VBAT supply drops below VBAT(STB)

level. The transceiver will enter the standby mode. The flag

is reset when VBAT supply recovers. The transceiver then

enters the mode defined by inputs STB and EN.

Power−up Flag

This flag is set when VBAT supply recovers after being

below VBAT(PWUP) level, which corresponds to a

connection of the transceiver to the battery. The VCC/VIO

undervoltage flag is cleared so that the transceiver cannot

enter the Go−to−sleep Mode, ensuring that INH Pin is high

and the external voltage regulators are activated at the

battery connection. In Receive−only mode, the powerup

flag can be observed on the ERR Pin. The flag is reset when

Normal mode is entered.

Wake−up Flag

This flag is set when the transceiver detects a valid

wake−up request via the bus or via the WAKE Pin. Setting

the wake−up flag is blocked during the waiting time of the

VCC/VIO undervoltage flag. The wake−up flag is

immediately propagated to Pins ERR and RxD – provided

that supplies VCC and VIO are available. The wake−up flag

is reset at power−up or when VCC/VIO undervoltage occurs

or when Normal mode is entered.

Local wake−up Flag

This flag is set when a valid wake−up request through

WAKE Pin occurs. It can be observed on the ERR Pin in

normal mode. It can only be set when the powerup flag is

reset. The local wake−up flag is reset at powerup or at

leaving Normal mode.

Failure Flag

The failure flag is set in one of the following situations:

•TxD Pin is Low (i.e. dominant is requested by the CAN

controller) for longer than tdom(TxD) − Under this

condition, the transmitter is disabled so that a bus

lockup is avoided in case of an application failure

which would drive permanent dominant on the bus. The

transmitter remains disabled until the failure flag is

reset.

•Overtemperature − If the junction temperature reaches

TJ(SD), the transmitter is disabled in order to protect it

from overheating and the failure flag is set. The

transmitter remains disabled until the failure flag is

reset.

The failure flag is reset when Normal mode is entered or

when TxD pin is High while RxD pin is Low. In case of

overtemperature, the failure flag is observable on pin ERR.

Bus Failure Flag (NCV7341D20)

The transmitter of the NCV7341D20 device version

allows bus failure detection. During dominant bit

transmission, a short of the CANH or CANL line to ground

or supply (VCC, VBAT or other) is internally detected. If the

short circuit condition lasts for four consecutive dominant

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transmissions, an internal bus failure flag is set and made

immediately visible through a Low level on the ERR pin.

The transmission and reception circuitry continues to

function.

When four consecutive dominant transmissions succeed

without a bus line short being detected, the internal bus

failure flag is reset and ERR pin is released to High level.

Split Circuit

The VSPLIT Pin is operational only in normal and

receive−only modes. It is floating in standby and sleep

modes. The VSPLIT can be connected as shown in Figure 2

and Figure 3 and its purpose is to provide a stabilized DC

voltage of VCC/2 to the bus avoiding possible steps in the

common−mode signal, therefore reducing EME. These

unwanted steps could be caused by an unpowered node on

the network with excessive leakage current from the bus that

shifts the recessive voltage from its nominal VCC/2 level.

Wake−up

The transceiver can detect wake−up events in stand−by,

go−to−sleep and sleep modes. Two types of wake−up events

are handled – remote wake−up via the CAN bus or a local

wake−up via the WAKE pin. A valid remote wake−up is

recognized after two dominant states of the CAN bus of at

least tdom, each of them followed by a recessive state of at

least trec.

A local wake−up is detected after a change of state (High

to Low, or Low to High) on WAKE Pin which is stable for

at least tWAKE. To increase the EMS level of the WAKE Pin,

an internal current source is connected to it. If the state of the

WAKE Pin is stable at least for tWAKE, the direction of the

current source follows (pulldown current for Low state,

pullup current for High state). It is recommended to connect

Pin WAKE either to GND or VBAT if it’s not used in the

application.

Fail Safe Features

Fail safe behavior is ensured by the detection functions

associated with the internal flags.

Furthermore, a current−limiting circuit protects the

transmitter output stage from damage caused by accidental

short circuit to either positive or negative supply voltage,

although power dissipation increases during this fault

condition.

The Pins CANH and CANL are protected from

automotive electrical transients (according to ISO 7637; see

Figure 9). Pins TxD is pulled high and Pins STB and EN are

pulled low internally should the input become disconnected.

Pins TxD, STB, EN and RxD will be floating, preventing

reverse supply should the VIO supply be removed.

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ELECTRICAL CHARACTERISTICS

Definitions

All voltages are referenced to GND (Pin 2). Positive

currents flow into the IC. Sinking current means the current

is flowing into the pin; sourcing current means the current

is flowing out of the pin.

Absolute Maximum Ratings

Stresses above those listed in the following table may

cause permanent device failure. Exposure to absolute

maximum ratings for extended periods may affect device

reliability.

Table 5. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Conditions Min. Max. Unit

VBAT Supply voltage −0.3 58 V

VCC Supply voltage −0.3 +7 V

VIO Supply voltage −0.3 +7 V

VCANH DC voltage at pin CANH 0 < VCC < 5.25 V;

no time limit

−58 +58 V

VCANL DC voltage at pin CANL 0 < VCC < 5.25 V;

no time limit

−58 +58 V

VCANL−VCANH DC voltage between bus pins CANH and CANL 0 < VCC < 5.25 V;

no time limit

−58 +58 V

VSPLIT DC voltage at pin VSPLIT 0 < VCC < 5.25 V;

no time limit

−58 +58 V

VINH DC voltage at pin INH −0.3 VBAT+0.3 V

VWAKE DC voltage at pin WAKE −0.3 58 V

VTxD DC voltage at pin TxD −0.3 7 V

VRxD DC voltage at pin RxD −0.3 VIO + 0.3 V

VSTB DC voltage at pin STB −0.3 7 V

VEN DC voltage at pin EN −0.3 7 V

VERR DC voltage at pin ERR −0.3 VIO + 0.3 V

Vtran(CANH) Transient voltage at pin CANH (Note 1) −300 +300 V

Vtran(CANL) Transient voltage at pin CANL (Note 1) −300 +300 V

Vtran(VSPLIT) Transient voltage at pin VSPLIT (Note 1) −300 +300 V

Vesd(CANL/CANH/

VSPLIT, VBAT, WAKE)

Electrostatic discharge voltage at pins intended to be

wired outside of the module

(CANH, CANL, VSPLIT

, VBAT, WAKE)

(Note 2)

(Note 4)

−4

−500

500

Vesd Electrostatic discharge voltage at all other pins (Note 2)

(Note 4)

−3

−500

500

Latch−up Static latch−up at all pins (Note 3) 120 mA

Tstg Storage temperature −50 +150 °C

Tamb Ambient temperature −50 +125 °C

Tjunc Maximum junction temperature −50 +180 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 9).

2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.

3. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78.

4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.

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Operating Conditions

Operating conditions define the limits for functional operation, parametric characteristics and reliability specification of the

device. Functionality of the device is not guaranteed outside the operating conditions.

Table 6. OPERATING RANGES

Symbol Parameter Conditions Min Max Unit

VBAT Supply Voltage 5.0 50 V

VBAT_SLEEP Supply Voltage in the Sleep Mode (Note 1) 6.0 50 V

VCC Supply Voltage 4.75 5.25 V

VIO Supply Voltage 2.8 5.25 V

VCANH DC Voltage at Pin CANH Receiver Function Guaranteed −35 +35 V

VCANL DC Voltage at Pin CANL Receiver Function Guaranteed −35 +35 V

VCANL−VCANH DC Voltage Between Bus Pins CANH

and CANL

Receiver Function Guaranteed −35 +35 V

VSPLIT DC Voltage at Pin VSPLIT Leakage and Current Limitation are

Guaranteed

−35 +35 V

VINH DC Voltage at Pin INH −0.3 VBAT + 0.3 V

VWAKE DC Voltage at Pin WAKE −0.3 VBAT + 0.3 V

VTxD DC Voltage at Pin TxD −0.3 VIO + 0.3 V

VRxD DC Voltage at Pin RxD −0.3 VIO + 0.3 V

VSTB DC Voltage at Pin STB −0.3 VIO + 0.3 V

VEN DC Voltage at Pin EN −0.3 VIO + 0.3 V

VERR DC Voltage at Pin ERR −0.3 VIO + 0.3 V

CLOAD Capacitive Load on Digital Outputs

(Pins RxD and ERR)

15 pF

TAAmbient Temperature −40 +125 °C

TJMaximum Junction Temperature −40 +150 °C

1. In the sleep mode, all relevant parameters are guaranteed only for VBAT > 6 V. For VBAT between 5 V and 6 V, no power−on−reset will occur

and the functionality is also guaranteed, but some parameters might get slightly out of the specification − e.g. the wakeup detection

thresholds.

Table 7. THERMAL CHARACTERISTICS

Symbol Parameter Conditions Value Unit

Rth(vj−a) Thermal Resistance from Junction−to−Ambient in SOIC−14 Package 1S0P PCB 128 K/W

Rth(vj−a) Thermal Resistance from Junction−to−Ambient in SOIC−14 Package 2S2P PCB 70 K/W

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Characteristics

The characteristics of the device are valid for operating conditions defined in Table 7 and the bus lines are considered to be

loaded with RLT = 60 W, unless specified otherwise.

Table 8. DC CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit

SUPPLY (PIN VBAT)

VBAT(STB) Level for Setting VBAT

Undervoltage Flag

VCC = 5 V 2.75 3.3 4.5 V

VBAT(PWUP) Level for Setting Powerup

Flag

VCC = 0 V 2.75 3.3 4.5 V

IVBAT VBAT Current Consumption in

Normal and Receive−Only

Modes

INH and WAKE Not Loaded 1.0 10 40 mA

VBAT Current Consumption in

Standby and Go−to−Sleep

Modes. The total supply

current is drawn partially from

VBAT and partially from VCC.

VVCC > 4.75 V, VVIO > 2.8 V

VINH = VWAKE = VVBAT = 12 V

Tamb < 100°C

18 mA

VVCC > 4.75 V, VVIO > 2.8 V

VINH = VWAKE = VVBAT = 12 V

8.0 12 22.5 mA

VBAT Current Consumption in

Sleep Mode. The supply

current is drawn from VBAT

only.

VVCC = VINH = VVIO = 0 V

VWAKE = VVBAT = 12 V

Tamb < 100°C

35 mA

VVCC = VINH = VVIO = 0 V

VWAKE = VVBAT = 12 V

10 20 50 mA

SUPPLY (PIN VCC)

VCC(SLEEP) VCC Level for Setting VCC/VIO

Undervoltage Flag

VBAT = 12 V 2.75 3.3 4.5 V

IVCC VCC Current Consumption in

Normal or Receive−Only

Mode

Normal Mode:

VTxD = 0 V, i.e. Dominant

25 55 80 mA

Normal Mode: VTxD = VIO, i.e.

Recessive (or Receive−Only

Mode)

2.0 6.0 10 mA

VCC Current Consumption in

Standby and Go−to−Sleep

Mode. The total supply

current is drawn partially from

VBAT and partially from VCC.

Tamb < 100°C 17.5 mA

6.5 12 19.5 mA

VCC Current Consumption in

Sleep Mode

Tamb < 100°C 1.0 mA

0.2 0.5 2.0 mA

SUPPLY (PIN VIO)

VIO(SLEEP) VIO Level for Setting VCC/VIO

Undervoltage Flag

0.9 1.6 2.0 V

IVIO VIO Current Consumption in

Normal or Receive−Only

Mode

Normal Mode:

VTxD = 0V, i.e. Dominant

100 350 1000 mA

Normal Mode: VTxD = VIO, i.e.

Recessive (or Receive−Only

mode)

0 0.2 1.0 mA

VIO Current Consumption in

Standby or Sleep Mode

Tamb < 100°C 1.0 mA

0 0 5.0 mA

TRANSMITTER DATA INPUT (PIN TxD)

VIH High−Level Input Voltage Output Recessive 0.7VVIO −VIO +

0.3

VIL Low−Level Input Voltage Output Dominant −0.3 −0.3VVIO V

IIH High−Level Input Current VTxD = VVIO −5.0 0 +5.0 mA

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Table 8. DC CHARACTERISTICS

Symbol UnitMaxTypMinConditionsParameter

TRANSMITTER DATA INPUT (PIN TxD)

IIL Low−Level Input Current VTxD = 0.3 VVIO −70 −250 −500 mA

CiInput Capacitance Not Tested 1.0 5.0 10 pF

STANDBY AND ENABLE INPUTS (PINS STB AND EN)

VIH High−Level Input Voltage 0.7VVIO −VIO +

0.3

VIL Low−Level Input Voltage −0.3 −0.3VVIO V

IIH High−Level Input Current VSTB = VEN = 0.7VVIO 1.0 5.0 10 mA

IIL Low−Level Input Current VSTB = VEN = 0 V −0.5 0 5.0 mA

CiInput Capacitance 1.0 5.0 10 pF

RECEIVER DATA OUTPUT (PIN RxD)

IOH High−Level Output Current VRxD = VVIO − 0.4 V

VVIO = VVCC

−1.0 −3.0 −6.0 mA

IOL Low−Level Output Current VRxD = 0.4 V

VTxD = 0 V Bus is Dominant

2.0 5.0 12 mA

FLAG INDICATION OUTPUT (PIN ERR)

IOH High−Level Output Current VERR = VVIO − 0.4 V

VVIO = VVCC

−4.0 −20 −50 mA

IOL Low−Level Output Current VERR = 0.4 V 100 200 350 mA

LOCAL WAKE−UP INPUT (PIN WAKE)

IIH High−Level Input Current VWAKE = VVBAT − 1.9 V −1.0 −5.0 −10 mA

IIL Low−Level Input Current VWAKE = VVBAT − 3.1 V 1.0 5.0 10 mA

Vthreshold Threshold of the Local

Wake−up Comparator

Sleep or Standby Mode VVBAT −

3 V

VVBAT −

2.5 V

VVBAT −

2 V

INHIBIT OUTPUT (PIN INH)

VHDROP High Level Voltage Drop IINH = −180 mA50 200 800 mV

ILEAK Leakage Current in Sleep

Mode

0−5.0 mA

Tamb < 100°C 0 −1.0 mA

BUS LINES (PINS CANH AND CANL)

Vo(reces) (norm) Recessive Bus Voltage VTxD = VVCC; No Load, Normal

Mode

2.0 2.5 3.0 V

Vo(reces) (stby) Recessive Bus Voltage VTxD = VVCC; No Load, Standby

Mode

−100 0 100 mV

Io(reces) (CANH) Recessive Output Current at

Pin CANH

−35 V < VCANH < +35 V;

0 V < VCC < 5.25 V

−2.5 −+2.5 mA

Io(reces) (CANL) Recessive Output Current at

Pin CANL

−35 V < VCANL < +35 V;

0 V < VVCC < 5.25 V

−2.5 −+2.5 mA

Vo(dom) (CANH) Dominant output Voltage at

Pin CANH

VTxD = 0 V 3.0 3.6 4.25 V

Vo(dom) (CANL) Dominant Output Voltage at

Pin CANL

VTxD = 0 V 0. 5 1.4 1.75 V

Vo(dif) (bus_dom) Differential Bus Output

Voltage (VCANH − VCANL)

VTxD = 0 V; Dominant;

42.5 W < RLT < 60 W

1.5 2.25 3.0 V

Vo(dif) (bus_rec) Differential Bus Output

Voltage (VCANH − VCANL)

VTxD = VCC; Recessive; No

Load

−120 0 +50 mV

Io(sc) (CANH) Short−Circuit Output Current

at Pin CANH

VCANH = 0 V; VTxD = 0 V −45 −70 −120 mA

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Table 8. DC CHARACTERISTICS

Symbol UnitMaxTypMinConditionsParameter

BUS LINES (PINS CANH AND CANL)

Io(sc) (CANL) Short−Circuit Output Current

at Pin CANL

VCANL = 42 V; VTxD = 0 V 45 70 120 mA

Vi(dif) (th) Differential Receiver Threshold

Voltage (see Figure 7)

−12 V < VCANL < +12 V

−12 V < VCANH < +12 V

0.5 0.7 0.9 V

Vihcm(dif) (th) Differential Receiver Threshold

Voltage for High

Common−Mode (see Figure 7)

−35 V < VCANL < +35 V

−35 V < VCANH < +35 V

0.35 0.7 1.00 V

Vi(dif) (hys) Differential Receiver Input

Voltage Hysteresis

(see Figure 7)

−35 V < VCANL < +35 V

−35V <VCANH < +35 V

50 70 100 mV

VI(dif)_WAKE Differential Receiver Input

Voltage for Bus Wake−up

Detection (in Sleep or

Standby Mode)

−12 V < VCANH < +12 V

0.4 0.8 1.15 V

Ri(cm) (CANH) Common−Mode Input

Resistance at Pin CANH

15 26 39 kW

Ri(cm) (CANL) Common−Mode Input

Resistance at Pin CANL

15 26 39 kW

Ri(cm)(m) Matching between Pin CANH

and Pin CANL Common

Mode Input Resistance

VCANH = VCANL −3.0 0 +3.0 %

Ri(dif) Differential Input Resistance 25 50 75 kW

Ci(CANH) Input Capacitance at Pin

CANH

VTxD = VCC 7.5 20 pF

Ci(CANL) Input Capacitance at Pin

CANL

VTxD = VCC 7.5 20 pF

Ci(dif) Differential Input Capacitance VTxD = VCC 3.75 10 pF

COMMON−MODE STABILIZATION (PIN VSPLIT)

VSPLIT Reference Output Voltage at

Pin VSPLIT

Normal mode;

−500 mA < ISPLIT < 500 mA

0.3 x

VCC

0.5 x

VCC

0.7 x

VCC

ISPLIT(i) VSPLIT Leakage Current Standby Mode

−27 V < VSPLIT < 40 V

−50 +50 mA

Standby Mode

−27 V < VSPLIT < 40 V

Tamb < 100°C

−5.0 +5.0

ISPLIT(lim) VSPLIT Limitation Current

(Absolute Value)

Normal Mode 1.3 3.0 5.0 mA

THERMAL SHUTDOWN

TJ(SD) Shutdown Junction

Temperature

150 160 180 °C

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Table 9. AC CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit

TIMING CHARACTERISTICS (Figure 6)

td(TxD−BUSon) Delay TxD to Bus Active Setup According to Figure 8 40 85 105 ns

td(TxD−BUSoff) Delay TxD to Bus Inactive Setup According to Figure 8 30 60 105 ns

td(BUSon−RxD) Delay Bus Active to RxD Setup According to Figure 8 25 55 105 ns

td(BUSoff−RxD) Delay Bus Inactive to RxD Setup According to Figure 8 40 65 105 ns

tpd(rec−dom) Propagation Delay TxD to

RxD from Recessive to

Dominant

Setup According to Figure 8 90 130 230 ns

td(dom−rec) Propagation Delay TxD to

RxD from Dominant to

Recessive

Setup According to Figure 8 90 140 245 ns

tUV(VCC) Undervoltage Detection Time

on VCC

5.0 10 12.5 ms

tUV(VIO) Undervoltage Detection Time

on VIO

5.0 10 12.5 ms

tdom(TxD) TxD Dominant Timeout 300 600 1000 ms

th(min) Minimum Hold−Time for the

Go−to−Sleep Mode

15 35 50 ms

tdom Dominant Time for Wake−up

via the Bus

Vdif(CAN) > 1.4 V 0.75 2.5 5.0 ms

Vdif(CAN) > 1.2 V 0.75 3.0 5.8 ms

trec Recessive Time for Wake−up

via the Bus

VBAT = 12 V 0.75 2.5 5.0 ms

tWAKE Debounce Time for the

Wake−up via WAKE Pin

VBAT = 12 V 5.0 25 50 ms

terrdet Minimum dominant bit time for

bus error detection

NCV7341D20 version 1 2 4 ms

MEASUREMENT DEFINITIONS AND SETUPS

CANH

CANL

TxD

RxD

dominant

0.9V

0.5V

recessive

0.7 x VCC

Vi(dif) = VCANH − V

CANL

td(BUSon−RxD)

PC20060915.2

0.3 X V

tpd(dom−rec)

50%

recessive

50%

td(BUSoff−RxD)

td(TxD−BUSoff)

d(TxD−BUSon)

tpd(rec−dom)

Figure 6. Timing Diagram for AC Characteristics

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VRxD

Vi(dif)(hys)

High

Low

0.5 0.9

PC20040829.7

Hysteresis

Figure 7. Hysteresis of the Receiver

CANH

CANL

VSPLIT

PC20060921.6

RxD

TxD

GND

Vcc

VBAT

INH

Vio

+5V

WAKE

1kW

10 nF

100 nF

47 mF

NCV7341

ERR

STB

RLT CLT

+12V

60 W100 pF

Generator

15 pF

Figure 8. Test Circuit for Timing Characteristics

CANH

CANL

VSPLIT

PC20060921.5

1nF

NCV7341

RxD

TxD

GND

Vcc

VBAT

INH

Vio

+5V

WAKE

1kW

10 nF

100 nF

47 mF

15 pF

Transient

Generator

1nF

10 nF

ERR

STB

Figure 9. Test Circuit for Automotive Transients

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DEVICE ORDERING INFORMATION

Part Number Description Temperature Range Package Type Shipping†

NCV7341D20G HS CAN Transceiver

with bus error detection

−40°C − 125°C SOIC−14

(Pb−Free)

55 Tube / Tray

NCV7341D20R2G −40°C − 125°C SOIC−14

(Pb−Free)

3000 / Tape & Reel

NCV7341D21G HS CAN Transceiver −40°C − 125°C SOIC−14

(Pb−Free)

55 Tube / Tray

NCV7341D21R2G −40°C − 125°C SOIC−14

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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SOIC 14

CASE 751AP−01

ISSUE A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

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Phone: 81−3−5773−3850

NCV7341/D

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