GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 11
Normally – OFF Silicon Carbide
Junction Transistor
Features
Package
• 175 °C Maximum Operating Temperature
• Gate Oxide Free SiC Switch
• Exceptional Safe Operating Area
• Excellent Gain Linearity
• Temperature Independent Switching Performance
• Low Output Capacitance
• Positive Temperature Coefficient of RDS,ON
• Suitable for Connecting an Anti-parallel Diode
TO-247
Advantages
Applications
• Compatible with Si MOSFET/IGBT Gate Drive ICs
• > 20 µs Short-Circuit Withstand Capability
• Lowest-in-class Conduction Losses
• High Circuit Efficiency
• Minimal Input Signal Distortion
• High Amplifier Bandwidth
• Down Hole Oil Drilling, Geothermal Instrumentation
• Hybrid Electric Vehicles (HEV)
• Solar Inverters
• Switched-Mode Power Supply (SMPS)
• Power Factor Correction (PFC)
• Induction Heating
• Uninterruptible Power Supply (UPS)
•
Motor Drives
Table of Conte nts
Section I: Absolute Maximum Ratings .......................................................................................................... 1
Section II: Static Electrical Characteristics ................................................................................................... 2
Section III: D ynamic Electrical Char acteristics ............................................................................................ 2
Section IV: Figures .......................................................................................................................................... 3
Section V: Driving the GA50JT12-247 ........................................................................................................... 7
Section VI: Package Dimensions ................................................................................................................. 11
Section VII: SPICE Model Parameters ......................................................................................................... 12
Section I: Absolute Maximum Ratings
Parameter Symbol Conditions Value Unit Notes
Drain – Source Voltage
VDS
VGS = 0 V
V
Continuous Drain Current
ID
T
C
= 25°C
A
Fig. 17
Continuous Drain Current
ID
TC = 145°C
A
Fig. 17
Continuous Gate Current
IG
A
Turn-Off Safe Operating Area RBSOA TVJ = 175
o
C,
Clamped Inductive Load
D,max
A Fig. 19
Short Circuit Safe Operating Area SCSOA TVJ = 175
o
C, IG = 1 A, VDS = 80 0 V,
Non Repetitive
>20 µs
Reverse Gate – Source Voltage
VSG
V
Reverse Drain – Source Voltage
VSD
V
Power Dissipation Ptot TC = 25 °C / 145 °C, tp > 100 ms 583 / 116 W Fig. 16
Storage Temperature Tstg -55 to 175 °C
S
G
D
D
VDS = 1200 V
RDS(ON) = 20 mΩ
ID (Tc = 25°C) = 100 A
ID (Tc > 125°C) = 50 A
hFE (Tc = 25°C) = 85
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 11
Section II: Static Electrical Characteristics
A: On State
B: Off State
C: Thermal
Section III: Dynamic Electrical Characteristics
A: Capacitance and Gate Charge
B: Switching1
1 – All times are relative to the Drain-Source Voltage VDS
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Drain – Source On Resistance RDS(ON) ID = 50 A, Tj = 2 5 ° C
ID = 50 A, Tj = 150 °C
ID = 50 A, Tj = 175 °C
20
30
35
mΩ Fig. 5
Gate – Source Saturation Voltage VGS,SAT ID = 50 A, ID/IG = 40, Tj = 25 °C
ID = 50 A, ID/IG = 30, Tj = 175 °C
3.42
3.23
V Fig. 7
DC Current Gain hFE VDS = 8 V, ID = 50 A, Tj = 25 °C
VDS = 8 V, ID = 50 A, Tj = 125 °C
VDS = 8 V, ID = 50 A, Tj = 175 °C
85
57
51
– Fig. 4
Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, T j = 25 °C
VDS = 1200 V, VGS = 0 V, Tj = 150 °C
VDS = 1200 V, VGS = 0 V, Tj = 175 °C
10
20
20
μA Fig. 8
Gate Leakage Current
ISG
V
SG
= 20 V, T
j
= 25 °C
20
nA
Thermal resistance, junction - case RthJC
0.26
°C/W Fig. 20
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Input Capacitance
Ciss
VGS = 0 V, VDS = 800 V, f = 1 MHz
7080
pF
Fig. 9
Reverse Transfer/Output Capacitance
Crss/Coss
V
DS
= 800 V,
f
= 1 MHz
130
pF
Fig. 9
Output Capacitance Stored Energy
EOSS
VGS = 0 V, VDS = 800 V, f = 1 MHz
50
µJ
Fig. 10
Effective Output Capacitance,
time related
Coss,tr ID = constant, VGS = 0 V, V DS = 0…800 V 230 pF
Effective Output Capacitance,
energy related Coss,er VGS = 0 V, VDS = 0…800 V 160 pF
Gate-Source Charge
Q
GS
VGS = -5…3 V
60
nC
Gate-Drain Charge
QGD
V
GS
= 0 V, V
DS
= 0…800 V
185
nC
Gate Charge - Total
QG
245
nC
Internal Gate Resistance – ON
RG(INT-ON)
V
GS
> 2.5 V, V
DS
= 0 V, T
j
= 175 ºC
0.1
Ω
Turn On Delay Time
td(on)
Tj = 25 º C, VDS = 800 V,
ID = 50 A, Resistive Load
Refer to Section V for additional
driving information.
15
ns
Fall Time, V
DS
t
f
35
ns
Fig. 11, 13
Turn Off Delay Time
t
d(off)
35
ns
Rise Time, VDS
tr
20
ns
Fig. 12, 14
Turn On Delay Time
td(on)
Tj = 175 ºC, VDS = 800 V,
ID = 50 A, Resistive Load
15
ns
Fall Time, VDS
tf
35
ns
Fig. 11
Turn Off Delay Time
td(off)
40
ns
Rise Time, VDS tr 20 ns Fig. 12
Turn-On Energy Per Pulse
E
on
Tj = 25 º C, VDS = 800 V,
ID = 50 A, Inductive Load
Refer to Section V.
1070
µJ
Fig. 11, 13
Turn-Off Energy Per Pulse
Eoff
360
µJ
Fig. 12, 14
Total Switching Energy
Etot
1430
µJ
Turn-On Energy Per Pulse
Eon
Tj = 175 ºC, VDS = 800 V,
ID = 50 A, Inductive Load
1030
µJ
Fig. 11
Turn-Off Energy Per Pulse
Eoff
320
µJ
Fig. 12
Total Switching Energy
Etot
1350
µJ
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 11
Section IV: Figures
A: Static Characteristics
Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C
Figure 3: Typical Output Characteristics at 175 °C Figure 4: DC Curr ent Gain vs. Drain Current
Figure 5: On-Resistance vs. Gate Current Figure 6: Normalized On-Resistance vs. Tempe ratur e
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 11
Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics
B: Dynamic Cha racteristi cs
Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance
Figure 11: Typical Switching Times and T ur n On Energy
Losses vs. Temperature
Figure 12: Typical Switching Times and Turn O ff Energy
Losses vs. Temperature
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 11
Figure 13: Typical Switching Times and T ur n On Energy
Losses vs. Drain Current
Figure 14: Typical Switching Times and Turn O ff Energy
Losses vs. Drain Current
C: Current and Power Derating
Figure 15: Typical Hard Switched Device Power Loss vs.
Switching Fr eq uen cy
2
Figure 16: Power Derating Curve
Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias Safe Operating Area at Tc= 25 oC
2 – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 11
Figure 19: Turn-Off Safe Operating Area
Figure 20: Trans ient Thermal Impedance
Figure 21: Drain Current Derating vs. Pulse Width
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 11
Section V: Driving the GA50JT12-247
Drive Topology Gate Drive Power
Consumption Switching
Frequency Application Emphasis Availability
TTL Logic
High
Low
Wide Temperature Range
Coming Soon
Constant Current Medium Medium Wide Temperature Range Coming Soon
High Speed – Boost Capacitor
Medium
High
Fast Switching
Production
High Speed – Boost Inductor
Low
High
Ultra Fast Switching
Coming Soon
Proportional
Lowest
High
Wide Drain Current Range
Coming Soon
Pulsed Power Medium N/A Pulse Power Coming Soon
A: Static TTL Logic Driving
The GA50JT12-247 may be driven using direct (5 V) TTL logic after current ampli fication. The (ampl ifi ed) current level of the supply must meet
or exceed the steady state gate current (IG,steady) required to operat e the GA50JT12-247. The power level of the supply can be estimated from
the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC current
gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 4.
,
(,)1.5
Figure 22: TT L Gate Dr ive Schematic
B: High Speed Driving
The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate
current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 23 which features a positive
current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on.
Figure 23: An idealized gate current waveform for fast switching of an SJT.
An SJT is rapidly switched from its blocking state to on-state, when the nec essary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
 =, 1
  +
TTL
Gate Signal
5 / 0 V
TTL i/p
5 V
D
S
G
C
G
R
G
I
G,steady
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 11
Ideally, IG,on should terminate when the drain voltage falls to its on-state value i n order to avoid unnecessary drive l osses during the steady on-
state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the devic e package and drive circuit. A voltage
developed across the parasiti c inductance in the source path, Ls, can de-bias the gate-source juncti on, when high drain currents begi n to flow
through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter
these effects.
A high negative peak current, -IG,off is recommended at the s tart of the turn -off t ransi tion, i n order to r apidl y s weep out the injec ted carri ers from
the gate, and achieve rapid turn -off. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in
order to speed up the turn-off transition.
Two high-speed drive topologies for the SiC SJTs are presented below.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4
The GA50JT12-247 may be driven using a High Speed, Lo w Loss Drive with Boos t Capacitor topolog y in which multiple vol tage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. An evaluation gate drive board (GA15IDDJT22-FR4) utilizing this topology is commercially available for low-side driving, its
datasheet provides additional details.
Figure 24: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance3 of RG = 0.7 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation
of the GA50JT12-247. The steady state current supplied to the gate pin of the GA50JT12-247 with on-board RG = 0.7 Ω, is shown in
Figure 25. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 26.
For the GA50JT12-247, RG must be reduced for ID ≥ ~60 A for safe operation with the GA15IDDJT22-FR4.
For operation at ID ≥ ~60 A, RG ma y be calculated from the foll owing equati on, which contai ns the DC current gain hFE (Figu re 4) and the gate-
source saturation voltage VGS,sat (Figure 7).
, =4.7 ,  (,)
1.5 0.1
I
G
CG2
SJT
V
GH
D1
R5
R1 U4
V
GL
V
EE
V
GL
X2
V
GH
X1
V
EE
C2
C1
V
EE
U2
V
GL
V
EE
CG1
RG1
RG2
R2
C5
C21
C8
C9
C6
C7
+12 V
+12 V
VCC High
VCC High RTN
VCC Low
VCC Low RTN
Signal
Signal RTN
Gate
Source
Gate Driver Board
R3
R4
U1
U3
C4
V
GL
V
EE C10
R6
D
S
G
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 11
Figure 25: Typical steady state gate current supplied by the
GA15IDDJT22-FR4 board for the GA50JT12-247 with the on
board resistance of 0.7 Ω
Figure 26: Maximum gate resistance for safe operation of
the GA50JT12-247 at different drain currents using the
GA15IDDJT22-FR4 board.
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with Boos t Induct or i s al so c apable of driv ing the GA50JT12-247 at high-speed. It uti l i zes a gate drive i nductor
instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified IG,on
current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 27. After turn on,
while the device remains on the neces sary steady state gate c urrent IG,steady is supplied from source VCC through R G. Please refer to the artic le
“A current-sourc e concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this
driving topology.4
Figure 27: Simplified Inductive Pulsed Drive Topology
3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = 2.2 Ω, RG2 = 1.0 Ω
4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013
SiC SJT D
S
G
L
R
G
V
EE
V
CC
V
CC
V
EE
S
1
S
2
S
3
S
4
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 11
C: Proportional Gate Current Driving
For applications in which the GA50JT12-247 will operate over a wide range of drain current conditi ons, it may be beneficial to drive the device
using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain
current ID feedback to vary the steady state gate current IG,steady supplied to the GA50JT12-247
C:1: Voltage Controlled Proportional Driver
The voltage controlled proportional driver relies on a gate drive IC to detect the GA50JT12-247 drain-source voltage VDS during on-state to
sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power
consumption, to be reduced whi le ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connec ted between the
drain and sense protects the IC from high-vol tage when the driver and GA50JT12-247 are in off-state. A simplified version of this topology is
shown in Figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
Figure 28: Simplified Voltage Controlled Proportional Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional dri ver relies on a low-l oss transformer in t he drain or source path to provide feedback ID of the GA50JT12-
247 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain
which is set be the turns ratio of t he transfo rmer, hforce = ID / IG = N2 / N1. GA50JT12-247 is initially tuned-on using a gate c urrent puls e suppl ied
into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be
reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 29,
additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/.
Figure 29: Simplified Current Controlled Proportional Driver
SiC SJT
Proportional
Gate Current
Driver D
S
G
Gate Signal
I
G,steady
HV Diode
Sense
Signal Output
SiC SJT D
S
G
N
2
N
2
N
1
N
3
Gate Signal
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 11 of 11
Section VI: Package Dimensions
TO-247 PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSI O N IS INCH. DIMENSION IN BRACKET IS MILLIME TE R.
2. DIMENSIONS DO NOT INCLUDE END FLAS H, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes
2015/12/07 4 Updated Electrical Characteristics
2015/01/29 3 Updated Electrical Characteristics
2014/12/18 2 Updated Electrical Characteristics
2014/11/12 1 Updated Electrical Characteristics
2014/08/25 0 Initial release
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
(15.748)
(16.256)
0.620
0.640
Ø 0.140 (3.556)
0.143 (3.632)
0.065 (1.651)
0.083 (2.108)
0.040 (1.016)
0.055 (1.397) 0.2146 (5.451) BSC.
0.016 (0.406)
0.031 (0.787)
0.059 (1.498)
0.098 (2.489)
0.171 (4.699)
0.208 (5.283)
0.075 (1.905)
0.115 (2.921)
(4.318 REF.) 0.170 REF.
(5.486) 0.216
0.819
0.844
(20.803)
(21.438)
0.780
0.800
(19.812)
(20.320)
0.177
MAX
(4.496)
0.242 BSC.
(6.147 BSC.)
Ø 0.118 (3.00)
0.22
(5.59)
Ø 0.283 (7.19)
0.652
(16.56)
0.55 (13.97)
0.236
(5.99) 0.054
(1.36)
0.012
(0.3)
0.045
(1.14)
GA50JT12-247
XXXXXX
Lot code
GA50JT12-247
Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1
Section VII: SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/products_sic/sjt/GA50JT12-247_SPICE.pdf) into LTSPICE
(version 4) software for simulation of the GA50JT12-247.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 3.0 $
* $Date: 07-DEC-2015 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
*
* COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA50JT12 NPN
+ IS 9.833E-48
+ ISE 1.073E-26
+ EG 3.23
+ BF 89
+ BR 0.55
+ IKF 9000
+ NF 1
+ NE 2
+ RB 0.95
+ IRB 0.005
+ RBM 0.073
+ RE 0.004
+ RC 0.0125
+ CJC 2.124E-9
+ VJC 3.788
+ MJC 0.537
+ CJE 6.026E-09
+ VJE 3.1791
+ MJE 0.5295
+ XTI 3
+ XTB -1.5
+ TRC1 9.00E-3
+ VCEO 1200
+ ICRATING 50
+ MFG GeneSiC_Semiconductor
*
* End of GA50JT12 SPICE Model