Revised March 2000 DM74LS670 3-STATE 4-by-4 Register File General Description These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits writing into one location, and reading from another word location, simultaneously. Four data inputs are available to supply the word to be stored. Location of the word is determined by the write select inputs A and B, in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high level signal is desired from the output, a high level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are HIGH. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, GW, is HIGH, the data inputs are inhibited and their levels can cause no change in the information stored in the internal latches. When the read-enable input, GR, is HIGH, the data outputs are inhibited and go into the high impedance state. nates recovery times, permits simultaneous reading and writing, and is limited in speed only by the write time (27 ns typical) and the read time (24 ns typical). The register file has a non-volatile readout in that data is not lost when addressed. All inputs (except read enable and write enable) are buffered to lower the drive requirements to one normal Series DM74LS load, and input clamping diodes minimize switching transients to simplify system design. High speed, double ended AND-OR-INVERT gates are employed for the read-address function and have high sink current, 3-STATE outputs. Up to 128 of these outputs may be wire-AND connected for increasing the capacity up to 512 words. Any number of these registers may be paralleled to provide nbit word length. Features For use as: Scratch pad memory Buffer storage between processors Bit storage in fast multiplication designs The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. When the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. Separate read/write addressing permits simultaneous reading and writing This arrangement--data entry addressing separate from data read addressing and individual sense line -- elimi- Fast access times 20 ns typ Organized as 4 words of 4 bits Expandable to 512 words of n-bits 3-STATE versions of DM74LS170 Ordering Code: Order Number Package Number Package Description DM74LS670M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS670N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2000 Fairchild Semiconductor Corporation DS006436 www.fairchildsemi.com DM74LS670 3-STATE 4-by-4 Register File August 1986 DM74LS670 Connection Diagram Function Tables Write Table Read Table (Note 1)(Note 2) Write Inputs Word (Note 3) Read Inputs Outputs WB WA GW 0 1 2 3 RB RA GR Q1 Q2 Q3 Q4 L L L Q=D Q0 Q0 Q0 L L L WOB1 WOB2 WOB3 WOB4 L H L Q0 Q=D Q0 Q0 L H L W1B1 W1B2 W1B3 W1B4 H L L Q0 Q0 Q=D Q0 H L L W2B1 W2B2 W2B3 W2B4 H H L Q0 Q0 Q0 Q=D H H L W3B1 W3B2 W3B3 W3B4 X X H Q0 Q0 Q0 Q0 X X H Z Z Z Z H = HIGH Level L = LOW Level X = Don't Care Z = High Impedance (OFF) Note 1: (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. Note 2: Q0 = The level of Q before the indicated input conditions were established. Note 3: WOB1 = The first bit of word 0, etc. Logic Diagram www.fairchildsemi.com 2 Supply Voltage Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage 7V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current -2.6 mA IOL LOW Level Output Current 24 mA tW Write Enable Pulse Width (Note 5) 25 tSU Setup Time Data 10 (Note 5)(Note 6) WA , W B 15 Hold Time Data 15 (Note 5)(Note 6) WA , W B 5 tH 2 tLATCH Latch Time for New Data (Note 5)(Note 7) 25 TA Free Air Operating Temperature 0 V V ns ns ns ns 70 C Note 5: TA = 25C and VCC = 5V. Note 6: Times are with respect to the Write-Enable input. Write-Select time will protect the data written into the previous address. If protection of data in the previous address, tSETUP (WA, W B) can be ignored. As any address selection sustained for the final 30 ns of the Write-Enable pulse and during tH (WA, WB) will result in data being written into that location. Depending on the duration of the input conditions, one or a number of previous addresses may have been written into. Note 7: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to read from a location immediately after that location has received new data. 3 www.fairchildsemi.com DM74LS670 Absolute Maximum Ratings(Note 4) DM74LS670 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = -18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL II IIH IIL IOZH Min 2.4 Typ (Note 8) Units -1.5 V 3.4 V LOW Level VCC = Min, IOL = Max Output Voltage IOL = Max, VIH = Min Input Current @ Max VCC = Max D, R or W 0.1 Input Voltage VI = 7V GW 0.2 GR 0.3 0.34 0.5 HIGH Level VCC = Max D, R or W 20 Input Current VI = 2.7V GW 40 GR 60 LOW Level VCC = Max D, R or W -0.4 Input Current VI = 0.4V GW -0.8 GR -1.2 Off-State Output Current with VCC = Max, VO = 2.7V HIGH Level Output Voltage Applied VIH = Min, VIL = Max IOZL Max Off-State Output Current with VCC = Max, VO = 0.4V LOW Level Output Voltage Applied VIH = Min, VIL = Max IOS Short Circuit Output Current VCC = Max (Note 9) ICC Supply Current VCC = Max (Note 10) -20 30 V mA A mA 20 A -20 A -100 mA 50 mA Note 8: All typicals are at VCC = 5V, TA = 25C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: ICC is measured with 4.5V applied to all DATA inputs and both ENABLE inputs, all ADDRESS inputs are grounded and all outputs are OPEN. Switching Characteristics at VCC = 5V and TA = 25C RL = 667 Symbol Parameter CL = 45 pF From (Input) To (Output) tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPZH Output Enable Time to HIGH Level Output tPZL Output Enable Time to LOW Level Output tPHZ Output Disable Time from HIGH Level Output (Note 11) tPLZ Output Disable Time from LOW Level Output (Note 11) Min CL = 150 pF Min Units Max Read Select to Q 40 50 ns Read Select to Q 45 55 ns Write Enable to Q 45 55 ns Write Enable to Q 50 60 ns Data to Q 45 55 ns Data to Q 40 50 ns Read Enable to Any Q 35 45 ns Read Enable to Any Q 40 50 ns Read Enable to Any Q 50 ns Read Enable to Any Q 35 ns Note 11: CL = 5 pF. www.fairchildsemi.com Max 4 DM74LS670 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74LS670 3-STATE 4-by-4 Register File Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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