DM74LS670M - Fairchild Semiconductor

August 1986

Revised March 2000

DM74LS670 3-STATE 4-by-4 Register File

DM74LS670

3-STATE 4-by-4 Register File

General Descript ion

These register files are organized as 4 words of 4 bits

each, and separate on-chip decoding is provided for

addressing the four word locations to either write-in or

retrieve data. This permits writing into one location, and

reading from another word location, simultaneously.

Four data inputs are available to supply the word to be

stored. Location of the word is determined by the write

select inputs A and B, in conjunction with a write-enable

signal. Data applied at the inputs should be in its true form.

That is, if a high level signal is desired from the output, a

high leve l is applied at the data in put for that p articular bit

location. The latch inputs are arranged so that new data

will be accepted only if both internal address gate inputs

are HIGH. When this condition exists, data at the D input is

transferred to the latch output. When the write-enable

input, GW, is HIGH, the data inputs are inhibite d and their

levels can cause no change in the information stored in the

interna l l at ches . W h en the r ead-enab l e in pu t, GR, is HIGH,

the data outputs are inhibited and go into the high imped-

ance state.

The individual address lines permit direct acquisition of

data stored in any four of the latches. Four individual

decodin g gat es ar e use d to co mple te th e ad dre ss for rea d-

ing a word . When th e read addre ss is ma de in con juncti on

with the read-enable signal, the word appears at the four

outputs.

This arrangement—data entry addressing separate from

data read addressing and individual sense line — elimi-

nates recovery times, permits simultaneous reading and

writing, and is limited in speed only by the write time (27 ns

typical) and the r ead time (24 ns t ypical). The register file

has a non-volatile readout in that data is not lost when

addressed.

All inputs (except read enable and write enable) are buff-

ered to lower the dr ive req uirements to one normal Series

DM74L S load, and inpu t clamping diod es minimize switch-

ing transie nts to simplify system des ign. High spee d, dou-

ble ended AND-OR-INVERT gates are employed for the

read-address function and have high sink current, 3-ST ATE

outputs. U p to 1 28 o f th ese o utp uts may be wir e-AN D c on-

nected for increasing the capacity up to 512 words. Any

number o f these reg isters may be paralleled to provide n-

bit word length.

Features

■For use as:

Scratch pad memory

Buffer storage between processors

Bit storage in fast multiplication designs

■Separate read/write addressing permits simultaneous

reading and writing

■Organized as 4 words of 4 bits

■Expandable to 512 words of n-bits

■3-STATE versions of DM74LS170

■Fast access times 20 ns typ

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the orderin g c ode.

Order Number Package Number Package Description

DM74LS670M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDE C MS-012, 0.150 Narrow

DM74LS670N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2

DM74LS670

Connection Diagram

Function Tables

Write Table (Note 1)(Note 2) Read Table (Note 3)

H = HIGH Level L = LOW Lev el X = Don’t Care Z = High Impedance (OFF)

Note 1: (Q = D) = The four selected internal f lip-flop o ut puts will as s um e the sta te s applied to th e f our external data inputs.

Note 2: Q0 = The level of Q befo re t he indic at ed input co nditions were established.

Note 3: WOB1 = The first bit of word 0, etc.

Logic Diagram

Write Inputs Word

WBWAGW0123

LLLQ = DQ

0Q0Q0

LHL Q

0Q = DQ

0Q0

HLL Q

0Q0Q = DQ

HHL Q

0Q0Q0Q = D

XXH Q

0Q0Q0Q0

Read Inputs Outputs

RBRAGRQ1 Q2 Q3 Q4

L L L WOB1 WOB2 WOB3 WOB4

L H L W1B1 W1B2 W1B3 W1B4

H L L W2B1 W2B2 W2B3 W2B4

H H L W3B1 W3B2 W3B3 W3B4

XXHZZZZ

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DM74LS670

Absolute Maximum Ratings(Note 4) Note 4: The “A bsol ute M axim um Ratin gs” are those valu es b eyo nd which

the safety of the device cannot be guaranteed. The device should not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum ratings.

The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 5: TA = 25°C and VCC = 5V.

Note 6: Times are wit h resp ec t t o the Write-Enable inp ut . Write-Select time w ill prot ec t t he data w ritten into th e previous address. If p rotection of data in the

previou s address, t SETUP (WA, WB) can be ignored. As any ad dress selec t ion sust ained for t he final 30 ns of th e Wr it e-Enable pulse an d during tH (WA, WB)

will result in data being w ritten into th at loca tion. Dep endin g on the dur ation of the inpu t co nditi ons, on e or a nu mb er of previous addresses may h ave been

written in to .

Note 7: Latch time is the time allowed for the internal output of the latch to assume the state of new data. This is important only when attempting to r e ad fr om

a location immediately a fter that loc ation has rec eived new data.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltag e 0.8 V

IOH HIGH Level Output Current −2.6 mA

IOL LOW Level Output Current 24 mA

tWWrite Enable Pulse Width (Note 5) 25 ns

tSU Setup Time Data 10 ns

(Note 5)(Note 6) WA, WB15

tHHold Time Data 15 ns

(Note 5)(Note 6) WA, WB5

tLATCH Latch Time for New Data (Note 5)(Note 7) 25 ns

TAFree Air Operating Temperature 0 70 °C

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DM74LS670

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 8: All typic als are at VCC = 5V, TA = 25°C.

Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 10: ICC is measured with 4.5 V applied to all DATA inputs and bo th EN ABLE in puts, all ADDRESS inputs are grounded and all outputs are OPEN.

Switching Characteri stics

at VCC = 5V and TA = 25°C

Note 11: CL = 5 pF.

Symbol Parameter Conditions Min Typ Max Units

(Note 8)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.4 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.34 0.5 V

Output Voltage IOL = Max, VIH = Min

IIInput Current @ Max VCC = Max D, R or W 0.1

Input Voltage VI = 7V GW0.2 mA

GR0.3

IIH HIGH Level VCC = Max D, R or W 20

Input Current VI = 2.7V GW40 µA

GR60

IIL LOW Level VCC = Max D, R or W −0.4

Input Current VI = 0.4V GW−0.8 mA

GR−1.2

IOZH Off-State Output Current with VCC = Max, VO = 2.7V 20 µA

HIGH Level Output Voltage Applied VIH = Min, VIL = Max

IOZL Off-State Output Current with VCC = Max, VO = 0.4V −20 µA

LOW Level Output Voltage Applied VIH = Min, VIL = Max

IOS Short Circuit Output Current VCC = Max (Note 9) −20 −100 mA

ICC Supply Current VCC = Max (Note 10) 30 50 mA

RL = 667Ω

Symbol Parameter From (Input) CL = 45 pF CL = 150 pF Units

To (Ou tput) Min Max M i n Max

tPLH Propagation Delay Time Read Select to Q 40 50 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Read Select to Q 45 55 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Write Enable to Q 45 55 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Write Enable to Q 50 60 ns

HIGH-to-LOW Level Output

tPLH Propagation Delay Time Data to Q 45 55 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time Data to Q 40 50 ns

HIGH-to-LOW Level Output

tPZH Output Enable Time Read Enable to Any Q 35 45 ns

to HIGH Level Output

tPZL Output Enable Time Read Enable to Any Q 40 50 ns

to LOW Level Output

tPHZ Output Disable Time from Read Enable to Any Q 50 ns

HIGH Level Output (Note 11)

tPLZ Output Disable Time from Read Enable to Any Q 35 ns

LOW Level Output (Note 11)

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DM74LS670

Physical Dimensions in ches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

www.fairchildsemi.com 6

DM74LS670 3-STATE 4-by-4 Register File

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses are imp lied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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