TigerSHARC Embedded Processor ADSP-TS101S FEATURES BENEFITS 300 MHz, 3.3 ns instruction cycle rate 6M bits of internal--on-chip--SRAM memory 19 mm x 19 mm (484-ball) or 27 mm x 27 mm (625-ball) PBGA package Dual computation blocks--each containing an ALU, a multiplier, a shifter, and a register file Dual integer ALUs, providing data addressing and pointer manipulation Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin for system integration 1149.1 IEEE compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2) Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture Enables scalable multiprocessing systems with low communications overhead COMPUTATIONAL BLOCKS SHIFTER PROGRAM SEQUENCER PC IAB ALU BTB INTERNAL MEMORY DATA ADDRESS GENERATION IRQ INTEGER J ALU ADDR FETCH 32 32 32 x 32 INTEGER K ALU 32 x 32 MEMORY M0 64K x 32 A D MEMORY M1 64K x 32 A D 6 JTAG PORT MEMORY M2 64K x 32 A SDRAM CONTROLLER D MULTIPLIER X REGISTER FILE 32 x 32 128 32 M0 ADDR 128 M0 DATA EXTERNAL PORT MULTIPROCESSOR INTERFACE 32 HOST INTERFACE 32 M1 ADDR 128 M1 DATA 128 ADDR INPUT FIFO 64 DAB OUTPUT BUFFER DAB 32 M2 ADDR 128 M2 DATA DATA OUTPUT FIFO 128 128 Y REGISTER FILE 32 x 32 I/O ADDRESS 32 CNTRL CLUSTER BUS ARBITER I/O PROCESSOR 3 DMA CONTROLLER L0 LINK PORT CONTROLLER MULTIPLIER L1 DMA ADDRESS 32 256 DMA DATA ALU SHIFTER 8 3 CONTROL/ STATUS/ TCBs 256 LINK PORTS LINK DATA CONTROL/ STATUS/ BUFFERS 8 3 8 L2 3 L3 8 Figure 1. Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2009 Analog Devices, Inc. All rights reserved. ADSP-TS101S TABLE OF CONTENTS Benefits ................................................................. 1 Designing an Emulator-Compatible DSP Board (Target) .......................................... 11 Table of Contents ..................................................... 2 Additional Information ........................................ 11 Revision History ...................................................... 2 Pin Function Descriptions ........................................ 12 General Description ................................................. 3 Pin States at Reset ................................................ 12 Dual Compute Blocks ............................................ 4 Pin Definitions ................................................... 12 Data Alignment Buffer (DAB) .................................. 4 Strap Pin Function Descriptions ................................ 19 Dual Integer ALUs (IALUs) .................................... 4 Specifications ........................................................ 20 Program Sequencer ............................................... 5 Operating Conditions ........................................... 20 On-Chip SRAM Memory ........................................ 5 Electrical Characteristics ....................................... 20 External Port (Off-Chip Memory/Peripherals Interface) ................ 6 Absolute Maximum Ratings ................................... 21 DMA Controller ................................................... 7 Package Information ............................................ 21 Link Ports ........................................................... 9 Timing Specifications ........................................... 21 Timer and General-Purpose I/O ............................... 9 Output Drive Currents ......................................... 32 Reset and Booting ................................................. 9 Test Conditions .................................................. 34 Features ................................................................. 1 ESD Caution ...................................................... 21 Low Power Operation ............................................ 9 Environmental Conditions .................................... 36 Clock Domains .................................................... 9 PBGA Pin Configurations ........................................ 37 Output Pin Drive Strength Control ......................... 10 Outline Dimensions ................................................ 43 Power Supplies ................................................... 10 Surface-Mount Design ............................................. 44 Filtering Reference Voltage and Clocks .................... 10 Ordering Guide ..................................................... 45 Development Tools ............................................. 10 REVISION HISTORY 5/09--Rev. B to Rev. C Added parameter value (IDD_A max) in Operating Conditions ............................................. 20 Updated footnotes in 484-Ball PBGA (B-484) ............... 43 Updated footnotes in 625-Ball PBGA (B-625) ............... 44 Added surface-mount design info in Surface-Mount Design ......................................... 44 Updated models in Ordering Guide ............................ 45 Rev. C | Page 2 of 48 | May 2009 ADSP-TS101S GENERAL DESCRIPTION The ADSP-TS101S TigerSHARC(R) processor is an ultrahigh performance, Static SuperscalarTM processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks--supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing--to set a new standard of performance for digital signal processors. The TigerSHARC processor's Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations. 2 This value is for six iterations of the algorithm. For eight iterations of the turbo decoder, this benchmark is 67 MIPS. 3 Adaptive multi rate (AMR) 4 Megachips per second (Mcps) The ADSP-TS101S is code compatible with the other TigerSHARC processors. The Functional Block Diagram on Page 1 shows the processor's architectural blocks. These blocks include: * Dual compute blocks, each consisting of an ALU, multiplier, 64-bit shifter, and 32-word register file and associated data alignment buffers (DABs) Three independent 128-bit-wide internal data buses, each connecting to one of the three 2M bit memory banks, enable quad word data, instruction, and I/O accesses and provide 14.4G bytes per second of internal memory bandwidth. Operating at 300 MHz, the ADSP-TS101S processor's core has a 3.3 ns instruction cycle time. Using its single-instruction, multipledata (SIMD) features, the ADSP-TS101S can perform 2.4 billion 40-bit MACs or 600 million 80-bit MACs per second. Table 1 and Table 2 show the DSP's performance benchmarks. * Dual integer ALUs (IALUs), each with its own 31-word register file for data addressing * A program sequencer with instruction alignment buffer (IAB), branch target buffer (BTB), and interrupt controller * Three 128-bit internal data buses, each connecting to one of three 2M bit memory banks * On-chip SRAM (6M bit) * An external port that provides the interface to host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, and external SRAM and SDRAM Table 1. General-Purpose Algorithm Benchmarks at 300 MHz Clock Benchmark Speed Cycles 32-bit algorithm, 600 million MACs/s peak performance 1024 point complex FFT (Radix 2) 32.78 s 9,835 50-tap FIR on 1024 input 91.67 s 27,500 Single FIR MAC 1.83 ns 0.55 16-bit algorithm, 2.4 billion MACs/s peak performance 256 point complex FFT (Radix 2) 3.67 s 1,100 50-tap FIR on 1024 input 24.0 s 7,200 Single FIR MAC 0.47 ns 0.14 Single complex FIR MAC 1.9 ns 0.57 I/O DMA transfer rate External port 800M bytes/s n/a Link ports (each) 250M bytes/s n/a Table 2. 3G Wireless Algorithm Benchmarks Benchmark Turbo decode 384 kbps data channel Viterbi decode 12.2 kbps AMR3 voice channel Complex correlation 3.84 Mcps4 with a spreading factor of 256 1 The execution speed is in instruction cycles per second. Static Superscalar is a trademark of Analog Devices, Inc. Execution (MIPS)1 51 MIPS2 0.86 MIPS 0.27 MIPS Rev. C | * A 14-channel DMA controller * Four link ports * Two 64-bit interval timers and timer expired pin * A 1149.1 IEEE compliant JTAG test access port for on-chip emulation Figure 2 shows a typical single-processor system with external SDRAM. Figure 4 on Page 8 shows a typical multiprocessor system. The TigerSHARC processor uses a Static Superscalar architecture. This architecture is superscalar in that the ADSP-TS101S processor's core can execute simultaneously from one to four 32-bit instructions encoded in a very large instruction word (VLIW) instruction line using the DSP's dual compute blocks. Because the DSP does not perform instruction reordering at runtime--the programmer selects which operations will execute in parallel prior to runtime--the order of instructions is static. With few exceptions, an instruction line, whether it contains one, two, three, or four 32-bit instructions, executes with a throughput of one cycle in an eight-deep processor pipeline. For optimal DSP program execution, programmers must follow the DSP's set of instruction parallelism rules when encoding an instruction line. In general, the selection of instructions that the DSP can execute in parallel each cycle depends on the instruction line resources each instruction requires and on the source and destination registers used in the instructions. The programmer has direct control of three core components--the IALUs, the compute blocks, and the program sequencer. Page 3 of 48 | May 2009 ADSP-TS101S * Register file--each compute block has a multiported 32-word, fully orthogonal register file used for transferring data between the computation units and data buses and for storing intermediate results. Instructions can access the registers in the register file individually (word aligned), or in sets of two (dual aligned) or four (quad aligned). The ADSP-TS101S, in most cases, has a two-cycle arithmetic execution pipeline that is fully interlocked, so whenever a computation result is unavailable for another operation dependent on it, the DSP automatically inserts one or more stall cycles as needed. Efficient programming with dependency-free instructions can eliminate most computational and memory transfer data dependencies. BOOT EPROM (OPTIONAL) ADSP-TS101S LCLK_P CLK CS ADDR RAS DATA CAS DQM SCLK_P S/LCLK_N VREF BRST LCLKRAT2-0 SCLKFREQ ADDR31-0 ADDR IRQ3-0 DATA RAS * Accelerator--128-bit unit for trellis decoding (for example, Viterbi and turbo decoders) and complex correlations for communication applications. OE RD WE ACK WRH/WRL ACK MS1-0 CS Using these features, the compute blocks can: LDQM HDQM SDWE SDCKE A10 SDA10 FLYBY MSH HOST PROCESSOR INTERFACE (OPTIONAL) HBR HBG IOEN LXDAT7-0 LXCLKIN LXCLKOUT * Shifter--the 64-bit shifter performs logical and arithmetic shifts, bit and bit stream manipulation, and field deposit and extraction operations. MEMORY (OPTIONAL) CAS WE CKE LINK DEVICES (4 MAX) (OPTIONAL) DATA DATA63-0 FLAG3-0 ID2-0 MSSD ADDR BR7-0 ADDR CPA DATA * Provide 8 MACs per cycle peak and 7.1 MACs per cycle sustained 16-bit performance and provide 2 MACs per cycle peak and 1.8 MACs per cycle sustained 32-bit performance (based on FIR) * Execute six single-precision, floating-point or execute 24 fixed-point (16-bit) operations per cycle, providing 1,800 MFLOPS or 7.3 GOPS performance DPA BOFF DMAR3-0 DMA DEVICE (OPTIONAL) DATA * Perform two complex 16-bit MACs per cycle LXDIR TMR0E BM BUSLOCK CONTROLIMP2-0 DS2-0 RESET JTAG * Execute eight trellis butterflies in one cycle DATA ALIGNMENT BUFFER (DAB) DATA SDRAM MEMORY (OPTIONAL) * Multiplier--the multiplier performs both fixed- and floating-point multiplication and fixed-point multiply and accumulate. CS ADDRESS REFERENCE BMS CONTROL CLOCK * ALU--the ALU performs a standard set of arithmetic operations in both fixed- and floating-point formats. It also performs logic operations. The DAB is a quad word FIFO that enables loading of quad word data from nonaligned addresses. Normally, load instructions must be aligned to their data size so that quad words are loaded from a quad-aligned address. Using the DAB significantly improves the efficiency of some applications, such as FIR filters. Figure 2. Single-Processor System with External SDRAM In addition, the ADSP-TS101S supports SIMD operations two ways--SIMD compute blocks and SIMD computations. The programmer can direct both compute blocks to operate on the same data (broadcast distribution) or on different data (merged distribution). In addition, each compute block can execute four 16-bit or eight 8-bit SIMD computations in parallel. DUAL INTEGER ALUS (IALUS) The ADSP-TS101S has two IALUs that provide powerful address generation capabilities and perform many general-purpose integer operations. Each of the IALUs: * Provides memory addresses for data and update pointers DUAL COMPUTE BLOCKS * Supports circular buffering and bit-reverse addressing The ADSP-TS101S has compute blocks that can execute computations either independently or together as a SIMD engine. The DSP can issue up to two compute instructions per compute block each cycle, instructing the ALU, multiplier, or shifter to perform independent, simultaneous operations. * Performs general-purpose integer operations, increasing programming flexibility The compute blocks are referred to as X and Y in assembly syntax, and each block contains three computational units--an ALU, a multiplier, a 64-bit shifter, and a 32-word register file. Rev. C | * Includes a 31-word register file for each IALU As address generators, the IALUs perform immediate or indirect (pre- and post-modify) addressing. They perform modulus and bit-reverse operations with no constraints placed on memory addresses for the modulus data buffer placement. Each IALU can specify either a single, dual, or quad word access from memory. Page 4 of 48 | May 2009 ADSP-TS101S The IALUs have hardware support for circular buffers, bit reverse, and zero-overhead looping. Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing, and they are commonly used in digital filters and Fourier transforms. Each IALU provides registers for four circular buffers, so applications can set up a total of eight circular buffers. The IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 128-bit instruction line, which can contain up to four 32-bit instructions, accommodates a variety of parallel operations for concise programming. For example, one instruction line can direct the DSP to conditionally execute a multiply, an add, and a subtract in both computation blocks while it also branches to another location in the program. Some key features of the instruction set include: * Enhanced instructions for communications infrastructure to govern trellis decoding (for example, Viterbi and turbo decoders) and despreading via complex correlations Because the IALU's computational pipeline is one cycle deep, in most cases, integer results are available in the next cycle. Hardware (register dependency check) causes a stall if a result is unavailable in a given cycle. * Algebraic assembly language syntax * Direct support for all DSP, imaging, and video arithmetic types, eliminating hardware modes PROGRAM SEQUENCER * Branch prediction encoded in instruction, enables zerooverhead loops The ADSP-TS101S processor's program sequencer supports: * A fully interruptible programming model with flexible programming in assembly and C/C++ languages; handles hardware interrupts with high throughput and no aborted instruction cycles. * Parallelism encoded in instruction line * Conditional execution optional for all instructions * User-defined, programmable partitioning between program and data memory * An eight-cycle instruction pipeline--three-cycle fetch pipe and five-cycle execution pipe--with computation results available two cycles after operands are available. ON-CHIP SRAM MEMORY * The supply of instruction fetch memory addresses; the sequencer's instruction alignment buffer (IAB) caches up to five fetched instruction lines waiting to execute; the program sequencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution. The ADSP-TS101S has 6M bits of on-chip SRAM memory, divided into three blocks of 2M bits (64K words 32 bits). Each block--M0, M1, and M2--can store program, data, or both, so applications can configure memory to suit specific needs. Placing program instructions and data in different memory blocks, however, enables the DSP to access data while performing an instruction fetch. * The management of program structures and determination of program flow according to JUMP, CALL, RTI, RTS instructions, loop structures, conditions, interrupts, and software exceptions. * Branch prediction and a 128-entry branch target buffer (BTB) to reduce branch delays for efficient execution of conditional and unconditional branch instructions and zero-overhead looping; correctly predicted branches that are taken occur with zero-to-two overhead cycles, overcoming the three-to-six stage branch penalty. * Compact code without the requirement to align code in memory; the IAB handles alignment. Interrupt Controller The DSP supports nested and non-nested interrupts. Each interrupt type has a register in the interrupt vector table. Also, each has a bit in both the interrupt latch register and the interrupt mask register. All interrupts are fixed as either level sensitive or edge sensitive, except the IRQ3-0 hardware interrupts, which are programmable. The DSP's internal and external memory (Figure 3) is organized into a unified memory map, which defines the location (address) of all elements in the system. The memory map is divided into four memory areas--host space, external memory, multiprocessor space, and internal memory--and each memory space, except host memory, is subdivided into smaller memory spaces. Each internal memory block connects to one of the 128-bitwide internal buses--block M0 to bus MD0, block M1 to bus MD1, and block M2 to bus MD2--enabling the DSP to perform three memory transfers in the same cycle. The DSP's internal bus architecture provides a total memory bandwidth of 14.4G bytes per second, enabling the core and I/O to access eight 32-bit data words (256 bits) and four 32-bit instructions each cycle. The DSP's flexible memory structure enables: The DSP distinguishes between hardware interrupts and software exceptions, handling them differently. When a software exception occurs, the DSP aborts all other instructions in the instruction pipe. When a hardware interrupt occurs, the DSP continues to execute instructions already in the instruction pipe. Rev. C | Page 5 of 48 | * DSP core and I/O access of different memory blocks in the same cycle * DSP core access of all three memory blocks in parallel-- one instruction and two data accesses * Programmable partitioning of program and data memory * Program access of all memory as 32-, 64-, or 128-bit words--16-bit words with the DAB * Complete context switch in less than 20 cycles (66 ns) May 2009 ADSP-TS101S GLOBAL SPACE 0xFFFFFFFF HOST (MSH) INTERNAL SPACE 0x10000000 0x003FFFFF EXTERNAL MEMORY SPACE 0x00300000 RESERVED BANK 1 (MS1) 0x00280000 0x0C000000 BANK 0 (MS0) 0x08000000 SDRAM (MSSD) 0x04000000 0x00200000 MULTIPROCESSOR MEMORY SPACE PROCESSOR ID 7 0x001807FF INTERNAL REGISTERS (UREGS) 0x00180000 RESERVED 0x0010FFFF INTERNAL MEMORY 2 0x00100000 RESERVED 0x03C00000 PROCESSOR ID 6 0x03800000 PROCESSOR ID 5 0x03400000 PROCESSOR ID 4 0x03000000 PROCESSOR ID 3 0x02C00000 EACH IS A COPY OF INTERNAL SPACE PROCESSOR ID 2 0x02800000 PROCESSOR ID 1 0x02400000 PROCESSOR ID 0 0x02000000 BROADCAST 0x01C00000 0x0008FFFF INTERNAL MEMORY 1 0x00080000 RESERVED RESERVED 0x003FFFFF 0x0000FFFF INTERNAL MEMORY 0 INTERNAL MEMORY 0x00000000 0x00000000 Figure 3. Memory Map EXTERNAL PORT (OFF-CHIP MEMORY/PERIPHERALS INTERFACE) The ADSP-TS101S processor's external port provides the processor's interface to off-chip memory and peripherals. The 4G word address space is included in the DSP's unified address space. The separate on-chip buses--three 128-bit data buses and three 32-bit address buses--are multiplexed at the external port to create an external system bus with a single 64-bit data bus and a single 32-bit address bus. The external port supports data transfer rates of 800M bytes per second over external bus. The external bus can be configured for 32- or 64-bit operation. When the system bus is configured for 64-bit operation, the lower 32 bits of the external data bus connect to even addresses, and the upper 32 bits connect to odd addresses. Rev. C | The external port supports pipelined, slow, and SDRAM protocols. Addressing of external memory devices and memorymapped peripherals is facilitated by on-chip decoding of highorder address lines to generate memory bank select signals. The ADSP-TS101S provides programmable memory, pipeline depth, and idle cycle for synchronous accesses, and external acknowledge controls to support interfacing to pipelined or slow devices, host processors, and other memory-mapped peripherals with variable access, hold, and disable time requirements. Page 6 of 48 | May 2009 ADSP-TS101S Host Interface The ADSP-TS101S provides an easy and configurable interface between its external bus and host processors through the external port. To accommodate a variety of host processors, the host interface supports pipelined or slow protocols for accesses of the host as slave. Each protocol has programmable transmission parameters, such as idle cycles, pipe depth, and internal wait cycles. The host interface supports burst transactions initiated by a host processor. After the host issues the starting address of the burst and asserts the BRST signal, the DSP increments the address internally while the host continues to assert BRST. The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the DSP. The BOFF signal provides the deadlock recovery mechanism. When the host asserts BOFF, the DSP backs off the current transaction and asserts HBG and relinquishes the external bus. The host can directly read or write the internal memory of the ADSP-TS101S, and it can access most of the DSP registers, including DMA control (TCB) registers. Vector interrupts support efficient execution of host commands. Multiprocessor Interface The ADSP-TS101S offers powerful features tailored to multiprocessing DSP systems through the external port and link ports. This multiprocessing capability provides highest bandwidth for interprocessor communication, including: The SDRAM interface provides a glueless interface with standard SDRAMs--16M bit, 64M bit, 128M bit, and 256M bit. The DSP directly supports a maximum of 64M words 32 bits of SDRAM. The SDRAM interface is mapped in external memory in the DSP's unified memory map. EPROM Interface The ADSP-TS101S can be configured to boot from external 8-bit EPROM at reset through the external port. An automatic process (which follows reset) loads a program from the EPROM into internal memory. This process uses 16 wait cycles for each read access. During booting, the BMS pin functions as the EPROM chip select signal. The EPROM boot procedure uses DMA Channel 0, which packs the bytes into 32-bit instructions. Applications can also access the EPROM (write flash memories) during normal operation through DMA. The EPROM or flash memory interface is not mapped in the DSP's unified memory map. It is a byte address space limited to a maximum of 16M bytes (24 address bits). The EPROM or flash memory interface can be used after boot via a DMA. DMA CONTROLLER The ADSP-TS101S processor's on-chip DMA controller, with 14 DMA channels, provides zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the DSP's core, enabling DMA operations to occur while the DSP's core continues to execute program instructions. The DMA controller performs DMA transfers between: * Internal memory and external memory and memorymapped peripherals * Up to eight DSPs on a common bus * On-chip arbitration for glueless multiprocessing * Internal memory of other DSPs on a common bus, a host processor, or link port I/O * Link ports for point-to-point communication The external port and link ports provide integrated, glueless multiprocessing support. * External memory and external peripherals or link port I/O The external port supports a unified address space (see Figure 3) that enables direct interprocessor accesses of each ADSP-TS101S processor's internal memory and registers. The DSP's on-chip distributed bus arbitration logic provides simple, glueless connection for systems containing up to eight ADSPTS101S processors and a host processor. Bus arbitration has a rotating priority. Bus lock supports indivisible read-modifywrite sequences for semaphores. A bus fairness feature prevents one DSP from holding the external bus too long. * External bus master and internal memory or link port I/O The DMA controller provides a number of additional features. The DMA controller supports flyby transfers. Flyby operations only occur through the external port (DMA Channel 0) and do not involve the DSP's core. The DMA controller acts as a conduit to transfer data from one external device to another through external memory. During a transaction, the DSP: * Relinquishes the external data bus * Outputs addresses, memory selects (MS1-0, MSSD, RAS, CAS, and SDWE) and the FLYBY, IOEN, and RD/WR strobes The DSP's four link ports provide a second path for interprocessor communications with throughput of 1G bytes per second. The cluster bus provides 800M bytes per second throughput-- with a total of 1.8G bytes per second interprocessor bandwidth. SDRAM Controller The SDRAM controller controls the ADSP-TS101S processor's transfers of data to and from synchronous DRAM (SDRAM). The throughput is 32 or 64 bits per SCLK cycle using the external port and SDRAM control pins. Rev. C | * Responds to ACK DMA chaining is also supported by the DMA controller. DMA chaining operations enable applications to automatically link one DMA transfer sequence to another for continuous transmission. The sequences can occur over different DMA channels and have different transmission attributes. Page 7 of 48 | May 2009 ADSP-TS101S CONTROL ADDRESS DATA ADDRESS DATA ADSP-TS101 #7 ADSP-TS101 #6 ADSP-TS101 #5 ADSP-TS101 #4 ADSP-TS101 #3 ADSP-TS101 #2 CONTROL The DMA controller also supports two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify registers for both the X and Y dimensions. ADSP-TS101 #1 001 BR7-2,0 BR1 ID2-0 RESET ADDR31-0 CLKS/REFS DATA63-0 LINK CONTROL ADSP-TS101 #0 000 BR7-1 BR0 ID2-0 RESET RESET ADDR31-0 ADDR CLKS/REFS DATA63-0 DATA RD SCLK_P CLOCK LCLK_P REFERENCE VOLTAGE ACK CS CS ADDR CPA S/LCLK_N DPA BOFF DMAR3-0 BRST VREF LCLKRAT2-0 SCLKFREQ IRQ3-0 HBR FLAG3-0 HBG MSH LINK LINK DEVICES (4 MAX) (OPTIONAL) OE WE WRH/L ACK MS1-0 BUSLOCK BMS LXDAT7-0 LXCLKIN DATA FLYBY ADDR IOEN DATA CS RAS CAS RAS CAS TMR0E LDQM HDQM SDWE BM SDCKE WE CKE SDA10 A10 CONTROLIMP2-0 HOST PROCESSOR INTERFACE (OPTIONAL) SDRAM MEMORY (OPTIONAL) DQM ADDR CONTROL DS2-0 BOOT EPROM (OPTIONAL) CLOCK MSSD LXCLKOUT LXDIR GLOBAL MEMORY AND PERIPHERALS (OPTIONAL) DATA CLK Figure 4. Shared Memory Multiprocessing System The DMA controller performs the following DMA operations: * External port block transfers. Four dedicated bidirectional DMA channels transfer blocks of data between the DSP's internal memory and any external memory or memorymapped peripheral on the external bus. These transfers support master mode and handshake mode protocols. * Link port transfers. Eight dedicated DMA channels (four transmit and four receive) transfer quad word data only between link ports and between a link port and internal or Rev. C | Page 8 of 48 | external memory. These transfers only use handshake mode protocol. DMA priority rotates between the four receive channels. * AutoDMA transfers. Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I/O. These transfers only use slave mode protocol, and an external bus master must initiate the transfer. May 2009 ADSP-TS101S LINK PORTS The DSP's four link ports provide additional 8-bit bidirectional I/O capability. With the ability to operate at a double data rate-- latching data on both the rising and falling edges of the clock-- running at 125 MHz, each link port can support up to 250M bytes per second, for a combined maximum throughput of 1G bytes per second. After reset, the ADSP-TS101S has four boot options for beginning operation: * Boot from EPROM. The DSP defaults to EPROM booting when the BMS pin strap option is set low. See Strap Pin Function Descriptions on Page 19. * Boot by an external master (host or another ADSPTS101S). Any master on the cluster bus can boot the ADSP-TS101S through writes to its internal memory or through autoDMA. The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing pointto-point interprocessor communications. Applications can also use the link ports for booting. * Boot by link port. All four receive link DMA channels are initialized after reset to transfer a 256-word block to internal memory address 0 to 255, and to issue an interrupt at the end of the block (similar to EP DMA). The corresponding DMA interrupts are set to address zero (0). Each link port has its own double-buffered input and output registers. The DSP's core can write directly to a link port's transmit register and read from a receive register, or the DMA controller can perform DMA transfers through eight (four transmit and four receive) dedicated link port DMA channels. Each link port has three signals that control its operation. LxCLKOUT and LxCLKIN implement clock/acknowledge handshaking. LxDIR indicates the direction of transfer and is used only when buffering the LxDAT signals. An example application would be using differential low-swing buffers for long twisted-pair wires. LxDAT provides the 8-bit data bus input/output. Applications can program separate error detection mechanisms for transmit and receive operations (applications can use the checksum mechanism to implement consecutive link port transfers), the size of data packets, and the speed at which bytes are transmitted. * No boot--Start running from an external memory. Using the "no boot" option, the ADSP-TS101S must start running from an external memory, caused by asserting one of the IRQ3-0 interrupt signals. The ADSP-TS101S core always exits from reset in the idle state and waits for an interrupt. Some of the interrupts in the interrupt vector table are initialized and enabled after reset. LOW POWER OPERATION Under certain conditions, the link port receiver can initiate a token switch to reverse the direction of transfer; the transmitter becomes the receiver and vice versa. The ADSP-TS101S can enter a low power sleep mode in which its core does not execute instructions, reducing power consumption to a minimum. The ADSP-TS101S exits sleep mode when it senses a falling edge on any of its IRQ3-0 interrupt inputs. The interrupt, if enabled, causes the ADSP-TS101S to execute the corresponding interrupt service routine. This feature is useful for systems that require a low power standby mode. TIMER AND GENERAL-PURPOSE I/O CLOCK DOMAINS The ADSP-TS101S has a timer pin (TMR0E) that generates output when a programmed timer counter has expired. Also, the DSP has four programmable general-purpose I/O pins (FLAG3-0) that can function as either single-bit input or output. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching. As shown in Figure 5, the ADSP-TS101S has two clock inputs, SCLK (system clock) and LCLK (local clock). RESET AND BOOTING SCLK_P DLL DLL EXTERNAL INTERFACE LCLK_P PLL DLL CCLK (INSTRUCTION RATE) LCLKRATx The ADSP-TS101S has two levels of reset (see reset specifications Page 24): /LR DLL LxCLKOUT/LxCLKIN (LINK PORT RATE) SPD BITS, LCTLx REGISTER * Power-up reset--after power-up of the system, and strap options are stable, the RESET pin must be asserted (low). Figure 5. Clock Domains * Normal reset--for any resets following the power-up reset sequence, the RESET pin must be asserted. These inputs drive its two major clock domains: The DSP can be reset internally (core reset) by setting the SWRST bit in SQCTL. The core is reset, but not the external port or I/O. * SCLK (system clock). Provides clock input for the external bus interface and defines the ac specification reference for the external bus signals. The external bus interface runs at 1 the SCLK frequency. A DLL locks internal SCLK to SCLK input. * LCLK (local clock). Provides clock input to the internal clock driver, CCLK, which is the internal clock for the core, internal buses, memory, and link ports. The instruction execution rate is equal to CCLK. A PLL from LCLK gener- Rev. C | Page 9 of 48 | May 2009 ADSP-TS101S ates CCLK, which is phase-locked. The LCLKRAT pins define the clock multiplication of LCLK to CCLK (see Table 4). The link port clock is generated from CCLK via a software programmable divisor. RESET must be asserted until LCLK is stable and within specification for at least 2 ms. This applies to power-up as well as any dynamic modification of LCLK after power-up. Dynamic modification may include LCLK going out of specification as long as RESET is asserted. FILTERING REFERENCE VOLTAGE AND CLOCKS Figure 6 shows a possible circuit for filtering VREF, SCLK_N, and LCLK_N. This circuit provides the reference voltage for the switching voltage, system clock, and local clock references. VDD_IO VREF SCLK_N R1 Connecting SCLK and LCLK to the same clock source is a requirement for the device. Using an integer clock multiplication value provides predictable cycle-by-cycle operation, a requirement of fault-tolerant systems and some multiprocessing systems. LCLK_N R2 C1 C2 VSS R1: 2k SERIES RESISTOR R2: 1.67k SERIES RESISTOR C1: 1F CAPACITOR (SMD) C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP'S PINS Noninteger values are completely functional and acceptable for applications that do not require predictable cycle-by-cycle operation. Figure 6. VREF, SCLK_N, and LCLK_N Filter OUTPUT PIN DRIVE STRENGTH CONTROL Pins CONTROLIMP2-0 and DS2-0 work together to control the output drive strength of two groups of pins, the Address/Data/Control pin group and the Link pin group. CONTROLIMP2-0 independently configures the two pin groups to the maximum drive strength or to a digitally controlled drive strength that is selectable by the DS2-0 pins (see Table 13 on Page 18). If the digitally controlled drive strength is selected for a pin group, the DS2-0 pins determine one of eight strength levels for that group (see Table 14 on Page 18). The drive strength selected varies the slew rate of the driver. Drive strength 0 (DS2-0 = 000) is the weakest and slowest slew rate. Drive strength 7 (DS2-0 = 111) is the strongest and fastest slew rate. The stronger drive strengths are useful for high frequency switching while the lower strengths may allow use of a relaxed design methodology. The strongest drive strengths have a larger di/dt and thus require more attention to signal integrity issues such a ringing, reflections and coupling. Also, a larger di/dt can increase external supply rail noise, which impacts power supply and power distribution design. The drive strengths for the EMU, CPA, and DPA pins are not controllable and are fixed to the maximum level. For drive strength calculation, see Output Drive Currents on Page 32. POWER SUPPLIES The ADSP-TS101S has separate power supply connections for internal logic (VDD), analog circuits (VDD_A), and I/O buffer (VDD_IO) power supply. The internal (VDD) and analog (VDD_A) supplies must meet the 1.2 V requirement. The I/O buffer (VDD_IO) supply must meet the 3.3 V requirement. The analog supply (VDD_A) powers the clock generator PLLs. To produce a stable clock, systems must provide a clean power supply to power input VDD_A. Designs must pay critical attention to bypassing the VDD_A supply. The required power-on sequence for the DSP is to provide VDD (and VDD_A) before VDD_IO. Rev. C | DEVELOPMENT TOOLS The ADSP-TS101S is supported with a complete set of CROSSCORE(R) software and hardware development tools, including Analog Devices emulators and VisualDSP++(R) development environment. The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP-TS101S. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Page 10 of 48 | May 2009 ADSP-TS101S Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert breakpoints * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Perform source level debugging * Create custom debugger windows The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: * Control how the development tools process inputs and generate outputs * Maintain a one-to-one correspondence with the tool's command-line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command-line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-TS101S processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the TigerSHARC processor family. Hardware tools include TigerSHARC processor PC plug-in cards. Third-party software tools include DSP libraries, realtime operating systems, and block diagram design tools. DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG DSP. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-TS101S processor's architecture and functionality. For detailed information on the ADSP-TS101S processor's core architecture and instruction set, see the ADSP-TS101 TigerSHARC Processor Programming Reference and the ADSP-TS101 TigerSHARC Processor Hardware Reference. For detailed information on the development tools for this processor, see the VisualDSP++ User's Guide. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with a drag of the mouse, examine run-time stack and heap usage. The Expert Linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. Rev. C | Page 11 of 48 | May 2009 ADSP-TS101S PIN FUNCTION DESCRIPTIONS While most of the ADSP-TS101S processor's input pins are normally synchronous--tied to a specific clock--a few are asynchronous. For these asynchronous signals, an on-chip synchronization circuit prevents metastability problems. The synchronous ac specification for asynchronous signals is used only when predictable cycle-by-cycle behavior is required. All inputs are sampled by a clock reference, therefore input specifications (asynchronous minimum pulse widths or synchronous input setup and hold) must be met to guarantee recognition. PIN STATES AT RESET The output pins can be three-stated during normal operation. The DSP three-states all outputs during reset, allowing these pins to get to their internal pull-up or pull-down state. Some output pins (control signals) have a pull-up or pull-down that maintains a known value during transitions between different drivers. PIN DEFINITIONS The Type column in the following pin definitions tables describes the pin type, when the pin is used in the system. The Term (for termination) column describes the pin termination type if the pin is not used by the system. Note that some pins are always used (indicated with au symbol). Table 3. Pin Definitions--Clocks and Reset Signal LCLK_N LCLK_P Type I I Term au au Description Local Clock Reference. Connect this pin to VREF as shown in Figure 6. Local Clock Input. DSP clock input. The instruction cycle rate = n LCLK, where n is userprogrammable to 2, 2.5, 3, 3.5, 4, 5, or 6. For more information, see Clock Domains on Page 9. LCLKRAT2-01 I (pd2) au LCLK Ratio. The DSP's core clock (instruction cycle rate) = n LCLK, where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These pins must have a constant value while the DSP is powered. SCLK_N I au System Clock Reference. Connect this pin to VREF as shown in Figure 6. SCLK_P I au System Clock Input. The DSP's system input clock for cluster bus. This pin must be connected to the same clock source as LCLK_P. For more information, see Clock Domains on Page 9. SCLKFREQ3 I (pu2) au SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must have a constant value while the DSP is powered. RESET I/A au Reset. Sets the DSP to a known state and causes program to be in idle state. RESET must be asserted at specified time according to the type of reset operation. For details, see Reset and Booting on Page 9. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. 2 Table 4. LCLK Ratio LCLKRAT2-0 000 (default) 001 010 011 100 101 110 111 Ratio 2 2.5 3 3.5 4 5 6 Reserved Rev. C | Page 12 of 48 | May 2009 ADSP-TS101S Table 5. Pin Definitions--External Port Bus Controls Signal ADDR31-01 Type I/O/T Term nc Description Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O processor registers of other ADSP-TS101S processors. The DSP inputs addresses when a host or another DSP accesses its internal memory or I/O processor registers. DATA63-01 I/O/T nc External Data Bus. Data and instructions are received, and driven by the DSP, on these pins. RD2 I/O/T (pu3) nc Memory Read. RD is asserted whenever the DSP reads from any slave in the system, excluding SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its internal memory or universal registers. In a multiprocessor system, the bus master drives RD. The RD pin changes concurrently with ADDR pins. I/O/T (pu3) nc Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to an even address word WRL2 of external memory or to another external bus agent; and when the ADSP-TS101S writes to a 32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing to a DSP's low word of internal memory. In a multiprocessor system, the bus master drives WRL. The WRL pin changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input and indicates write transactions that access its internal memory or universal registers. 2 3 WRH I/O/T (pu ) nc Write High. WRH is asserted when the ADSP-TS101S writes a long word (64 bits) or writes to an odd address word of external memory or to another external bus agent on a 64-bit data bus. An external master (host or another DSP) must assert WRH for writing to a DSP's high word of 64-bit data bus. In a multiprocessing system, the bus master drives WRH. The WRH pin changes concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write transactions that access its internal memory or universal registers. ACK I/O/T epu Acknowledge. External slave devices can deassert ACK to add wait states to external memory accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data phase. The DSP can deassert ACK to add wait states to read accesses of its internal memory. The ADSP-TS101S does not drive ACK during slave writes. Therefore, an external (approximately 10 k) pull-up is required. BMS2, 4 O/T au Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During reset, the (pu/pd3) DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. When the DSP is configured to boot from EPROM, BMS is active during the boot sequence. Pull-down enabled during RESET (asserted); pull-up enabled after RESET (deasserted). In a multiprocessor system, the DSP bus master drives BMS. For details see Reset and Booting on Page 9 and the EBOOT signal description in Table 16 on Page 19. O/T (pu3) nc Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 or 1, MS1-02 respectively. MS1-0 are decoded memory address pins that change concurrently with ADDR pins. When ADDR31:26 = 0b000010, MS0 is asserted. When ADDR31:26 = 0b000011, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1-0. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. Rev. C | Page 13 of 48 | May 2009 ADSP-TS101S Table 5. Pin Definitions--External Port Bus Controls (Continued) Signal MSH2 Type O/T (pu3) Term nc Description Memory Select Host. MSH is asserted whenever the DSP accesses the host address space (ADDR31:28 0b0000). MSH is a decoded memory address pin that changes concurrently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH. BRST2 I/O/T (pu3) nc Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading or writing data associated with consecutive addresses. A slave device can ignore addresses after the first one and increment an internal address counter after each transfer. For host-to-DSP burst accesses, the DSP increments the address automatically while BRST is asserted. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The address and data buses may float for several cycles during bus mastership transitions between a TigerSHARC processor and a host. Floating in this case means that these inputs are not driven by any source and that dc-biased terminations are not present. It is not necessary to add pull-ups as there are no reliability issues and the worst-case power consumption for these floating inputs is negligible. Unconnected address pins may require pull-ups or pull-downs to avoid erroneous slave accesses, depending on the system. Unconnected data pins may be left floating. 2 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. 3 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 4 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. Table 6. Pin Definitions--External Port Arbitration Signal BR7-0 Type I/O Term epu Description Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In systems with fewer than eight DSPs, set the unused BRx pins high. ID2-01 I (pd2) au Multiprocessor ID. Indicates the DSP's ID. From the ID, the DSP determines its order in a multiprocessor system. These pins also indicate to the DSP which bus request (BR0-BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2, 011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2-0 must have a constant value during system operation and can change during reset only. 1 2 BM O (pd ) au Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this is a strap pin. For more information, see Table 16 on Page 19. BOFF I epu Back Off. A deadlock situation can occur when the host and a DSP try to read from each other's bus at the same time. When deadlock occurs, the host can assert BOFF to force the DSP to relinquish the bus before completing its outstanding transaction, but only if the outstanding transaction is to host memory space (MSH). BUSLOCK3 O/T (pu2) nc Bus Lock Indication. Provides an indication that the current bus master has locked the bus. HBR I epu Host Bus Request. A host must assert HBR to request control of the DSP's external bus. When HBR is asserted in a multiprocessing system, the bus master relinquishes the bus and asserts HBG once the outstanding transaction is finished. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. Rev. C | Page 14 of 48 | May 2009 ADSP-TS101S Table 6. Pin Definitions--External Port Arbitration (Continued) Signal HBG3 Type I/O/T (pu2) Term nc Description Host Bus Grant. Acknowledges HBR and indicates that the host can take control of the external bus. When relinquishing the bus, the master DSP three-states the ADDR31-0, DATA63-0, MSH, MSSD, MS1-0, RD, WRL, WRH, BMS, BRST, FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and the DSP puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave DSPs monitor HBG. I/O (o/d) See Core Priority Access. Asserted while the DSP's core accesses external memory. This pin enables CPA next a slave DSP to interrupt a master DSP's background DMA transfers and gain control of the column external bus for core-initiated transactions. CPA is an open drain output, connected to all DSPs in the system. The CPA pin has an internal 500 pull-up resistor, which is only enabled on the DSP with ID2-0 = 0. If ID0 is not used, terminate this pin as either epu or nc. If ID7-1 is not used, terminate this pin as epu. DPA I/O (o/d) See DMA Priority Access. Asserted while a high-priority DSP DMA channel accesses external next memory. This pin enables a high-priority DMA channel on a slave DSP to interrupt transfers of column a normal-priority DMA channel on a master DSP and gain control of the external bus for DMAinitiated transactions. DPA is an open drain output, connected to all DSPs in the system. The DPA pin has an internal 500 pull-up resistor, which is only enabled on the DSP with ID2-0 = 0. If ID0 is not used, terminate this pin as either epu or nc. If ID7-1 is not used, terminate this pin as epu. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. 2 Table 7. Pin Definitions--External Port DMA/Flyby Signal DMAR3-0 Description DMA Request Pins. Enable external I/O devices to request DMA services from the DSP. In response to DMARx, the DSP performs DMA transfers according to the DMA channel's initialization. The DSP ignores DMA requests from uninitialized channels. FLYBY1 O/T (pu2) nc Flyby Mode. When a DSP DMA channel is initiated in FLYBY mode, it generates flyby transactions on the external bus. During flyby transactions, the DSP asserts FLYBY, which signals the source or destination I/O device to latch the next data or strobe the current data, respectively, and to prepare for the next data on the next cycle. 1 2 IOEN O/T (pu ) nc I/O Device Output Enable. Enables the output buffers of an external I/O device for flyby transactions between the device and external memory. Active on flyby transactions. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 2 Type I/A Term epu The internal pull-up may not be sufficient. A stronger pull-up may be necessary. See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. Rev. C | Page 15 of 48 | May 2009 ADSP-TS101S Table 8. Pin Definitions--External Port SDRAM Controller Signal MSSD1 Type I/O/T (pu2) Term nc Description Memory Select SDRAM. MSSD is asserted whenever the DSP accesses SDRAM memory space. MSSD is a decoded memory address pin that is asserted whenever the DSP issues an SDRAM command cycle (access to ADDR31:26 = 0b000001). MSSD in a multiprocessor system is driven by the master DSP. RAS1 I/O/T (pu2) nc Row Address Select. When sampled low, RAS indicates that a row address is valid in a read or write of SDRAM. In other SDRAM accesses, RAS defines the type of operation to execute according to SDRAM specification. CAS1 I/O/T (pu2) nc Column Address Select. When sampled low, CAS indicates that a column address is valid in a read or write of SDRAM. In other SDRAM accesses, CAS defines the type of operation to execute according to the SDRAM specification. LDQM1 O/T (pu2) nc Low Word SDRAM Data Mask. When LDQM is sampled high, the DSP three-states the SDRAM DQ buffers. LDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read transactions. On write transactions, LDQM is active when accessing an odd address word on a 64-bit memory bus to disable the write of the low word. HDQM1 O/T (pu2) nc High Word SDRAM Data Mask. When HDQM is sampled high, the DSP three-states the SDRAM DQ buffers. HDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read transactions. On write transactions, HDQM is active when accessing an even address in word accesses or is active when memory is configured for a 32-bit bus to disable the write of the high word. 1 2 SDA10 O/T (pu ) nc SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation while the DSP executes non-SDRAM transactions. 1, 3 SDCKE I/O/T nc SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A (pu/pd2) slave DSP in a multiprocessor system does not have the pull-up or pull-down. A master DSP (or ID = 0 in a single processor system) has a 100 k pull-up before granting the bus to the host, except when the SDRAM is put in self-refresh mode. In self-refresh mode, the master has a 100 k pull-down before granting the bus to the host. SDWE1 I/O/T (pu2) nc SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an SDRAM write access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM specification. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 3 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. 2 Table 9. Pin Definitions--JTAG Port Signal EMU TCK Type O (o/d) I Term Description nc1 Emulation. Connected only to the DSP's JTAG emulator target board connector. epd or Test Clock (JTAG). Provides an asynchronous clock for JTAG scan. epu1 TDI2 I (pu3) nc1 Test Data Input (JTAG). A serial data input of the scan path. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. Rev. C | Page 16 of 48 | May 2009 ADSP-TS101S Table 9. Pin Definitions--JTAG Port (Continued) Signal TDO TMS2 TRST2 Type O/T I (pu3) I/A (pu3) Term nc1 nc1 au Description Test Data Output (JTAG). A serial data output of the scan path. Test Mode Select (JTAG). Used to control the test state machine. Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after power-up for proper device operation. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 See the reference Page 11 to the JTAG emulation technical reference EE-68. The internal pull-up may not be sufficient. A stronger pull-up may be necessary. 3 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 2 Table 10. Pin Definitions--Flags, Interrupts, and Timer Signal FLAG3-01 Type I/O/A (pd2) Term nc Description FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be configured individually for input or for output. FLAG3-0 are inputs after power-up and reset. I/A (pu2) nc Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3-0 pins can IRQ3-03 be independently set for edge triggered or level sensitive operation. After reset, these pins are disabled unless the IRQ3-0 strap option is initialized for booting. TMR0E1 O (pd2) au Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires. At reset this is a strap pin. For additional information, see Table 16 on Page 19. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. 2 Table 11. Pin Definitions--Link Ports Signal Type Term Description L0DAT7-01 I/O nc Link0 Data 7-0 L1DAT7-01 I/O nc Link1 Data 7-0 1 I/O nc Link2 Data 7-0 L2DAT7-0 L3DAT7-01 I/O nc Link3 Data 7-0 L0CLKOUT O nc Link0 Clock/Acknowledge Output L1CLKOUT O nc Link1 Clock/Acknowledge Output L2CLKOUT O nc Link2 Clock/Acknowledge Output L3CLKOUT O nc Link3 Clock/Acknowledge Output L0CLKIN I/A epu Link0 Clock/Acknowledge Input L1CLKIN I/A epu Link1 Clock/Acknowledge Input L2CLKIN I/A epu Link2 Clock/Acknowledge Input L3CLKIN I/A epu Link3 Clock/Acknowledge Input L0DIR O nc Link0 Direction. (0 = input, 1 = output) Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. Rev. C | Page 17 of 48 | May 2009 ADSP-TS101S Table 11. Pin Definitions--Link Ports (Continued) Signal L1DIR L2DIR2 Type O O (pd3) Term nc au Description Link1 Direction. (0 = input, 1 = output) Link2 Direction. (0 = input, 1 = output) At reset this is a strap pin. For more information, see Table 16 on Page 19. L3DIR O (pd3) nc Link3 Direction. (0 = input, 1 = output) Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The link port data pins, if connected or floated for extended periods (for example, token slave with no token master), do not require pull-ups or pull-downs as there are no reliability issues and the worst-case power consumption for these floating inputs is negligible. Floating in this case means that these inputs are not driven by any source and that dc-biased terminations are not present. 2 The internal pull-down may not be sufficient. A stronger pull-down may be necessary. 3 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. Table 12. Pin Definitions--Impedance and Drive Strength Control Signal CONTROLIMP2-11 CONTROLIMP02 Type I (pu3) I (pd3) Term au au Description Impedance Control. For ADC (Address/Data/Controls) and LINK (all link port outputs) signals, the CONTROLIMP2-0 pins control impedance as shown in Table 13. These pins enable or disable dig_ctrl mode. When dig_ctrl: 0 = Disabled (maximum drive strength) 1 = Enabled (use DS2-0 drive strength selection) 1 3 DS2-0 I (pu ) au Digital Drive Strength Selection. Selected as shown in Table 14. For drive strength calculation, see Output Drive Currents on Page 32. The drive strength for some pins is preset, not controlled by the DS2-0 pins. The pins that are always at drive strength 7 (100%) are: CPA, DPA, and EMU. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. 1 The internal pull-up may not be sufficient. A stronger pull-up may be necessary. The internal pull-down may not be sufficient. A stronger pull-down may be necessary. 3 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances. 2 Table 13. Control Impedance Selection CONTROLIMP2-0 000 001 010 011 100 101 110 (default) 111 ADC dig_ctrl 0 0 0 reserved 1 reserved 1 reserved Table 14. Drive Strength Selection LINK dig_ctrl 0 0 1 reserved 0 reserved 1 reserved Rev. C | DS2-0 000 001 010 011 100 101 110 111 (default) Page 18 of 48 | May 2009 Drive Strength Strength 0 Strength 1 Strength 2 Strength 3 Strength 4 Strength 5 Strength 6 Strength 7 ADSP-TS101S Table 15. Pin Definitions--Power, Ground, and Reference Signal VDD VDD_A VDD_IO VREF Type P P P I Term au au au au Description VDD pins for internal logic. VDD pins for analog circuits. Pay critical attention to bypassing this supply. VDD pins for I/O buffers. Reference voltage defines the trip point for all input buffers, except RESET, IRQ3-0, DMAR3-0, ID2-0, CONTROLIMP2-0, TCK, TDI, TMS, and TRST. The value is 1.5 V 100 mV (which is the TTL trip point). VREF can be connected to a power supply or set by a voltage divider circuit. The voltage divider should have an HF decoupling capacitor (1 nF HF SMD) connected to VSS. Tie the decoupling capacitor between VREF input and VSS, as close to the DSP's pins as possible. For more information, see Filtering Reference Voltage and Clocks on Page 10. VSS G au Ground pins. VSS_A G au Ground pins for analog circuits. NC No connect. Do not connect these pins to anything (not to any supply, signal, or each other), because they are reserved and must be left unconnected. Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply; pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k to VDD-IO, nc = not connected; au = always used. STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset. Strap options set DSP operating modes. During reset, the DSP samples the strap option pins. Strap pins have an approximately 100 k pulldown for the default value. If a strap pin is not connected to an external pull-up or logic load, the DSP samples the default value during reset. If strap pins are connected to logic inputs, a stronger external pull-down may be required to ensure default value depending on leakage and/or low level input current of the logic load. To set a mode other than the default mode, connect the strap pin to a sufficiently stronger external pull-up. In a multiprocessor system, up to eight DSPs may be connected on the cluster bus, resulting in parallel combination of strap pin pulldown resistors. Table 16 lists and describes each of the DSP's strap pins. Table 16. Pin Definitions--I/O Strap Pins Signal EBOOT On Pin ... BMS IRQEN BM TM1 L2DIR TM2 TMR0E Description EPROM boot. 0 = boot from EPROM immediately after reset (default) 1 = idle after reset and wait for an external device to boot DSP through the external port or a link port Interrupt Enable. 0 = disable and set IRQ3-0 interrupts to level sensitive after reset (default) 1 = enable and set IRQ3-0 interrupts to edge sensitive immediately after reset Test Mode 1. 0 = required setting during reset. 1 = reserved. Test Mode 2. 0 = required setting during reset. 1 = reserved. Rev. C | Page 19 of 48 | May 2009 ADSP-TS101S SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS Parameter VDD Internal Supply Voltage VDD_A Analog Supply Voltage VDD_IO I/O Supply Voltage TCASE Case Operating Temperature VIH High Level Input Voltage1 Low Level Input Voltage1 VIL IDD VDD Supply Current for Typical Activity2 IDD VDD Supply Current for Typical Activity2 IDDIDLELP VDD Supply Current for IDLELP Instruction Execution VDD_IO Supply Current for Typical Activity2 VDD_A Supply Current Voltage Reference IDD_IO IDD_A VREF 1 2 Test Conditions @ VDD, VDD_IO = max @ VDD, VDD_IO = min @ CCLK = 250 MHz, VDD = 1.25 V, TCASE = 25C @ CCLK = 300 MHz, VDD = 1.25 V, TCASE = 25C @ CCLK = 300 MHz, VDD = 1.20 V, TCASE = 25C @ SCLK = 100 MHz, VDD_IO = 3.3 V, TCASE = 25C @ VDD = 1.25 V, TCASE = 25C Min 1.14 1.14 3.15 -40 2 -0.5 Typ Max 1.26 1.26 3.45 +85 VDD_IO + 0.5 +0.8 1.2 Unit V V V C V V A 1.5 A 173 mA 137 mA 25 31.25 1.6 1.4 mA V Applies to input and bidirectional pins. For details on internal and external power estimation, including: power vector definitions, current usage descriptions, and formulas, see EE-169, Estimating Power for the ADSP-TS101S on the Analog Devices website--use site search on "EE-169" (www.analog.com). This document is updated regularly to keep pace with silicon revisions. ELECTRICAL CHARACTERISTICS Parameter VOH High Level Output Voltage1 Low Level Output Voltage1 VOL IIH High Level Input Current2 IIHP High Level Input Current (pd)2 IIL Low Level Input Current3 IILP Low Level Input Current (pu)4 IOZH Three-State Leakage Current High5, 6 Three-State Leakage Current High (pd)7 IOZHP IOZL Three-State Leakage Current Low8 IOZLP Three-State Leakage Current Low (pu)9 IOZLO Three-State Leakage Current Low (od)7 CIN Input Capacitance10, 11 Test Conditions @VDD_IO = min, IOH = -2 mA @VDD_IO = min, IOL = 4 mA @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = 0 V @VDD_IO = max, VIN = 0 V @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = VDD_IO max @VDD_IO = max, VIN = 0 V @VDD_IO = max, VIN = 0 V @VDD_IO = max, VIN = 0 V @fIN = 1 MHz, TCASE = 25C, VIN = 2.5 V 1 Applies to output and bidirectional pins. Applies to input pins with internal pull-downs (pd). 3 Applies to input pins without internal pull-ups (pu). 4 Applies to input pins with internal pull-ups (pu). 5 Applies to three-stateable pins without internal pull-downs (pd). 6 Applies to open drain (od) pins with 500 pull-ups (pu). 7 Applies to three-stateable pins with internal pull-downs (pd). 8 Applies to three-stateable pins without internal pull-ups (pu). 9 Applies to three-stateable pins with internal pull-ups (pu). 10 Applies to all signals. 11 Guaranteed but not tested. 2 Rev. C | Page 20 of 48 | May 2009 Min 2.4 17.2 -69 17.2 -69 -9.8 Max 0.4 10 44.5 10 -23 10 44.5 10 -23 -4.6 5 Unit V V A A A A A A A A mA pF ADSP-TS101S ABSOLUTE MAXIMUM RATINGS Table 18. Package Brand Information Stresses greater than those listed in Table 19 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 17. Absolute Maximum Ratings Parameter Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (VDD_A) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Storage Temperature Range Rating -0.3 V to +1.40 V -0.3 V to +1.40 V -0.3 V to +4.6 V -0.5 V to VDD_IO + 0.5 V -0.5 V to VDD_IO + 0.5 V -65C to +150C ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Field Description Temperature Range Package Type Lead Free Option (optional) See Ordering Guide Silicon Lot Number Silicon Revision Date Code Assembly Lot Code TIMING SPECIFICATIONS With the exception of link port, IRQ3-0, DMAR3-0, TMR0E, FLAG3-0 (input), and TRST pins, all ac timing for the ADSPTS101S is relative to a reference clock edge. Because input setup/hold, output valid/hold, and output enable/disable times are relative to a clock edge, the timing data for the ADSPTS101S has few calculated (formula-based) values. For information on ac timing, see General AC Timing. For information on link port transfer timing, see Link Ports Data Transfer and Token Switch Timing on Page 29. General AC Timing Timing is measured on signals when they cross the 1.5 V level as described in Figure 16 on Page 28. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. The ac asynchronous timing data for the IRQ3-0, DMAR3-0, TMR0E, FLAG3-0 (input), and TRST pins appears in Table 21. PACKAGE INFORMATION The information presented in Figure 7 provide details about the package branding for the ADSP-TS101S processors. For a complete listing of product availability, see Ordering Guide on Page 45. a The general ac timing data appears in Table 21, Table 29, and Table 30. All ac specifications are measured with the load specified in Figure 8, and with the output drive strength set to strength 4. Output valid and hold are based on standard capacitive loads: 30 pF on all pins. The delay and hold specifications given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF. In order to calculate the output valid and hold times for different load conditions and/or output drive strengths, refer to Figure 32 on Page 34 through Figure 39 on Page 36 (Rise and Fall Time vs. Load Capacitance) and Figure 40 on Page 36 (Output Valid vs. Load Capacitance and Drive Strength). ADSP-TS101S tppZ-ccc LLLLLLLLL-L 2.0 yyww country_of_origin T Brand Key t pp Z ccc LLLLLLLLL-L R.R yyww vvvvvv vvvvv TO OUTPUT PIN Figure 7. Typical Package Brand 50 1.5V 30pF Figure 8. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Rev. C | Page 21 of 48 | May 2009 ADSP-TS101S For power-up sequencing, power-up reset, and normal reset (hot reset) timing requirements, refer to Table 26 and Figure 13, Table 27 and Figure 14, and Table 28, and Figure 15 respectively. Table 19. AC Asynchronous Signal Specifications (All values in this table are in nanoseconds) Name IRQ3-01 DMAR3-01 TMR0E2 FLAG3-01, 3 TRST Description Interrupt request input DMA request input Timer 0 expired output Flag pins input JTAG test reset input Pulse Width Low (min) tCCLK + 3 ns tCCLK + 4 ns 3 tCCLK ns 1 ns Pulse Width High (min) tCCLK + 4 ns 4 tSCLK ns 3 tCCLK ns 1 These input pins do not need to be synchronized to a clock reference. This pin is a strap option. During reset, an internal resistor pulls the pin low. 3 For output specifications, see Table 29 and Table 30. 2 Table 20. Reference Clocks--Core Clock (CCLK) Cycle Time Parameter tCCLK1 1 Grade = 100 (300 MHz) Min Max 3.3 12.5 Description Core Clock Cycle Time Grade = 000 (250 MHz) Min Max 4.0 12.5 Unit ns CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio (SCLKRAT2-0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 45. tCCLK CCLK Figure 9. Reference Clocks--Core Clock (CCLK) Cycle Time Table 21. Reference Clocks--Local Clock (LCLK) Cycle Time Parameter tLCLK1, 2, 3, 4 tLCLKH tLCLKL tLCLKJ5, 6 Description Local Clock Cycle Time Local Clock Cycle High Time Local Clock Cycle Low Time Local Clock Jitter Tolerance Min 10 0.4 x tLCLK 0.4 x tLCLK 1 For more information, see Table 3 on Page 12. For more information, see Clock Domains on Page 9. 3 LCLK_P and SCLK_P must be connected to the same source. 4 The value of (tLCLK / LCLKRAT2-0) must not violate the specification for tCCLK. 5 Actual input jitter should be combined with ac specifications for accurate timing analysis. 6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 ttLCLK LCLK ttLCLKH LCLKH ttLCLKJ LCLKJ tLCLKL LCLKL LCLK_P LCLK_P Figure 10. Reference Clocks--Local Clock (LCLK) Cycle Time Rev. C | Page 22 of 48 | May 2009 Max 25 0.6 x tLCLK 0.6 x tLCLK 500 Unit ns ns ns ps ADSP-TS101S Table 22. Reference Clocks--System Clock (SCLK) Cycle Time Parameter tSCLK1, 2, 3, 4 tSCLKH tSCLKL tSCLKJ5, 6 Description System Clock Cycle Time System Clock Cycle High Time System Clock Cycle Low Time System Clock Jitter Tolerance Min 10 0.4 x tSCLK 0.4 x tSCLK Max 25 0.6 x tSCLK 0.6 x tSCLK 500 Unit ns ns ns ps 1 For more information, see Table 3 on Page 12. For more information, see Clock Domains on Page 9. 3 LCLK_P and SCLK_P must be connected to the same source. 4 The value of (tSCLK / LCLKRAT2-0) must not violate the specification for tCCLK. 5 Actual input jitter should be combined with ac specifications for accurate timing analysis. 6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 ttSCLK SCLK ttSCLKH SCLKH ttSCLKJ SCLKJ tSCLKL SCLKL SCLK_P SCLK_P Figure 11. Reference Clocks--System Clock (SCLK) Cycle Time Table 23. Reference Clocks--Test Clock (TCK) Cycle Time Parameter tTCK tTCKH tTCKL Description Test Clock (JTAG) Cycle Time Test Clock (JTAG) Cycle High Time Test Clock (JTAG) Cycle Low Time Min Greater of 30 or tCCLK x 4 12.5 12.5 Max Unit ns ns ns tTCK tTCKH tTCKL TCK Figure 12. Reference Clocks--Test Clock (TCK) Cycle Time Table 24. Power-Up Timing1 Parameter Timing Requirement tVDD_IO VDD_IO Stable and Within Specification After VDD and VDD_A Are Stable and Within Specification 1 Min >0 For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing. VDD VDD_A tVDD_IO VDD_IO Figure 13. Power-Up Sequencing Timing Rev. C | Page 23 of 48 | May 2009 Max Unit ms ADSP-TS101S Table 25. Power-Up Reset Timing Parameter Timing Requirements tSTART_LO RESET Deasserted After VDD, VDD_A, VDD_IO, SCLK/LCLK, and Static/Strap Pins Are Stable and Within Specification tPULSE1_HI RESET Deasserted for First Pulse tPULSE2_LO RESET Asserted for Second Pulse tTRST_PWR1 TRST Asserted During Power-Up Reset 1 Min Max 2 Unit ms 50 tSCLK 100 tSCLK 2 tSCLK 100 tSCLK ns ns ns Applies after VDD, VDD_A, VDD_IO, and SCLK/LCLK and static/strap pins are stable and within specification, and before RESET is deasserted. t P ULS E 1 _H I t P U L S E2_ LO t S TA R T_ LO RESET t T RS T _P W R TRST V D D , V D D_ A , V D D_IO , SCL K/LCLK, STAT IC/STR AP PINS Figure 14. Power-Up Reset Timing Table 26. Normal Reset Timing Parameter Timing Requirements tRST_IN RESET Asserted RESET Deasserted After Strap Pins Stable tSTRAP Min 100 tSCLK 2 tRST_IN RESET tSTRAP STRAP PINS Figure 15. Normal Reset (Hot Reset) Timing Rev. C | Page 24 of 48 | May 2009 Max Unit ns ms ADSP-TS101S Rev. C | 2.6 2.6 2.6 2.6 2.6 2.6 2.6 2.6 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.6 2.6 2.6 0.5 0.5 0.5 2.6 2.6 2.6 2.6 1.5 1.5 1.5 0.5 0.5 0.5 0.5 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 4.2 1.0 0.9 2.5 4.2 4.2 4.2 4.2 4.2 5.8 5.8 4.2 4.2 1.0 1.0 1.0 1.0 1.0 0.9 0.9 2.5 2.5 0.9 0.9 1.0 1.0 0.9 1.0 2.5 2.5 2.5 2.5 2.5 4.0 6.0 1.0 1.0 5.0 4.2 5.5 1.0 1.0 1.0 11.0 16.0 Page 25 of 48 | May 2009 5.0 Reference Clock 0.5 Output Disable (max)2 2.6 Output Enable (min)2 0.5 0.5 Output Hold (min) 2.6 2.6 Output Valid (max)1 Description External Address Bus External Data Bus Memory Select Host Line Memory Select SDRAM Line Memory Select for Static Blocks Memory Read Write Low Word Write High Word Acknowledge for Data SDRAM Clock Enable Row Address Select Column Address Select SDRAM Write Enable Low Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Bus Request Host Bus Grant Back Off Request Bus Lock Burst Access Multiprocessing Bus Request Flyby Mode Selection Flyby I/O Enable Core Priority Access DMA Priority Access Boot Memory Select FLAG Pins Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Bus Master Debug Aid Only Emulation System Input System Output Chip ID--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Input Hold (min) Name ADDR31-0 DATA63-0 MSH MSSD MS1-0 RD WRL WRH ACK SDCKE RAS CAS SDWE LDQM HDQM SDA10 HBR HBG BOFF BUSLOCK BRST BR7-0 FLYBY IOEN CPA 3, 4 DPA 3, 4 BMS5 FLAG3-06 RESET4, 7 TMS4 TDI4 TDO TRST4, 7, 9 BM5 EMU10 JTAG_SYS_IN11 JTAG_SYS_OUT12 ID2-09 CONTROLIMP2-09 DS2-09 LCLKRAT2-09 SCLKFREQ9 Input Setup (min) Table 27. AC Signal Specifications (for SCLK <16.7 ns) (All values in this table are in nanoseconds) SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK TCK TCK TCK_FE8 TCK SCLK TCK or LCLK TCK TCK_FE8 ADSP-TS101S 1 The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive loading, see Figure 40 on Page 36. 2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual. 3 CPA and DPA pins are open drains and have 0.5 k internal pull-ups. 4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for recognition in the current clock reference cycle. 5 This pin is a strap option. During reset, an internal resistor pulls the pin low. 6 For input specifications, see Table 21. 7 For additional requirement details, see Reset and Booting on Page 9. 8 TCK_FE indicates TCK falling edge. 9 These pins may change only during reset; recommend connecting it to VDD_IO/VSS. 10 Reference clock depends on function. 11 System inputs are: IRQ3-0, BMS, LCLKRAT2-0, SCLKFREQ, BM, TMR0E, FLAG3-0, ID2-0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7-0, L0CLKIN, L0DAT7-0, L1CLKIN, L1DAT7-0, L2CLKIN, L2DAT7-0, L2DIR, L3CLKIN, L3DAT7-0, DS2-0, CONTROLIMP2-0, RESET, DMAR3-0. 12 System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3-0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1-0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, ACK, BR7-0, L0CLKOUT, L0DAT7-0, L0DIR, L1CLKOUT, L1DAT7-0, L1DIR, L2CLKOUT, L2DAT7-0, L2DIR, L3CLKOUT, L3DAT7-0, L3DIR, EMU. Rev. C | 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 2.8 2.8 2.8 0.5 0.5 0.5 2.8 2.8 2.8 2.8 Page 26 of 48 | 0.5 0.5 0.5 0.5 May 2009 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 4.2 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 4.2 0.8 0.3 2.5 4.2 4.2 4.2 4.2 4.2 5.8 5.8 4.2 4.2 0.8 0.8 0.8 0.8 0.8 0.3 0.3 2.5 2.5 0.3 0.3 0.8 1.0 0.3 1.0 2.5 2.5 2.5 2.5 2.5 4.0 Reference Clock 0.5 Output Disable (max)2 2.8 Output Enable (min)2 0.5 0.5 Output Hold (min) 2.8 2.8 Output Valid (max)1 Description External Address Bus External Data Bus Memory Select Host Line Memory Select SDRAM Line Memory Select for Static Blocks Memory Read Write Low Word Write High Word Acknowledge for Data SDRAM Clock Enable Row Address Select Column Address Select SDRAM Write Enable Low Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Bus Request Host Bus Grant Back Off Request Bus Lock Burst Access Multiprocessing Bus Request Flyby Mode Selection Flyby Mode I/O Enable Core Priority Access DMA Priority Access Boot Memory Select FLAG Pins Input Hold (min) Name ADDR31-0 DATA63-0 MSH MSSD MS1-0 RD WRL WRH ACK SDCKE RAS CAS SDWE LDQM HDQM SDA10 HBR HBG BOFF BUSLOCK BRST BR7-0 FLYBY IOEN CPA 3, 4 DPA 3, 4 BMS5 FLAG3-06 Input Setup (min) Table 28. AC Signal Specifications (for 16.7 ns <SCLK <25 ns) (All values in this table are in nanoseconds) SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK ADSP-TS101S 1.5 1.5 1.5 1.0 1.0 6.0 1.0 4.2 5.5 0.8 11.0 16.0 1 1.0 5.0 5.0 Reference Clock Output Disable (max)2 Output Enable (min)2 Output Hold (min) Output Valid (max)1 Description Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Bus Master Debug Aid Only Emulation System Input System Output Chip ID--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Static Pins--Must Be Constant Input Hold (min) Name RESET4, 7 TMS4 TDI4 TDO TRST4, 7, 9 BM5 EMU10 JTAG_SYS_IN11 JTAG_SYS_OUT12 ID2-09 CONTROLIMP2-09 DS2-09 LCLKRAT2-09 SCLKFREQ9 Input Setup (min) Table 28. AC Signal Specifications (for 16.7 ns <SCLK <25 ns) (All values in this table are in nanoseconds) (Continued) SCLK TCK TCK TCK_FE8 TCK SCLK TCK or LCLK TCK TCK_FE8 The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive loading, see Figure 40 on Page 36. 2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual. 3 CPA and DPA pins are open drains and have 0.5 k internal pull-ups. 4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for recognition in the current clock reference cycle. 5 This pin is a strap option. During reset, an internal resistor pulls the pin low. 6 For input specifications, see Table 21. 7 For additional requirement details, see Reset and Booting on Page 9. 8 TCK_FE indicates TCK falling edge. 9 These pins may change only during reset; recommend connecting it to VDD_IO/VSS. 10 Reference clock depends on function. 11 System inputs are: IRQ3-0, BMS, LCLKRAT2-0, SCLKFREQ, BM, TMR0E, FLAG3-0, ID2-0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7-0, L0CLKIN, L0DAT7-0, L1CLKIN, L1DAT7-0, L2CLKIN, L2DAT7-0, L2DIR, L3CLKIN, L3DAT7-0, DS2-0, CONTROLIMP2-0, RESET, DMAR3-0. 12 System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3-0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1-0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, ACK, BR7-0, L0CLKOUT, L0DAT7-0, L0DIR, L1CLKOUT, L1DAT7-0, L1DIR, L2CLKOUT, L2DAT7-0, L2DIR, L3CLKOUT, L3DAT7-0, L3DIR, EMU. Rev. C | Page 27 of 48 | May 2009 ADSP-TS101S REFERENCE CLOCK 1.5V INPUT SIGNAL INPUT SETUP 1.5V INPUT HOLD OUTPUT SIGNAL OUTPUT VALID OUTPUT HOLD 1.5V THREE-STATE OUTPUT DISABLE OUTPUT ENABLE ASYNCHRONOUS INPUT OR OUTPUT SIGNAL 1.5V PULSE WIDTH Figure 16. General AC Parameters Timing Rev. C | Page 28 of 48 | May 2009 ADSP-TS101S Link Ports Data Transfer and Token Switch Timing Table 31, Table 32, Table 33, and Table 34 with Figure 17, Figure 18, Figure 19, and Figure 20 provide the timing specifications for the link ports data transfer and token switch. Table 29. Link Ports--Transmit Parameter Timing Requirements Connectivity Pulse Setup tCONNS1 tCONNS2 Connectivity Pulse Setup tCONNIW3 Connectivity Pulse Input Width tACKS Acknowledge Setup Min Max 2 tCCLK + 3.5 8 tLXCLK_TX + 1 0.5 tLXCLK_TX Switching Characteristics tLXCLK_TX4 Transmit Link Clock Period Transmit Link Clock Width High tLXCLKH_TX1 2 tLXCLKH_TX Transmit Link Clock Width High tLXCLKL_TX1 Transmit Link Clock Width Low tLXCLKL_TX2 Transmit Link Clock Width Low tDIRS LxDIR Transmit Setup tDIRH LxDIR Transmit Hold LxDAT7-0 Output Setup tDOS1 1 tDOH LxDAT7-0 Output Hold tDOS2 LxDAT7-0 Output Setup tDOH2 LxDAT7-0 Output Hold tLDOE LxDAT7-0 Output Enable 5 tLDOD LxDAT7-0 Output Disable 0.9 LR tCCLK 0.33 tLXCLK_TX 0.4 tLXCLK_TX 0.33 tLXCLK_TX 0.4 tLXCLK_TX 0.5 tLXCLK_TX 0.5 tLXCLK_TX 0.25 tLXCLK_TX - 1 0.25 tLXCLK_TX - 1 Greater of 0.8 or 0.17 tLXCLK_TX - 1 Greater of 0.8 or 0.17 tLXCLK_TX - 1 1 1 Unit ns ns ns ns 1 1.1 LR tCCLK 0.66 tLXCLK_TX 0.6 tLXCLK_TX 0.66 tLXCLK_TX 0.6 tLXCLK_TX 2 tLXCLK_TX 2 tLXCLK_TX ns ns ns ns ns ns ns ns ns ns ns ns ns The formula for this parameter applies when LR is 2. The formula for this parameter applies when LR is 3, 4, or 8. 3 LxCLKIN shows the connectivity pulse with each of the three possible transitions to "Acknowledge." After a connectivity pulse low minimum, LxCLKIN may [1] return high and remain high for "Acknowledge," [2] return high and subsequently go low (meeting tACKS) for "Not Acknowledge," or [3] remain low for "Not Acknowledge." 4 The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register. The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK 250 MHz. 5 This specification applies to the last data byte or the "Dummy" byte that follows the verification byte if enabled. For more information, see the ADSP-TS101 TigerSHARC Processor Hardware Reference. 2 tCONNS tLxCLK_Tx tDIRS tDOH tLxCLKH_Tx tDOH tLxCLKL_Tx tDOS tDOS 1 LxCLKOUT 0 tDIRH tACKS 3 2 5 4 7 6 9 8 11 10 13 12 15 14 tCONNIW LxCLKIN tLDOD tLDOE LxDAT7-0 LxDIR Figure 17. Link Ports--Transmit Rev. C | Page 29 of 48 | May 2009 ADSP-TS101S Table 30. Link Ports--Receive Parameter Timing Requirements tLXCLK_RX1, 2 Receive Link Clock Period Receive Link Clock Width High tLXCLKH_RX3 tLXCLKH_RX4 Receive Link Clock Width High 3 tLXCLKL_RX Receive Link Clock Width Low tLXCLKL_RX4 Receive Link Clock Width Low tDIS LxDAT7-0 Input Setup tDIH LxDAT7-0 Input Hold Min Max Unit 0.9 LR tCCLK 0.33 tLXCLK_RX 0.4 tLXCLK_RX 0.33 tLXCLK_RX 0.4 tLXCLK_RX 0.6 0.6 1.1 LR tCCLK 0.66 tLXCLK_RX 0.6 tLXCLK_RX 0.66 tLXCLK_RX 0.6 tLXCLK_RX ns ns ns ns ns ns ns Switching Characteristics Connectivity Pulse Valid tCONNV tCONNOW Connectivity Pulse Output Width 0 1.5 tLXCLK_RX 2.5 tLXCLK_RX ns ns 1 The link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register. The maximum LxCLK is 125 MHz. LR = 2 may not be used when CCLK 250 MHz. 3 The formula for this parameter applies when LR is 2. 4 The formula for this parameter applies when LR is 3, 4, or 8. 2 tLxCLK_Rx 0 tDIS tLxCLKL_Rx 1 LxCLKIN 3 5 2 4 tDIH tDIH tLxCLKH_Rx tCONNV tDIS 7 6 9 8 tCONNOW LxCLKOUT LxDAT7-0 LxDIR Figure 18. Link Ports--Receive Rev. C | Page 30 of 48 | 13 11 10 May 2009 12 15 14 ADSP-TS101S Table 31. Link Ports--Token Switch, Token Master Parameter Timing Requirements tREQI Token Request Input Width Token Request from Token Enable1 tTKRQ Min 2 Unit 3.0 tLXCLK_TX ns ns 5.0 tLXCLK_RX Switching Characteristics tTKENO Token Switch Enable Output tREQO Token Request Output Width2 1 Max 8.0 tLXCLK_TX 6.0 tLXCLK_TX ns ns For guaranteeing token switch during token enable. LxCLKOUT shows both possible responses to the token request: [1] a "Token Grant" (LxCLKOUT remains high), and [2] a "Token Regret" (LxCLKOUT goes low). tTKENO LxCLKOUT tREQO 15 14 tTKRQ tREQI LxCLKIN Figure 19. Link Ports--Token Switch, Token Master Table 32. Link Ports--Token Switch, Token Requester 1 2 Parameter Timing Requirements tTKENI1 Token Switch Enable Input Min Max Unit 8.0 tLXCLK_RX ns Switching Characteristics tREQO Token Request Output Width2 6.0 tLXCLK_RX ns Required whenever there is a break in transmission. LxCLKOUT shows both possible responses to the token request: [1] a "Token Grant" (LxCLKOUT remains high), and [2] a "Token Regret" (LxCLKOUT goes low). tTKENI LxCLKIN (FOR TOKEN REGRET) 13 12 tREQO 15 14 tTKRQ tREQO LxCLKOUT (FOR TOKEN REGRET) tTKENI LxCLKIN (FOR TOKEN GRANT) 13 12 15 14 tTKRQ tREQO 1 LxCLKOUT (FOR TOKEN GRANT) 0 Figure 20. Link Ports--Token Switch, Token Requester Rev. C | Page 31 of 48 | May 2009 3 2 ADSP-TS101S OUTPUT DRIVE CURRENTS STRENGTH 0 30 25 IOL 20 IOL 60 VDD_IO = 3.45V, -40C 40 VDD_IO = 3.3V, +25C 20 VDD_IO = 3.45V, -40C VDD_IO = 3.15V, +85C 0 VDD_IO = 3.3V, +25C -20 VDD_IO = 3.15V, +85C -40 -60 VDD_IO = 3.45V, -40C 15 OUTPUT PIN CURRENT (mA) STRENGTH 2 80 OUTPUT PIN CURRENT (mA) Figure 21 through Figure 28 show typical I-V characteristics for the output drivers of the ADSP-TS101S. The curves in these diagrams represent the current drive capability of the output drivers as a function of output voltage over the range of drive strengths. For complete output driver characteristics, refer to IBIS models, available on the Analog Devices website, www.analog.com. IOH -80 VDD_IO = 3.3V, +25C 10 -100 5 0 -5 0 VDD_IO = 3.45V, -40C VDD_IO = 3.15V, +85C 0.5 VDD_IO = 3.3V, +25C -10 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 3.5 Figure 23. Typical Drive Currents at Strength 2 VDD_IO = 3.15V, +85C -15 STRENGTH 3 -20 125 IOH -25 IOL 100 -30 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 3.5 75 OUTPUT PIN CURRENT (mA) 0 Figure 21. Typical Drive Currents at Strength 0 STRENGTH 1 60 IOL 50 OUTPUT PIN CURRENT (mA) 40 10 VDD_IO = 3.15V, +85C 0 25 VDD_IO = 3.15V, +85C 0 VDD_IO = 3.45V, -40C VDD_IO = 3.3V, +25C -25 VDD_IO = 3.15V, +85C -50 IOH -100 VDD_IO = 3.3V, +25C 20 VDD_IO = 3.3V, +25C -75 VDD_IO = 3.45V, -40C 30 VDD_IO = 3.45V, -40C 50 -125 VDD_IO = 3.45V, -40C 0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 VDD_IO = 3.3V, +25C -10 -20 V DD_IO = 3.15V, +85C Figure 24. Typical Drive Currents at Strength 3 -30 -40 IOH -50 -60 -70 0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 3.5 Figure 22. Typical Drive Currents at Strength 1 Rev. C | Page 32 of 48 | May 2009 3.5 ADSP-TS101S STRENGTH 7 STRENGTH 4 140 IOL 120 100 VDD_IO = 3.45V, -40C 60 OUTPUT PIN CURRENT (mA) OUTPUT PIN CURRENT (mA) 80 VDD_IO = 3.3V, +25C 40 20 VDD_IO = 3.45V, -40C VDD_IO = 3.15V, +85C 0 -20 VDD_IO = 3.3V, +25C -40 VDD_IO = 3.15V, +85C -60 -80 -100 IOH -120 -140 -160 0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 220 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 IOL VDD_IO = 3.45V, -40C VDD_IO = 3.3V, +25C VDD_IO = 3.15V, +85C VDD_IO = 3.3V, +25C VDD_IO = 3.15V, +85C IOH 0 3.5 STRENGTH 5 OUTPUT PIN CURRENT (mA) IOL 120 100 80 VDD_IO = 3.45V, -40C VDD_IO = 3.3V, +25C 60 40 20 VDD_IO = 3.45V, -40C VDD_IO = 3.15V, +85C 0 -20 -40 VDD_IO = 3.3V, +25C -60 -80 -100 VDD_IO = 3.15V, +85C -120 -140 -160 IOH -180 0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 3.5 Figure 26. Typical Drive Currents at Strength 5 OUTPUT PIN CURRENT (mA) STRENGTH 6 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 -220 IOL VDD_IO = 3.45V, -40C VDD_IO = 3.3V, +25C VDD_IO = 3.15V, +85C VDD_IO = 3.45V, -40C VDD_IO = 3.3V, +25C VDD_IO = 3.15V, +85C IOH 0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 0.5 1.0 1.5 2.0 2.5 OUTPUT PIN VOLTAGE (V) 3.0 Figure 28. Typical Drive Currents at Strength 7 Figure 25. Typical Drive Currents at Strength 4 160 140 VDD_IO = 3.45V, -40C 3.5 Figure 27. Typical Drive Currents at Strength 6 Rev. C | Page 33 of 48 | May 2009 3.5 ADSP-TS101S TEST CONDITIONS The test conditions for timing parameters appearing in Table 29 on Page 29 and Table 30 on Page 30 include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 29. INPUT OR OUTPUT 1.5V t RAMP C V L = --------------I D The output enable time tENA is the difference between tMEASURED_ENA and tRAMP as shown in Figure 30. The time tMEASURED_ENA is the interval from when the reference signal switches to when the output voltage ramps V from the measured three-stated output level. The tRAMP value is calculated with test load CL, drive current ID, and with V equal to 0.5 V. 1.5V Capacitive Loading Figure 31 shows the circuit with variable capacitance that is used for measuring typical output rise and fall times. Figure 32 through Figure 39 show how output rise time varies with capacitance. Figure 40 graphically shows how output valid varies with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 34.) The graphs of Figure 32 through Figure 40 may not be linear outside the ranges shown. Figure 29. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) REFERENCE SIGNAL tMEASURED_DIS tMEASURED_ENA tENA tDIS VOH (MEASURED) VOH (MEASURED) - V VOL (MEASURED) + V VOL (MEASURED) tDECAY OUTPUT STOPS DRIVING TO OUTPUT PIN 2.0V 1.5V VARIABLE (10pF to 100pF) 1.0V tRAMP Figure 31. Equivalent Device Loading for AC Measurements (Includes All Fixtures) OUTPUT STARTS DRIVING HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V. STRENGTH 0 25 Figure 30. Output Enable/Disable Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the following equation: C L V t DECAY = --------------IL RISE AND FALL TIMES (ns) (VDD_IO = 3.3V) 20 RISE TIME 15 y = 0.2015x + 3.8869 FALL TIME y = 0.174x + 2.6931 10 5 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) The output disable time tDIS is the difference between tMEASURED_DIS and tDECAY as shown in Figure 30. The time tMEASURED_DIS is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. The tDECAY value is calculated with test loads CL and IL, and with V equal to 0.5 V. Figure 32. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 0 Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The time for the voltage on the bus to ramp by V is dependent on the capacitive load, CL, and the drive current, ID. This ramp time can be approximated by the following equation: Rev. C | Page 34 of 48 | May 2009 ADSP-TS101S STRENGTH 4 25 STRENGTH 1 25 (VDD_IO = 3.3V) RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) (VDD_IO = 3.3V) 20 15 RISE TIME 10 y = 0.1349x + 1.9955 FALL TIME y = 0.1163x + 1.4058 5 20 15 10 RISE TIME y = 0.1071x + 0.9877 FALL TIME 5 y = 0.0798x + 1.0743 0 0 10 20 30 40 50 60 70 80 90 0 100 0 10 20 LOAD CAPACITANCE (pF) STRENGTH 2 25 RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) 60 70 80 90 100 STRENGTH 5 (VDD_IO = 3.3V) 20 15 RISE TIME y = 0.1304x + 0.8427 FALL TIME y = 0.1144x + 0.7025 5 50 Figure 36. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 4 (VDD_IO = 3.3V) 10 40 LOAD CAPACITANCE (pF) Figure 33. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 1 25 30 20 15 10 RISE TIME y = 0.1001x + 0.7763 5 FALL TIME y = 0.0793x + 0.8691 0 0 10 20 30 40 50 60 70 80 90 0 100 0 10 20 LOAD CAPACITANCE (pF) STRENGTH 3 60 70 80 90 100 STRENGTH 6 25 (VDD_IO = 3.3V) RISE AND FALL TIMES (ns) RISE AND FALL TIMES (ns) 50 Figure 37. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 5 (VDD_IO = 3.3V) 20 15 10 40 LOAD CAPACITANCE (pF) Figure 34. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 2 25 30 RISE TIME y = 0.1082x + 1.3123 FALL TIME y = 0.0912x + 1.2048 5 20 15 10 RISE TIME y = 0.0946x + 1.2187 FALL TIME 5 y = 0.0906x + 0.4597 0 0 10 20 30 40 50 60 70 80 90 0 100 0 LOAD CAPACITANCE (pF) 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 35. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 3 Rev. C | Page 35 of 48 | Figure 38. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 6 May 2009 ADSP-TS101S ensure that the TCASE data sheet specification is not exceeded, a heat sink and/or an air flow source may be used. See Table 33 and Table 34 for thermal data. STRENGTH 7 25 RISE AND FALL TIMES (ns) (VDD_IO = 3.3V) Table 33. Thermal Characteristics for 19 mm 19 mm Package 20 15 Parameter JA1 10 RISE TIME y = 0.0907x + 1.0071 FALL TIME 5 JC JB y = 0.09x + 0.3134 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 39. Typical Output Rise and Fall Time (10%-90%, VDD_IO = 3.3 V) vs. Load Capacitance at Strength 7 15 Unit C/W C/W C/W C/W C/W (VDD_IO = 3.3V) 10 Determination of parameter is system dependent and is based on a number of factors, including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow. 2 Per JEDEC JESD51-2 procedure using a four layer board (compliant with JEDEC JESD51-9). 3 Per SEMI Test Method G38-87 using a four layer board (compliant with JEDEC JESD51-9). Table 34. Thermal Characteristics for 27 mm 27 mm Package 0 STRENGTH 0-7 OUTPUT VALID (ns) Typical 16.6 14.0 12.9 6.7 5.8 1 0 Parameter JA1 1 2 3 4 JC JB 5 5 6 7 1 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (pF) Figure 40. Typical Output Valid (VDD_IO = 3.3 V) vs. Load Capacitance at Max Case Temperature and Strength 0-71 1 Condition Airflow2 = 0 m/s Airflow3 = 1 m/s Airflow3 = 2 m/s Typical 13.8 11.7 10.8 3.1 5.9 Unit C/W C/W C/W C/W C/W Determination of parameter is system dependent and is based on a number of factors, including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, and air flow. 2 Per JEDEC JESD51-2 procedure using a four layer board (compliant with JEDEC JESD51-9). 3 Per SEMI Test Method G38-87 using a four layer board (compliant with JEDEC JESD51-9). The line equations for the output valid vs. load capacitance are: Strength 0: y = 0.0956x + 3.5662 Strength 1: y = 0.0523x + 3.2144 Strength 2: y = 0.0433x + 3.1319 Strength 3: y = 0.0391x + 2.9675 Strength 4: y = 0.0393x + 2.7653 Strength 5: y = 0.0373x + 2.6515 Strength 6: y = 0.0379x + 2.1206 Strength 7: y = 0.0399x + 1.9080 ENVIRONMENTAL CONDITIONS The ADSP-TS101S is rated for performance over the extended commercial temperature range, TCASE = -40C to +85C. Thermal Characteristics The ADSP-TS101S is packaged in a 19 mm 19 mm and 27 mm 27 mm Plastic Ball Grid Array (PBGA). The ADSP-TS101S is specified for a case temperature (TCASE). To Rev. C | Condition Airflow2 = 0 m/s Airflow3 = 1 m/s Airflow3 = 2 m/s Page 36 of 48 | May 2009 ADSP-TS101S PBGA PIN CONFIGURATIONS The 484-ball PBGA pin configurations appear in Table 35 and Figure 41. The 625-ball PBGA pin configurations appear in Table 36 and Figure 42. Table 35. 484-Ball (19 mm 19 mm) PBGA Pin Assignments Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 Mnemonic VSS DATA14 DATA11 DATA8 DATA4 DATA1 L0DIR L0CLKIN L0DAT6 L0DAT3 L0DAT1 VSS LCLK_N VSS_A SCLK_N SCLK_P CONTROLIMP2 CONTROLIMP1 RESET DMAR1 EMU VSS DATA29 DATA30 DATA26 VDD_IO VDD_IO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO VDD_IO LCLKRAT0 SCLKFREQ Pin No. B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 Mnemonic DATA21 DATA18 DATA12 DATA13 DATA7 DATA5 DATA2 NC L0DAT7 L0DAT4 L0DAT0 VSS VDD_A VSS_A VSS DS1 CONTROLIMP0 DMAR2 DMAR0 TMS TDI IRQ1 L3DAT1 DATA28 DATA27 VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO FLAG3 BUSLOCK Pin No. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 Rev. C | Mnemonic DATA23 DATA17 DATA15 DATA9 DATA10 DATA6 DATA3 DATA0 L0CLKOUT L0DAT5 L0DAT2 LCLK_P VSS VDD_A DS0 DS2 VREF TRST DMAR3 TCK IRQ3 IRQ0 L3DAT2 L3DAT0 DATA31 VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_IO VDD_IO FLAG1 FLAG2 Page 37 of 48 | Pin No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 May 2009 Mnemonic DATA24 DATA19 DATA16 VDD_IO VDD VDD VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD VDD_IO VDD VDD_IO TDO IRQ2 LCLKRAT1 L3DAT5 L3DAT3 L3DAT4 VDD_IO VDD_IO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO ID0 ID2 Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 Mnemonic DATA25 DATA22 DATA20 VDD_IO VDD VDD VDD_IO VDD VDD VDD VDD_IO VDD VDD_IO VDD VDD_IO VDD VDD_IO VDD_IO VDD_IO BM BMS LCLKRAT2 L3CLKOUT L3DAT7 L3DAT6 VDD_IO VDD_IO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO IOEN FLYBY ADSP-TS101S Table 35. 484-Ball (19 mm 19 mm) PBGA Pin Assignments (Continued) Pin No. F22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Mnemonic TMR0E L3CLKIN NC L3DIR VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD_IO VDD_IO BRST WRH RD L1DIR DATA36 DATA37 VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO ADDR23 ADDR25 ADDR27 Pin No. Mnemonic G22 FLAG0 M1 L1DAT0 M2 L1DAT2 M3 L1DAT1 M4 VDD_IO M5 VSS M6 VSS M7 VSS M8 VSS M9 VSS M10 VSS M11 VSS M12 VSS M13 VSS M14 VSS M15 VSS M16 VSS M17 VSS M18 VDD_IO M19 VDD M20 HDQM M21 MS0 M22 MS1 U1 NC U2 DATA38 U3 DATA39 U4 VDD_IO U5 VDD U6 VSS U7 VSS U8 VSS U9 VSS U10 VSS U11 VSS U12 VSS U13 VSS U14 VSS U15 VSS U16 VSS U17 VSS U18 VDD U19 VDD_IO U20 ADDR30 U21 ADDR22 U22 ADDR26 Pin No. Mnemonic H22 ID1 N1 L1DAT3 N2 L1DAT5 N3 L1DAT7 N4 VDD_IO N5 VDD_IO N6 VSS N7 VSS N8 VSS N9 VSS N10 VSS N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N17 VSS N18 VDD N19 VDD_IO N20 SDWE N21 MSSD N22 LDQM V1 DATA34 V2 DATA41 V3 DATA35 V4 VDD_IO V5 VDD V6 VDD V7 VDD_IO V8 VDD V9 VDD V10 VDD V11 VDD V12 VDD_IO V13 VDD V14 VSS V15 VDD V16 VDD V17 VDD V18 VDD V19 VDD_IO V20 ADDR14 V21 ADDR19 V22 ADDR24 Rev. C | Page 38 of 48 | Pin No. Mnemonic J22 MSH P1 L1DAT4 P2 L1CLKOUT P3 L1CLKIN P4 VDD_IO P5 VDD P6 VSS P7 VSS P8 VSS P9 VSS P10 VSS P11 VSS P12 VSS P13 VSS P14 VSS P15 VSS P16 VSS P17 VSS P18 VDD_IO P19 VDD_IO P20 ADDR31 P21 RAS P22 SDCKE W1 DATA40 W2 DATA43 W3 DATA46 W4 VDD_IO W5 VDD_IO W6 VDD_IO W7 VDD_IO W8 VDD_IO W9 VDD_IO W10 VDD_IO W11 VDD_IO W12 VDD_IO W13 VDD_IO W14 VDD_IO W15 VDD_IO W16 VDD_IO W17 VDD_IO W18 VDD_IO W19 VDD_IO W20 ADDR12 W21 ADDR17 W22 ADDR20 May 2009 Pin No. K22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Mnemonic WRL L1DAT6 DATA32 DATA33 VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO ADDR28 ADDR29 CAS DATA42 DATA45 L2DAT5 DATA48 DATA52 DATA58 DATA60 DATA63 L2DAT4 L2CLKOUT NC BR4 ACK CPA ADDR0 BR7 HBG ADDR1 ADDR11 ADDR21 ADDR18 ADDR16 ADSP-TS101S Table 35. 484-Ball (19 mm 19 mm) PBGA Pin Assignments (Continued) Pin No. AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 Mnemonic DATA44 DATA50 DATA47 DATA49 DATA51 DATA54 DATA57 DATA61 L2DAT0 Pin No. AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 2 1 Mnemonic L2DAT3 L2DAT7 BR2 BR6 HBR DPA ADDR2 ADDR5 ADDR8 4 3 6 5 Pin No. AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 8 7 10 9 Mnemonic SDA10 ADDR10 ADDR13 ADDR15 VSS DATA53 DATA55 DATA56 DATA59 14 12 11 13 Pin No. AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 16 15 20 18 17 19 Mnemonic DATA62 L2DAT1 L2DAT2 L2DAT6 L2CLKIN L2DIR BR0 BR1 BR3 22 Pin No. AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 TOP VIEW 21 A B C D E F G KEY: H J VDD K VDD_IO L VSS M SIGNAL N VDD_A P VSS_A R T U V W Y AA AB Figure 41. 484-Ball PBGA Pin Configurations (Top View, Summary) Rev. C | Page 39 of 48 | May 2009 Mnemonic BR5 BOFF ADDR3 ADDR4 ADDR6 ADDR7 ADDR9 VSS ADSP-TS101S Table 36. 625-Ball (27 mm 27 mm) PBGA Pin Assignments Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 Mnemonic VSS DATA17 DATA14 DATA11 DATA9 DATA7 DATA4 DATA1 L0DIR L0DAT7 L0DAT4 L0DAT1 LCLK_N LCLK_P VDD_A SCLK_N VREF DS1 CONTROLIMP2 RESET DMAR2 EMU TRST TMS VSS DATA26 DATA25 DATA24 VDD_IO VDD_IO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_IO BM BUSLOCK TMR0E Pin No. Mnemonic B1 VSS B2 VSS B3 DATA16 B4 DATA13 B5 DATA12 B6 DATA10 B7 DATA5 B8 DATA2 B9 NC B10 L0CLKOUT B11 L0DAT5 B12 L0DAT2 B13 VSS B14 VSS B15 VSS_A B16 SCLK_P B17 VSS B18 DS2 B19 CONTROLIMP1 B20 DMAR3 B21 DMAR0 B22 IRQ3 B23 TCK B24 IRQ1 B25 TDO G1 DATA29 G2 DATA28 G3 DATA27 G4 VDD_IO G5 VDD G6 VDD G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS G12 VSS G13 VSS G14 VSS G15 VSS G16 VSS G17 VSS G18 VSS G19 VSS G20 VDD G21 VDD G22 VDD_IO G23 FLAG3 G24 FLAG2 G25 FLAG1 Pin No. Mnemonic C1 VSS C2 DATA20 C3 DATA21 C4 DATA18 C5 DATA15 C6 DATA8 C7 DATA6 C8 DATA3 C9 DATA0 C10 L0CLKIN C11 L0DAT6 C12 L0DAT3 C13 L0DAT0 C14 VSS_A C15 VDD_A C16 VSS C17 DS0 C18 CONTROLIMP0 C19 DMAR1 C20 TDI C21 IRQ2 C22 LCLKRAT0 C23 LCLKRAT1 C24 IRQ0 C25 VSS H1 L3DAT0 H2 DATA31 H3 DATA30 H4 VDD_IO H5 VDD H6 VDD H7 VSS H8 VSS H9 VSS H10 VSS H11 VSS H12 VSS H13 VSS H14 VSS H15 VSS H16 VSS H17 VSS H18 VSS H19 VSS H20 VDD H21 VDD_IO H22 VDD_IO H23 FLAG0 H24 ID2 H25 ID1 Rev. C | Page 40 of 48 | Pin No. Mnemonic D1 VSS D2 VSS D3 DATA19 D4 VDD_IO D5 VDD_IO D6 VDD_IO D7 VDD_IO D8 VDD_IO D9 VDD_IO D10 VDD_IO D11 VDD_IO D12 VDD_IO D13 VDD_IO D14 VDD_IO D15 VDD_IO D16 VDD_IO D17 VDD_IO D18 VDD_IO D19 VDD_IO D20 VDD_IO D21 VDD_IO D22 VDD_IO D23 BMS D24 VSS D25 VSS J1 L3DAT3 J2 L3DAT2 J3 L3DAT1 J4 VDD_IO J5 VDD_IO J6 VDD J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS J13 VSS J14 VSS J15 VSS J16 VSS J17 VSS J18 VSS J19 VSS J20 VDD J21 VDD_IO J22 VDD_IO J23 ID0 J24 NC J25 NC May 2009 Pin No. E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 Mnemonic DATA23 DATA22 VSS VDD_IO VDD_IO VDD VDD VDD_IO VDD_IO VDD VDD VDD_IO VDD_IO VDD VDD VDD_IO VDD_IO VDD VDD VDD_IO VDD_IO VDD_IO VSS SCLKFREQ LCLKRAT2 L3DAT6 L3DAT5 L3DAT4 VDD_IO VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO NC NC NC ADSP-TS101S Table 36. 625-Ball (27 mm 27 mm) PBGA Pin Assignments (Continued) Pin No. Mnemonic L1 L3CLKIN L2 L3CLKOUT L3 L3DAT7 L4 VDD_IO L5 VDD L6 VDD L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS L13 VSS L14 VSS L15 VSS L16 VSS L17 VSS L18 VSS L19 VSS L20 VDD L21 VDD L22 VDD_IO L23 NC L24 NC L25 FLYBY T1 NC T2 L1DIR T3 L1CLKIN T4 VDD_IO T5 VDD T6 VDD T7 VSS T8 VSS T9 VSS T10 VSS T11 VSS T12 VSS T13 VSS T14 VSS T15 VSS T16 VSS T17 VSS T18 VSS T19 VSS T20 VDD T21 VDD_IO T22 VDD_IO T23 SDCKE T24 NC T25 SDWE Pin No. Mnemonic M1 L1DAT0 M2 NC M3 L3DIR M4 VDD_IO M5 VDD M6 VDD M7 VSS M8 VSS M9 VSS M10 VSS M11 VSS M12 VSS M13 VSS M14 VSS M15 VSS M16 VSS M17 VSS M18 VSS M19 VSS M20 VDD M21 VDD_IO M22 VDD_IO M23 IOEN M24 MSH M25 BRST U1 DATA34 U2 DATA33 U3 DATA32 U4 VDD_IO U5 VDD_IO U6 VDD U7 VSS U8 VSS U9 VSS U10 VSS U11 VSS U12 VSS U13 VSS U14 VSS U15 VSS U16 VSS U17 VSS U18 VSS U19 VSS U20 VDD U21 VDD_IO U22 VDD_IO U23 CAS U24 NC U25 RAS Pin No. N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 Rev. C | Mnemonic L1DAT2 NC L1DAT1 VDD_IO VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD_IO VDD_IO WRH WRL RD DATA37 DATA36 DATA35 VDD_IO VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO ADDR31 ADDR30 ADDR29 Page 41 of 48 | Pin No. P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 May 2009 Mnemonic L1DAT5 L1DAT4 L1DAT3 VDD_IO VDD_IO VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO MS1 MS0 HDQM DATA40 DATA39 DATA38 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO ADDR28 NC ADDR27 Pin No. R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Mnemonic L1CLKOUT L1DAT7 L1DAT6 VDD_IO VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD_IO LDQM NC MSSD DATA43 DATA42 DATA41 VDD_IO VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_IO VDD_IO ADDR26 ADDR25 ADDR24 ADSP-TS101S Table 36. 625-Ball (27 mm 27 mm) PBGA Pin Assignments (Continued) Pin No. Mnemonic AA1 DATA46 AA2 DATA45 AA3 DATA44 AA4 VDD_IO AA5 VDD_IO AA6 VDD_IO AA7 VDD AA8 VDD AA9 VDD_IO AA10 VDD_IO AA11 VDD AA12 VDD AA13 VDD_IO AA14 VDD_IO AA15 VDD AA16 VDD AA17 VDD_IO AA18 VDD_IO AA19 VDD AA20 VDD AA21 VDD_IO AA22 VDD_IO AA23 ADDR23 AA24 ADDR22 AA25 ADDR21 Pin No. Mnemonic AB1 DATA49 AB2 DATA48 AB3 DATA47 AB4 VDD_IO AB5 VDD_IO AB6 VDD_IO AB7 VDD_IO AB8 VDD_IO AB9 VDD_IO AB10 VDD_IO AB11 VDD_IO AB12 VDD_IO AB13 VDD_IO AB14 VDD_IO AB15 VDD_IO AB16 VDD_IO AB17 VDD_IO AB18 VDD_IO AB19 VDD_IO AB20 VDD_IO AB21 VDD_IO AB22 VDD_IO AB23 ADDR20 AB24 ADDR19 AB25 ADDR18 2 1 4 3 6 5 Pin No. Mnemonic AC1 VSS AC2 VSS AC3 DATA50 AC4 DATA51 AC5 DATA54 AC6 DATA57 AC7 DATA60 AC8 DATA63 AC9 L2DAT2 AC10 L2DAT5 AC11 L2CLKOUT AC12 NC AC13 BR2 AC14 BR5 AC15 ACK AC16 HBG AC17 ADDR0 AC18 ADDR3 AC19 ADDR6 AC20 ADDR9 AC21 ADDR11 AC22 ADDR14 AC23 VSS AC24 ADDR17 AC25 ADDR16 8 7 10 9 14 12 11 13 16 15 Pin No. Mnemonic AD1 VSS AD2 VSS AD3 VSS AD4 DATA52 AD5 DATA55 AD6 DATA58 AD7 DATA61 AD8 L2DAT0 AD9 L2DAT3 AD10 L2DAT6 AD11 L2CLKIN AD12 BR0 AD13 BR3 AD14 BR6 AD15 HBR AD16 CPA AD17 ADDR1 AD18 ADDR4 AD19 ADDR7 AD20 SDA10 AD21 ADDR12 AD22 ADDR15 AD23 VSS AD24 VSS AD25 VSS 20 18 17 19 24 22 21 23 Pin No. AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 TOP VIEW 25 A B C D E F G H KEY: J K VDD L VDD_IO M N VSS P SIGNAL R VDD_A T VSS_A U V W Y AA AB AC AD AE Figure 42. 625-Ball PBGA Pin Configurations (Top View, Summary) Rev. C | Page 42 of 48 | May 2009 Mnemonic VSS VSS VSS DATA53 DATA56 DATA59 DATA62 L2DAT1 L2DAT4 L2DAT7 L2DIR BR1 BR4 BR7 BOFF DPA ADDR2 ADDR5 ADDR8 ADDR10 ADDR13 VSS VSS VSS VSS ADSP-TS101S OUTLINE DIMENSIONS The ADSP-TS101S is available in a 19 mm x 19 mm, 484-ball PBGA package with 22 rows of balls (B-484); the DSP also is available in a 27 mm x 27 mm, 625-ball PBGA package with 25 rows of balls (B-625). 19.10 19.00 18.90 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB 1.10 BSC 19.10 19.00 18.90 17.05 16.95 16.85 16.80 BSC SQ 0.80 BSC SQ BALL PITCH 1.10 BSC 17.05 16.95 16.85 19.10 19.00 SQ 18.90 TOP VIEW BOTTOM VIEW DETAIL A 1.30 MAX 0.65 0.55 0.45 2.50 MAX NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 mm OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. CENTER DIMENSIONS ARE NOMINAL. SEATING PLANE 0.55 0.50 0.45 BALL DIAMETER DETAIL A Figure 43. 484-Ball PBGA (B-484) Rev. C | Page 43 of 48 | May 2009 0.40 MIN 0.20 MAX ADSP-TS101S 27.20 27.00 26.80 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 1.50 BSC SQ 24.20 24.00 23.80 24.00 BSC SQ 27.20 27.00 26.80 1.00 BSC SQ BALL PITCH 1.50 BSC SQ 24.20 24.00 23.80 27.20 27.00 SQ 26.80 TOP VIEW BOTTOM VIEW DETAIL A 1.25 MAX 0.65 0.55 0.45 2.50 MAX NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 mm OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. CENTER DIMENSIONS ARE NOMINAL. 4. THIS PACKAGE COMPLIES WITH THE JEDEC MS-034 SPECIFICATION, BUT USES TIGHTER TOLERANCES THAN THE MAXIMUMS ALLOWED IN THAT SPECIFICATION. SEATING PLANE BALL DIAMETER 0.70 0.60 0.50 0.40 MIN 0.20 MAX DETAIL A Figure 44. 625-Ball PBGA (B-625) SURFACE-MOUNT DESIGN The following table is provided as an aide to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Package 625-ball (27 mm) PBGA 484-ball (19 mm) PBGA Ball Attach Type Solder Mask Defined (SMD) Solder Mask Defined (SMD) Rev. C | Solder Mask Opening 0.45 mm diameter 0.40 mm diameter Page 44 of 48 | May 2009 Ball Pad Size 0.60 mm diameter 0.53 mm diameter ADSP-TS101S ORDERING GUIDE Part Number1, 2, 3, 4 ADSP-TS101SAB1-000 ADSP-TS101SAB1-100 ADSP-TS101SAB1Z000 ADSP-TS101SAB1Z100 ADSP-TS101SAB2-000 ADSP-TS101SAB2-100 ADSP-TS101SAB2Z000 ADSP-TS101SAB2Z100 Temperature Range (Case) -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Core Clock (CCLK) Rate5 250 MHz 300 MHz 250 MHz 300 MHz 250 MHz 300 MHz 250 MHz 300 MHz On-Chip SRAM 6M Bit 6M Bit 6M Bit 6M Bit 6M Bit 6M Bit 6M Bit 6M Bit Package Description 625-Ball Plastic Ball Grid Array (PBGA) 625-Ball Plastic Ball Grid Array (PBGA) 625-Ball Plastic Ball Grid Array (PBGA) 625-Ball Plastic Ball Grid Array (PBGA) 484-Ball Plastic Ball Grid Array (PBGA) 484-Ball Plastic Ball Grid Array (PBGA) 484-Ball Plastic Ball Grid Array (PBGA) 484-Ball Plastic Ball Grid Array (PBGA) 1 S indicates 1.2 V and 3.3 V supplies. A indicates -40C to +85C temperature. 3 000 indicates 250 MHz speed grade; 100 indicates 300 MHz speed grade. 4 Z indicates RoHS compliant part. 5 The instruction rate runs at the internal DSP clock (CCLK) rate. 6 The B-625 package measures 27 mm 27 mm. 7 The B-484 package measures 19 mm 19 mm. 2 Rev. C | Page 45 of 48 | May 2009 Package Option B-6256 B-6256 B-6256 B-6256 B-4847 B-4847 B-4847 B-4847 ADSP-TS101S Rev. C | Page 46 of 48 | May 2009 ADSP-TS101S Rev. C | Page 47 of 48 | May 2009 ADSP-TS101S (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03164-0-5/09(C) Rev. C | Page 48 of 48 | May 2009