TNL17SZ74USG - ON Semiconductor - Datasheet.Directory

April, 2006 − Rev. 4 1Publication Order Number:

NL17SZ74/D

NL17SZ74

Single D Flip Flop

The NL17SZ74 is a high performance, full function Edge triggered

D Flip Flop, with all the features of a standard logic device such as the

74LCX74.

Features

•Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5.0 V

•Designed for 1.65 V to 5.5 V VCC Operation

•5.0 V Tolerant Inputs − Interface Capability with 5.0 V TTL Logic

•LVTTL Compatible

•LVCMOS Compatible

•24 mA Balanced Output Sink and Source Capability

•Near Zero Static Supply Current (10 mA) Substantially Reduces

System Power Requirements

•Replacement for NC7SZ74

•Tiny Ultra Small Package Only 2.1 X 3.0 mm

•High ESD Ratings: 2000 V Human Body Model

High ESD Ratings: 200 V Machine Model

•Chip Complexity: FET = 64

•Pb−Free Packages are Available

TRUTH TABLE

Inputs Outputs

Operating Mode

PR CLR CP D Q Q

Asynchronous Set

Asynchronous Clear

Undetermined

H↑

↑h

HLoad and Read Register

H H ↑X NC NC Hold

H = High Voltage Level

h = High Voltage Level One Setup Time Prior to the Low−to−High

Clock Transition

L = Low Voltage Level

l = Low Voltage Level One Setup Time Prior to the Low−to−High

Clock Transition

NC = No Change

X = High or Low Voltage Level and Transitions are Acceptable

↑= Low−to−High Transition

↑= Not a Low−to−High T ransition

For ICC reasons, DO NOT FLOAT Inputs

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See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAM

US8

US SUFFIX

CASE 493

PINOUT DIAGRAM

VCC

CLR

GND

CP 1

CLR

VCC = 8, GND = 4

LOGIC DIAGRAM

M = Date Code

G= Pb−Free Package

MH M

NL17SZ74

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MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage −0.5 to +7.0 V

VIDC Input Voltage −0.5 to +7.0 V

VODC Output Voltage − Output in High or Low State (Note 1) −0.5 to VCC +0.5 V

IIK DC Input Diode Current VI < GND −50 mA

IOK DC Output Diode Current VO < GND −50 mA

IODC Output Sink Current ±50 mA

ICC DC Supply Current Per Supply Pin ±100 mA

IGND DC Ground Current Per Ground Pin ±100 mA

TSTG Storage Temperature Range −65 to +150 °C

TLLead Temperature, 1 mm from Case for 10 Seconds 260 °C

TJJunction Temperature Under Bias +150 °C

qJA Thermal Resistance (Note 2) 250 °C/W

PDPower Dissipation in Still Air at 85°C 250 mW

MSL Moisture Sensitivity Level 1

FRFlammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

VESD ESD Withstand Voltage Human Body Model (Note 3)

Machine Model (Note 4)

Charged Device Model (Note 5)

>2000

>200

N/A

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended O p e r a t i n g Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. IO absolute maximum rating must be observed.

2. Measured with minimum pad spacing on an FR4 board, using 10 mm X 1 inch, 2 ounce copper trace with no air flow.

3. Tested to EIA/JESD22−A114−A.

4. Tested to EIA/JESD22−A115−A.

5. Tested to JESD22−C101−A.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC Supply Voltage Operating

Data Retention Only 1.65

1.5 5.5

5.5 V

VIInput Voltage (Note 6) 0 5.5 V

VOOutput Voltage (HIGH or LOW State) 0 VCC V

TAOperating Free−Air Temperature −40 +85 °C

Dt/DVInput Transition Rise or Fall Rate VCC = 2.5 V ±0.2 V

VCC = 3.0 V ±0.3 V

VCC = 5.0 V ±0.5 V

5.0

ns/V

6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.

ORDERING INFORMATION

Device Package Shipping†

NL17SZ74US US8 3000 / Tape & Reel

NL17SZ74USG US8

(Pb−Free) 3000 / Tape & Reel

TNL17SZ74USG US8

(Pb−Free) 3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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DETAILED DEVICE ORDERING INFORMATION

Device Order

Number

Device Nomenclature

Package

Type Tape and

Reel Size

Logic

Circuit

Indicator

No. of

Gates per

Package

Temp

Range

Identifier Technology Device

Function Package

Suffix

NL17SZ74US NL 1 7 SZ 74 US US8 178 mm, 3000 Unit

DC ELECTRICAL CHARACTERISTICS

Symbo

Parameter Condition VCC

(V)

TA = 25_C*40_C v TA v 85_C

Unit

Min Typ Max Min Max

VIH High−Level Input Voltage 1.65 0.75 VCC 0.75 VCC V

2.3 to 5.5 0.7 VCC 0.7 VCC

VIL Low−Level Input Voltage 1.65 0.25 VCC 0.25 VCC V

2.3 to 5.5 0.3 VCC 0.3 VCC

VOH High−Level Output Voltage

VIN = VIL or VIL

IOH = 100 mA

IOH = − 3 mA

IOH = − 8 mA

IOH = − 12 mA

IOH = − 16 mA

IOH = − 24 mA

= − 32 mA

1.65 to 5.5

1.65

2.3

2.7

3.0

4.5

VCC − 0 .1

1.29

1.9

2.2

2.4

2.3

3.8

VCC

1.52

2.1

2.4

2.7

2.5

4.0

VCC − 0 .1

1.29

1.9

2.2

2.4

2.3

3.8

VOL Low−Level Output Voltage

VIN = VIH

IOL = 100 mA

IOL = 3 mA

IOL = 8 mA

IOL = 12 mA

IOL = 16 mA

IOL = 24 mA

= 32 mA

1.65 to 5.5

1.65

2.3

2.7

3.0

4.5

0.008

0.10

0.12

0.15

0.19

0.30

0.1

0.24

0.3

0.4

0.55

0.1

0.24

0.3

0.4

0.55

IIN Input Leakage Current VIN = VCC or GND 5.5 $0.1 $1.0 mA

IOFF Power off Input

Leakage Current 5.5V or VIN = GND 0 1.0 10 mA

ICC Quiescent Supply Current VIN = VCC or GND 5.5 1.0 10 mA

NL17SZ74

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

Symbo

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

VCC (V)

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎ

TA = −40 to 85°C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

fMAX

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Maximum Clock

Frequency

(50% Duty Cycle)

(Waveform 1)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

MHz

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

150

ÎÎÎ

150

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

200

ÎÎÎ

200

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

250

ÎÎÎ

250

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

175

ÎÎÎ

175

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

200

ÎÎÎ

200

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Propagation Delay,

CP to Q or Q

(Waveform 1)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

2.5

ÎÎÎ

6.5

ÎÎÎ

12.5

ÎÎÎ

2.5

ÎÎÎ

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

1.5

ÎÎÎ

3.8

ÎÎÎ

7.5

ÎÎÎ

1.5

ÎÎÎ

8.0

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

1.0

ÎÎÎ

2.8

ÎÎÎ

6.5

ÎÎÎ

1.0

ÎÎÎ

7.0

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

0.8

ÎÎÎ

2.2

ÎÎÎ

4.5

ÎÎÎ

0.8

ÎÎÎ

5.0

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

1.0

ÎÎÎ

3.4

ÎÎÎ

7.0

ÎÎÎ

1.0

ÎÎÎ

7.5

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

1.0

ÎÎÎ

2.6

ÎÎÎ

5.0

ÎÎÎ

1.0

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Propagation Delay,

PR or CLR to Q or Q

(Waveform 2)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

2.5

ÎÎÎ

6.5

ÎÎÎ

2.5

ÎÎÎ

14.5

ÎÎÎ

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

1.5

ÎÎÎ

3.8

ÎÎÎ

9.0

ÎÎÎ

1.5

ÎÎÎ

9.5

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

1.0

ÎÎÎ

2.8

ÎÎÎ

6.5

ÎÎÎ

1.0

ÎÎÎ

7.0

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

0.8

ÎÎÎ

2.2

ÎÎÎ

5.0

ÎÎÎ

0.8

ÎÎÎ

5.5

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

1.0

ÎÎÎ

3.4

ÎÎÎ

7.0

ÎÎÎ

1.0

ÎÎÎ

7.5

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

1.0

ÎÎÎ

2.6

ÎÎÎ

5.0

ÎÎÎ

1.0

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Setup Time, D to CP

(Waveform 1)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

6.5

ÎÎÎ

6.5

ÎÎÎ

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

3.5

ÎÎÎ

3.5

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

1.5

ÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

1.5

ÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Hold Time, D to CP

(Waveform 1)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

0.5

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Pulse Width,

CP, CLR, PR

(Waveform 3)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

6.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

4.0

ÎÎÎ

4.0

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tREC

ÎÎÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Recover Time

PR; CLR to CP

(Waveform 3)

ÎÎÎÎÎ

1.8 ± 0.15

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

CL = 15 pF

RD = 1 MW

S1 = Open

ÎÎÎ

8.0

ÎÎÎ

8.0

ÎÎÎ

MHz

ÎÎÎÎÎ

2.5 ± 0.2

ÎÎÎ

4.5

ÎÎÎ

4.5

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

ÎÎÎÎÎ

3.3 ± 0.3

ÎÎÎÎÎÎÎÎ

CL = 50 pF,

RD = 500 W, S1 = Open

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

ÎÎÎÎÎ

5.0 ± 0.5

ÎÎÎ

3.0

ÎÎÎ

3.0

ÎÎÎ

7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/2 (per flip−flop). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

CAPACITANCE (Note 8)

Symbol Parameter Condition Typical Unit

CIN Input Capacitance VCC = 5.5 V 7.0 pF

COUT Output Capacitance VCC = 5.5 V 7.0 pF

CPD Power Dissipation Capacitance (Note 9)

Frequency = 10 MHz VCC = 3.3 V

VCC = 5.0 V 16

21 pF

8. TA = +25°C, f = 1 MHz

9. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at

no output loading and operating at 50% duty cycle. (See Figure 1) CPD is related to ICCD dynamic operating current by the expression:

ICCD = CPD  VCC  fin + ICC(static).

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trec

WAVEFORM 3 − RECOVERY TIME

tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns

Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V

Vcc

0 V

Vcc

0 V

50%

Figure 1. AC Waveforms

WAVEFORM 2 − PROPAGATION DELAYS

tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

PR, CLR

Vcc

0 V

CLR 50%

Vcc

0 V

VOH

50%

VOL

50%

tPLH tPHL

tPHL

tPLH

WAVEFORM 1 − PROPAGATION DELAYS, SETUP AND HOLD TIMES

tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns

Vcc

0 V

50%

Vcc

0 V

VOH

VOL

tPLH, tPHL

50%

fmax

50%

PULSE

GENERATOR RT

DUT

VCC

Figure 2. Test Circuit

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PACKAGE DIMENSIONS

US8

US SUFFIX

CASE 493−02

ISSUE B

DIM

AMIN MAX MIN MAX

INCHES

1.90 2.10 0.075 0.083

MILLIMETERS

B2.20 2.40 0.087 0.094

C0.60 0.90 0.024 0.035

D0.17 0.25 0.007 0.010

F0.20 0.35 0.008 0.014

G0.50 BSC 0.020 BSC

H0.40 REF 0.016 REF

J0.10 0.18 0.004 0.007

K0.00 0.10 0.000 0.004

L3.00 3.20 0.118 0.126

M0 6 0 6

N5 10 5 10

P0.23 0.34 0.010 0.013

R0.23 0.33 0.009 0.013

S0.37 0.47 0.015 0.019

U0.60 0.80 0.024 0.031

V0.12 BSC 0.005 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION “A” DOES NOT INCLUDE MOLD

FLASH, PROTRUSION OR GATE BURR.

MOLD FLASH. PROTRUSION AND GATE

BURR SHALL NOT EXCEED 0.140 MM

(0.0055”) PER SIDE.

4. DIMENSION “B” DOES NOT INCLUDE

INTER−LEAD FLASH OR PROTRUSION.

INTER−LEAD FLASH AND PROTRUSION

SHALL NOT E3XCEED 0.140 (0.0055”) PER

SIDE.

5. LEAD FINISH IS SOLDER PLATING WITH

THICKNESS OF 0.0076−0.0203 MM.

(300−800 “).

6. ALL TOLERANCE UNLESS OTHERWISE

SPECIFIED ±0.0508 (0.0002 “).

SEATING

DETAIL E

NR 0.10 TYP

−Y−

−X−

−T−

DETAIL E

0.10 (0.004) XY

T0.10 (0.004)

____

PLANE

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ǒmm

inchesǓ

SCALE 8:1

3.8

0.015

0.50

0.0197

1.0

0.0394

0.30

0.012

1.8

0.07

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

NL17SZ74/D

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