Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
DESCRIPTION QUICK REFERENCE DATA
Monolithic overload protected logic SYMBOL PARAMETER MAX. UNIT
level power MOSFET in a surface
mount plastic envelope, intended as VDS Continuous drain source voltage 50 V
a general purpose switch for
automotive systems and other IDContinuous drain current 0.7 A
applications. PDTotal power dissipation 1.8 W
APPLICATIONS TjContinuous junction temperature 150 ˚C
General controller for driving
lamps RDS(ON) Drain-source on-state resistance 200 mΩ
small motors
solenoids
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Overload protected up to
85˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
Fig.1. Elements of the TOPFET.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 drain
3 source
4 drain (tab)
POWER
MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
RIG
4
123
P
D
S
I
TOPFET
March 1997 1 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Continuous drain source voltage1- - 50 V
IDContinuous drain current2- - self limiting A
IIContinuous input current clamping - 3 mA
IIRM Non-repetitive peak input current tp ≤ 1 ms - 10 mA
PDTotal power dissipation Tamb = 25 ˚C - 1.8 W
Tstg Storage temperature - -55 150 ˚C
TjContinuous junction temperature normal operation3- 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCElectrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EDSM Non-repetitive clamping energy Tb ≤ 25 ˚C; IDM < ID(lim); - 100 mJ
inductive load
EDRM Repetitive clamping energy Tb ≤ 75 ˚C; IDM = 50 mA; - 4 mJ
f = 250 Hz
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from short circuit loads.
Overload protection operates by means of drain current limiting and activating the overtemperature protection.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDP Protected drain source supply voltage VIS = 5 V - 35 V
VIS = 4 V - 16 V
OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off to protect itself when there is an overload fault condition.
It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Overload protection
ID(lim) Drain current limiting VIS = 5 V 0.7 1.1 1.5 A
Overtemperature protection only in drain current limiting
Tj(TO) Threshold junction temperature VIS = 5 V 100 130 160 ˚C
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Not in an overload condition with drain current limiting.
March 1997 2 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
Rth j-sp Junction to solder point - 12 18 K/W
Rth j-b Junction to board1Mounted on any PCB - 40 - K/W
Rth j-a Junction to ambient Mounted on PCB of fig. 19 - - 70 K/W
STATIC CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA 50 55 - V
V(CL)DSS Drain-source clamping voltage VIS = 0 V; IDM = 200 mA; - 56 70 V
tp ≤ 300 µs; δ ≤ 0.01
IDSS Off-state drain current VDS = 45 V; VIS = 0 V - 0.5 2 µA
IDSS Off-state drain current VDS = 50 V; VIS = 0 V - 1 20 µA
IDSS Off-state drain current VDS = 40 V; VIS = 0 V; Tj = 100 ˚C - 10 100 µA
RDS(ON) Drain-source on-state VIS = 5 V; IDM = 100 mA; - 150 200 mΩ
resistance2tp ≤ 300 µs; δ ≤ 0.01
INPUT CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA 1.7 2.2 2.7 V
IIS Input supply current normal operation; VIS = 5 V - 330 450 µA
VIS = 4 V - 170 270 µA
IISL Input supply current protection latched; VIS = 5 V - 500 650 µA
VIS = 3.5 V - 250 400 µA
VISR Protection latch reset voltage31 2.2 3.5 V
V(CL)IS Input clamping voltage II = 1.5 mA 6 7.5 - V
RIG Input series resistance to gate of power MOSFET - 33 - kΩ
SWITCHING CHARACTERISTICS
Tamb = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
td on Turn-on delay time VIS = 0 V to VIS = 5 V - 8 - µs
trRise time - 30 - µs
td off Turn-off delay time VIS = 5 V to VIS = 0 V - 3 - µs
tfFall time - 6 - µs
1 Temperature measured 1.3 mm from tab.
2 Continuous input voltage. The specified pulse width is for the drain current.
3 The input voltage below which the overload protection circuits will be reset.
March 1997 3 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
Fig.2. Normalised limiting power dissipation.
P
D
% = 100
⋅
P
D
/P
D
(25 ˚C) = f(T
mb
)
Fig.3. Continuous drain current.
I
D
= f(T
amb
); condition: V
IS
= 5 V
Fig.4. Typical on-state characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
IS
; t
p
= 300
µ
s
Fig.5. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)
25 ˚C = f(T
j
); I
D
= 100 mA; V
IS
= 5 V
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
IS
); conditions: I
D
= 100 mA, t
p
= 300
µ
s
Fig.7. Typical transfer characteristics, T
j
= 25 ˚C.
I
D
= f(V
IS
); conditions: V
DS
= 10 V, t
p
= 300
µ
s
0 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
aNormalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
0 20 40 60 80 100 120 140
Tamb / C
ID / A BUK107-50DL
2.0
1.5
1.0
0.5
0
WITHIN THE SHADED REGION
CURRENT LIMITING OCCURS
TYP.
0 2 4 6 8 10
VIS / V
RDS(ON) / mOhm BUK107-50DL
240
200
160
120
80
40
0
TYP.
MAX.
0 4 8 12 16 20 24 28 32
VDS / V
ID / A BUK107-50DL
1.5
1
0.5
0
VIS / V = 7
6
5
4
0 2 4 6 8 10
VIS / V
ID / A BUK107-50DL
1.5
1
0.5
0
March 1997 4 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
Fig.8. Typical overtemperature protection threshold.
T
j(TO)
= f(V
IS
); condition: V
DS
= 10 V
Fig.9. Typical DC input characteristics, T
j
= 25 ˚C.
I
IS
& I
ISL
= f(V
IS
); normal operation & protection latched
Fig.10. Typical DC input current.
I
IS
= f(T
j
); parameter V
IS
; normal operation
Fig.11. Input threshold voltage.
V
IS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= 5 V
Fig.12. Typical input clamping characteristic.
I
I
= f(V
IS
); normal operation, T
j
= 25 ˚C.
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
I
D
= f(V
DS
); conditions: V
IS
= 0 V; t
p
≤
300
µ
s
0 2 4 6 8 10
VIS / V
Tj(TO) / C BUK107-50DL
200
180
160
140
120
100
80
60
TYP.
-50 050 150
Tj / C
VIS(TO) / V BUK107-50DL
3
2
1
TYP.
MAX.
MIN.
100
0 2 4 6 8
VIS / V
IIS & IISL / mA BUK107-50DL
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IISL
IIS
RESET
NORMAL
LATCHED
0 2 4 6 8 10
VIS / V
II / mA BUK107-50DL
10
9
8
7
6
5
4
3
2
1
0
-50 50 150
Tj / C
IIS / uA BUK107-50DL
500
400
300
200
100
0 1000
5 V
4 V
VIS / V =
50 52 54 56 58 60
VDS / V
ID / mA BUK107-50DL
200
150
100
50
0
TYP.
March 1997 5 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
Fig.14. Test circuit for resistive load switching times.
V
IS
= 5 V
Fig.15. Typical switching waveforms, resistive load .
R
L
= 50
Ω
; adjust V
DD
to obtain I
D
= 250 mA; T
j
= 25˚C
Fig.16. Typical drain source leakage current
I
DSS
= f(T
j
); conditions: V
DS
= 40 V; V
IS
= 0 V.
VDD
D.U.T.
0V
VIS
D
S
I
TOPFET
P
RL
VDS
measure
-50 50 150
Tj / C
IDSS BUK107-50DL
10 uA
1 uA
100 nA
10 nA 1000
-20 0 20 40 60 80 100 120 140 160 180
time / us
VIS & VDS / V BUK107-50DL
15
10
5
0
VIS
VDS
Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19.
Z
th j-amb
= f(t); parameter D = t
p
/T
0.5
0.2
0.1
0.05
0.02
1E-07 1E-05 1E-03 1E-01 1E+01 1E+03
t / s
Zth j-amb / (K/W)
1E+02
1E+01
1E+00
1E-01
1E-02 0
BUK107-50DL
D =
t
p
t
p
T
T
P
t
D
D =
March 1997 6 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
MOUNTING INSTRUCTIONS
Dimensions in mm.
Fig.18. Soldering pattern for surface mounting.
PRINTED CIRCUIT BOARD
Dimensions in mm.
Fig.19. PCB for thermal resistance and power rating.
PCB: FR4 epoxy glass (1.6 mm thick),
copper laminate (35
µ
m thick).
36
60
9
10
4.6
18
4.5
7
15
50
3.8
min
6.3
2.3
4.6
1.5
min
1.5
min
1.5
min
(3x)
March 1997 7 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
MECHANICAL DATA
Dimensions in mm
Net Mass: 0.11 g
Fig.20. SOT223 surface mounting package
1
.
handbook, full pagewidth
6.7
6.3
0.95
0.85
2.3 0.80
0.60
4.6
3.1
2.9
3.7
3.3 7.3
6.7
A
B
0.2 A
1.80
max
16
16
o
max
10
o
max
0.10
0.01
0.32
0.24
4
123
MSA035 - 1
(4x)
0.1 B
M
M
S seating plane 0.1 S
o
1 For further information, refer to surface mounting instructions for SOT223 envelope. Epoxy meets UL94 V0 at 1/8".
March 1997 8 Rev 1.200
Philips Semiconductors Product specification
PowerMOS transistor BUK107-50DL
Logic level TOPFET
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
March 1997 9 Rev 1.200
