3XEOLFDWLRQ1XPEHU
5HYLVLRQ
%
$PHQGPHQW
,VVXH'DWH
2FWREHU
-XO\
7KHIROORZLQJGRFXPHQWVSHFLILHV6SDQVLRQPHPRU\SURGXFWVWKDWDUHQRZRIIHUHGE\ERWK$GYDQFHG
0LFUR'HYLFHVDQG)XMLWVX$OWKRXJKWKHGRFXPHQWLVPDUNHGZLWKWKHQDPHRIWKHFRPSDQ\WKDWRULJ
LQDOO\GHYHORSHGWKHVSHFLILFDWLRQWKHVHSURGXFWVZLOO EHRIIHUHG WR FXVWRPHUVRIERWK$0' DQG
)XMLWVX
Continuity of Specifications
7KHUHLVQRFKDQJHWRWKLVGDWDVKHHWDVDUHVXOWRIRIIHULQJWKHGHYLFHDVD6SDQVLRQSURGXFW$Q\
FKDQJHVWKDWKDYHEHHQPDGHDUHWKHUHVXOWRIQRUPDOGDWDVKHHWLPSURYHPHQWDQGDUHQRWHGLQWKH
GRFXPHQWUHYLVLRQVXPPDU\ZKHUHVXSSRUWHG)XWXUHURXWLQHUHYLVLRQVZLOORFFXUZKHQDSSURSULDWH
DQGFKDQJHVZLOOEHQRWHGLQDUHYLVLRQVXPPDU\
Continuity of Ordering Part Numbers
$0'DQG)XMLWVXFRQWLQXHWRVXSSRUWH[LVWLQJSDUWQXPEHUVEHJLQQLQJZLWK$PDQG0%07RRUGHU
WKHVHSURGXFWVSOHDVHXVHRQO\WKH2UGHULQJ3DUW1XPEHUVOLVWHGLQWKLVGRFXPHQW
For More Information
3OHDVHFRQWDFW\RXUORFDO$0'RU)XMLWVXVDOHVRIILFHIRUDGGLWLRQDOLQIRUPDWLRQDERXW6SDQVLRQ
PHPRU\VROXWLRQV
Am29BDS640G
Data Sheet
ADVANCE INFORMATION
T
his document contains information on a product under development at Advanced Micro Devices. The information
i
s intended to h elp you evaluate thi s product. AMD reserves the right to chan ge or discontinue w ork on this proposed
p
roduct without notice.
Publication# 25903 Rev: B Amendment+0
Issue Date: Octobe r 31, 2002
Refer to AMD’s Website (www.amd.com) for the latest informat ion .
Am29BDS640G
64 Megabit (4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
■Manufactured on 0.17 µm process technology
■Enhanced Ve rsatileIO™ (VIO) Feature
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
— 1.8V and 3V compatible I/O signals
■Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
■Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Contin uou s Sequ ent ial Burst
■Sector Architecture
— Eight 8 Kword sectors and one hun dred twenty-six 32
Kword sectors
— Banks A and D each contain four 8 Kword sectors
and thirty-one 32 Kword sectors; Banks B and C
each contain thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address ra nge , an d f our at the bottom o f th e a ddress
range
■Minimum 1 million erase cycle guarantee per sector
■20-year data retention at 125°C
— Reliable operation for the life of the system
■80-ball FBGA package
PERFORMANCE CHARCTERISTICS
■Read access times at 54/40 MHz (at 30 pF)
— Burst access times of 13.5/20 ns
— Asynchronous random access times of 70 ns
— Initial Synchronous access times as fast as 87.5/95 ns
■Power dissipation (typical values, CL = 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standb y mod e: 0.2 µA
HARDWARE FEATURES
■Sector Protection
— Software command sector locking
■Reduced Wait-State Handshaking feature available
— Provi des ho st s y ste m wi th m inimum po ss ibl e l aten cy
by monitoring RDY
■Hardware reset input (RESET#)
— Hardware method to reset the device for reading array
data
■WP# input
— Write protect (WP#) func tion protects s ectors 0 and 1
(bottom boot), or sectors 132 and 133 (top boot),
regardless of sector protect status
■ACC input: Acceleration function reduces
programming time; all sectors locked when ACC = VIL
■CMOS compatible inputs, CMOS compatible outputs
■Low VCC write inhibit
SOFTWARE FEATURES
■Supports Common Flash Memory Interface (CFI)
■Software command set compatible with JEDEC 42.4
standards
— Backwards compatible with Am29F and Am29LV
families
■Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
■Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resume s the eras e ope rati on
■Unlock Bypas s Pro gram com man d
— Reduces overall programming time when issuing
multiple program command sequences
2 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device, orga-
nized as 4,194,304 words of 16 bits each. This device uses
a single VCC of 1.65 to 1.95 V to read , program, and er ase
the memory array. The device supports Enhanced VIO to
offer up to 3V compatible inputs and outputs. A 12.0-volt VID
may be used for faster program performance if desired. The
device can also be programmed in st andard EPROM pro-
grammers.
At 54 MHz, the device provides a burst access of 13.5 ns at
30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de-
vice provides a burst access of 20 ns at 30 pF with a latency
of 95 ns at 30 pF. The dev ice operat es within th e industri al
temperature range of -40°C to +85°C. The device is offered
in the 80-ball FBGA package.
The Simult aneous Read/Write arch itecture p rovides simul-
taneous operati on by dividing the memory space into four
banks. The device can improve overall system performance
by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank, with zero latency. This releases the system from wait-
ing for the completion of program or erase operations.
The device is divided as shown i n the following table:
The Enha nced Versati leIO™ (V IO) contro l allows the host
system to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data inputs
to th e same vol tage leve l that is asserted on the VIO pin.
This allows the device to operate in 1.8 V and 3 V system
env i ronments as required.
The device uses Chip Enable (CE#), Write Enable (WE#),
Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with
minim al glue l ogic to a wid e ran ge of micr oproc essors/m icro-
controllers for high performance read operations.
The burst read mode feature gives sy stem design ers fl ex ibi l-
ity in the interface to the device. The user can preset the
burst lengt h and wrap through the same memory space, or
read the flash array in cont inu ous mode.
The clock polarity feature provides system designers a
choice of active clock edges, either rising or falling. The ac-
tive clock edge initiates burst accesses and determines
when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 s ingle- power- supply F lash s tandar d. Com-
mands ar e writte n to the c ommand re gister us ing stan dard
micropro cessor write timing. Regist er contents ser ve as in-
puts to an internal state-machine that controls the erase and
programmi ng circuit ry. Write cycles also i ntern ally la tch ad -
dresses a nd data needed f or the p rogramming a nd erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or prog ram data to , any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in
progress an d resets th e internal stat e machine to reading
array data. The RESET# pi n may be tie d to the system res et
circuitry. A system reset would t hus also reset the device,
enabling t he system micro processor t o read boot- up firm-
ware from the Flash memory device.
The ho st sy ste m ca n d ete ct whe t he r a p rog r am or er a se op-
eration is complete by using the device status bit DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program
or eras e cy cl e has bee n complet ed, the de vic e au tom atically
returns to reading array data.
The sector eras e arch itecture allows memory secto rs to be
erased and reprogrammed without affecting t he data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The device also offers two types of data
protection at the sector level. The sector lock/unlock com-
mand sequence disables or re-enables both program and
erase operations in any sector. When at VIL, WP# locks sec-
tors 0 and 1 (bott om boot device) or sect ors 132 and 133
(top boot device).
The device offers two power-saving features. When ad-
dresses hav e been stable for a specified am ou nt of tim e, the
device ent ers the automati c sleep mode. Th e system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both modes.
AMD’s F lash te chnol ogy co mbine s year s of Fl ash m emory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using
hot electron injection.
Bank Quantity Size
A4 8 Kwords
31 32 Kw ords
B 32 32 Kwords
C 32 32 Kwords
D31 32 Kw ords
4 8 Kwords
October 31, 2002 Am29BDS640G 3
ADVANCE INFORMATION
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Special Handling Instructions for FBGA Package ....................8
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . .11
Table 1. Device Bus Operations ....................................................11
Enhanced VersatileIO™ (VIO) C ontrol ....................................11
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................11
Requirements for Synchronous (Burst) Read Operation ........12
8-, 16-, and 32-Word Linear Burst with Wrap Around ............12
Table 2. Burst Address Groups .......................................................12
Burst Mode Configuration Register ........................................12
Reduced Wait-State Handshaking Option ..............................13
Simultaneous Read/Write Operations with Zero Latency .......13
Writing Commands/Command Sequences ............................13
Accelerated Program Operation .............................................13
Autoselect Functions ..............................................................13
Standby Mode ........................................................................14
Automatic Sleep Mode ...........................................................14
RESET#: Hardware Reset Input .............................................14
Output Disable Mode ..............................................................14
Hardware Data Protection ......................................................14
Write Protect (WP#) ................................................................14
Low VCC Write Inhibit ..............................................................15
Write Pulse “Glitch” Protection ...............................................15
Logical Inhibit ..........................................................................15
Power-Up Write Inhibit ............................................................15
VCC and VIO Power-up And Power-down Sequencing ...........15
Common Flash Memory Interface (CFI) . . . . . . .15
Table 3. CFI Query Identification String ..........................................15
Table 4. System Interface String .....................................................16
Table 5. Device Geometry Definition ..............................................16
Table 6. Primary Vendor-Specific Extended Query ........................17
Table 7. Sector Address Table ........................................................18
Command Definitions . . . . . . . . . . . . . . . . . . . . . .22
Reading Array Data ................................................................22
Set Burst Mode Configuration Register Command Sequence 22
Figure 1. Synchronous/Asynchronous State Diagram.................... 22
Read Mode Setting .................................................................22
Programmable Wait State Configuration ................................22
Table 8. Programmable Wait State Settings ...................................23
Reduced Wait-State Handshaking Option ..............................23
Table 9. Initial Access Cycles vs. Frequency ..................................23
Standard Handshaking Operation ..........................................23
Table 10. Wait States for Standard Handshaking ...........................23
Burst Read Mode Configuration .............................................23
Table 11. Burst Read Mode Settings ..............................................24
Burst Active Clock Edge Configuration ...................................24
RDY Configuration ..................................................................24
Configuration Register ............................................................24
Table 12. Burst Mode Configuration Register .................................24
Sector Lock/Unlock Command Sequence ..............................24
Reset Command .....................................................................24
Autoselect Command Sequence ............................................25
Table 13. Device IDs ...................................................................... 25
Program Command Sequence ...............................................25
Unlock Bypass Command Sequence .....................................26
Figure 2. Erase Operation.............................................................. 26
Chip Erase Command Sequence ...........................................26
Sector Erase Command Sequence ........................................27
Erase Suspend/Erase Resume Commands ...........................27
Figure 3. Program Operation......................................................... 28
Command Definitions .............................................................29
Table 14. Command Definitions .................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling .................................................................30
Figure 4. Data# Polling Algorithm.................................................. 30
RDY: Ready ............................................................................31
DQ6: Toggle Bit I ....................................................................31
Figure 5. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ...................................................................31
Table 15. DQ6 and DQ2 Indications .............................................. 32
Reading Toggle Bits DQ6/DQ2 ...............................................32
DQ5: Exceeded Timing Limits ................................................32
DQ3: Sector Erase Timer .......................................................33
Table 16. Write Operation Status ................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 6. Maximum Negative Overshoot Waveform...................... 34
Figure 7. Maximum Positive Overshoot Waveform........................ 34
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Test Setup....................................................................... 36
Table 17. Test Specifications ......................................................... 36
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Input Waveforms and Measurement Levels................... 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
VCC and VIO Power-up ..........................................................37
Figure 10. VCC and VIO Power-up Diagram................................... 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Synchronous/Burst Read ........................................................38
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK).......................................................................... 39
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)..................................................................... 40
Figure 13. Synchronous Burst Mode Read.................................... 41
Figure 14. 8-word Linear Burst with Wrap Around......................... 41
Figure 15. Burst with RDY Set One Cycle Before Data................. 42
Figure 16. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address .......................................................... 43
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address............................................................ 44
Asynchronous Read ...............................................................45
Figure 18. Asynchronous Mode Read with Latched Addresses.... 45
Figure 19. Asynchronous Mode Read............................................ 46
Figure 20. Reset Timings............................................................... 47
Erase/Program Operations .....................................................48
Figure 21. Asynchronous Program Operation Timings.................. 49
Figure 22. Alternate Asynchronous Program Operation Timings... 50
4 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Figure 23. Synchronous Program Operation Timings..................... 51
Figure 24. Alternate Synchronous Program Operation Timings..... 52
Figure 25. Chip/Sector Erase Command Sequence....................... 53
Figure 26. Accelerated Unlock Bypass Programming Timing......... 54
Figure 27. Data# Polling Timings (During Embedded Algorithm)... 55
Figure 28. Toggle Bit Timings (During Embedded Algorithm)......... 55
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings. 56
Figure 30. Latency with Boundary Crossing................................... 57
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank................................................................ 58
Figure 32. Example of Wait States Insertion (Standard
Handshaking Device)..................................................................... 59
Figure 33. Back-to-Back Read/Write Cycle Timings...................... 60
Erase and Programming Performance . . . . . . . 61
FBGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62
FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm Package ..............................................................62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63
October 31, 2002 Am29BDS640G 5
ADVANCE INFORMATION
PRODUCT SELEC TOR GUIDE
1. Speed O pti ons e ndi ng in “3” and “8 ” indicate the “red uce d wait-s tat e handshak ing ” o ptio n, w hich speeds initial s yn ch rono us
accesses for even addresses.
2. Speed Options ending in “4” and “9” indicate the “standard handshaking” option.
3. See the AC Characteristics section of this datasheet for full specifications.
Part Number Am29BDS640G
Burst Frequency 54 MHz 40 MHz
Speed Op tion VCC, = 1.65 – 1.95 V, VIO = 2.7 – 3.15 V D3, D4 C3, C4
VCC, VIO = 1.65 – 1.95 V D8, D9 C8, C9
Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state
Handshaking: Even Address 87.5 95
Max Initial Synchronous Access Time, ns (tIACC) Reduced Wait-state
Handshaking: Odd Address; or Standard Handshaking 106 120
Max Burst Access Time, ns (tBACC) 13.5 20
Max Asynchronous Access Time, ns (tACC)70 90
Max CE# Access, ns (tCE)
Max OE# Access, ns (tOE) 13.5 20
6 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
BLOCK DIAGRAM
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enab le
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC
Detector
State
Control
Command
Register
VCC
VSS
VSSIO
VIO
WE#
RESET#
WP#
ACC
CE#
OE#
DQ15–DQ0
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A21–A0
RDY
Buffer RDY
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
October 31, 2002 Am29BDS640G 7
ADVANCE INFORMATION
BLOCK DIAGRAM OF SIMULTANEOUS
OPERATION CIRCUIT
V
SS
V
CC
V
IO
V
SSIO
Bank B Address
RESET#
ACC
WE#
CE#
AVD#
RDY
DQ15–DQ0
WP#
STATE
CONTROL
&
COMMAND
REGISTER
Bank B
X-Decoder
Y-Decoder
Latches and
Control Logic
Bank A
X-Decoder
Y-Decoder
Latches and
Control Logic
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
Bank C
Y-Decoder
X-Decoder
Latches and
Control Logic
Bank D
Y-Decoder
X-Decoder
Latches and
Control Logic
OE#
Status
Control
A21–A0
A21–A0
A21–A0
A21–A0
A21–A0
Bank C Address
Bank D Address
Bank A Address
8 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
CONNECTION DIAGRAM
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
C2 D2 E2 F2 G2 H2 J2 K2
C3 D3 E3 F3 G3 H3 J3 K3
C4 D4 E4 F4 G4 H4 J4 K4
C5 D5 E5 F5 G5 H5 J5 K5
C6 D6 E6 F6 G6 H6 J6 K6
C7 D7A7 B7
A8 B8
A1 B1
A2
E7 F7 G7 H7 J7 K7 L7
L8
M7
M8
L1
L2
M1
M2
NC NCNC
B2
NC
NC NC NC NC
NC NC
NC NCNC NC
NC NC DQ15 VSSNCA16A15A14A12A13
C8 D8 E8 F8 G8 H8 J8 K8
NC NC
NCVSSIO
VIO
NCNCNC
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19A21RESET#WE#
DQ11 DQ3DQ10DQ2A20A18ACCRDY
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSSCE#A0A1A2A4A3
C1 D1 E1 F1 G1 H1 J1 K1
VSSIO NCVIO
AVD#WP#CLKVCC
NC
80-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
October 31, 2002 Am29BDS640G 9
ADVANCE INFORMATION
INPUT/OUTPUT DESCRIPTIONS
A21-A0 = Address inputs
DQ15-DQ0 = Data input/output
CE# = Chip Enable input. Asynchronous
relative to CLK for the Burst mode.
OE# = Output Enable input. Asynchronous
relative to CLK for the Burst mode.
WE# = Write Enable input.
VCC = Device Power Supply
(1.65 – 1.95 V).
VIO = Input & Output Buffer Power Supply
(either 1.65 – 1.95 V or 2.7 – 3.15 V).
VSS = Ground
VSSIO = Output Buffer Ground
NC = No Connect; not connected internally
RDY = Ready output; indicates the status of
the Burst read. Low = data not valid at
expected time. High = data valid.
CLK = CLK is not required in asynchronous
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
AVD# = Address Valid input. Indica tes to
device that the valid address is
presen t on the address input s
(A21–A0).
Low = for asynchronous mode,
indicates valid address; for burst
mode, causes starting address to be
latched.
High = device ignores address inputs
RESET# = Hardware reset input. Low = device
resets a nd returns to reading array
data
WP# = Hardware write protect input. At VIL,
disables program and erase functions
in the two outermost sectors. Should
be at VIH for all other conditions.
ACC = At VID, accelerates programming;
automatically places device in unlock
bypass mode. At VIL, locks all sectors.
Should be at VIH for all other
conditions.
LOGIC SYMBOL
22 16
DQ15–DQ0
A21–A0
CE#
OE#
WE#
RESET#
CLK
RDY
AVD#
WP#
ACC
10 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Valid Combinations
V alid Combinations list configurations planned to be supported in
volume for this device. Consul t the local AMD sales of fice to con-
firm availability of specific valid combinations and to check on
newly released combinations.
Note:For the Am29BDS640G, the last digit of the speed
grade specifies the VIO range of the device. Speed options
ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt VIO
range. Speed grades ending in “3” and “4” (e.g., D3, D4)
indicate a 3.0 Volt VIO range.
Am29BDS640G T D 8 WS I TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
PACKAGE TYPE
WS = 80-Ball Fine-Pitch Grid Array (FBGA)
0.80 mm pitch, 11 x 12 mm package (FBE080)
VIO AND HANDSHAKING FEAT URES
8=1.8 V V
IO, reduced wait-state handshaking
9=1.8 V V
IO, standard handsh ak ing
3=3 V V
IO, reduced wait-state handshaking
4=3 V V
IO, standard handshaking
CLOCK RATE/ASYNCHRONOUS SPEED
D = 54 MHz/70 ns
C = 40 MHz/90 ns
BOOT CODE SECTOR ARCHITECTURE
T = Top boot sector
B = Bottom boot sector
DEVICE NUMBER/DESCRIPTION
Am29BDS640G
64 Megabit (4 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write,
Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase
Valid Combina tions Burst Frequency
(MHz) VIO Range
Order Number Package M ar kin g
Am29BDS640GTD8
Am29BDS640GBD8
WSI
BS640GTD8V
BS640GBD8V 54
1.65–1.95V
Am29BDS640GTD9
Am29BDS640GBD9 BS640GTD9V
BS640GBD9V
Am29BDS640GTC8
Am29BDS640GBC8 BS640GTC8V
BS640GBC8V 40
Am29BDS640GTC9
Am29BDS640GBC9 BS640GTC9V
BS640GBC9V
Am29BDS640GTD3
Am29BDS640GBD3
WSI
BS640GTD3V
BS640GBD3V 54
2.7–3.15V
Am29BDS640GTD4
Am29BDS640GBD4 BS640GTD4V
BS640GBD4V
Am29BDS640GTC3
Am29BDS640GBC3 BS640GTC3V
BS640GBC3V 40
Am29BDS640GTC4
Am29BDS640GBC4 BS640GTC4V
BS640GBC4V
October 31, 2002 Am29BDS640G 11
ADVANCE INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command . The conte nts of th e
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Tab le 1. Device Bus Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions.
Note: Default active edge of CLK is the rising edge.
Enhanced VersatileIO™ (VIO) Control
The Enhanced V ersatileIO (VIO) control allows the host
system to set the volta ge leve ls that the de vice gener-
ates at its data outputs and the voltages tolerated at its
data and address inputs to the same voltage level that
is asserted on the VIO pin. The device is available with
either 1.65–1.95 or 2.7–3.15 VIO. This allows the
device to operate in 1.8 V or 3 V system environments
as required.
For examp le , a V IO of 2.7 – 3.1 5 v olts allows for I/ O a t
the 3 volt level, driving and receiving signals to and
from other 3 V devices on the same bus.
Requirements for Asynchronous Read
Operation (Non-Burst)
To read dat a from the memor y array, the sys tem must
first assert a valid address on A21–A0, while driving
AVD# and CE # to VIL. WE# s ho uld r em ain at VIH. The
rising edge of AVD# latches the address. The data will
appear on DQ15–DQ0. Since the memory array is
divided into four banks, each bank remains enabled for
read access until the command register contents are
altered.
Addres s access time (tACC) is equal to the delay from
stable addresses to valid ou tput da ta. The ch ip en abl e
access time (tCE) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enabl e access time (tOE) i s the del ay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon dev ice power -up, or after a hardwa re res et. Th is
ensures that no spurious alteration of the memory
content occurs during the power transition.
Operation CE# OE# WE# A21–0 DQ15–0 RESET#
CLK
(See
Note) AVD#
Asynchronous Read - Addresses Latched L L H Addr In I/O H X
Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L
Asynchronous Write L H L Addr In I/O H L L
Synchronous Write L H L Addr In I/O H
Standby (CE#) H X X HIGH Z HIGH Z H X X
Hardware Reset X X X HIGH Z HIGH Z L X X
Burst Read Operations
Load Starting Burst Address L X H Addr In X H
Advance Burst to next addres s with appropriate
Data presented on the Data Bus LLHHIGH Z
Burst
Data Out HH
Terminate current Burst read cycle H X H HIGH Z HIGH Z H X
Terminate current Burst read cycle via RESET# X X H HIGH Z HIGH Z L X X
Terminate current Burst read cycle and start
new Burst read cycle L X H HIGH Z I/O H
12 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous sequential burst
operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for asyn-
chronous read operation.
Prior to e nter i ng b urst mod e, th e s ystem should d eter -
mine how many wait states are desired for the initial
word (tIACC) of each burst acces s, what m ode of bur st
operation is desired, which edge of the clock will be the
active cl ock edge, and how the RD Y signal will transi-
tion with valid data. The system would then write the
burst mode configuration register command sequence.
See “Set Burst Mode Configuration Register Command
Sequence” and “Command Definitions” for further
details.
Once the system has written the “Set Burst Mode Con-
figurati on Regi ster ” comma nd seq uence , the device is
enabled for synchronous reads only.
The initi al word is output tIACC aft er the a ctive edg e of
the first CLK cycle. Subsequent words are output tBACC
after the active edge of each successive clock cycle,
which automatically increments the internal address
counter. Note that the device has a fixed internal
address boundary that occurs every 64 words, starting
at address 00003Fh. During the time the device is out-
putting data at this fixed internal address boundary
(address 00003Fh, 00007Fh, 0000BFh, etc.), a two
cycle latency occurs before data appears for the next
address (address 000 040h, 000080h , 0000C0h, etc.).
The RDY out put indicates this conditi on to the system
by pulsing low. For standard handshaking devices,
there is no two cyc le latenc y betwee n 3Fh and 40h (or
address es offset fro m 3F and 40h by a mul ti ple of 64) .
See Table 10.
For reduced wait-state handshaking devices, if the
address latched is 3Dh (or offset from 3Dh by a multiple
of 64), an additional cycle latency occurs prior to the
initial access. If the address latched is 3Eh (or offset
from 3Eh by a multiple of 64) two additional cycle
latency occurs prior to the initial access and the 2 cycle
latency between 3 Fh and 40h (or o ffset from 3Fh by a
multiple of 64) will not occur. For 3Fh latched
addresses (or offset from 3Fh by a multiple of 64) three
additional cycle latency occurs prior to the initial access
and the 2 cycle latency between 3Fh and 40h (or offset
from these addresses by a multiple of 64) will not occur .
The device will continue to output sequential burst
data, wrapping around to address 000000h after it
reaches the highest addressable memory location,
until the system drives CE# high, RESET# low, or
AVD# low in conjunction with a new address. See
Table 1, “Device Bus Operations,” on page 11.
If the host system crosses the bank boundary while
reading in b urst mode, and the de vice is not prog ram-
ming or erasing, a two-cycle latency will occur as
described above in the subsequent bank. If the host
system crosse s the bank boundar y while the devic e is
programming or erasing, the device will provide read
status in formatio n. The clock wil l be ignored. After the
host has completed status reads, or the device has
completed the program or erase operation, the host
can restar t a b ur st oper at ion us ing a ne w add re ss an d
AVD# pulse.
If the clock frequency is less than 6 MHz during a burst
mode operation, additional latencies will occur. RDY
indicates the length of the latency by pulsing low.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three modes are of the linear wrap
around design, in which a fixed number of words are
read from consecutive addresses. In each of these
modes, the burst addresses read are determined by
the group within which the starting address falls. The
groups are sized according to the number of words
read in a si ngl e bur st s equ enc e for a gi ve n m ode ( see
Table 2.)
Table 2. Burst Address Groups
As an example: if the starting address in the 8-word
mode is 39h, the address range to be read would be
38-3Fh, and the burst sequence would be
39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence
begins with the sta rting address written to the device,
but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word
Linear Wrap mode s begi n their burst se quenc e on the
starting address written to the device, and then wrap
back to the first address in the selected address group.
Note that in these three burst read modes the
address pointer does not cross the boundary that
occurs every 64 words; thus, no wait states are
inserted (except during the initial access).
The RDY p in indicates when data is va lid on the bus.
The devices can wrap through a maximum of 128
words of data (8 words up to 16 times, 16 wor ds up to
8 times, or 32 words up to 4 times) be fore requiring a
new synchronous access (latching of a new address).
Burst Mode Configuration Register
The device uses a configuration register to set the
various bur s t pa ramete rs : num ber of wai t s tate s, bur st
Mode Group Size Group Address Ranges
8-word 8 words 0-7h, 8-Fh, 10-17h, ...
16-word 16 words 0-Fh, 10-1Fh, 20-2Fh, ...
32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh, ...
October 31, 2002 Am29BDS640G 13
ADVANCE INFORMATION
read mod e, a ctiv e c lo ck ed ge, RDY co nfi gur ation , an d
synchronous mode active.
Reduced Wait-State Handshaking Option
The dev ice c an b e eq ui ppe d with a r ed uc ed w ait -state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to deter-
mine when th e initial word of burst data is ready to be
read. The host system should use the programmable
wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of
burst data is indicated by th e rising edge of RDY after
OE# goes low.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect
command sequence to the device. See “Autoselect
Command Sequence” for details.
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock frequency
and the presence of a boundary crossing. See “Set
Burst Mode Configuration Register Command
Sequence” section on pag e 22 section for more infor-
mation. The device will automatically delay RDY and
data by one additional clock cycle when the starting
address is odd.
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Rea d/Write Ope rations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in another
bank of me mory. An erase oper ati on ma y al so be sus -
pended to read from or program to another location
within the same bank (except the sector being erased).
Figure 33, “Back-to-Back Read/Write Cycle Timings,”
on page 60 shows how read and write cycles may be
initiated for simultaneous operation with zero latency.
Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. During a
synchronous write operation, to write a command or
command sequence (which includes programming
data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to VIL, and OE# to
VIH when providing an address to the device, and drive
WE# and CE# to VIL, and OE# to VIH. when writing
commands or data. During an asynchronous write
operatio n, the syste m must dr ive CE#, W E#, and CLK
to VIL and OE# to VIH when providing an address, com-
mand, and data. The asynchronous and synchronous
programing operation is independent of the Set Device
Read Mode bit in the Burst Mode Configuration Reg-
ister.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word, instead of four.
An erase operation can erase one sector , multiple sec-
tors, or the entire device. Table 8, “Programmable W ait
State Settings,” on page 23 indicates the address
space that each sector occupies. The device address
space is divided into four banks: Banks B and C contain
only 32 Kword sectors, while Banks A and D contain
both 8 Kword boot sectors in addition to 32 Kword sec-
tors. A “bank address” is the address bits required to
uniquely select a bank. Si milarly, a “s ector address ” is
the address bits required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program O peration
The device offers accelerated program operations
through the ACC function. ACC is primarily intended to
allow faster manufacturing throughput at the factory.
If the system asserts VID on this input, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the input to
reduce the time required for program operations. The
system would use a two-cycle program command
sequence as required by the Unlock Bypass mode.
Removing VID from the ACC input returns the device to
normal operatio n. Note that s ectors mu st be unl ocked
prior to raising ACC to VID. Note that the ACC pin must
not be at VID for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the ACC pin must not b e left floating or unconnected;
inconsistent behavior of the device may result.
When at VIL, ACC l ocks a ll se ctors. ACC should be at
VIH for all other conditions.
Autoselect Fun ctions
If the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ15–DQ0. Autoselect mode may only be
entered and used when in the asynchronous read
mode. Refer to the “Autoselect Command Sequence”
section on page 25 section for more information.
14 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The devic e ente rs the CM OS stan dby m ode whe n the
CE# and RESET# inputs are both held at VCC ± 0. 2 V.
The device requires standard access time (tCE) for
read access, before it is ready to read data.
If the devic e is deselec ted duri ng erasure or pr ogram-
ming, the device draws active current until the opera-
tion is completed.
ICC3 in the DC Characteristics table represents the
standb y cu rren t spec if ic ati on.
Automatic Slee p Mode
The automatic sleep mode minimizes Flash device
energy consumption. While in asynchronous mode, the
device automatically enables this mode when
addresses remain stable for tACC + 60 ns. The auto-
matic sleep mode is independent of the CE#, WE#, and
OE# contro l si gna ls . Sta nda rd addres s acces s ti mings
provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. While in synchronous mode, the
device automatically enables this mode when either
the first activ e CLK edge o ccurs after t ACC or the CLK
runs slower than 5MHz. Note that a new burst opera-
tion is required to provide new data.
ICC4 in the “DC Characteristics” section on page 35
represents the automatic sleep mode current specifica-
tion.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of
resetting the device to reading array data. When
RESET# is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress , tristates all ou tputs, resets the c onfiguratio n
register, and ignores all read/write commands for the
duration of the RESET # pu lse. Th e devi ce al so res ets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated
once the device is ready to accept another command
sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS ± 0 .2 V, th e dev ice
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS ± 0.2 V, the standby current will
be greater.
RESET# may be tied to the system reset circuitry. A
system reset w ould thus a lso res et the Flas h memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the device requires a time of tREADY (during
Embedded Algorithms) before the device is ready to
read data again. If RESET# is asserted when a
progra m or er ase op eration is not exec uting, the rese t
operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read
data tRH after RESET# returns to VIH.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 20, “Reset Timings,” on
page 47 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, outp ut f rom th e de vice is
disabled. The outputs are placed in the high imped-
ance state.
Hardware Data Protection
The comm and seq uenc e requirement of unlock cycl es
for programming or erasing provides data protection
against inadvertent writes (refer to Table 14, “Com-
mand Definitions,” on page 29 for command defini-
tions).
The device offers two types of data protection at the
sector level:
■The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
■When WP# is at VIL, se ct ors 0 and 1 (bottom boot)
or sectors 132 and 133 (top boot) are locked.
■When ACC is at VIL, all sectors are locked.
The following hardware data protection measures
prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signals during VCC power-up and power-down transi-
tions, or from system noise.
Write Protect (WP#)
The Write Protect (WP#) input provides a hardware
method of protecting data without using VID.
If the system asserts VIL on the WP# pin, the device
disables program and erase functions in sectors 0 and
1 (bottom boot) or sectors 132 and 133 (top boot).
If the system asserts VIH on the WP# pin, the device
reverts to whether the two outermost 8K Byte boot
sectors were last set to be protected or unprotected.
Note that the WP# pin must not be left floating or
unconnec ted; inco nsistent behavior of the devi ce may
result.
October 31, 2002 Am29BDS640G 15
ADVANCE INFORMATION
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets to reading array data. Subsequent writes
are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control inputs to
prevent unintention al writes when VCC is greater than
VLKO.
Write Pulse “Glitch ” Prot ec tio n
Nois e puls es of less t han 5 n s (typ ical) on OE#, CE# o r
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = V IH or WE# = V IH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during
power up, the device does not accept commands on
the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up.
VCC and VIO Power-up And Power-down
Sequencing
The device imposes no restrictions on VCC and VIO
power-up or power-down sequencing. Asserting
RESET# to VIL is required during the entire VCC and
VIO power sequence until the respective supplies reach
their operating voltages. Once VCC and VIO attain their
respective operating voltages, de-assertion of
RESET# to VIH is permitted.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-indepen-
dent, JEDE C ID-i ndependent, and forw ard- and back-
ward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h any time the device is ready to read array
data. The system can read CFI information at the
addresses given in Tables 3-6. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 3-6. The
system must write the reset command to return the
device to the reading array data.
For further information, please refer to the CFI Specifi-
cation and CF I P ubl ic ati on 1 00, av ai la ble v ia the AM D
site at the following URL:
http://www.amd.com/flash/cfi. Alternatively, contact an
AMD representative for copies of these documents.
Table 3. CFI Query Identification String
Addresses Data Description
10h
11h
12h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 0002h
0000h Primary OEM Command Set
15h
16h 0040h
0000h Ad dres s for Prima ry Exte nde d Table
17h
18h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
16 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Table 4. System Interface String
Table 5. Device Geometry Definition
Addresses Data Description
1Bh 0017h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0019h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0004h Typical timeout per single byte/word write 2N µs
20h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 0009h Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0004h Max. timeout for byte/word write 2N times typical
24h 0000h Max. timeout for buffer write 2N times typical
25h 0004h Max . time out per ind iv idu al blo ck erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Addresses Data Description
27h 0017h Device Size = 2N byte
28h
29h 0001h
0000h Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh 0000h
0000h Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch 0003h Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
0003h
0000h
0040h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
October 31, 2002 Am29BDS640G 17
ADVANCE INFORMATION
Table 6. Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
0050h
0052h
0049h Query-un ique ASC II string “PRI”
43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII
45h 0004h Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Technology (Bits 5-2) 0001 = 0.17 µm
46h 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 0001h Sector Protect
0 = Not Supp orted, X = Number o f sect ors in per group
48h 0000h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0005h Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah 0063h Simu ltan eo us Op eration
Number of Sectors in all banks except boot block
4Bh 0001h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh 00B5h ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 00C5h ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 00xxh Top/Bottom Boot Sec tor Flag
02h = Bottom Boot Device, 03h = Top Boot Device
50h 0000h Program Suspend. 00h = not supported
57h 0004h B ank Or ganiz ation: X = Number of banks
58h 0023h Bank A Region Information. X = Number of sectors in bank
59h 0020h Bank B Region Information. X = Number of sectors in bank
5Ah 0020h Bank C Region Information. X = Number of sectors in bank
5Bh 0023h Bank D Region Information. X = Number of sectors in bank
18 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Table 7. Sector Address Table
Sector Sector Size (x16) Address Range
Bank D
SA0 8 Kwords 000000h-001FFFh
SA1 8 Kwords 002000h-003FFFh
SA2 8 Kwords 004000h-005FFFh
SA3 8 Kwords 006000h-007FFFh
SA4 32 Kwords 008000h-00FFFFh
SA5 32 Kwords 010000h-017FFFh
SA6 32 Kwords 018000h-01FFFFh
SA7 32 Kwords 020000h-027FFFh
SA8 32 Kwords 028000h-02FFFFh
SA9 32 Kwords 030000h-037FFFh
SA10 32 Kwords 038000h-03FFFFh
SA11 32 Kwords 040000h-047FFFh
SA12 32 Kwords 048000h-04FFFFh
SA13 32 Kwords 050000h-057FFFh
SA14 32 Kwords 058000h-05FFFFh
SA15 32 Kwords 060000h-067FFFh
SA16 32 Kwords 068000h-06FFFFh
SA17 32 Kwords 070000h-077FFFh
SA18 32 Kwords 078000h-07FFFFh
SA19 32 Kwords 080000h-087FFFh
SA20 32 Kwords 088000h-08FFFFh
SA21 32 Kwords 090000h-097FFFh
SA22 32 Kwords 098000h-09FFFFh
SA23 32 Kwords 0A0000h-0A7FFFh
SA24 32 Kwords 0A8000h-0AFFFFh
SA25 32 Kwords 0B0000h-0B7FFFh
SA26 32 Kwords 0B8000h-0BFFFFh
SA27 32 Kwords 0C0000h-0C7FFFh
SA28 32 Kwords 0C8000h-0CFFFFh
SA29 32 Kwords 0D0000h-0D7FFFh
SA30 32 Kwords 0D8000h-0DFFFFh
SA31 32 Kwords 0E0000h-0E7FFFh
SA32 32 Kwords 0E8000h-0EFFFFh
SA33 32 Kwords 0F0000h-0F7FFFh
SA34 32 Kwords 0F8000h-0FFFFFh
October 31, 2002 Am29BDS640G 19
ADVANCE INFORMATION
Bank C
SA35 32 Kwords 100000h-107FFFh
SA36 32 Kwords 108000h-10FFFFh
SA37 32 Kwords 110000h-117FFFh
SA38 32 Kwords 118000h-11FFFFh
SA39 32 Kwords 120000h-127FFFh
SA40 32 Kwords 128000h-12FFFFh
SA41 32 Kwords 130000h-137FFFh
SA42 32 Kwords 138000h-13FFFFh
SA43 32 Kwords 140000h-147FFFh
SA44 32 Kwords 148000h-14FFFFh
SA45 32 Kwords 150000h-157FFFh
SA46 32 Kwords 158000h-15FFFFh
SA47 32 Kwords 160000h-167FFFh
SA48 32 Kwords 168000h-16FFFFh
SA49 32 Kwords 170000h-177FFFh
SA50 32 Kwords 178000h-17FFFFh
SA51 32 Kwords 180000h-187FFFh
SA52 32 Kwords 188000h-18FFFFh
SA53 32 Kwords 190000h-197FFFh
SA54 32 Kwords 198000h-19FFFFh
SA55 32 Kwords 1A0000h-1A7FFFh
SA56 32 Kwords 1A8000h-1AFFFFh
SA57 32 Kwords 1B0000h-1B7FFFh
SA58 32 Kwords 1B8000h-1BFFFFh
SA59 32 Kwords 1C0000h-1C7FFFh
SA60 32 Kwords 1C8000h-1CFFFFh
SA61 32 Kwords 1D0000h-1D7FFFh
SA62 32 Kwords 1D8000h-1DFFFFh
SA63 32 Kwords 1E0000h-1E7FFFh
SA64 32 Kwords 1E8000h-1EFFFFh
SA65 32 Kwords 1F0000h-1F7FFFh
SA66 32 Kwords 1F8000h-1FFFFFh
Table 7. Sector Address Table (Continued)
Sector Sector Size (x16) Address Range
20 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Bank B
SA67 32 Kwords 200000h-207FFFh
SA68 32 Kwords 208000h-20FFFFh
SA69 32 Kwords 210000h-217FFFh
SA70 32 Kwords 218000h-21FFFFh
SA71 32 Kwords 220000h-227FFFh
SA72 32 Kwords 228000h-22FFFFh
SA73 32 Kwords 230000h-237FFFh
SA74 32 Kwords 238000h-23FFFFh
SA75 32 Kwords 240000h-247FFFh
SA76 32 Kwords 248000h-24FFFFh
SA77 32 Kwords 250000h-257FFFh
SA78 32 Kwords 258000h-25FFFFh
SA79 32 Kwords 260000h-267FFFh
SA80 32 Kwords 268000h-26FFFFh
SA81 32 Kwords 270000h-277FFFh
SA82 32 Kwords 278000h-27FFFFh
SA83 32 Kwords 280000h-287FFFh
SA84 32 Kwords 288000h-28FFFFh
SA85 32 Kwords 290000h-297FFFh
SA86 32 Kwords 298000h-29FFFFh
SA87 32 Kwords 2A0000h-2A7FFFh
SA88 32 Kwords 2A8000h-2AFFFFh
SA89 32 Kwords 2B0000h-2B7FFFh
SA90 32 Kwords 2B8000h-2BFFFFh
SA91 32 Kwords 2C0000h-2C7FFFh
SA92 32 Kwords 2C8000h-2CFFFFh
SA93 32 Kwords 2D0000h-2D7FFFh
SA94 32 Kwords 2D8000h-2DFFFFh
SA95 32 Kwords 2E0000h-2E7FFFh
SA96 32 Kwords 2E8000h-2EFFFFh
SA97 32 Kwords 2F0000h-2F7FFFh
SA98 32 Kwords 2F8000h-2FFFFFh
Table 7. Sector Address Table (Continued)
Sector Sector Size (x16) Address Range
October 31, 2002 Am29BDS640G 21
ADVANCE INFORMATION
Bank A
SA99 32K words 300000h-307FFFh
SA100 32K words 308000h-30FFFFh
SA101 32K words 310000h-317FFFh
SA102 32K words 318000h-31FFFFh
SA103 32K words 320000h-327FFFh
SA104 32K words 328000h-32FFFFh
SA105 32K words 330000h-337FFFh
SA106 32K words 338000h-33FFFFh
SA107 32K words 340000h-347FFFh
SA108 32K words 348000h-34FFFFh
SA109 32K words 350000h-357FFFh
SA110 32K words 358000h-35FFFFh
SA111 32K words 360000h-367FFFh
SA112 32K words 368000h-36FFFFh
SA113 32K words 370000h-377FFFh
SA114 32K words 378000h-37FFFFh
SA115 32K words 380000h-387FFFh
SA116 32K words 388000h-38FFFFh
SA117 32K words 390000h-397FFFh
SA118 32K words 398000h-39FFFFh
SA119 32K words 3A0000h-3A7FFFh
SA120 32K words 3A8000h-3AFFFFh
SA121 32K words 3 B0000h-3B7FFFh
SA122 32K words 3B8000h-3BFFFFh
SA123 32K words 3C0000h-3C7FFFh
SA124 32K words 3C8000h-3CFFFFh
SA125 32K words 3D0000h-3D7FFFh
SA126 32K words 3D8000h-3DFFFFh
SA127 32K words 3 E0000h-3E7FFFh
SA128 32K words 3E8000h-3EFFFFh
SA129 32K words 3F0000h-3F7FFFh
SA130 8K words 3F8000h-3F9FFFh
SA131 8K words 3FA000h-3FBFFFh
SA132 8K words 3FC000h-3FDFFFh
SA133 8K words 3FE000h-3FFFFFh
Table 7. Sector Address Table (Continued)
Sector Sector Size (x16) Address Range
22 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
COM MAND DEFINITI ONS
Writing specific address and data commands or
sequences into the command register initiates device
operati ons. Table 14, “Command Definitions,” on
page 29 defines the valid register command
sequences. Note that writing incorrect address and
data valu es or writing the m in the improper sequence
rmay place the device in an unknown state. A reset
command is required to return the device to normal
operation.
Refer to the AC Characteristics section for timing dia-
grams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the
“Erase Suspend/Erase Resume Commands” section
on page 27 section for more information.
The system mu st is sue the reset comm and to r eturn a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the “Reset
Comman d” sectio n on page 24 sec tion for mo re infor-
mation.
See also “Requirements for Asynchronous Read Oper-
ation (Non-Burst)” and “Requirements for Synchronous
(Burst) Read Operation” sections for more information.
The Asynchronous Read and Synchronous/Burst
Read tables provide the read parameters, and Figures
11, 13, and 18 show the timings.
Set Burst Mode Configuration Register
Command Sequence
The device uses a burst mode configuration register to
set the various burst parameters: number of wait
states, bu rst read mode, a ctive clock edg e, RDY con-
figuration, and synchronous mode active. The burst
mode configuration register must be set before the
dev ice wi ll enter burst mode.
The burs t mode c onfig urati on regis ter is lo aded with a
three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the
data should be C0h, address bits A11–A0 should be
555h, and address bits A19–A12 set the code to be
latched. The device will power up or after a hardw are
reset with the default setting, which is in asynchronous
mode. Th e regist er must be se t before th e device can
enter synchronous mode. The burst mode configura-
tion re gister ca n not be changed d uring de vice o pera-
tions (program, erase, or sector lock).
Figure 1. Synchronous/Asynchronous State
Diagram
Read Mode Setting
On power-up or hardware reset, the device is set to be
in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system
operations. Address A19 determines this setting: “1’ for
asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configura tion
The programmable wait state feature informs the
device of the numbe r of clock cycles th at must ela pse
after A VD# is driven active before data will be available.
This value is determined by the input frequ ency of the
device. Address bits A14–A12 determine the setting
(see Table 8).
The wait state command sequence instructs the device
to set a parti cular numb er of clock cycle s for th e init ial
access in burst mode. The number of wait states that
should be programmed into the device is directly
related to the clock frequency.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(A19 = 0)
Set Burst Mode
Configuration Registe
r
Command for
Asynchronous Mode
(A19 = 1)
October 31, 2002 Am29BDS640G 23
ADVANCE INFORMATION
Table 8. Programmable Wait Sta te Settings
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
3. Assumes even address.
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Reduced Wait-State Handshaking Option
If the device is equipped with the reduced wait-state
handshaking option, the host system should set
address bits A14–A12 to 010 fo r a clock freque ncy of
40 MHz o r to 011 for a clock freq uency of 54 MHz for
the system/device to execute at maximum speed.
Table 9 describes the typical number of clock cycles
(wait states) for various conditions.
Table 9. Initial Access Cycles vs. Frequency
Note: In the 8-, 16- and 32-word burst read modes, the
address pointer does not cross 64-word boundaries
(addresses which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Standard Handshaking Operation
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on the clock fre-
quency.
Table 10 describes the typical number of clock cycles
(wait states) for various conditions with A14–A12 set to
101.
Table 10. W ait States for Standard Handshaking
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
Burst Read Mode Configuration
The device supports four different burst read modes:
continuo us mode, and 8, 16, and 32 word li near wrap
around modes. A continuous sequence begins at the
starting address and advances the address pointer
until the burst operation is complete. If the highest
address in the device is reached during the continuous
burst read mo de, the addr ess poi nter wraps ar ound to
the lowest address.
For example, an eight-word linear burst with wrap
around be gins on the st arting burst ad dress written to
the device and then proceeds until the next 8 word
boundary. The address pointer the n returns to the firs t
word of the burst sequence, wrapping back to the
starting location. The sixteen- and thirty-two linear
wrap around modes op er ate i n a fa sh ion s imil ar to the
eight-word mode.
Table 11 shows the address bits and settings for the
four burst read mod es.
A14 A13 A12 Total Initial Access
Cycles
000 2
001 3
010 4
011 5
100 6
101 7
System
Frequency
Range
Even Initial Addr.
Odd Initial Addr.
Even Initial Addr.
with Boundary
Odd Initial Addr.
with Boundary
Device
Speed
Rating
6–11 MHz 2 2 3 4
40 MHz
12–23 MHz 2 3 4 5
24–33 MHz 3 4 5 6
34–40 MHz 4 5 6 7
40–47 MHz 4 5 6 7 54 MHz
48–54 MHz 5 6 7 8
Conditions at Address
Typical No. of Clock
Cycles af ter AVD# Low
40/54 MHz
Initial address is even 7
Initial address is odd 7
Initial address is even,
and is at boundary crossing* 7
Initial address is odd,
and is at boundary crossing* 7
24 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Table 11. Burst Read Mode Settings
Note: Upon power-up or har dware rese t the default setti ng
is continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subs equent outpu ts will also be on the follo wing
rising edges, barring any delays. The device can be set
so that the falling clock edge is active fo r all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will
output VOH whenever there is valid data on the outputs.
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines th is setti ng; “1” for RDY active with da ta, “0 ” for
RDY active one clock cycle before valid data.
Configuration Register
Table 12 shows the address bits that determine the
configurat ion register settings for various device func-
tions.
Table 12. Burst Mode Configuration Register
Note:Device will be in the default state upon power-up or hardware reset.
Sector Lock/Unlock Command Sequence
The sector lock/ unl oc k c omm and seq uence al lo ws th e
system to de termine whic h sec tors are pro tected from
accidental writes. When the device is first powered up,
all sectors are locked. To unlock a sector, the system
must write the sector lock/unlock command sequence.
Two cycles are first written: addresses are don’t care
and data is 60h. During the third cycle, the sector
address (SLA) and unlock command (60h) is written,
while specifying with address A6 whether that sector
should be locked (A6 = VIL) or unlocked (A6 = VIH).
Afte r th e thir d c ycle, the s yste m can cont inue to lo ck or
unlock additional cycles, or exit the sequence by
writing F0h (reset command).
Note that the last two outermost boot sectors can be
locked by taking the WP# signal to VIL.
Reset Command
Writing the reset command resets the banks to the read
or erase-suspend-read mode. Address bits are don’t
cares for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the bank to which
the system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
Burst Modes
Address Bits
A16 A15
Continuous 0 0
8-word lin ear wr ap arou nd 0 1
16-word linear wrap around 1 0
32-word linear wrap around 1 1
Address BIt Function Settings (Binary)
A19 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
A18 RDY 0 = RDY active one clock cycle before data
1 = RDY active with data (default)
A17 Clock 0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
A16
Burst Read Mode
00 = Continuous (default)
01 = 8-word linear with wrap around
10 = 16-word linear with wrap around
11 = 32-word linear with wrap around
A15
A14
Programmable
Wait State
000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH
001 = Data is valid on the 3rd active CLK edg e after AVD# transition to VIH
010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH
011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH
100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH
101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default)
A13
A12
October 31, 2002 Am29BDS640G 25
ADVANCE INFORMATION
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins (prior to the third cycle).
This resets the bank to which the system was writing to
the read mode. If the program co mmand sequence is
written to a bank that is in the Erase Suspend mode,
writing the reset command returns that bank to the
erase-suspend-read mode. Once programming
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to the read mode. If a bank entered
the autoselect mode while in the Erase Suspend mode,
writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
The reset command is used to exit the sector
lock/unlock sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to acce ss the manufac turer an d devi ce cod es,
and determine whether or not a sector is protected.
Table 14, “Command Definitions,” on page 29 shows
the address and data requirements. The autoselect
command sequence may be written to an address
within a bank that is either in the read or erase-sus-
pend-read mode. The autoselect command may not be
written while the device is actively programming or
erasing in the other bank.
The autos elect command sequence is ini tiated by firs t
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the
autoselect command. The bank then enters the
autoselect mode. No subsequent data will be made
availab le if the autosel ect data is read in sync hronous
mode. The system may read at any address within the
same bank any number of times without initiating
another au tos ele ct com m an d se que nce . T he fol lo win g
table describes the address requirements for the
various autoselect functions, and the resulting data. BA
represents the bank address, and SA represents the
sector address. The device ID is read in three cycles.
Table 13. Device IDs
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Program Command Sequence
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
control s or timings. The de vice automati cally provi des
internally generated program pulses and verifies the
programme d cell mar gin. Table 14 sho ws the address
and data requirements for the program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and addresses
are no longer latched. The system can determine the
status o f the progr am operati on by mo nitoring DQ7 or
DQ6/DQ2. Refer to the “Write Operation Status”
section on page 30 section for information on these
status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should be
reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from
“0” back to a “1.” Attempting to do so may cause that
bank to set DQ5 = 1, or cause the DQ7 and DQ6 status
bit to ind icate the operation wa s su ccessful. Howeve r,
a succeeding read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Description Address Read Data
Manufacturer ID (BA) + 00h 0001h
Device ID, Word 1 (BA) + 01h 227Eh
Device ID, Word 2,
Top Boot (BA) + 0Eh 2204h (1.8 V VIO),
2214h (3.0 V VIO)
Device ID, Word 2,
Bottom Boot (BA) + 0Eh 2224h (1.8 V VIO),
2234h (3.0 V VIO)
Device ID, Word 3 (BA) + 0Fh 2201h
Sector Block
Lock/Unlock (SA) + 02h 0001 (locke d),
0000 (unlocked)
Handshaking (BA) + 03h 43h (redu ced
wait-state),
42h (standard)
26 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to prima-
rily program to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock b ypas s progr am comm and se quence is al l that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock
bypass mode. The erase command sequences are
four cycles in length instead of six cycles. Table 14,
“Command Definitions,” on page 29 shows the require-
ments for the unlock bypass command sequences.
During the unlock bypass mode, only the Unlock
Bypass Program, Unlock Bypass Sector Erase, Unlock
Bypass Chip Erase, and Unlock Bypass Reset com-
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the ACC input. When the system asserts VID
on this input, the device automatically enters the
Unlock Bypa ss mode. The system ma y then write the
two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 2 illustrates t he algor it hm for the progr a m oper-
ation. Ref er to the Er ase/Program O perations tab le in
the AC Characteristics section for parameters, and
Figure 21, “Asynchronous Program Operation Tim-
ings,” on page 49 for timing diagrams.
Figure 2. Erase Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, fo llowed by a set- up comm and. Two additi onal
unlock write cycles are then followed by the chip erase
command , whi ch in tur n in vo kes t he E mb edded Eras e
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is no t require d to p rovide an y con-
trols or timings during these operations. Table 14,
“Command Definitions,” on page 29 shows the address
and data requirements for the chip erase command
sequence.
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedde
d
Erase
algorithm
in progres
s
Notes:
1. See Table 14 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
October 31, 2002 Am29BDS640G 27
ADVANCE INFORMATION
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no
longer latched. The system can determine the status of
the erase o perati on by us ing DQ7 or DQ6/ DQ2. Re fer
to the “Write O peration Status ” section for in formation
on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, th e chip erase com mand sequenc e should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
The host system may also initiate the chip erase
command sequence while the device is in the unlock
bypass mode. The command sequence is two cycles
cycle s in length inst ead of six cy cles. Se e Table 14 for
details on the unlock bypass command sequences.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters and
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 14 shows the
address and data requirements for the sector erase
comma nd se quen ce .
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of no less than 35 µs occurs. During the
time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector
erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sec-
tors. The time between these additional cycles must be
less than 50 µs, otherwise erasure may begin. Any
sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the time-out
period rese ts that bank to the read mode. The system
must rewrite the command sequence and any addi-
tional addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out (See “DQ3: Sector Erase
Timer ” section on p age 33.). T he time- o ut b egi ns f ro m
the rising edge of the final WE# pulse in the command
sequence.
When the Emb edde d Eras e al gor it hm is com pl ete, the
bank ret urns to reading array data and a ddresses are
no longer latched. Note that while the Embedded Erase
operation is in progress, the system can read data from
the non-erasing bank. The system can determine the
status of the erase operation by reading DQ7 or
DQ6/DQ2 in the erasing bank. Refer to the “Write
Operation Status” section on page 30 section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that
occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
The host system may also initiate the sector erase
command sequence while the device is in the unlock
bypass mode. The command sequence is four cycles
cycles in length instead of six cycles.
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters and
timing diagrams.
Erase S uspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system
to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the minimum 50 µs
time-out period during the sector erase command
sequenc e. The Erase Su spend comm and is ignored if
written during the chip erase operation or Embedded
Program algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a
maximum of 35 µs to suspend the erase operation.
However, when the Erase Suspend command is
written during the sector erase time-out, the device
immediately terminates the time-out period and sus-
pends the erase operation.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The
system can read data from or program data to any
sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces
status info rmation on DQ 7–DQ0. Th e system can use
28 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
DQ7, or DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer
to the Write Operation Status section for information on
these status bits.
After an erase-suspended program operation is com-
plete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard program operation. Refer to the
“Write Operation Status” section for more information.
In the e rase -sus pe nd- read mode, the sys tem ca n al s o
issue t he a utos elec t c om man d s equ enc e. Refer t o th e
“Autoselect Functions” section on page 13 and
“Autose lect Command Seque nce” section on page 25
sections for details.
To resume the sector erase operation, the system must
write the Er ase Res ume c omm and . T he ban k add re ss
of the e rase-suspe nded bank is requir ed when wri ting
this command. Further writes of the Resume command
are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
Figure 3. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note: See Table 14 for program command sequence.
October 31, 2002 Am29BDS640G 29
ADVANCE INFORMATION
Command Definitions Table 14. Command Definitions
Legend:
X = Don’t care
RA = Address of th e me mo r y loc at ion to be rea d.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latc h on the r isi n g edge of the AVD# puls e.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# pulse.
SA = Addr e ss of the sec tor to be ver if ied (in au t os elect mode ) or
erased. Address bits A21–A14 uniquely select any sector .
BA = Address of the bank (A21, A20) that is being switched to
autoselect mode, is in bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Conf ig ura tio n R egi st er ad d res s bi ts A1 9– A1 2.
Notes:
1. See Table 1 for description of bus operation s.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A21–A12 are don’t cares.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or performing
sector lock/unlock.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
9. The data in the fifth cycle is 2204h for 1.8 V VIO, and 2214h for
3.0 V VIO (top boot); 2224h for 1.8 V VIO, and 2234h for 3.0 V VIO
(bottom boot).
10. The data is 0000h for an unlocked sector and 0001h for a locked
sector
11. The data is 0043h for reduced wait-state handshaking and 0042h
for standard handshaking.
12. The Unlock Bypass command sequence is required prior to this
command sequence.
13. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
14. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
16. See “Set Burst Mode Configuration Register Command
Sequence” for details.
17. Command is valid when device is ready to read array data or
when device is in autoselect mode.
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Asynchronous Read (6) 1 RA RD
Reset (7) 1 XXX F0
Autoselect (8)
Manufacturer ID 4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001
Device ID (9) 6 555 AA 2AA 55 (BA)555 90 (BA)X01 22 7E (BA)
X0E (Note 9) (BA)
X0F 2201
Sector Lock Verify (10) 4 555 AA 2AA 55 (SA)555 90 (SA)X02 0000/0001
Handshaking Option (11) 4 555 AA 2AA 55 (BA)555 90 (BA)X03 0042/0043
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypas s Progr am (12) 2 XXX A0 PA PD
Unlock Bypas s Sect or Eras e (12) 2 XXX 80 SA 30
Unlock Bypass Chip Erase (12) 2 XXX 80 XXX 10
Unlock Bypass Reset (13) 2 BA 90 XX X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2A A 55 555 10
Sector Eras e 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (14) 1 BA B0
Erase Resume (15) 1 BA 30
Sector Lock/Unlock 3 XXX 60 XXX 60 SLA 60
Set Burst Mode
Configuration Register (16) 3 555 AA 2AA 55 (CR)555 C0
CFI Query (17) 1 55 98
30 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Table 16, “Write Operation
Status,” on page 33 and the following subsections
describe the function of these bits. DQ7 and DQ6 each
offers a method for determinin g whether a program or
erase operation is complete or in progress.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Program or Erase algo-
rit h m is in progre ss or co mp le te d, or wh eth e r a ba nk is
in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embed ded Program algorithm i s compl ete, the devi ce
outputs the datum programmed to DQ7. The system
must pro vide the program add ress to re ad v alid sta t us
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approxi matel y 1 µs, then that ba nk r eturns to the rea d
mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The syste m mu st pr ov ide an a ddr ess within an y of th e
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the bank returns to the read mode. If not all selected
sect ors are protect ed, the Embedded E rase algorithm
erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the co mpletion of an Embedded Program
or Erase o peration , DQ7 may chan ge asynchrono usly
with DQ6–DQ0 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data , the data outputs on DQ6–DQ 0 may be still
invalid. Valid data on DQ7–DQ0 will appear on succes-
sive read cycles.
Table 16 shows the outpu ts for Data # Poll ing on DQ7.
Figu re 3 sh ows the Da ta# Po llin g alg ori thm . Figure 27,
“Data# Polling T imings (During Embedded Algorithm),”
on page 55 in the AC Characteristics section shows the
Data# Polling timing diagram.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
October 31, 2002 Am29BDS640G 31
ADVANCE INFORMATION
RDY: Ready
The RDY is a dedicated output that, by default, indi-
cates (when at logic low) the system should wait 1
clock cycle before expecting the next word of data.
Using the RDY Configuration Command Sequence,
RDY can be set so that a logic low indicates the system
should wait 2 clock cycles before expecting valid data.
RDY functions only while reading data in burst mode.
The following conditions cause the RDY output to be
low: during the initial access (in burst mode), and after
the boundary that occurs every 64 words beginning
with the 64th address, 3Fh.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether th e de vi ce has entered the E r ase S us pen d
mode. Toggle Bit I may be read at any address in th e
same bank, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. When the operation is complete,
DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to
reading array data . If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases the
unprotec ted sectors, and igno res th e selected sect ors
that are protecte d.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-su sp ended. Wh en the devi ce is ac tively er asin g
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector,
DQ6 toggl es for ap pr oxim atel y 1 ms af ter the progr am
command s equenc e is wri tten, then returns to readin g
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
See the following for additional information: Figure 4
(toggle bit flowchart), DQ6: Toggle Bit I (description),
Figure 28, “Toggle Bit Timings
(During Embedded Algorithm),” on page 55 (toggle bit
timing di agram), and Table 15, “DQ 6 and DQ2 Indica-
tions,” on page 32.
Figure 5. Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggl e B it II” o n DQ 2, whe n u sed wi th DQ 6, ind i-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
START
No
Yes
Yes
DQ5 = 1?
No
Yes
DQ6 = Toggle? No
Read Byte
DQ7–DQ0
Address = VA
DQ6 = Toggle?
Read Byte Twice
DQ7–DQ0
Address = VA
Read Byte
DQ7–DQ0
Address = VA
FAIL PASS
Note: The system should recheck the toggle bit even if DQ
5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
32 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
or whether that sector is erase-susp ended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot distinguish whether the sector is
actively er asing or is erase- suspended . DQ6, by com-
parison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode informa-
tion. Refer to Table 15 to compare outputs for DQ2 and
DQ6.
See the following for additional information: Figure 5,
“Toggle B it Alg or ith m,” on pag e 31, “ DQ 6: Tog gle Bi t I”
on page 31, Figure 28, “Toggle Bit Timings
(During Embedded Algorithm),” on page 55, and
Table 15, “DQ6 and DQ2 Indications,” on page 32.
Table 15. DQ6 and DQ2 Indications
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. T ypically , the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
The remaining scenario is that the system initially
determi nes that the toggl e bit is togglin g and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indic ates wh ether the progra m or er ase time has
exceede d a specified internal pulse count limit. Un der
these conditions DQ5 produces a “1,” indicating that
the prog ram o r eras e cycl e was not su cces sfull y com-
pleted.
The device may output a “1” on DQ5 if the system tries
to progra m a “1” to a loca tion that was pr eviously pro-
grammed to “0.” Only an erase operation can change a
“0” back to a “1.” Under this condition, the device halts
the operation, and when the timing limit has been
exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the
reset command to return to the read mode (or to the
erase-s uspend-read mo de if a bank was p revi ously in
the erase-suspend-program mode).
If device is and the system reads then DQ6 and DQ2
programming, at any address, toggles, does not toggle.
actively erasing,
at an address within a sector
selected for erasure, toggles, also toggles.
at an address within sector s not
selected for erasure, toggles, does not toggle.
erase suspended,
at an address within a sector
selected for erasure, does not toggle, toggles.
at an address within sector s not
selected for erasure, returns array data, return s array d ata. The syst em can read
from any sector not selected for erasure.
programming in
erase suspend at any address, toggles, is not applicable.
October 31, 2002 Am29BDS640G 33
ADVANCE INFORMATION
DQ3: Sector Eras e Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector
erase com man ds from the sy stem can b e assum ed t o
be less than 5 0 µs , the syste m ne ed n ot mo nit or DQ3 .
See also the Sector Erase Command Sequence sec-
tion.
After the s ector era se comman d is writte n, the syste m
should rea d the st atus of DQ7 ( Data# Poll ing) or DQ 6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system s oftware shou ld chec k the statu s of DQ3 p rior
to and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 16 show s the status of DQ 3 relativ e to the ot her
status bits.
Table 16. Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and D Q2 require a v alid address w hen reading st atus informatio n. Refer to the appropriate s ubsection for furth er details.
3. When readi ng write ope ration statu s bits, the sys tem must alwa ys provide the bank addres s where the Embe dded Algorith m
is in progress. The device outputs array data if the system addresses a non-busy bank.
4. The sys tem may rea d either a synchronous ly or sy nchronou sly (burs t) while in erase sus pend. RD Y will fu nction exac tly as i n
non-erase-suspended mode.
Status DQ7
(Note 2) DQ6 DQ5
(Note 1) DQ3 DQ2
(Note 2)
Standard
Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle
Embedded Erase Algorithm 0 Toggle 0 1 Toggle
Erase
Suspend
Mode
Erase-Suspend-
Read (Note 4)
Erase
Suspend ed Sec tor 1 No toggle 0 N/A Toggle
Non-Erase
Suspend ed Sec tor Data Data Data Data Data
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A
34 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
ABSOLUTE MAXIMUM RATINGS
Storage Tempe ra tur e
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1). . . . . . . –0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +3.5 V
ACC . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During
voltage transitio ns, inp uts or I/Os ma y undersh oot VSS to
–2.0 V for periods of up to 20 ns du ring voltage transitions
inputs mi ght overshoot to VCC +0.5 V fo r periods up to 20
ns. See Figure 6. Maximum DC voltage on input or I/Os is
VCC + 0.5 V. During voltage t ransitions outputs may
oversho ot to VCC + 2.0 V for periods up to 20 ns. See
Figure 7.
2. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
3. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stre ss rat ing on ly; fu nction al ope ration of the d e-
vice at these or any other conditions above those indi-
cated in the operational section s of this data s heet is not
implied. Exposure of the devic e to absolute maxim um rat-
ing conditions for extended perio ds may affect devic e reli-
ability.
Figure 6. Maximum Negative
Overshoot Waveform
Figure 7. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . .+1.65 V to +1.95 V
VIO Supply Voltages:
VIO ≤ VCC. . . . . . . . . . . . . . . . . . . +1.65 V to +1.95 V
VIO > VCC. . . . . . . . . . . . . . . . . . . . . . +2.7 to +3.15 V
Operati ng ranges defin e those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
VCC
+2.0 V
VCC
+0.5 V
20 ns
1.0 V
October 31, 2002 Am29BDS640G 35
ADVANCE INFORMATION
DC CHARACTERISTICS
CMOS Compatible
Note:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Devic e enters automatic sle ep mode when addres ses are stable for tACC + 60 ns. Typical sleep mode c urrent is equal t o ICC3.
Parameter Description Test Conditions (Note 1) Min Typ. Max Unit
ILI Input Load Cur rent VIN = VSS to VCC, VCC = VCCmax ±1 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCCmax ±1 µA
ICCB VCC Active Burst Read Current
CE# = VIL, OE# = VIH, WE# = VIH,
54 MHz 10 20 mA
CE# = VIL, OE# = VIH, WE# = VIH,
40 MHz 816mA
IIO VIO Non-active Output VIO = 1.8 V, OE# = VIH 0.2 10 µA
VIO = 3.0 V, OE# = VIH 0.2 10 µA
ICC1 VCC Active Asynchronous Read
Current (Note 2) CE# = VIL, OE# = VIH,
WE# = VIH
5 MHz 12 1 6 mA
1 MHz 3.5 5 mA
ICC2 VCC Active Write Current (Note 3) CE# = VIL, OE# = VIH, V PP = VIH 15 40 mA
ICC3 VCC Standby Current (Note 4) CE# = RESET# = VCC ± 0.2 V 0.2 10 µA
ICC4 VCC Reset Current RESET# = VIL, CLK = VIL 0.2 10 µA
ICC5 VCC Active Current
(Read While Write) CE# = VIL, OE# = VIH 25 60 mA
VIL Input Low Voltage VIO = 1.8 V –0.5 0.2 V
VIO = 3.0 V –0.5 0.4 V
VIH Input High Voltage VIO = 1.8 V VIO – 0.2 VIO + 0.2 V
VIO = 3.0 V VIO – 0.4 VIO + 0.4 V
VOL Output Low Voltage IOL = 100 µA, VCC = VCC min,
VIO = VIO min 0.1 V
VOH Output High Voltage IOH = –100 µA, VCC = VCC min,
VIO = VIO min VIO – 0.1 V
VID Voltage for Accelerated Program 11.5 12.5 V
VLKO Low VCC Lock-out Voltage 1.0 1.4 V
36 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
TEST CONDITIONS Table 17. Test Specifications
KEY TO SWITCHING WAVEFORMS
SWITCHING W AVEFO RMS
CL
Device
Under
Test
Figure 8. Test Setup
Test Condition All Speed Options Unit
Output Load Capacitance, CL
(including jig capacitance) 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0–VIO V
Input timing measurement
reference levels VIO/2 V
Output timing measurement
reference levels VIO/2 V
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
Figure 9. Input W aveforms and Measurement Levels
VIO
0.0 V OutputMeasurement LevelInput VIO/2 VIO/2
A
ll Inputs and Outputs
October 31, 2002 Am29BDS640G 37
ADVANCE INFORMATION
AC CHARACTERISTICS
VCC and VIO Power-up
Figure 10. VCC and VIO Power-up Diagram
Parameter Description Test Setup Speed Unit
tVCS VCC Setup Time Min 50 µs
tVIOS VIO Setup Time Min 50 µs
tRSTH RESET# Low Hold Time Min 50 µs
VCC
VIO
R
ESET#
tVCS
tRSTH
tVIOS
38 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Synchronous/Burst Read
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description D8
(54 MHz) D3
(54 MHz) C8
(40 MHz) C3
(40 MHz) Unit
JEDEC Standard
tIACC Latency (Even Address in Reduced
Wait-State Handshaking Mode) Max 87.5 95 ns
Parameter
Description D8, D9
(54 MHz) D3, D4
(40 MHz) C8, C9
(40 MHz) C3, C4
(54 MHz) Unit
JEDEC Standard
tIACC Latency—(Standard Handshaking or
Odd Address in Handshake mode) Max 106 120 ns
tBACC Burst Access Time V alid Clock to Output
Delay Max 13.5 20 ns
tACS Address Setup Time to CLK (Note 1) Min 5 ns
tACH Address Hold Ti me from CLK (Note 1) Min 7 ns
tBDH Data Hold Time from Next Clock Cycle Min 3 ns
tOE Output Enable to Output Valid Max 13.5 20 ns
tCEZ Chip Enable to High Z Max 10 10.5 10 10.5 ns
tOEZ Output Enable to High Z Max 10 10.5 10 10.5 ns
tCES CE# Setup T im e to CLK Min 5 ns
tRDYS RDY Setup Time to CLK Min 5 4.5 5 4.5 ns
tRACC Ready Access Time from CLK Max 13.5 14 20 20 ns
tAAS Address Setup Time to AVD# (Note 1) Min 5 ns
tAAH Address Hold Ti me to AVD# (Note 1) Min 7 ns
tCAS CE# Setup Time to AVD# Min 0 ns
tAVC AVD# Low to CLK Min 5 ns
tAVD AVD# Pulse Min 12 ns
tACC Access Time Max 70 ns
October 31, 2002 Am29BDS640G 39
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK)
Da Da + 1 Da + n
OE#
DQ15
-
DQ0
A21
-
A0 Aa
AVD#
RDY
CLK
CE# tCES
tACS
tAVC
tAVD
tACH
tOE tRACC
tOEZ
tCEZ
tIACC
tACC
tBDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
1 2 34 56 7
tRDYS
tBACC
40 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active falling edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 0.
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)
Da Da + 1 Da + n
OE#
DQ15
-
DQ0
A21
-
A0 Aa
AVD#
RDY
CLK
CE# tCES
tACS
tAVC
tAVD
tACH
tOE
tOEZ
tCEZ
tIACC
tACC
tBDH
4 cycles for initial access shown.
tRACC Hi-Z
Hi-Z
Hi-Z
12345
tRDYS
tBACC
October 31, 2002 Am29BDS640G 41
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 1.
Figure 13. Synchronous Burst Mode Read
Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data
waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within
the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the
7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register
command sequence has been written with A18=1; device will output RDY with valid data.
Figure 14. 8-word Linear Burst with Wrap Around
Da Da + 1 Da + n
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE# t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
1234567
t
RDYS
t
BACC
t
ACC
D6 D7
OE#
DQ15
-
DQ0
A21
-
A0 Aa
AVD#
RDY
CLK
CE# tCES
tACS
tAVDS
tAVD
tACH
tOE
tIACC
tBDH
D0 D1 D5 D6
7 cycles for initial access shown.
18.5 ns typ. (54 MHz)
Hi-Z tRACC
1234567
tRDYS
tBACC
tACC
42 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Note: Figure assumes 6 wait states for initial access, 40 MHz clock, and synchronous read. The Set Configuration Register
command sequence has been written with A18=0; device will output RDY one cycle before valid data.
Figure 15. Burst with RDY Set One Cycle Before Data
D1D0 D2 D3 Da + n
OE#
DQ15
-
DQ0
A21
-
A0 Aa
AVD#
RDY
CLK
CE# tCES
tACS
tAVDS
tAVD
tACH
tOE
tRACC tOEZ
tCEZ
tIACC
tBDH
6 wait cycles for initial access shown.
25 ns typ. (40 MHz)
Hi-Z
Hi-Z Hi-Z
123456
tRDYS
tBACC
tACC
October 31, 2002 Am29BDS640G 43
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This w avefo rm represents a s yn chr ono us burs t m od e, th e d ev ice wil l al so op erate in reduc ed w a it-s tat e ha nds ha ki ng u nd er
a CLK synchronous burst mode.
Figure 16. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address
Da Da + 1 Da + n
OE#
DQ15
-
DQ0
A21
-
A0 Aa
AVD#
RDY
CLK
CE# tCAS
tAAS
tAVC
tAVD
tAAH
tOE tRACC
tOEZ
tCEZ
tIACC
tBDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
1234567
tRDYS
tBACC
tACC
44 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This w avefo rm represents a s yn chr ono us burs t m od e, th e d ev ice wil l al so op erate in reduc ed w a it-s tat e ha nds ha ki ng u nd er
a CLK synchronous burst mode.
Da Da + 1 Da + n
OE#
DQ15
-
DQ0
A21
-
A0
Aa
AVD#
RDY
CLK
CE# t
CAS
t
AAS
t
AVC
t
AVD
t
AAH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
BDH
7 cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
12345 78
t
RDYS
t
BACC
t
ACC
6
October 31, 2002 Am29BDS640G 45
ADVANCE INFORMATION
AC CHARACTERISTICS
Asynchronous Read
Notes:
1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#.
2. Not 100% tested.
Note: RA = Read Address, RD = Read Data.
Figure 18. Asynchronous Mode Read with Latched Addresses
Parameter
Description D3, D4
D8, D9 C3, C4
C8, C9 UnitJEDEC Standard
tCE Access Time from CE# Low Max 70 90 ns
tACC Asynchronous Access Time (Note 1) Max 7 0 90 ns
tAVDP AVD# Low Time Min 1 2 ns
tAAVDS Address Setup Time to Rising Edge of AVD Min 5 ns
tAAVDH Address Hold Time from Rising Edge of AVD Min 7 ns
tOE Output Enable to Output Valid Max 13.5 20 ns
tOEH Output Enable Hold
Time
Read Min 0 ns
Toggle and
Data# Poll in g Min 10 ns
tOEZ Output E nable to High Z (Note 2) Max 10 10.5 ns
tCAS CE# Setup Time to AVD# Min 0 ns
t
CE
WE#
A21
-
A0
CE#
OE#
Valid RD
t
ACC
t
OEH
t
OE
D
Q15
-
DQ0
t
OEZ
t
AAVDH
t
AVDP
t
AAVDS
AVD#
RA
t
CAS
46 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Note: RA = Read Address, RD = Read Data.
Figure 19. Asynchronous Mode Read
t
CE
WE#
A21
-
A0
CE#
OE#
Valid RD
t
ACC
t
OEH
t
OE
DQ15
-
DQ0
t
OEZ
AVD#
RA
October 31, 2002 Am29BDS640G 47
ADVANCE INFORMATION
AC CHARACTERISTICS
Hardware Reset (RESET# )
Note: Not 100% tested.
Parameter
Description All Speed
Options UnitJEDEC Std
tReadyw RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note) Max 35 µs
tReady RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note) Max 500 ns
tRP RESET# Pulse Width Min 500 ns
tRH Reset High Time Before Read (See Note) Min 200 ns
tRPD RESET# Low to Standby Mode Min 20 µs
RESET#
tRP
tReadyw
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
Figure 20. Reset Timings
48 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the
first of either the rising edge of A VD# or the active edge of CLK.
3. See the “Erase and Programming Performance” section for more information.
4. Does not inc lu de the prep rog ram mi ng t ime.
Parameter
Description All Speed
Options UnitJEDEC Standard
tAVAV tWC Write Cycle Ti me (Note 1) Min 80 ns
tAVWL tAS Address Setup Time
(Not e 2) Synchronous Min 5ns
Asynchronous 0
tWLAX tAH Address Hold Time
(Not e 2) Synchronous Min 7ns
Asynchronous 45
tACS Address Setup Time to CLK (Note 2) Min 5 ns
tACH Address Hold Time to CLK (Note 2) Min 7 ns
tDVWH tDS Data Setup Time Min 45 ns
tWHDX tDH Data Hold Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write Min 0 ns
tCAS CE# Setup Time to AVD# Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 50 ns
tWHWL tWPH Write Pulse Width High Min 30 ns
tSR/W Latency Between Read and Write Operations Min 0 ns
tWHWH1 tWHWH1 Programming Op eration (Not e 3) Typ 8 µs
tWHWH1 tWHWH1 Accelerated Programming Operation (Note 3) Typ 2.5 µs
tWHWH2 tWHWH2 Sector Erase Operation (Notes 3, 4) Typ 0.2 sec
Chip Erase Operation (Notes 3, 4) 26.8
tVID VACC Rise and Fall Time Min 500 ns
tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs
tVCS VCC Setup Time Min 50 µs
tCSW1 Clock Setup Time to WE# (Asynchronous) Min 5 ns
tCSW2 Clock Setup Time to WE# (Synchronous) Min 1 ns
tCHW Clock Hold Time from WE# Max 1 ns
tELWL tCS CE# Setup Time to WE# Min 0 ns
tAVSW AVD# Setup Time to WE# Min 5 ns
tAVHW AVD# Hold Ti me to WE# Min 5 ns
tAVHC AVD# Hold Time to CLK Min 5 ns
tAVDP AVD# Low Time Min 12 ns
October 31, 2002 Am29BDS640G 49
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. The Asynchronous programming operation is
independent of the Set Device Re ad Mode bit in the Burst
Mode Configuration Register.
Figure 21. Asynchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AS
t
AVSW
t
AVHW
t
CSW1
t
AH
t
WC
t
WPH
PA
t
VCS
t
WP
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
t
DS
V
IH
V
IL
t
AVDP
A0h
t
CS
50 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. The Asynchronous programming operation is
independent of the Set Device Re ad Mode bit in the Burst
Mode Configuration Register.
Figure 22. Alternate Asynchronous Program Oper ation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AS
t
AVSW
t
AVHW
t
CHW
t
AH
t
WC
t
WPH
PA
t
VCS
t
WP
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
t
DS
V
IH
V
IL
t
AVDP
A0h
t
CS
October 31, 2002 Am29BDS640G 51
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configur ation Register.
7. CLK must not have an active edge while WE# is at VIL.
8. AVD# must tog gle durin g command sequence unl oc k cy -
cles.
Figure 23. Synchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
V
CC
555h
PD
t
AS
t
WP
t
AH
t
WC
t
WPH
PA
t
VCS
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
t
DS
t
AVDP
A0h
t
AVSW
t
ACS
t
CAS
t
CSW2
52 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid
Address for reading status bits.
2. “In progress” and “complete” refer to status of program
operation.
3. A21–A12 are don’t care during command sequence
unlock cycles.
4. Addresses are latched on the first of either the rising edge
of AVD# or the active edge of CLK.
5. Either CS# or AVD# is required to go from low to high in
between programming command sequences.
6. The Synchronous programming operation is independent
of the Set Device Read Mode bit in the Burst Mode
Configur ation Register.
7. AVD# must tog gle durin g command sequence unl oc k cy -
cles.
8. tAH = 45 ns.
9. CLK must not have an active edge while WE# is at VIL.
Figure 24. Alternate Synchronous Program Operation Timings
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
VCC
555h
PD
tAH
tWC
tWPH
tWP
PA
tVCS
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
tDS
tAVDP
A0h
tACS
tCAS
tAVHC
tCSW2
tAS
(Note 8)
October 31, 2002 Am29BDS640G 53
ADVANCE INFORMATION
AC CHARACTERISTICS
Figure 25. Chip/Sect or Er ase Command Sequen ce
Notes:
1. SA is the sector address for Sector Erase.
2. Address bits A21–A12 are don’t cares during unlock cycles in the command sequence.
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
VCC
tAS
tWP
tAH
tWC
tWPH
SA
tVCS
tCS
tDH
tCH
In
Progress
tWHWH2
VA
Complete
VA
Erase Command Sequence (last two cycles) Read Status Data
tDS
10h for
chip erase
555h for
chip erase
VIH
VIL
tAVDP
55h
2AAh
30h
54 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Note: Use setup and hold times from conventional program operation.
Figure 26. Accelerated Unlock Bypass Programming Timing
CE#
AVD#
WE#
Addresses
Data
OE#
ACC
Don't Care Don't CareA0h Don't Care
PA
PD
V
ID
1 µs
V
IL
or V
IH
tVID
tVIDS
October 31, 2002 Am29BDS640G 55
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, and Data# Polling will output true
data.
3. AVD# must toggle between data reads.
Figure 27. Data# Polling Timings (During Embedded Algorithm)
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
3. AVD# must toggle between data reads.
Figure 28. Toggle Bit Timings (During Embedded Algorithm)
WE#
CE#
OE# tOE
Addresses
AVD#
tOEH
tCE
tCH tOEZ
tCEZ
Status Data Status Data
tACC
VA VA
Data
WE#
CE#
OE# tOE
Addresses
Data
AVD#
tOEH
tCE
tCH tOEZ
tCEZ
Status Data Status Data
tACC
VA VA
56 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to
determine status. When the Embedded Algorithm
operation is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Burst Mode
Configuration Register). When A18 = 1 in the Burst Mode
Configuration Register, RDY is active one clock cycle before
data.
4. AVD# must toggle between data reads.
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings
C
E#
C
LK
A
VD#
A
ddresses
O
E#
D
ata
R
DY
Status Data Status Data
VA VA
tIACC tIACC
October 31, 2002 Am29BDS640G 57
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register).
3. Cxx i ndicates the clo ck that triggers Dxx on the outpu ts; for example, C 60 triggers D60 . Figure shows the device not cr ossing
a bank in the process of performing an erase or program.
Figure 30. Latency with Boundary Crossing
CLK
Address (hex)
C60 C61 C62 C63 C63 C63 C64 C65 C66 C67
D60 D61 D62 D63 D64 D65 D66 D67
(stays high)
AVD#
RDY
Data
Address boundary occurs every 64 words, beginning at address
00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing.
3C 3D 3E 3F 3F 3F 40 41 42 43
latency
RDY latency
tRACC
(Note 1)
(Note 2)
tRACC
tRACC
tRACC
58 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Notes:
1. RDY active with data (A18 = 1 in the Burst Mode Configuration Register).
2. RDY active one clock cycle before data (A18 = 0 in the Burst Mode Configuration Register).
3. Cxx indicates the c lo ck tha t trig gers Dxx on the o utp uts ; for e xa mp le, C6 0 tri gge rs D60. Figure shows the d evi ce crossing a
bank in the process of performing an erase or program.
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank
CLK
Address (hex)
C60 C61 C62 C63 C63 C63 C64
D60 D61 D62 D63 Read Status
(stays high)
AVD#
RDY
Data
OE#,
CE# (stays low)
Address boundary occurs every 64 words, beginning at address
00003Fh (00007Fh, 0000BFh, etc.). Address 000000h is also a boundary crossing
3C 3D 3E 3F 3F 3F 40
latency
RDY latency
tRACC
(Note 1)
(Note 2)
tRACC
tRACC
tRACC
Invalid
October 31, 2002 Am29BDS640G 59
ADVANCE INFORMATION
AC CHARACTERISTICS
Wait State Deco ding Addr es ses :
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 32. Example of Wait States Insertion (Standard Handshaking Device)
Data
A
VD#
OE#
CLK
12345
D0 D
1
01
6
2
7
3
total number of clock cycles
following AVD# falling edge
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
45
60 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
AC CHARACTERISTICS
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking
the status of the program or eras e operation in the “busy” ban k. The syste m should read status twice to ensure valid informatio n.
Figure 33. Back-to-Back Read/Write Cycle Timings
OE#
CE#
WE#
tOEH
Data
A
ddresses
AVD#
PD/30h AAh
RA
PA/SA
tWC
tDS tDH
tRC tRC
tOE
tAS
tAH
tACC
tOEH
tWP
tGHWL
tOEZ
tWC
tSR/W
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank Begin another
write or program
command sequence
RD
RA 555h
RD
tWPH
October 31, 2002 Am29BDS640G 61
ADVANCE INFORMATION
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1 million cycles. Additionally,
programming typicals assumes a checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 14 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1 million cycles.
FBGA BALL CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
3. Fortified BGA ball capacitance TBD.
DATA RETENTION
Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 0.4 5 s Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 54 s
Word Programming Time 11.5 210 µs Excludes syst em level
overhead (Note 5)
Accelerated Word Programming Time 4 120 µs
Chip Programming Time (Note 3) 48 144 s Excludes system level
overhead (Note 5)
Accelerated Chip Programming Time 16 48 s
Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 4.2 5.0 pF
COUT Outp ut Capacitance VOUT = 0 5.4 6.5 pF
CIN2 Control Pin Capacitance VIN = 0 3.9 4.7 pF
Parameter Test Conditions Min Unit
Minimum Pattern Data Retention Time 150°C10Years
125°C20Years
62 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
PHYSICAL DIMENSIONS
FBE080—80-ball Fine-Pitch Ball Grid Array (FBGA)
11 x 12 mm Package
Note: BSC is an ANSI standard for Basic Space Centering
D
AA2
eD D1
E1
SE
SD
eE
0.20 (4X)
A1 CORNER INDEX MARK A1 CORNER
A1 SEATING PLANE
10 67
7
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
E
B
ZZ0.08
Z0.25
Z
ZAB
φ0.08
φ0.15 M
M
NXOb
ABCDEFGHJKLM
7
6
5
4
3
2
1
8
A3-A6, B3-B6,
L3-L6, M3-M6
N/A
10.95 mm x 11.95 mm
PACKAGE
FBE 080
NOM.
---
---
---
1.20
---
0.94
MAX.
10.95 BSC.
11.95 BSC.
12
---
MIN.
0.84
0.20
8.80 BSC.
5.60 BSC.
8
80
0.30 0.35
0.40 BSC.
E
0.25 0.80 BSC.
ME
D
JEDEC
PACKAGE
SYMBOL
A
A2
A1
MD
D1
E
E1
b
N
NOTE
PACKAGE OUTLINE TYPE
ROW MATRIX SIZE E DIRECTION
BALL FOOTPRINT
BALL PITCH
SOLDER BALL PLACEMENT
BODY SIZE
BALL HEIGHT
BODY SIZE
BODY THICKNESS
OVERALL THICKNESS
BALL DIAMETER
ROW MATRIX SIZE D DIRECTION
TOTAL BALL COUNT
BALL FOOTPRINT
DEPOPULATED SOLDER BALLS
e
SD / SE
3150\38.9G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"
DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE
IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER
BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM Z.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER
OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D
OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" IN THE PACKAGE DRAWING INDICATES THE THEORETICAL
CENTER OF DEPOPULATED BALLS.
9 FOR PACKAGE THICKNESS, "A" IS THE CONTROLLING DIMENSION
.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, INK MARK,
METALLIZED MARKINGS INDENTION OR OTHER MEANS.
October 31, 2002 Am29BDS640G 63
ADVANCE INFORMATION
REVISION SUMMARY
Revision A (February 13, 2002)
Initial release.
Revision A+1 (February 19, 2002)
Automatic Sleep Mode
Clarified description to indicate that sleep mode is acti-
vated when the first CLK edge occurs after tACC.
Figure 20, Asynchronous Program Operation
Timings
Modified to sh ow that CLK is don’ t care prior to AVD #
going low, and tha t AVD# mu st not b e low bef ore CE #
transitions low.
Revision A+2 (February 27, 2002)
Figure 21, Asynchronous Program Operation
Timings
Extended don’t care section of CLK to falling edge of
WE#.
Revisi on A+3 (May 9, 2002)
Requirements for Synchronous (Burst) Read
Operation
Shifted address, clock, and data cycle references in
third paragraph up by one.
Table 4, System Interface String
Corrected data for address 23h.
Table 9, Initial Access Cycles vs. Frequency
Added table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Table 14, Command Definitions
Added bottom boot device IDs to table.
RDY: Ready
Corrected address boundary from 63rd word/3Eh to
64th word/3Fh.
DC Characteristics
Added VIO = VIO min to test conditions for VOL and VOH
in table.
Erase/Program Operations table
Added specifications for parameters tCSW1, tCSW2,
tCHW, tAHC.
Figure 21, Figure 23
Added note to indicate AVD# must toggle during
command sequence unlock cycles. Added tCSW1 to
Figure 21.
Figure 22, Figure 24
Added figures, which show different timings between
addresses, CLK, WE#, and AVD#.
Figure 25, Figure 27, Figure 28
Added note to indicate AVD # must toggle during dat a
reads.
Figure 30, Figure 31
Shifted address, clock, and data cycle counts up by
one.
Revision A + 4 (July 26, 2002)
Table 1, Device Bus Operations
Changed Synchronous Write to rising edge of CLK.
Writing Commands/Command Sequences
Added CLK as part of the asynchronous write opera-
tion system drive.
Added VCC and VIO Power-up and Power-down
Sequencing section.
AC Characteristics
Changed tCHW erase/program time from Min to Max.
Figure 20, Asynchronous Program Operation
Timings
Changed tCSW1 reference to WE# from AVD#.
Figure 21, Alternate Asynchronous Program
Operation T imings
Changed to show CLK low after tCHW time.
Figure 22, Synchronous Program Operation
Timings
Removed tACH.
Changed tAHW to tAVSW and added tCSW2.
Figure 23, Alternate Synchronous Program
Operation T imings
Changed tAVCH to tAVHC.
Removed tACH.
DC Characterist ics, CMOS Compatible
Corrected ICCB OE# = VIL to = VIH; sw itched Typ. and
Max. val ue s.
Revision B (October 31, 2002)
Global
Renamed Handshaking Enabled to Reduced
Wait-State Handshaking
Renamed non-Handshaking to Standard Handshaking
64 Am29BDS640G October 31, 2002
ADVANCE INFORMATION
Product Selector Guide
Revised wi th renam ed speed opti ons and ad ded Syn-
chronous Access Time with Reduced Wait-state
Handshaking.
Added Asynchronous Access Time.
Connection Diagram
Corrected pin numbers on bottom row.
Ordering Information
Revised with global changes
Revised Valid Combinations with updated ordering
information.
FBGA Capacitance
Added BGA Capacitance Table after Erase and Pro-
gramming Performance.
Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
