Atmel 8-bit AVR Microcontroller with 512/1024 Bytes In-System Programmable Flash ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 DATASHEET COMPLETE Introduction (R) The Atmel ATtiny4/5/9/10 is a low-power CMOS 8-bit microcontroller based on the AVR(R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieves throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. Feature * * * * * (R) High Performance, Low Power AVR 8-Bit Microcontroller Advanced RISC Architecture - 54 Powerful Instructions - Most Single Clock Cycle Execution - 16 x 8 General Purpose Working Registers - Fully Static Operation - Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories - 512/1024 Bytes of In-System Programmable Flash Program Memory - 32 Bytes Internal SRAM - Flash Write/Erase Cycles: 10,000 - Data Retention: 20 Years at 85C / 100 Years at 25C Peripheral Features (R) - QTouch Library Support for Capacitive Touch Sensing (1 Channel) - One 16-bit Timer/Counter with Prescaler and Two PWM Channels - Programmable Watchdog Timer with Separate On-chip Oscillator - 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only) - On-chip Analog Comparator Special Microcontroller Features - In-System Programmable (at 5V, only) Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 * * * * * * - External and Internal Interrupt Sources - Low Power Idle, ADC Noise Reduction, and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Supply Voltage Level Monitor with Interrupt and Reset - Internal Calibrated Oscillator I/O and Packages - Four Programmable I/O Lines - 6-pin SOT and 8-pad UDFN Operating Voltage: - 1.8 - 5.5V Programming Voltage: - 5V Speed Grade: - 0 - 4 MHz @ 1.8 - 5.5V - 0 - 8 MHz @ 2.7 - 5.5V - 0 - 12 MHz @ 4.5 - 5.5V Industrial and Extended Temperature Ranges Low Power Consumption - Active Mode: * 200A at 1MHz and 1.8V - Idle Mode: * 25A at 1MHz and 1.8V Power-down Mode: * <0.1A at 1.8V Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 2 Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Pin Configurations..................................................................................................... 7 1.1. Pin Descriptions............................................................................................................................7 2. Ordering Information..................................................................................................9 2.1. 2.2. 2.3. 2.4. ATtiny4..........................................................................................................................................9 ATtiny5..........................................................................................................................................9 ATtiny9........................................................................................................................................10 ATtiny10......................................................................................................................................11 3. Overview..................................................................................................................12 3.1. 3.2. Block Diagram............................................................................................................................ 12 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10............................................................. 13 4. General Information................................................................................................. 14 4.1. 4.2. 4.3. 4.4. Resources.................................................................................................................................. 14 Data Retention............................................................................................................................14 About Code Examples................................................................................................................14 Capacitive Touch Sensing.......................................................................................................... 14 5. AVR CPU Core........................................................................................................ 15 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Overview.....................................................................................................................................15 ALU - Arithmetic Logic Unit........................................................................................................16 Status Register...........................................................................................................................16 General Purpose Register File................................................................................................... 17 The X-register, Y-register, and Z-register................................................................................... 17 Stack Pointer.............................................................................................................................. 18 5.7. 5.8. 5.9. Instruction Execution Timing...................................................................................................... 18 Reset and Interrupt Handling..................................................................................................... 19 Register Description................................................................................................................... 20 6. AVR Memories.........................................................................................................25 6.1. 6.2. 6.3. 6.4. Overview.....................................................................................................................................25 In-System Reprogrammable Flash Program Memory................................................................ 25 SRAM Data Memory...................................................................................................................25 I/O Memory.................................................................................................................................27 7. AVR Memories.........................................................................................................28 7.1. 7.2. 7.3. 7.4. Overview.....................................................................................................................................28 In-System Reprogrammable Flash Program Memory................................................................ 28 SRAM Data Memory...................................................................................................................28 I/O Memory.................................................................................................................................30 8. Clock System...........................................................................................................31 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. Clock Distribution........................................................................................................................31 Clock Subsystems......................................................................................................................31 Clock Sources............................................................................................................................ 32 System Clock Prescaler............................................................................................................. 33 Starting....................................................................................................................................... 34 Register Description................................................................................................................... 35 9. Power Management and Sleep Modes....................................................................40 9.1. 9.2. 9.3. 9.4. 9.5. Overview.....................................................................................................................................40 Sleep Modes...............................................................................................................................40 Power Reduction Register..........................................................................................................41 Minimizing Power Consumption................................................................................................. 42 Register Description................................................................................................................... 43 10. System Control and Reset.......................................................................................46 10.1. 10.2. 10.3. 10.4. Resetting the AVR...................................................................................................................... 46 Reset Sources............................................................................................................................46 Watchdog Timer......................................................................................................................... 49 Register Description................................................................................................................... 51 11. Interrupts..................................................................................................................56 11.1. 11.2. 11.3. 11.4. Overview.....................................................................................................................................56 Interrupt Vectors ........................................................................................................................ 56 External Interrupts...................................................................................................................... 57 Register Description................................................................................................................... 58 12. I/O-Ports.................................................................................................................. 65 12.1. Overview.....................................................................................................................................65 12.2. Ports as General Digital I/O........................................................................................................66 12.3. Register Description................................................................................................................... 75 13. 16-bit Timer/Counter0 with PWM.............................................................................81 13.1. Features..................................................................................................................................... 81 13.2. Overview.....................................................................................................................................81 13.3. Accessing 16-bit Registers.........................................................................................................83 13.4. Timer/Counter Clock Sources.................................................................................................... 86 13.5. Counter Unit............................................................................................................................... 87 13.6. Input Capture Unit...................................................................................................................... 89 13.7. Output Compare Units................................................................................................................90 13.8. Compare Match Output Unit.......................................................................................................92 13.9. Modes of Operation....................................................................................................................93 13.10. Timer/Counter Timing Diagrams.............................................................................................. 101 13.11. Register Description................................................................................................................. 102 14. Analog Comparator............................................................................................... 120 14.1. Overview...................................................................................................................................120 14.2. Register Description................................................................................................................. 120 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 4 15. ADC - Analog to Digital Converter.........................................................................124 15.1. Features................................................................................................................................... 124 15.2. Overview...................................................................................................................................124 15.3. Starting a Conversion...............................................................................................................125 15.4. Prescaling and Conversion Timing...........................................................................................126 15.5. Changing Channel or Reference Selection.............................................................................. 128 15.6. ADC Input Channels.................................................................................................................129 15.7. ADC Voltage Reference........................................................................................................... 129 15.8. ADC Noise Canceler................................................................................................................ 129 15.9. Analog Input Circuitry............................................................................................................... 130 15.10. Analog Noise Canceling Techniques........................................................................................130 15.11. ADC Accuracy Definitions........................................................................................................ 131 15.12. ADC Conversion Result........................................................................................................... 132 15.13. Register Description.................................................................................................................133 16. Programming interface.......................................................................................... 140 16.1. 16.2. 16.3. 16.4. 16.5. 16.6. Features................................................................................................................................... 140 Overview...................................................................................................................................140 Physical Layer of Tiny Programming Interface.........................................................................141 Instruction Set...........................................................................................................................145 Accessing the Non-Volatile Memory Controller........................................................................ 148 Control and Status Space Register Descriptions..................................................................... 148 17. MEMPROG- Memory Programming......................................................................152 17.1. 17.2. 17.3. 17.4. 17.5. 17.6. 17.7. Features................................................................................................................................... 152 Overview...................................................................................................................................152 Non-Volatile Memories (NVM)..................................................................................................153 Accessing the NVM.................................................................................................................. 156 Self programming..................................................................................................................... 159 External Programming..............................................................................................................159 Register Description................................................................................................................. 159 18. Electrical Characteristics....................................................................................... 162 18.1. 18.2. 18.3. 18.4. 18.5. 18.6. 18.7. 18.8. Absolute Maximum Ratings*.................................................................................................... 162 DC Characteristics....................................................................................................................162 Speed....................................................................................................................................... 164 Clock Characteristics................................................................................................................164 System and Reset Characteristics........................................................................................... 165 Analog Comparator Characteristics..........................................................................................166 ADC Characteristics (ATtiny5/10, only).................................................................................... 167 Serial Programming Characteristics.........................................................................................167 19. Typical Characteristics...........................................................................................169 19.1. 19.2. 19.3. 19.4. 19.5. Supply Current of I/O Modules................................................................................................. 169 Active Supply Current...............................................................................................................170 Idle Supply Current...................................................................................................................173 Power-down Supply Current.....................................................................................................175 Pin Pull-up................................................................................................................................ 176 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 5 19.6. Pin Driver Strength................................................................................................................... 179 19.7. Pin Threshold and Hysteresis...................................................................................................183 19.8. Analog Comparator Offset........................................................................................................187 19.9. Internal Oscillator Speed.......................................................................................................... 188 19.10. VLM Thresholds....................................................................................................................... 190 19.11. Current Consumption of Peripheral Units.................................................................................192 19.12. Current Consumption in Reset and Reset Pulsewidth............................................................. 195 20. Register Summary.................................................................................................196 20.1. Note..........................................................................................................................................197 21. Instruction Set Summary....................................................................................... 198 22. Packaging Information...........................................................................................202 22.1. 6ST1.........................................................................................................................................202 22.2. 8MA4........................................................................................................................................ 203 23. Errata.....................................................................................................................204 23.1. 23.2. 23.3. 23.4. ATtiny4......................................................................................................................................204 ATtiny5......................................................................................................................................204 ATtiny9......................................................................................................................................205 ATtiny10....................................................................................................................................206 24. Datasheet Revision History................................................................................... 207 24.1. 24.2. 24.3. 24.4. 24.5. 24.6. Rev. 8127F - 02/13.................................................................................................................. 207 Rev. 8127E - 11/11.................................................................................................................. 207 Rev. 8127D - 02/10..................................................................................................................207 Rev. 8127C - 10/09..................................................................................................................207 Rev. 8127B - 08/09.................................................................................................................. 207 Rev. 8127A - 04/09.................................................................................................................. 208 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 6 1. Pin Configurations Figure 1-1 Pinout of ATtiny4/5/9/10 SOT-23 (PCINT0/TPIDATA /OC0A/ADC0/AIN0) PB0 1 6 PB3 (RESET/PCINT3/ADC3) GND 2 5 VCC (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 3 4 PB2 (T0/CLKO/PCINT2/INT0/ADC2) UDFN (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 8 PB2 (T0/CLKO/PCINT2/INT0/ADC2) NC 2 7 VCC NC 3 6 PB3 (RESET/PCINT3/ADC3) GND 4 5 PB0 (AIN0/ADC0/OC0A/TPIDATA /PCINT0) Power Digital Analog Clock GND NC 1.1. Pin Descriptions 1.1.1. VCC Digital supply voltage. 1.1.2. GND Ground. 1.1.3. Port B (PB[3:0]) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.4. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in System and Reset Characteristics of Electrical Characteristics. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. Related Links Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 7 System and Reset Characteristics on page 165 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 8 2. Ordering Information 2.1. ATtiny4 Supply Voltage Speed (1) Temperature Package (2) Ordering Code (3) 1.8 - 5.5V 12 MHz Industrial 6ST1 ATtiny4-TSHR(5) 8MA4 ATtiny4-MAHR (6) 6ST1 ATtiny4-TS8R (5) (-40C to 85C) (4) 10 MHz Extended (-40C to 125C) (6) Note: 1. For speed vs. supply voltage, see section Speed. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. Top/bottomside markings: - Top: T4x, where x = die revision - Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C) 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125C. Table 2-1 Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN) Related Links Speed on page 164 2.2. ATtiny5 Supply Voltage Speed (1) Temperature Package (2) Ordering Code (3) 1.8 - 5.5V 12 MHz Industrial 6ST1 ATtiny5-TSHR(5) 8MA4 ATtiny5-MAHR (6) 6ST1 ATtiny5-TS8R (5) (-40C to 85C) (4) 10 MHz Extended (-40C to 125C) (6) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 9 Note: 1. For speed vs. supply voltage, see section Speed. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. Top/bottomside markings: - Top: T5x, where x = die revision 6. - Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C) For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125C. Table 2-2 Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN) Related Links Speed on page 164 2.3. ATtiny9 Supply Voltage Speed (1) Temperature Package (2) Ordering Code (3) 1.8 - 5.5V 12 MHz Industrial 6ST1 ATtiny9-TSHR(5) 8MA4 ATtiny9-MAHR (6) 6ST1 ATtiny9-TS8R (5) (-40C to 85C) (4) 10 MHz Extended (-40C to 125C) (6) Note: 1. For speed vs. supply voltage, see section Speed. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. Top/bottomside markings: - Top: T9x, where x = die revision - Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C) 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125C. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 10 Table 2-3 Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN) Related Links Speed on page 164 2.4. ATtiny10 Supply Voltage Speed (1) Temperature Package (2) Ordering Code (3) 1.8 - 5.5V 12 MHz Industrial 6ST1 ATtiny10-TSHR(5) 8MA4 ATtiny10-MAHR (6) 6ST1 ATtiny10-TS8R (5) (-40C to 85C) (4) 10 MHz Extended (-40C to 125C) (6) Note: 1. For speed vs. supply voltage, see section Speed. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. Top/bottomside markings: - Top: T10x, where x = die revision - Bottom: zHzzz or z8zzz, where H = (-40C to 85C), and 8 = (-40C to 125C) 6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125C. Table 2-4 Package Type 6ST1 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) 8MA4 8-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN) Related Links Speed on page 164 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 11 3. Overview This device is low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. 3.1. Block Diagram Figure 3-1 Block Diagram SRAM FLASH CPU Clock generation 8MHz Calib Osc External clock 128 kHz Internal Osc Vcc RESET GND Power Supervision POR & RESET Power management and clock control Watchdog Timer Internal Reference I/O PORTS D A T A B U S Interrupt PCINT[3:0] INT0 ADC ADC[7:0] Vcc AC AIN0 AIN1 ACO ADCMUX TC 0 OC0A/B T0 ICP0 (16-bit) 3.1.1. PB[3:0] Description The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. This device provides the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel and 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 12 or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel's high density Non-Volatile Memory (NVM) technology. The onchip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 3.2. Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 A comparison of the devices is shown in the table below. Table 3-1 Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10 Device Flash ADC Signature ATtiny4 512 bytes No 0x1E 0x8F 0x0A ATtiny5 512 bytes Yes 0x1E 0x8F 0x09 ATtiny9 1024 bytes No 0x1E 0x90 0x08 ATtiny10 1024 bytes Yes 0x1E 0x90 0x03 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 13 4. General Information 4.1. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.2. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. 4.3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. 4.4. Capacitive Touch Sensing 4.4.1. QTouch Library (R) (R) The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on (R) most Atmel AVR microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel (R) QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API's to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: http:// www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 14 5. AVR CPU Core 5.1. Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 5-1 Block Diagram of the AVR Architecture Da ta Bus 8-bit Flas h Program Me mory S tatus a nd Control Program Counte r 16 x 8 Ge ne ra l Purpos e Re gis tre rs Instruction Re gis te r Indire ct Addre s s ing Control Line s Dire ct Addre s s ing Instruction De code r Inte rrupt Unit Wa tchdog Time r ALU Analog Compa rator ADC Da ta S RAM Time r/Counte r 0 I/O Line s In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 16 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 15 as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F. 5.2. ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set Summary section for a detailed description. Related Links Instruction Set Summary on page 198 5.3. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. Related Links Instruction Set Summary on page 198 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 16 5.4. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * * * One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input One 16-bit output operand and one 16-bit result input Figure 5-2 AVR CPU General Purpose Working Registers 7 0 R16 R17 General R18 Purpose ... Working R26 X-register Low Byte Registers R27 X-register High Byte R28 Y-register Low Byte R29 Y-register High Byte R30 Z-register Low Byte R31 Z-register High Byte Note: A typical implementation of the AVR register file includes 32 general purpose registers but ATtiny4/5/9/10 implement only 16 registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15. Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. 5.5. The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in the figure. Figure 5-3 The X-, Y-, and Z-registers 15 X-re gis te r 7 15 Y-re gis te r Z-re gis te r XH XL 0 7 0 R27 R26 YH YL 7 0 0 7 0 R29 R28 15 ZH ZL 7 0 7 R31 0 0 0 R30 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 17 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement. See Instruction Set Summary for details. Related Links Instruction Set Summary on page 198 5.6. Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack, and the Stack Pointer must be set to point above 0x40. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM. See the table for Stack Pointer details. Table 5-1 Stack Pointer Instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack ICALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt RCALL POP Incremented by 1 Data is popped from the stack RET Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt RETI The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 5.7. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 18 Figure 5-4 The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch The following Figure shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 5-5 Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.8. Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Interrupts. They have determined priority levels: The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts: * The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 19 occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. * The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) Note: See Code Examples Related Links Interrupts on page 56 About Code Examples on page 14 5.8.1. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 5.9. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 20 5.9.1. Configuration Change Protection Register Name: CCP Offset: 0x3C Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 0 0 0 0 CCP[7:0] Access Reset 0 0 0 0 Bits 7:0 - CCP[7:0]: Configuration Change Protection In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending interrupts will be executed according to their priority. When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled, while CCP[7:1] will always read as zero. CCP[7:1] only have write access. CCP[0] has both read and write access. Table 5-2 Signatures Recognized by the Configuration Change Protection Register Signature Group Description 0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR Protected I/O register Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 21 5.9.2. Stack Pointer Register High byte Name: SPH Offset: 0x3E Reset: RAMEND Property: - Bit 7 6 5 4 3 2 1 0 RW RW RW (SP[15:8]) SPH[7:0] Access RW RW RW RW RW Reset Bits 7:0 - (SP[15:8]) SPH[7:0]: Stack Pointer Register SPL and SPH are combined into SP. It means SPH[7:0] is SP[15:8]. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 22 5.9.3. Stack Pointer Register Low byte Name: SPL Offset: 0x3D Reset: RAMEND Property: - Bit 7 6 5 4 3 2 1 0 RW RW RW (SP[7:0]) SPL[7:0] Access RW RW RW RW RW Reset Bits 7:0 - (SP[7:0]) SPL[7:0]: Stack Pointer Register SPL and SPH are combined into SP. It means SPL[7:0] is SP[7:0]. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 23 5.9.4. Status Register Name: SREG Offset: 0x3F Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 I T H S V N Z C R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. Bit 6 - T: Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in BCD arithmetic. See the Instruction Set Description for detailed information. Bit 4 - S: Sign Flag, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the Instruction Set Description for detailed information. Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetic. See the Instruction Set Description for detailed information. Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 24 6. AVR Memories 6.1. Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. All memory spaces are linear and regular. 6.2. In-System Reprogrammable Flash Program Memory The ATtiny4/5/9/10 contains 512/1024 bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The device Program Counter (PC) is 9 bits wide, thus addressing the 256/512 program memory locations, starting at 0x000. Memory Programming contains a detailed description on Flash data serial downloading. Constant tables can be allocated within the entire address space of program memory by using load/store instructions. Since program memory can not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address 0x4000 in data memory. Although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. Internal write operations to Flash program memory have been disabled and program memory therefore appears to firmware as read-only. Flash memory can still be written to externally but internal write operations to the program memory area will not be successful. Timing diagrams of instruction fetch and execution are presented in Instruction Execution Timing section. Related Links MEMPROG- Memory Programming on page 152 Instruction Execution Timing on page 18 MEMPROG- Memory Programming on page 152 Instruction Execution Timing on page 18 6.3. SRAM Data Memory Data memory locations include the I/O memory, the internal SRAM memory, the Non-Volatile Memory (NVM) Lock bits, and the Flash memory. The following figure shows how the ATtiny4/5/9/10 SRAM Memory is organized. The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal data SRAM. The Non-Volatile Memory (NVM) Lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware. The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 25 The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF. The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. Figure 6-1 Data Memory Map (Byte Addressing) I/O SPACE 0x0000 ... 0x003F SRAM DATA MEMORY 0x0040 ... 0x005F (reserved) 0x0060 ... 0x3EFF NVM LOCK BITS 0x3F00 ... 0x3F01 (reserved) 0x3F02 ... 0x3F3F CONFIGURATION BITS 0x3F40 ... 0x3F41 (reserved) 0x3F42 ... 0x3F7F CALIBRATION BITS 0x3F80 ... 0x3F81 (reserved) 0x3F82 ... 0x3FBF DEVICE ID BITS 0x3FC0 ... 0x3FC3 (reserved) 0x3FC4 ... 0x3FFF FLASH PROGRAM MEMORY (reserved) 0x4400 ... 0xFFFF Data Memory Access Times The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure. Figure 6-2 On-chip Data SRAM Access Cycles T1 T2 Compute Address Address valid T3 clkCPU Address Write Data WR Data Read 6.3.1. 0x4000 ... 0x41FF/0x43FF RD Memory Access Instruction Next Instruction Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 26 6.4. I/O Memory The I/O space definition of the device is shown in the Register Summary. All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD and ST instructions, transferring data between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set Summary section for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00-0x1F only. The I/O and Peripherals Control Registers are explained in later sections. Related Links Register Summary on page 196 Instruction Set Summary on page 198 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 27 7. AVR Memories 7.1. Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. All memory spaces are linear and regular. 7.2. In-System Reprogrammable Flash Program Memory The ATtiny4/5/9/10 contains 512/1024 bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The device Program Counter (PC) is 9 bits wide, thus addressing the 256/512 program memory locations, starting at 0x000. Memory Programming contains a detailed description on Flash data serial downloading. Constant tables can be allocated within the entire address space of program memory by using load/store instructions. Since program memory can not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address 0x4000 in data memory. Although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. Internal write operations to Flash program memory have been disabled and program memory therefore appears to firmware as read-only. Flash memory can still be written to externally but internal write operations to the program memory area will not be successful. Timing diagrams of instruction fetch and execution are presented in Instruction Execution Timing section. Related Links MEMPROG- Memory Programming on page 152 Instruction Execution Timing on page 18 MEMPROG- Memory Programming on page 152 Instruction Execution Timing on page 18 7.3. SRAM Data Memory Data memory locations include the I/O memory, the internal SRAM memory, the Non-Volatile Memory (NVM) Lock bits, and the Flash memory. The following figure shows how the ATtiny4/5/9/10 SRAM Memory is organized. The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal data SRAM. The Non-Volatile Memory (NVM) Lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware. The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 28 The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF. The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. Figure 7-1 Data Memory Map (Byte Addressing) I/O SPACE 0x0000 ... 0x003F SRAM DATA MEMORY 0x0040 ... 0x005F (reserved) 0x0060 ... 0x3EFF NVM LOCK BITS 0x3F00 ... 0x3F01 (reserved) 0x3F02 ... 0x3F3F CONFIGURATION BITS 0x3F40 ... 0x3F41 (reserved) 0x3F42 ... 0x3F7F CALIBRATION BITS 0x3F80 ... 0x3F81 (reserved) 0x3F82 ... 0x3FBF DEVICE ID BITS 0x3FC0 ... 0x3FC3 (reserved) 0x3FC4 ... 0x3FFF FLASH PROGRAM MEMORY (reserved) 0x4400 ... 0xFFFF Data Memory Access Times The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure. Figure 7-2 On-chip Data SRAM Access Cycles T1 T2 Compute Address Address valid T3 clkCPU Address Write Data WR Data Read 7.3.1. 0x4000 ... 0x41FF/0x43FF RD Memory Access Instruction Next Instruction Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 29 7.4. I/O Memory The I/O space definition of the device is shown in the Register Summary. All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD and ST instructions, transferring data between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessible using the SBI and CBI instructions, except USART registers. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set Summary section for more details. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00-0x1F only. The I/O and Peripherals Control Registers are explained in later sections. Related Links Register Summary on page 196 Instruction Set Summary on page 198 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 30 8. Clock System 8.1. Clock Distribution The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in the section on Power Management and Sleep Modes. The clock systems are detailed below. Figure 8-1 Clock Distribution ANALOG-TO-DIGITAL CONVERTER clk ADC GENERAL I/O MODULES CPU CORE clk I/O NVM RAM clk NVM clk CPU CLOCK CONTROL UNIT SOURCE CLOCK RESET LOGIC WATCHDOG CLOCK CLOCK PRESCALER WATCHDOG TIMER CLOCK SWITCH EXTERNAL CLOCK WATCHDOG OSCILLATOR CALIBRATED OSCILLATOR Related Links Power Management and Sleep Modes on page 40 8.2. Clock Subsystems 8.2.1. CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU clock inhibits the core from performing general operations and calculations. 8.2.2. I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 31 8.2.3. NVM Clock - clkNVM The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously with the CPU clock. 8.2.4. ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ADC is available in ATtiny5/10, only. 8.3. Clock Sources The device has the following clock source options, selectable by Clock Main Select Bits in Clock Main Settings Register (CLKMSR.CLKMS). All synchronous clock signals are derived from the main clock. The three alternative sources for the main clock are as follows: * Calibrated Internal 8 MHz Oscillator * External Clock * Internal 128 kHz Oscillator. Refer to description of Clock Main Select Bits in Clock Main Settings Register (CLKMSR.CLKMS) for how to select and change the active clock source. Related Links CLKMSR on page 36 8.3.1. Calibrated Internal 8 MHz Oscillator The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. This clock may be selected as the main clock by setting the Clock Main Select bits in CLKMSR (CLKMSR.CLKMS) to 0b00. Once enabled, the oscillator will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory calibration in Accuracy of Calibrated Internal Oscillator of Electrical Characteristics chapter. When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and reset time-out. For more information on the pre-programmed calibration value, see section Calibration Section. Related Links Calibration Section on page 155 Accuracy of Calibrated Internal Oscillator on page 164 Internal Oscillator Speed on page 188 CLKMSR on page 36 8.3.2. External Clock To drive the device from an external clock source, CLKI should be driven as shown in the Figure below. To run the device on an external clock, the CLKMSR.CLKMS must be programmed to '0b10': Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 32 Table 8-1 External Clock Frequency Frequency CLKMSR.CLKMS 0 - 16MHz 0b10 Figure 8-2 External Clock Drive Configuration EXTERNAL CLOCK S IGNAL CLKI GND When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during the changes. Related Links CLKMSR on page 36 8.3.3. Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMSR.CLKMS to 0b01. Related Links CLKMSR on page 36 8.3.4. Switching Clock Source The main clock source can be switched at run-time using the CLKMSR - Clock Main Settings Register. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock. Related Links CLKMSR on page 36 8.3.5. Default Clock Source The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has been reset. The synchronous system clock is the main clock divided by 8, controlled by the System Clock Prescaler. The Clock Prescaler Select Bits in Clock Prescale Register (CLKPSR.CLKPS) can be written later to change the system clock frequency. See section "System Clock Prescaler". Related Links CLKMSR on page 36 8.4. System Clock Prescaler The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided by setting the "CLKPSR - Clock Prescale Register". The system clock prescaler can be used to decrease power consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 33 The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. 8.4.1. Switching Prescaler Setting When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPSR.CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 8.5. Starting 8.5.1. Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels. The reset start-up time is counted using the internal 128 kHz oscillator. Note: The actual supply voltage is not monitored by the start-up logic. The device will count until the reset start-up time has elapsed even if the device has reached sufficient supply voltage levels earlier. 2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator has reached a stable state before it is used by the other parts of the system. The calibrated internal oscillator needs to oscillate for a minimum number of cycles before it can be considered stable. 3. The last step before releasing the internal reset is to load the calibration and the configuration values from the Non-Volatile Memory to configure the device properly. The configuration time is listed in the next table. Table 8-2 Start-up Times when Using the Internal Calibrated Oscillator with Normal start-up time Reset Oscillator Configuration Total start-up time 64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles (1) Note: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator, divided by 8 8.5.2. Starting from Power-Down Mode When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock selected. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 34 Table 8-3 Start-up Time from Power-Down Sleep Mode. Oscillator start-up time Total start-up time 6 cycles 6 oscillator cycles (1) Note: 1. The start-up time is measured in main clock oscillator cycles. 8.5.3. Starting from Idle / ADC Noise Reduction / Standby Mode When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscillator start-up time is introduced. The ADC is available in ATtiny5/10, only. 8.6. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 35 8.6.1. Clock Main Settings Register Name: CLKMSR Offset: 0x37 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 CLKMS[1:0] Access Reset R/W R/W 0 0 Bits 1:0 - CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. Table 8-4 Selection of Main Clock CLKM Main Clock Source 00 Calibrated Internal 8 MHzOscillator 01 Internal 128 kHz Oscillator (WDT Oscillator) 10 External clock 11 Reserved To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the CLKMS bits, as follows: 1. Write the signature for change enable of protected I/O register to register CCP. 2. Within four instruction cycles, write the CLKMS bits with the desired value. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 36 8.6.2. Oscillator Calibration Register Name: OSCCAL Offset: 0x39 Reset: xxxxxxxx Property: - Bit 7 6 5 4 3 2 1 0 CAL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 - CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in the table of Calibration Accuracy of Internal RC Oscillator. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in the table of Calibration Accuracy of Internal RC Oscillator. Calibration outside that range is not guaranteed. The CAL[7:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0xFF gives the highest frequency in the range. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 37 8.6.3. Clock Prescaler Register Name: CLKPSR Offset: 0x36 Reset: 0x00000011 Property: - Bit 7 6 5 4 3 2 1 0 CLKPS[3:0] Access Reset R/W R/W R/W R/W 0 0 1 1 Bits 3:0 - CLKPS[3:0]: Clock Prescaler Select These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in the table below. Table 8-5 Clock Prescaler Select CLKPS[3:0] Clock Division Factor 0000 1 0001 2 0010 4 0011 8 (default) 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS bits: 1. Write the signature for change enable of protected I/O register to register CCP 2. Within four instruction cycles, write the desired value to CLKPS bits Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 38 At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a frequency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 39 9. Power Management and Sleep Modes 9.1. Overview The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. 9.2. Sleep Modes The following Table shows the different sleep modes and their wake up Table 9-1 Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators Wake-up Sources Sleep Mode clkCPU clkNVM clkIO clkADC(2) Main Clock Source Enabled INT0 and Pin Change ADC(2) Other I/O Watchdog Interrupt VLM Interrupt Idle Yes Yes Yes Yes Yes Yes Yes(1) Yes Yes Yes Yes Yes(1) Yes Yes(1) Yes Yes ADC Noise Reduction Standby Yes Yes Power-down Yes Note: 1. For INT0, only level interrupt. 2. The ADC is available in ATtiny5/10, only. To enter any of the four sleep modes (Idle, ADC Noise Reduction, Power-down or Standby), the Sleep Enable bit in the Sleep Mode Control Register (SMCR.SE) must be written to '1' and a SLEEP instruction must be executed. Sleep Mode Select bits (SMCR.SM) select which sleep mode will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Note: If a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See External Interrupts for details. Related Links Interrupts on page 56 SMCR on page 44 9.2.1. Idle Mode When the SMCR.SM is written to '0x000', the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the Analog Comparator, Timer/Counters, Watchdog, and the interrupt Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 40 system to continue operating. This sleep mode basically halts clkCPU and clkNVM, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register (ACSR.ACD). This will reduce power consumption in Idle mode. If the ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered. Related Links ACSR on page 121 SMCR on page 44 9.2.2. ADC Noise Reduction Mode When the SMCR.SM is written to '0x001', the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkNVM, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC. Related Links SMCR on page 44 9.2.3. Power-Down Mode When the SMCR.SM is written to '0x010', the SLEEP instruction makes the MCU enter Power-Down mode. In this mode, the external Oscillator is stopped, while the external interrupts and the Watchdog continue operating (if enabled). Only an these events can wake up the MCU: * Watchdog System Reset * External level interrupt on INT0 * Pin change interrupt This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Related Links SMCR on page 44 9.2.4. Standby Mode When the SMCR.SM is written to '0x100', the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-Down with the exception that the Oscillator is kept running. This reduces wake-up time, because the oscillator is already running and doesn't need to be started up. Related Links SMCR on page 44 9.3. Power Reduction Register The Power Reduction Register (PRR) provides a method to stop the clock to individual peripherals to reduce power consumption. When the clock for a peripheral is stopped then: Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 41 * * * The current state of the peripheral is frozen. The associated registers can not be read or written. Resources used by the peripheral will remain occupied. The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral and puts it in the same state as before shutdown. Peripheral module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. Related Links PRR on page 45 9.4. Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 9.4.1. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. In the power-down mode, the analog comparator is automatically disabled. See Analog Comparator for further details. Related Links Analog Comparator on page 120 9.4.2. Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Related Links ADC - Analog to Digital Converter on page 124 9.4.3. Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Related Links Watchdog Timer on page 49 9.4.4. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep Modes for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 42 For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR). Related Links Digital Input Enable and Sleep Modes on page 69 DIDR0 on page 123 9.5. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 43 9.5.1. Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Name: SMCR Offset: 0x3A Reset: 0x00 Property: Bit 7 6 5 4 3 2 1 SM[2:0] Access Reset 0 SE R/W R/W R/W R/W 0 0 0 0 Bits 3:1 - SM[2:0]: Sleep Mode Select The SM[2:0] bits select between the five available sleep modes. Table 9-2 Sleep Mode Select SM[2:0] Sleep Mode 000 Idle 001 ADC Noise Reduction 010 Power-down 011 Reserved 100 Standby 101 Reserved 110 Reserved 111 Reserved Note: 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC Bit 0 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 44 9.5.2. Power Reduction Register Name: PRR Offset: 0x35 Reset: 0x00 Property: - Bit 7 6 5 Access Reset 4 3 2 1 0 PRADC PRTIM0 R/W R/W 0 0 Bit 1 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. The ADC is available in ATtiny5/10, only. Bit 0 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 45 10. System Control and Reset 10.1. Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an Relative Jump instruction (RJMP) to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in the next shows the reset logic. Electrical parameters of the reset circuitry are defined in section System and Reset Characteristics. Figure 10-1 Reset Logic DATA BUS WDRF P ORF Powe r-on Re s e t Circuit EXTRF Re s e t Fla g Re gis te r (RS TFLR) VLM P ull-up Re s is tor S P IKE FILTER Wa tchdog Os cilla tor Clock Ge ne ra tor CK De lay Counte rs TIMEOUT The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. Related Links System and Reset Characteristics on page 165 Starting from Reset on page 34 10.2. Reset Sources The device has four sources of reset: * * Power-on Reset. The MCU is reset when the supply voltage is less than the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 46 * 10.2.1. Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog System Reset mode is enabled. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset after VCC rise. The Reset signal is activated again, without any delay, when VCC decreases below the detection level. Figure 10-2 MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 10-3 MCU Start-up, RESET Extended Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET Related Links System and Reset Characteristics on page 165 10.2.2. VCC Level Monitoring ATtiny4/5/9/10 have a VCC Level Monitoring (VLM) circuit that compares the voltage level at the VCC pin against fixed trigger levels. The trigger levels are set with VLM[2:0] bits, see VLMCSR - VCC Level Monitoring Control and Status register. The VLM circuit provides a status flag, VLMF, that indicates if voltage on the VCC pin is below the selected trigger level. The flag can be read from VLMCSR, but it is also possible to have an interrupt generated when the VLMF status flag is set. This interrupt is enabled by the VLMIE bit in the VLMCSR register. The flag can be cleared by changing the trigger level or by writing it to zero. The flag is automatically cleared when the voltage at VCC rises back above the selected trigger level. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 47 The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset (POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional any more. With VLM, it is possible to generate a reset earlier. When active, the VLM circuit consumes some power, as illustrated in the figure of VCC Level Monitor Current vs. VCC in Typical Characteristics. To save power the VLM circuit can be turned off completely, or it can be switched on and off at regular intervals. However, detection takes some time and it is therefore recommended to leave the circuitry on long enough for signals to settle. See VCC Level Monitor. When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM can be shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either flag an interrupt or generate a reset, depending on the configuration. When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long as VCC is below the reset level. If supply voltage rises above the reset level the condition is removed and the MCU will come out of reset, and initiate the power-up start-up sequence. If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been restored. Related Links VLMCSR on page 54 VCC Level Monitor on page 166 Electrical Characteristics on page 162 Typical Characteristics on page 169 10.2.3. External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay counter starts the MCU after the Time-out period (tTOUT ) has expired. The External Reset can be disabled by the RSTDISBL fuse. Figure 10-4 External Reset During Operation CC Related Links System and Reset Characteristics on page 165 10.2.4. Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 48 Figure 10-5 Watchdog System Reset During Operation CC CK 10.3. Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Watchdog System Reset on page 48 for details on how to configure the watchdog timer. Overview The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz, as the next figure. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted. The Watchdog Reset (WDR) instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the device resets and executes from the Reset Vector. Figure 10-6 Watchdog Timer WDP 0 WDP 1 WDP 2 WDP 3 OS C/512K OS C/1024K OS C/256K OS C/128K OS C/32K OS C/64K OS C/8K OS C/2K WATCHDOG RES ET OS C/16K WATCHDOG P RES CALER 128 kHz OS CILLATOR OS C/4K 10.3.1. MUX WDE MCU RES ET The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON. See Procedure for Changing the Watchdog Timer Configuration on page 50 for details. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 49 Table 10-1 WDT Configuration as a Function of the Fuse Settings of WDTON WDTON 10.3.2. Safety Level WDT Initial State How to Disable the WDT How to Change Timeout Unprogrammed 1 Disabled Protected change sequence No limitations Programmed Enabled Always enabled Protected change sequence 2 Procedure for Changing the Watchdog Timer Configuration The sequence for changing configuration differs between the two safety levels, as follows: 10.3.2.1. Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, in the same operation, write WDE and WDP bits 10.3.2.2. Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A protected change is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant 10.3.3. Code Examples The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: wdr ; Clear WDRF in RSTFLR in r16, RSTFLR andi r16, ~(1<<WDRF) out RSTFLR, r16 ; Write signature for change enable of protected I/O register ldi r16, 0xD8 out CCP, r16 ; Within four instruction cycles, turn off WDT ldi r16, (0<<WDE) out WDTCSR, r16 ret Note: See About Code Examples. Related Links About Code Examples on page 14 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 50 10.4. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 51 10.4.1. Watchdog Timer Control Register Name: WDTCSR Offset: 0x31 Reset: 0x00 Property: - Bit Access Reset 7 6 5 3 2 1 0 WDIF WDIE WDP3 4 WDE WDP2 WDP1 WDP0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 x 0 0 0 Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs. If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 10-2 Watchdog Timer Configuration WDTON(1) WDE WDIE Mode Action on Time-out 1 0 0 Stopped None 1 0 1 Interrupt Mode Interrupt 1 1 0 System Reset Mode Reset 1 1 1 Interrupt and System Reset Mode Interrupt, then go to System Reset Mode 0 X X System Reset Mode Reset Note: 1. WDTON Fuse set to "0" means programmed and "1" means unprogrammed. Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in RSTFLR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 52 Bits 5,2:0 - WDPn: Watchdog Timer Prescaler [n=3:0] The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in the table below. Table 10-3 Watchdog Timer Prescale Select WDP[3:0] Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0000 2K (2048) cycles 16ms 0001 4K (4096) cycles 32ms 0010 8K (8192) cycles 64ms 0011 16K (16384) cycles 0.125s 0100 32K (32768) cycles 0.25s 0101 64K (65536) cycles 0.5s 0110 128K (131072) cycles 1.0s 0111 256K (262144) cycles 2.0s 1000 512K (524288) cycles 4.0s 1001 1024K (1048576) cycles 8.0s 1010 Reserved Reserved 1011 Reserved Reserved 1100 Reserved Reserved 1101 Reserved Reserved 1110 Reserved Reserved 1111 Reserved Reserved Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 53 10.4.2. VCC Level Monitoring Control and Status register Name: VLMCSR Offset: 0x34 Reset: 0x00 Property: - Bit 7 6 VLMF VLMIE 5 4 3 2 1 0 Access R R/W R/W R/W R/W Reset 0 0 0 0 0 VLM[2:0] Bit 7 - VLMF: VLM Flag This bit is set by the VLM circuit to indicate that a voltage level condition has been triggered. The bit is cleared when the trigger level selection is set to "Disabled", or when voltage at VCC rises above the selected trigger level. Bit 6 - VLMIE: VLM Interrupt Enable When this bit is set the VLM interrupt is enabled. A VLM interrupt is generated every time the VLMF flag is set. Bits 2:0 - VLM[2:0]: Trigger Level of Voltage Level Monitor These bits set the trigger level for the voltage level monitor. Table 10-4 Setting the Trigger Level of Voltage Level Monitor VLM[2:0] Label Description 000 VLM0 Voltage Level Monitor disabled 001 VLM1L Triggering generates a regular Power-On Reset (POR). 010 VLM1H 011 VLM2 100 VLM3 The VLM flag is not set Triggering sets the VLM Flag (VLMF) and generates a VLM interrupt, if enabled 101 Not allowed 110 Not allowed 111 Not allowed Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 54 10.4.3. Reset Flag Register Name: RSTFLR Offset: 0x3B Reset: N/A Property: - Bit Access Reset 7 6 5 4 1 0 WDRF 3 2 EXTRF PORF R/W R/W R/W x x x Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 55 11. Interrupts 11.1. Overview This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. Related Links Reset and Interrupt Handling on page 19 11.2. Interrupt Vectors Interrupt vectors are described in the table below. Table 11-1 Reset and Interrupt Vectors Vector No. Program Address Source Interrupt Definition 1 0x000 RESET External Pin, Power-on Reset, VLM Reset and Watchdog Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 PCINT0 Pin Change Interrupt Request 0 4 0x003 TIM0_CAPT Timer/Counter0 Capture 5 0x004 TIM0_OVF Timer/Counter0 Overflow 6 0x005 TIM0_COMPA Timer/Counter0 Compare Match A 7 0x006 TIM0_COMPB Timer/Counter0 Compare Match B 8 0x007 ANA_COMP Analog Comparator 9 0x008 WDT Watchdog Time-out Interrupt 10 0x009 VLM VCC Voltage Level Monitor 11 0x00A ADC ADC Conversion Complete(1) Note: 1. The ADC is only available in ATtiny5/10. In case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in this device is: Address Labels Code Comments 0x000 rjmp RESET ; Reset Handler 0x001 rjmp INT0 ; IRQ0 Handler 0x002 rjmp PCINT0 ; PCINT0 Handler Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 56 0x003 rjmp TIM0_CAPT ; Timer0 Capture Handler 0x004 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x005 rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x006 rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x007 rjmp ANA_COMP ; Analog Comparator Handler 0x008 rjmp WDT ; Watchdog Interrupt Handler 0x009 rjmp VLM ; Voltage Level Monitor Handler 0x00A rjmp ADC ; ADC Conversion Handler <continues> ... ... ... 0x000B RESET: ldi r16, high (RAMEND) ; Main program start 0x000C out SPH,r16 ; Set Stack Pointer 0x000D ldi r16, low (RAMEND) ; to top of RAM 0x000E out SPL,r16 0x000F sei 0x0010 <instr> ... ... <continued> 11.3. ; Enable interrupts External Interrupts The External Interrupts are triggered by the INT0 pins or any of the PCINT[3:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[3:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI0 will trigger if any enabled PCINT[3:0] pin toggles. The Pin Change Mask 0/1 Register (PCMSK 0/1) controls which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[3:0] are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A (EICRA). When the INT0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in Clock Systems and their Distribution chapter. Related Links EICRA on page 59 Clock System on page 31 PCMSK on page 64 11.3.1. Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 57 Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined as described in Clock System If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. Related Links Clock System on page 31 11.3.2. Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in the following figure. Figure 11-1 Timing of pin change interrupts pin_lat PCINT(0) D LE clk pcint_in_(0) Q pin_sync 0 pcint_syn PCINT(0) in PCMSK(x) pcint_setflag PCIF x clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 11.4. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 58 11.4.1. External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Name: EICRA Offset: 0x15 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 ISC0[1:0] Access Reset R/W R/W 0 0 Bits 1:0 - ISC0[1:0]: Interrupt Sense Control 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in table below. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Value Description 00 The low level of INT0 generates an interrupt request. 01 Any logical change on INT0 generates an interrupt request. 10 The falling edge of INT0 generates an interrupt request. 11 The rising edge of INT0 generates an interrupt request. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 59 11.4.2. External Interrupt Mask Register Name: EIMSK Offset: 0x13 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 INT0 Access Reset R/W 0 Bit 0 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set ('1') and the I-bit in the Status Register (SREG) is set ('1'), the external pin interrupt is enabled. The Interrupt Sense Control 0 bits in the External Interrupt Control Register A (EICRA.ISC0) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 60 11.4.3. External Interrupt Flag Register Name: EIFR Offset: 0x14 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 INTF0 Access Reset R/W 0 Bit 0 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 61 11.4.4. Pin Change Interrupt Control Register Name: PCICR Offset: 0x12 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 PCIE0 Access Reset R/W 0 Bit 0 - PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT[3:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[3:0] pins are enabled individually by the PCMSK Register. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 62 11.4.5. Pin Change Interrupt Flag Register Name: PCIFR Offset: 0x11 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 PCIF0 Access Reset R/W 0 Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[3:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 63 11.4.6. Pin Change Mask Register Name: PCMSK Offset: 0x10 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R/W 0 0 0 0 Bits 3:0 - PCINTn: Pin Change Enable Mask [n = 3:0] Each PCINT[3:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[3:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[3:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 64 12. I/O-Ports 12.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in the following figure. Figure 12-1 I/O Pin Equivalent Schematic R pu Logic Pxn C pin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. Four I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, Pull-up Enable Register - PUEx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/ write. However, writing '1' to a bit in the PINx Register will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in next section. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Alternate Port Functions section in this chapter. Refer to the individual module sections for a full description of the alternate functions. Enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Related Links Electrical Characteristics on page 162 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 65 12.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2 General Digital I/O REx Q D PUExn Q CLR RESET Q WEx D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx SLEEP WPx RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O SLEEP: clk I/O: SLEEP CONTROL I/O CLOCK WEx: REx: WDx: RDx: WRx: RRx: RPx: WPx: WRITE PUEx READ PUEx WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER Note: WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP are common to all ports. 12.2.1. Configuring the Pin Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in the Register Description in this chapter, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written to '1', Pxn is configured as an output pin. If DDxn is written to '0', Pxn is configured as an input pin. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 66 If PORTxn is written to '1' when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written to '0' or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. Table 12-1 Port Pin Configurations DDxn PORTxn PUExn I/O Pull-up Comment 0 x 0 Input No Tri-state (hi-Z) 0 x 1 Input Yes Sources current if pulled low externally 1 0 0 Output No Output low (sink) 1 0 1 Output Yes NOT RECOMMENDED. Output low (sink) and internal pull-up active. Sources current through the internal pull-up resistor and consumes power constantly 1 1 0 Output No Output high (source) 1 1 1 Output Yes Output high (source) and internal pull-up active Port pins are tri-stated when a reset condition becomes active, even when no clocks are running. 12.2.2. Toggling the Pin Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port. 12.2.3. Break-Before-Make Switching In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tristate period lasting one system clock cycle, as indicated in the figure below. For example, if the system clock is 4 MHz and the DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of PORTxn is seen on the port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see PORTCR - Port Control Register. When switching the DDRxn bit from output to input no immediate tri-state period is introduced. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 67 Figure 12-3 Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK r16 0x02 r17 0x01 INSTRUCTIONS out DDRx, r16 nop PORTx DDRx 0x55 0x02 0x01 Px0 Px1 out DDRx, r17 0x01 tri-state tri-state tri-state intermediate tri-state cycle intermediate tri-state cycle Related Links PORTCR on page 76 12.2.4. Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 12-2 General Digital I/O on page 66, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. The following figure shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 12-4 Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the following figure. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 68 Figure 12-5 Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 12.2.5. Digital Input Enable and Sleep Modes As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Alternate Port Functions section in this chapter. If a logic high level is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 12.2.6. Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 12.2.7. Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 69 Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PUEB2) ldi r17,(1<<PB0) ldi r18,(1<<DDB1)|(1<<DDB0) out PUEB,r16 out PORTB,r17 out DDRB,r18 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... Related Links About Code Examples on page 14 12.2.8. Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. The following figure shows how the port pin control signals from the simplified in the figure of Ports as General Digital I/O can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 70 Figure 12-6 Alternate Port Functions PUOExn 1 REx PUOVxn Q 0 D PUExn Q CLR DDOExn RESET 1 WEx DDOVxn Q D DDxn 0 Q CLR PVOExn WDx RESET RDx 1 1 Pxn Q 0 D 0 PORTxn 0 PTOExn Q CLR DIEOExn 1 DATA BUS PVOVxn DIEOVxn WPx RESET WRx RRx SLEEP SYNCHRONIZER D SET Q RPx D Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE WEx: REx: WDx: RDx: RRx: WRx: RPx: WPx: clk I/O: DIxn: AIOxn: WRITE PUEx READ PUEx WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O and SLEEP are common to all ports. All other signals are unique for each pin. The following table summarizes the function of the overriding signals. The pin and port indexes from previous figure are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 12-2 Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when PUExn = 0b1. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/ cleared, regardless of the setting of the PUExn Register bit. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 71 Signal Name Full Name Description DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. PVOV Port Value Override Value If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. PTOE Port Toggle Override Enable If PTOE is set, the PORTxn Register bit is inverted. DIEOE Digital Input Enable Override Enable If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). DIEOV Digital Input Enable Override Value If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/ cleared, regardless of the MCU state (Normal mode, sleep mode). DI Digital Input This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the Schmitt Trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. AIO Analog Input/Output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 12.2.8.1. Alternate Functions of Port B The Port B pins with alternate functions are shown in the table below: Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 72 Table 12-3 Port B Pins Alternate Functions Port Pin Alternate Functions PB[0] ADC0: ADC Input Channel 0 AIN0: Analog Comparator, Positive Input OC0A: Timer/Counter0 Compare Match A Output PCINT0: Pin Change Interrupt 0, Source 0 TPIDATA: Serial Programming Data PB[1] ADC1: ADC Input Channel 1 AIN1: Analog Comparator, Negative Input CLKI: External Clock ICP0: Timer/Counter0 Input Capture Input OC0B: Timer/Counter0 Compare Match B Output PCINT1: Pin Change Interrupt 0, Source 1 TPICLK: Serial Programming Clock PB[2] ADC2: ADC Input Channel 2 CLKO: System Clock Output INT0: External Interrupt 0 Source PCINT2: Pin Change Interrupt 0, Source 2 T0: Timer/Counter0 Clock Source PB[3] ADC3: ADC Input Channel 3 PCINT3: Pin Change Interrupt 0, Source 3 RESET: Reset Pin The alternate pin configuration is as follows: * PB[0] - ADC0/AIN0/OC0A/PCINT0/TPIDATA - ADC0: Analog to Digital Converter, Channel 0 (ATtiny5/10, only) - AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pullup switched off to avoid the digital port function from interfering with the function of the Analog Comparator. - OC0A, Output Compare Match output: The PB0 pin can serve as an external output for the Timer/Counter0 Compare Match A. The pin has to be configured as an output (DDB0 set (one)) to serve this function. This is also the output pin for the PWM mode timer function. - PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source for pin change interrupt 0. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 73 * * * - TPIDATA: Serial Programming Data. PB[1] - ADC1/AIN1/CLKI/ICP0/OC0B/PCINT1/TPICLK - ADC1: Analog to Digital Converter, Channel 1 (ATtiny5/10, only) - AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. - CLKI: External Clock. - ICP0: Input Capture Pin. The PB1 pin can act as an Input Capture pin for Timer/Counter0. - OC0B: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. - PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change interrupt 0. - TPICLK: Serial Programming Clock. PB[2] - ADC2/CLKO/INT0/PCINT2/T0 - ADC2: Analog to Digital Converter, Channel 2 (ATtiny5/10, only) - CLKO: System Clock Output. The system clock can be output on pin PB2. The system clock will be output if CKOUT bit is programmed, regardless of the PORTB2 and DDB2 settings. - INT0: External Interrupt Request 0 - PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source for pin change interrupt 0. - T0: Timer/Counter0 counter source. PB[3] - ADC3/PCINT3/RESET - ADC3: Analog to Digital Converter, Channel 3 (ATtiny5/10, only) - PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source for pin change interrupt 0. - RESET: The following tables relate the alternate functions of Port B to the overriding signals shown in the figure of Alternate Port Functions. Table 12-4 Overriding Signals for Alternate Functions in PB[3:2] Signal Name PB3/ADC3/RESET/PCINT3 PB2/ADC2/INT0/T0/CLKO/PCINT2 PUOE RSTDISBL(1) CKOUT(2) PUOV 1 0 DDOE RSTDISBL(1) CKOUT(2) DDOV 0 1 PVOE 0 CKOUT(2) PVOV 0 (system clock) PTOE 0 0 DIEOE RSTDISBL(1) + (PCINT3 * PCIE0) + ADC3D (PCINT2 * PCIE0) + ADC2D + INT0 DIEOV RSTDISBL * PCINT3 * PCIE0 (PCINT2 * PCIE0) + INT0 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 74 Signal Name PB3/ADC3/RESET/PCINT3 PB2/ADC2/INT0/T0/CLKO/PCINT2 DI PCINT3 Input INT0/T0/PCINT2 Input AIO ADC3 Input ADC2 Input Note: 1. RSTDISBL is 1 when the configuration bit is "0" (Programmed). 2. CKOUT is 1 when the configuration bit is "0" (Programmed). Table 12-5 Overriding Signals for Alternate Functions in PB[1:0] Signal PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1 Name PB0/ADC0/AIN0/OC0A/PCINT0 PUOE EXT_CLOCK(1) 0 PUOV 0 0 DDOE EXT_CLOCK(1) 0 DDOV 0 0 PVOE EXT_CLOCK(1)+ OC0B Enable OC0A Enable PVOV EXT_CLOCK(1)* OC0B OC0A PTOE 0 0 DIEOE EXT_CLOCK(1)+ (PCINT1 * PCIE0) + ADC1D (PCINT0 * PCIE0) + ADC0D DIEOV EXT_CLOCK(1)* PWR_DOWN) + (EXT_CLOCK(1) * PCINT1 * PCIE0) PCINT0 * PCIE0 DI CLOCK/ICP0/PCINT1 Input PCINT0 Input AIO ADC1/Analog Comparator Negative Input ADC0/Analog Comparator Positive Input Note: 1. EXT_CLOCK is 1 when external clock is selected as main clock. 12.3. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 75 12.3.1. Port Control Register Name: PORTCR Offset: 0x0C Reset: 0 Property: Bit 7 6 5 4 3 2 1 0 BBMB Access Reset R/W 0 Bit 1 - BBMB: Break-Before-Make Mode Enable When this bit is set the Break-Before-Make mode is activated for the entire Port B. The intermediate tristate cycle is then inserted when writing DDRxn to make an output. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 76 12.3.2. Port B Pull-up Enable Control Register Name: PUEB Offset: 0x03 Reset: 0 Property: Bit 7 6 5 4 3 2 1 0 PUEB3 PUEB2 PUEB1 PUEB0 R/W R/W R/W R/W 0 0 0 0 Access Reset Bits 3:0 - PUEBn: Port B Input Pins Address [n = 3:0] Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 77 12.3.3. Port B Data Register Name: PORTB Offset: 0x02 Reset: 0x00 Property: Bit 7 6 5 4 Access Reset 3 2 1 0 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R/W 0 0 0 0 Bits 3:0 - PORTBn: Port B Data [n = 3:0] Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 78 12.3.4. Port B Data Direction Register Name: DDRB Offset: 0x01 Reset: 0 Property: Bit Access 7 6 5 4 3 2 1 0 DDRB3 DDRB2 DDRB1 DDRB0 R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 - DDRBn: Port B Input Pins Address [n = 3:0] Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 79 12.3.5. Port B Input Pins Address Name: PINB Offset: 0x00 Reset: N/A Property: Bit 7 6 5 4 Access Reset 3 2 1 0 PINB3 PINB2 PINB1 PINB0 R/W R/W R/W R/W x x x x Bits 3:0 - PINBn: Port B Input Pins Address [n = 3:0] Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 80 13. 16-bit Timer/Counter0 with PWM 13.1. Features * * * * * * * * * * * 13.2. True 16-bit Design (i.e., allows 16-bit PWM) Two independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV0, OCF0A, OCF0B, and ICF0) Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. A block diagram of the 16-bit Timer/Counter is shown below. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in Register Description on page 102. For the actual placement of I/O pins, refer to the Pin Configurations description. The Power Reduction TC0 bit in the Power Reduction Register (PRR.PRTIM0) must be written to zero to enable the Timer/Counter0 module. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 81 Figure 13-1 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn =0 = OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA TCCRnB Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0) See the related links for actual pin placement. 13.2.1. Definitions Many register and bit references in this section are written in general form: * n represents the Timer/Counter number * x=A,B represents the Output Compare Unit A or B However, when using the register or bit definitions in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value. The following definitions are used throughout the section: Table 13-1 Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x0 for 8-bit counters, or 0x00 for 16-bit counters). MAX The counter reaches its Maximum when it becomes 0xF (decimal 15, for 8-bit counters) or 0xFF (decimal 255, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 82 13.2.2. Registers The Timer/Counter (TCNT0), Output Compare Registers (OCR0A/B), and Input Capture Register (ICR0) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in section Accessing 16-bit Registers. The Timer/Counter Control Registers (TCCR0A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the block diagram) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A/B). See Output Compare Units. The compare match event will also set the Compare Match Flag (OCF0A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP0) or on the Analog Comparator pins. The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR0A Register, the ICR0 Register, or by a set of fixed values. When using OCR0A as TOP value in a PWM mode, the OCR0A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR0 Register can be used as an alternative, freeing the OCR0A to be used as PWM output. Related Links TCNT0H on page 109 TCNT0L on page 110 OCR0AH on page 111 OCR0AL on page 112 OCR0BH on page 113 OCR0BL on page 114 ICR0H on page 115 ICR0L on page 116 TCCR0A on page 103 TCCR0B on page 106 TIFR0 on page 118 TIMSK0 on page 117 Analog Comparator on page 120 13.3. Accessing 16-bit Registers The TCNT0, OCR0A/B, and ICR0 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be accessed byte-wise, using two read or write operations. Each 16-bit Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 83 timer has a single 8-bit TEMP register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the TEMP register in the same clock cycle as the low byte is read, and must be read subsequently. Note: To perform a 16-bit write operation, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR0A/B 16-bit registers does not involve using the temporary register. 16-bit Access The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B and ICR0 Registers. Note that when using C, the compiler handles the 16-bit access. Assembly Code Example ... ; Set TCNT0 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT0H,r17 out TCNT0L,r16 ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ... The assembly code example returns the TCNT0 value in the r17:r16 register pair. C Code Example unsigned int i; ... /* Set TCNT0 to 0x01FF */ TCNT0 = 0x1FF; /* Read TCNT0 into i */ i = TCNT0; ... Atomic Read It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to perform an atomic read of the TCNT0 Register contents. A OCR0A/B or ICR0 Registers can be ready by using the same principle. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 84 Assembly Code Example TIM16_ReadTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT0 into r17:r16 in r16,TCNT0L in r17,TCNT0H ; Restore global interrupt flag out SREG,r18 ret The assembly code example returns the TCNT0 value in the r17:r16 register pair. C Code Example unsigned int TIM16_ReadTCNT0( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT0 into i */ i = TCNT0; /* Restore global interrupt flag */ SREG = sreg; return i; } Atomic Write The following code examples show how to do an atomic write of the TCNT0 Register contents. Writing any of the OCR0A/B or ICR0 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT0. C Code Example void TIM16_WriteTCNT0( unsigned int i ) { Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 85 } unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT0 to i */ TCNT0 = i; /* Restore global interrupt flag */ SREG = sreg; 13.3.1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, the high byte only needs to be written once to TEMP. However, the same rule of atomic operation described previously also applies in this case. 13.4. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select bits in the Timer/Counter control Register B (TCCR0B.CS0[2:0]). 13.4.1. Internal Clock Source - Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the TCCR0B.CS0[2:0]=0x1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. Figure 13-2 Prescaler for Timer/Counter0 clk I/O Cle a r P S R10 T0 S ynchroniza tion clkT0 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 86 13.4.2. Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter 0 (T0). Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (TCCR0B.CS0[2:0] = 2, 3, 4, or 5). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 13.4.3. External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. See also the block diagram of the T0 synchronization and edge detector logic below. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CS0[2:0]=0x7) or negative (CS0[2:0]=0x6) edge it detects. Figure 13-3 T0 Pin Sampling Tn D Q D Q D Tn_s ync (To Clock S e le ct Logic) Q LE clk I/O S ynchroniza tion Edge De te ctor Note: The "n" indicates the device number (n = 0 for Timer/Counter 0) The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by the tolerances of the oscillator source (crystal, resonator, and capacitors), it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. 13.5. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit, as shown in the block diagram: Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 87 Figure 13-4 Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction TCNTn (16-bit Counter) Control Logic Edge Detector clkTn Tn ( From Prescaler ) TOP BOTTOM Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). Table 13-2 Signal description (internal signals) Signal Name Description Count Increment or decrement TCNT0 by 1. Direction Select between increment and decrement. Clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. TOP Signalize that TCNT0 has reached maximum value. BOTTOM Signalize that TCNT0 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight bits. The TCNT0H Register can only be accessed indirectly by the CPU. When the CPU does an access to the TCNT0H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT0H value when the TCNT0L is read, and TCNT0H is updated with the temporary register value when TCNT0L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. Note: That there are special cases when writing to the TCNT0 Register while the counter is counting will give unpredictable results. These special cases are described in the sections where they are of importance. Depending on the selected mode of operation, the counter is cleared, incremented, or decremented at each timer clock (clkT0). The clock clkT0 can be generated from an external or internal clock source, as selected by the Clock Select bits in the Timer/Counter0 Control Register B (TCCR0B.CS0[2:0]). When no clock source is selected (CS0[2:0]=0x0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, independent of whether clkT0 is present or not. A CPU write overrides (i.e., has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits in the Timer/ Counter Control Registers A and B (TCCR0B.WGM0[3:2] and TCCR0A.WGM0[1:0]). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0x. For more details about advanced counting sequences and waveform generation, see Modes of Operation on page 93. The Timer/Counter Overflow Flag in the TC0 Interrupt Flag Register (TIFR0.TOV0) is set according to the mode of operation selected by the WGM0[3:0] bits. TOV0 can be used for generating a CPU interrupt. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 88 13.6. Input Capture Unit The Timer/Counter0 incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP0 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the timestamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram below. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The lower case "n" in register and bit names indicates the Timer/Counter number. Figure 13-5 Input Capture Unit Block Diagram for Timer/Counter0 DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator TCNTnL (8-bit) TCNTn (16-bit Counter) ACIC* ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). Note: Analog comparator can be used for only Timer/Counter0 and not applicable for Timer/Counter3 or Timer/Counter4. When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), or alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered: the 16-bit value of the counter (TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag (ICF0) is set at the same system clock cycle as the TCNT0 value is copied into the ICR0 Register. If enabled (TIMSK0.ICIE0=1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF0 Flag can be cleared by software by writing '1' to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR0) is done by first reading the low byte (ICR0L) and then the high byte (ICR0H). When the low byte is read form ICR0L, the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR0H I/O location it will access the TEMP Register. The ICR0 Register can only be written when using a Waveform Generation mode that utilizes the ICR0 Register for defining the counter's TOP value. In these cases the Waveform Generation mode bits (WGM0[3:0]) must be set before the TOP value can be written to the ICR0 Register. When writing the ICR0 Register, the high byte must be written to the ICR0H I/O location before the low byte is written to ICR0L. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 89 See also Accessing 16-bit Registers on page 83. 13.6.1. Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP0). Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T0 pin. The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. The input of the noise canceler and edge detector is always enabled unless the Timer/ Counter is set in a Waveform Generation mode that uses ICR0 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP0 pin. Related Links ACSR on page 121 13.6.2. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler bit in the Timer/Counter Control Register B (TCCR0B.ICNC0). When enabled, the noise canceler introduces an additional delay of four system clock cycles between a change applied to the input and the update of the ICR0 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 13.6.3. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR0 Register before the next event occurs, the ICR0 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR0 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR0 Register has been read. After a change of the edge, the Input Capture Flag (ICF0) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF0 Flag is not required (if an interrupt handler is used). 13.7. Output Compare Units The 16-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0x). If TCNT equals OCR0x the comparator signals a match. A match will set the Output Compare Flag Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 90 (OCF0x) at the next timer clock cycle. If enabled (TIMSK0.OCIE0x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF0x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF0x Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM0[3:0]) bits and Compare Output mode (COM0x[1:0]) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation, see Modes of Operation on page 93. A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Below is a block diagram of the Output Compare unit. The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 13-6 Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, nonsymmetrical PWM pulses, thereby making the output glitch-free. When double buffering is enabled, the CPU has access to the OCR0x Buffer Register. When double buffering is disabled, the CPU will access the OCR0x directly. The content of the OCR0x (Buffer or Compare) Register is only changed by a write operation (the Timer/ Counter does not update this register automatically as the TCNT0 and ICR0 Register). Therefore OCR0x is not read via the high byte temporary register (TEMP). However, it is good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR0x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR0xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 91 value written. Then when the low byte (OCR0xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR0x buffer or OCR0x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers on page 83. 13.7.1. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a '1' to the Force Output Compare (TCCR0C.FOC0x) bit. Forcing compare match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare match had occurred (the TCCR0A.COM0x[1:0] bits define whether the OC0x pin is set, cleared or toggled). 13.7.2. Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 13.7.3. Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the TCCR0A.COM0x[1:0] bits are not double buffered together with the compare value. Changing the TCCR0A.COM0x[1:0] bits will take effect immediately. 13.8. Compare Match Output Unit The Compare Output mode bits in the Timer/Counter Control Register A (TCCR0A.COM0x) have two functions: * * The Waveform Generator uses the COM0x bits for defining the Output Compare (OC0x) register state at the next compare match. The COM0x bits control the OC0x pin output source The figure below shows a simplified schematic of the logic affected by COM0x. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers that are affected by the COM0x bits are shown, namely PORT and DDR. On system reset the OC0x Register is reset to 0x00. Note: 'OC0x state' is always referring to internal OC0x registers, not the OC0x pin. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 92 Figure 13-7 Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The In the Data Direction Register, the bit for the OC0x pin (DDR.OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x register state before the output is enabled. Some TCCR0A.COM0x[1:0] bit settings are reserved for certain modes of operation. The TCCR0A.COM0x[1:0] bits have no effect on the Input Capture unit. 13.8.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the TCCR0A.COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the TCCR0A.COM0x[1:0]=0x0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next compare match. Refer also to the descriptions of the output modes. A change of the TCCR0A.COM0x[1:0] bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the TCCR0C.FOC0x strobe bits. 13.9. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM0[3:0]) and Compare Output mode (TCCR0A.COM0x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The TCCR0A.COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the TCCR0A.COM0x[1:0] bits control whether the output should be set, cleared, or toggle at a compare match. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 93 13.9.1. Normal Mode The simplest mode of operation is the Normal mode (WGM0[3:0]=0x0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX=0xFFFF) and then restarts from BOTTOM=0x0000. In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. In this case, the TOV0 Flag in behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 13.9.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC modes (mode 4 or 12, WGM0[3:0]=0x4 or 0xC), the OCR0A or ICRn registers are used to manipulate the counter resolution: the counter is cleared to ZERO when the counter value (TCNT0) matches either the OCR0A (if WGM0[3:0]=0x4) or the ICR0 (WGM0[3:0]=0xC). The OCR0A or ICR0 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown below. The counter value (TCNT0) increases until a compare match occurs with either OCR0A or ICR0, and then TCNT0 is cleared. Figure 13-8 CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF0A or ICF0 Flag, depending on the actual CTC mode. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care, since the CTC mode does not provide double buffering. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then count to its maximum value (0xFF for a 8-bit counter, 0xFFFF for a 16-bit counter) and wrap around starting at 0x00 before the compare match will occur. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 94 In many cases this feature is not desirable. An alternative will then be to use the Fast PWM mode using OCR0A for defining TOP (WGM0[3:0]=0xF), since the OCR0A then will be double buffered. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A[1:0]=0x1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC0A=1). The waveform generated will have a maximum frequency of fOC0A = fclk_I/O/2 when OCR0A is set to ZERO (0x0000). The waveform frequency is defined by the following equation: OCnA = clk_I/O 2 1 + OCRnA Note: * The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0). * N represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the Timer Counter TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 13.9.3. Fast PWM Mode The Fast Pulse Width Modulation or Fast PWM modes (modes 5, 6, 7, 14,and 15, WGM0[3:0]= 0x5, 0x6, 0x7, 0xE, 0xF) provide a high frequency PWM waveform generation option. The Fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the Fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the Fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for Fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A register set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A registers set to MAX). The PWM resolution in bits can be calculated by using the following equation: FPWM = log TOP+1 log 2 In Fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM0[3:0] = 0x5, 0x6, or 0x7), the value in ICR0 (WGM0[3:0]=0xE), or the value in OCR0A (WGM0[3:0]=0xF). The counter is then cleared at the following timer clock cycle. The timing diagram for the Fast PWM mode using OCR0A or ICR0 to define TOP is shown below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT0 slopes mark compare matches between OCR0x and TCNT0. The OC0x Interrupt Flag will be set when a compare match occurs. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 95 Figure 13-9 Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition, when either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 Flag is set at the same timer clock cycle TOV0 is set. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR0x Registers are written. The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOP value. The ICR0 Register is not double buffered. This means that if ICR0 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR0 value written is lower than the current value of TCNT0. As result, the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR0A Register however, is double buffered. This feature allows the OCR0A I/O location to be written anytime. When the OCR0A I/O location is written the value written will be put into the OCR0A Buffer Register. The OCR0A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT0 matches TOP. The update is done at the same timer clock cycle as the TCNT0 is cleared and the TOV0 Flag is set. Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR0A as TOP is clearly a better choice due to its double buffer feature. In Fast PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Writing the COM0x[1:0] bits to 0x2 will produce an inverted PWM and a non-inverted PWM output can be generated by writing the COM0x[1:0] to 0x3. The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 96 OCnxPWM = clk_I/O 1 + TOP Note: * The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). * N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCR0x registers represents special cases when generating a PWM waveform output in the Fast PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR0x equal to TOP will result in a constant high or low output (depending on the polarity of the output which is controlled by COM0x[1:0]). A frequency waveform output with 50% duty cycle can be achieved in Fast PWM mode by selecting OC0A to toggle its logical level on each compare match (COM0A[1:0]=0x1). This applies only if OCR0A is used to define the TOP value (WGM0[3:0]=0xF). The waveform generated will have a maximum frequency of fOC0A = fclk_I/O/2 when OCR0A is set to zero (0x0000). This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the Fast PWM mode. 13.9.4. Phase Correct PWM Mode The Phase Correct Pulse Width Modulation or Phase Correct PWM modes (WGM0[3:0]= 0x1, 0x2, 0x3, 0xA, and 0xB) provide a high resolution, phase correct PWM waveform generation option. The Phase Correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while up-counting, and set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the Phase Correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated by using the following equation: PCPWM = log TOP+1 log 2 In Phase Correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM0[3:0]= 0x1, 0x2, or 0x3), the value in ICR0 (WGM0[3:0]=0xA), or the value in OCR0A (WGM0[3:0]=0xB). The counter has then reached the TOP and changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the Phase Correct PWM mode is shown below, using OCR0A or ICR0 to define TOP. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT0 slopes mark compare matches between OCR0x and TCNT0. The OC0x Interrupt Flag will be set when a compare match occurs. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 97 Figure 13-10 Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. When either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 Flag is set accordingly at the same timer clock cycle as the OCR0x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR0x registers is written. As illustrated by the third period in the timing diagram, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR0x Register. Since the OCR0x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value, there are practically no differences between the two modes of operation. In Phase Correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Writing COM0x[1:0] bits to 0x2 will produce a non-inverted PWM. An inverted PWM output can be generated by writing the COM0x[1:0] to 0x3. The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using Phase Correct PWM can be calculated by the following equation: OCnxPCPWM = clk_I/O 2 TOP N represents the prescale divider (1, 8, 64, 256, or 1024). Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 98 The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in the Phase Correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR0A is used to define the TOP value (WGM0[3:0]=0xB) and COM0A[1:0]=0x1, the OC0A output will toggle with a 50% duty cycle. 13.9.5. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM0[3:0] = 0x8 or 0x9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while up-counting, and set on the compare match while down-counting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR0x Register is updated by the OCR0x Buffer Register, (see Figure 13-10 Phase Correct PWM Mode, Timing Diagram on page 98 and the Timing Diagram below). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR0 or OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated using the following equation: PFCPWM = log TOP+1 log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR0 (WGM0[3:0]=0x8), or the value in OCR0A (WGM0[3:0]=0x9). The counter has then reached the TOP and changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown below. The figure shows phase and frequency correct PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. The OC0x Interrupt Flag will be set when a compare match occurs. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 99 Figure 13-11 Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated with the double buffer value (at BOTTOM). When either OCR0A or ICR0 is used for defining the TOP value, the OC0A or ICF0 Flag set when TCNT0 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x. As shown in the timing diagram above, the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR0x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR0A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to 0x2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x[1:0] to 0x3 (See description of TCCR0A.COM0x). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0 when the counter increments, and clearing (or setting) the OC0x Register at compare match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: OCnxPFCPWM = Note: clk_I/O 2 TOP Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 100 * * The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR0A is used to define the TOP value (WGM0[3:0]=0x9) and COM0A[1:0]=0x1, the OC0A output will toggle with a 50% duty cycle. 13.10. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR0x Register is updated with the OCR0x buffer value (only for modes utilizing double buffering). The first figure shows a timing diagram for the setting of OCF0x. Figure 13-12 Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The next figure shows the same timing data, but with the prescaler enabled. Figure 13-13 Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 101 Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR0x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 Flag at BOTTOM. Figure 13-14 Timer/Counter Timing Diagram, no Prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). The next figure shows the same timing data, but with the prescaler enabled. Figure 13-15 Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn(FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Note: The "n" in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the "x" indicates Output Compare unit (A/B). 13.11. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 102 13.11.1. Timer/Counter0 Control Register A Name: TCCR0A Offset: 0x2E Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 1 0 COM0A1 COM0A0 COM0B1 COM0B0 3 2 WGM01 WGM00 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 7:6 - COM0An: Compare Output Mode for Channel A [n = 1:0] Bits 5:4 - COM0Bn: Compare Output Mode for Channel B [n = 1:0] The COM0A[1:0] and COM0B[1:0] control the Output Compare pins (OC0A and OC0B respectively) behavior. If one or both of the COM0A[1:0] bits are written to one, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM0B[1:0] bit are written to one, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A or OC0B pin must be set in order to enable the output driver. When the OC0A or OC0B is connected to the pin, the function of the COM0x[1:0] bits is dependent of the WGM0[3:0] bits setting. The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to a Normal or a CTC mode (non-PWM). Table 13-3 Compare Output Mode, non-PWM COM0A1/COM0B1 COM0A0/COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 Toggle OC0A/OC0B on Compare Match. 1 0 Clear OC0A/OC0B on Compare Match (Set output to low level). 1 1 Set OC0A/OC0B on Compare Match (Set output to high level). The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the fast PWM mode. Table 13-4 Compare Output Mode, Fast PWM COM0A1/ COM0B1 COM0A0/ COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 WGM0[3:0]=0: Normal port operation, OC0A/OC0B disconnected WGM0[3:0]=1: Toggle OC0A on compare match, OC0B reserved Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 103 COM0A1/ COM0B1 COM0A0/ COM0B0 Description 1(1) 0 Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM (non-inverting mode) 1(1) 1 Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode on page 95 for details. The table below shows the COM0x[1:0] bit functionality when the WGM0[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 13-5 Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM COM0A1/ COM0B1 COM0A0/ COM0B0 Description 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 WGM0[3:0]=0: Normal port operation, OC0A/OC0B disconnected WGM0[3:0]=1: Toggle OC0A on compare match, OC0B reserved 1(1) 0 Clear OC0A/OC0B on Compare Match when up-counting. Set OC0A/OC0B on Compare Match when down-counting. 1(1) 1 Set OC0A/OC0B on Compare Match when up-counting. Clear OC0A/OC0B on Compare Match when down-counting. Note: 1. A special case occurs when OCR0A/OCR0B equals TOP and COM0A1/COM0B1 is set. Refer to Phase Correct PWM Mode on page 97 for details. Bits 1:0 - WGM0n: Waveform Generation Mode [n = 1:0] Combined with the WGM0[3:2] bits found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation on page 93). Table 13-6 Waveform Generation Mode Bit Description Mode WGM0[3:0] Timer/Counter Mode of Operation TOP Update of OCR0x at 0 0000 Normal 0xFFFF Immediate TOV0 Flag Set on MAX 1 0001 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0010 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0011 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0100 CTC (Clear Timer on Compare) OCR0A Immediate MAX 5 0101 Fast PWM, 8-bit 0x00FF TOP TOP 6 0110 Fast PWM, 9-bit 0x01FF TOP TOP Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 104 Mode WGM0[3:0] Timer/Counter Mode of Operation TOP Update of OCR0x at 7 0111 Fast PWM, 10-bit 0x03FF TOP TOV0 Flag Set on TOP 8 1000 PWM, Phase and Frequency Correct ICR0 BOTTOM BOTTOM 9 1001 PWM, Phase and Frequency Correct OCR0A BOTTOM BOTTOM 10 1010 PWM, Phase Correct ICR0 TOP BOTTOM 11 1011 PWM, Phase Correct OCR0A TOP BOTTOM 12 1100 CTC (Clear Timer on Compare) ICR0 Immediate MAX 13 1101 Reserved - - - 14 1110 Fast PWM ICR0 TOP TOP 15 1111 Fast PWM OCR0A TOP TOP Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 105 13.11.2. Timer/Counter0 Control Register B Name: TCCR0B Offset: 0x2D Reset: 0x00 Property: - Bit Access Reset 7 6 4 3 ICNC0 ICES0 5 WGM03 WGM02 2 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CS0[2:0] Bit 7 - ICNC0: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP0) is filtered. The filter function requires four successive equal valued samples of the ICP0 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. Bit 6 - ICES0: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP0) that is used to trigger a capture event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES0 setting, the counter value is copied into the Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR0 is used as TOP value (see description of the WGM0[3:0] bits located in the TCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Capture function is disabled. Bit 4 - WGM03: Waveform Generation Mode Refer to TCCR0A. Bit 3 - WGM02: Waveform Generation Mode Refer to TCCR0A. Bits 2:0 - CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to Figure 13-12 Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling on page 101 and Figure 13-13 Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) on page 101. Table 13-7 Clock Select Bit Description CA0[2] CA0[1] CS0[0] Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 106 CA0[2] CA0[1] CS0[0] Description 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter 0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 107 13.11.3. Timer/Counter0 Control Register C Name: TCCR0C Offset: 0x2C Reset: 0x00 Property: - Bit Access Reset 7 6 FOC0A FOC0B R/W R/W 0 0 5 4 3 2 1 0 Bit 7 - FOC0A: Force Output Compare for Channel A Bit 6 - FOC0B: Force Output Compare for Channel B The FOC0A/FOC0B bits are only active when the WGM0[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC0A/FOC0B bit, an immediate compare match is forced on the Waveform Generation unit. The OC0A/OC0B output is changed according to its COM0x[1:0] bits setting. Note that the FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the COM0x[1:0] bits that determine the effect of the forced compare. A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR0A as TOP. The FOC0A/FOC0B bits are always read as zero. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 108 13.11.4. Timer/Counter0 High byte Name: TCNT0H Offset: 0x29 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (TCNT0[15:8]) TCNT0H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (TCNT0[15:8]) TCNT0H[7:0]: Timer/Counter 0 High byte TCNT0H and TCNT0L are combined into TCNT0. It also means TCNT0H[7:0] is TCNT0 [15:8]. Refer to TCNT0L for more detail. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 109 13.11.5. Timer/Counter0 Low byte Name: TCNT0L Offset: 0x28 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (TCNT0[7:0]) TCNT0L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (TCNT0[7:0]) TCNT0L[7:0]: Timer/Counter 0 Low byte TCNT0H and TCNT0L are combined into TCNT0. It also means TCNT0L[7:0] is TCNT0[7:0]. The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers on page 83 for details. Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a compare match between TCNT0 and one of the OCR0x Registers. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock for all compare units. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 110 13.11.6. Output Compare Register 0 A High byte Name: OCR0AH Offset: 0x27 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (OCR0A[15:8]) OCR0AH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (OCR0A[15:8]) OCR0AH[7:0]: Output Compare 0 A High byte OCR0AH and OCR0AL are combined into OCR0A. It means OCR0AH[7:0] is OCR0A [15:8]. Refer to OCR0AL. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 111 13.11.7. Output Compare Register 0 A Low byte Name: OCR0AL Offset: 0x26 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (OCR0A[7:0]) OCR0AL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (OCR0A[7:0]) OCR0AL[7:0]: Output Compare 0 A Low byte OCR0AH and OCR0AL are combined into OCR0A. It means OCR0AL[7:0] is OCR0A[7:0]. The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers on page 83 for details. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 112 13.11.8. Output Compare Register 0 B High byte Name: OCR0BH Offset: 0x25 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (OCR0B[15:8]) OCR0BH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (OCR0B[15:8]) OCR0BH[7:0]: Output Compare 0 B High byte OCR0BH and OCR0BL are combined into OCR0B. It means OCR0BH[7:0] is OCR0B[15:8]. Refer to OCR0BL. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 113 13.11.9. Output Compare Register 0 B Low byte Name: OCR0BL Offset: 0x24 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (OCR0B[7:0]) OCR0BL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (OCR0B[7:0]) OCR0BL[7:0]: Output Compare 0 B Low byte OCR0BH and OCR0BL are combined into OCR0B. It means OCR0BL[7:0] is OCR0B[7:0]. The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See "Accessing 16-bit Registers". Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 114 13.11.10. Input Capture Register 0 High byte Name: ICR0H Offset: 0x23 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (ICR0[15:8]) ICR0H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (ICR0[15:8]) ICR0H[7:0]: Input Capture 0 High byte ICR0H and ICR0L are combined into ICR0. It means ICR0H[7:0] is ICR0[15:8]. Refer to ICR0L. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 115 13.11.11. Input Capture Register 0 Low byte Name: ICR0L Offset: 0x22 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 (ICR0[7:0]) ICR0L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - (ICR0[7:0]) ICR0L[7:0]: Input Capture 0 Low byte ICR0H and ICR0L are combined into ICR0. It means ICR0L[7:0] is ICR0[7:0]. The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers on page 83 for details. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 116 13.11.12. Timer/Counter0 Interrupt Mask Register Name: TIMSK0 Offset: 0x2B Reset: 0x00 Property: - Bit Access Reset 7 6 2 1 0 ICIE0 5 4 3 OCIE0B OCIE0A TOIE0 R/W R/W R/W R/W 0 0 0 0 Bit 5 - ICIE0: Timer/Counter0, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICF0 Flag, located in TIFR0, is set. Bit 2 - OCIE0B: Timer/Counter0, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter 0 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0B Flag, located in TIFR0, is set. Bit 1 - OCIE0A: Timer/Counter0, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCF0A Flag, located in TIFR0, is set. Bit 0 - TOIE0: Timer/Counter0, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the TOV0 Flag, located in TIFR0, is set. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 117 13.11.13. Timer/Counter0 Interrupt Flag Register Name: TIFR0 Offset: 0x2A Reset: 0x00 Property: Bit Access Reset 7 6 2 1 0 ICF0 5 4 3 OCF0B OCF0A TOV0 R/W R/W R/W R/W 0 0 0 0 Bit 5 - ICF0: Timer/Counter0, Input Capture Flag This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register (ICR0) is set by the WGM0[3:0] to be used as the TOP value, the ICF0 Flag is set when the counter reaches the TOP value. ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF0 can be cleared by writing a logic one to its bit location. Bit 2 - OCF0B: Timer/Counter0, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register B (OCR0B). Note that a Forced Output Compare (FOC0B) strobe will not set the OCF0B Flag. OCF0B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF0B can be cleared by writing a logic one to its bit location. Bit 1 - OCF0A: Timer/Counter0, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output Compare Register A (OCR0A). Note that a Forced Output Compare (FOC0A) strobe will not set the OCF0A Flag. OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF0A can be cleared by writing a logic one to its bit location. Bit 0 - TOV0: Timer/Counter0, Overflow Flag The setting of this flag is dependent of the WGM0[3:0] bits setting. In Normal and CTC modes, the TOV0 Flag is set when the timer overflows. Refer to Table 13-6 Waveform Generation Mode Bit Description on page 104 for the TOV0 Flag behavior when using another WGM0[3:0] bit setting. TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed. Alternatively, TOV0 can be cleared by writing a logic one to its bit location. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 118 13.11.14. General Timer/Counter Control Register Name: GTCCR Offset: 0x2F Reset: 0x00 Property: Bit Access Reset 7 6 5 4 3 2 1 0 TSM PSR R/W R/W 0 0 Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. Bit 0 - PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 119 14. Analog Comparator 14.1. Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO (on Port E[0]), is set. The comparator's output can be set to trigger the Timer/ Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown below. The Power Reduction ADC bit in the Power Reduction Register (PRR.PRADC) must be written to '0' in order to be able to use the ADC input MUX. Figure 14-1 Analog Comparator Block Diagram Note: Refer to the Pin Configuration and the I/O Ports description for Analog Comparator pin placement. Related Links Pin Configurations on page 7 14.2. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 120 14.2.1. Analog Comparator Control and Status Register Name: ACSR Offset: 0x1F Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit Access Reset 5 4 3 2 1 0 ACD 7 6 ACO ACI ACIE ACIC ACIS1 ACIS0 R/W R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter0 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/ Counter0 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter0 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK0) must be set. Bits 1:0 - ACISn: Analog Comparator Interrupt Mode Select [n = 1:0] These bits determine which comparator events that trigger the Analog Comparator interrupt. Table 14-1 ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 121 ACIS1 ACIS0 Interrupt Mode 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 122 14.2.2. Digital Input Disable Register 0 When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Name: DIDR0 Offset: 0x17 Reset: 0x00 Property: - Bit 7 6 5 4 Access Reset 3 2 1 0 ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R/W 0 0 0 0 Bit 3 - ADC3D: ADC3 Digital Input Disable Not apply for AC. Bit 2 - ADC2D: ADC2 Digital Input Disable Not apply for AC. Bit 1 - ADC1D: ADC1 Digital Input Disable Bit 0 - ADC0D: ADC0 Digital Input Disable For AC: When this bit is set, the digital input buffer on pin AIN1 (ADC1) / AIN0 (ADC0) is disabled and the corresponding PIN register bit will read as zero. When used as an analog input but not required as a digital input the power consumption in the digital input buffer can be reduced by writing this bit to logic one. For ADC: When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 123 15. ADC - Analog to Digital Converter 15.1. Features * * * * * * * * * * * * 15.2. 8-bit Resolution 0.5 LSB Integral Non-Linearity 1 LSB Absolute Accuracy 65 s Conversion Time 15 kSPS at Full Resolution Four Multiplexed Single Ended Input Channels Input Voltage Range: 0 - VCC Supply Voltage Range: 2.5 V - 5.5 V Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler Overview ATtiny5/10 feature an 8-bit, successive approximation ADC. The ADC is connected to a 4-channel analog multiplexer which allows four single-ended voltage inputs constructed from the pins of port B. The singleended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. Internal reference voltage of VCC is provided on-chip. The ADC is not available in ATtiny4/9. The Power Reduction ADC bit in the Power Reduction Register (PRR.PRADC) must be written to '0' in order to be enable the ADC. The ADC converts an analog input voltage to an 8-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the voltage on VCC. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 124 Figure 15-1 Analog to Digital Converter Block Schematic Operation ADCSRB ADCL ADIE ADEN ADP S 0 ADP S 1 ADP S 2 ADS C ADCSRA ADATE MUX1 ADC IRQ TRIGGER SELECT PRESCALER ADIF S TART CHANNEL DECODER ADC7:0 MUX0 ADMUX ADTS 2:0 INTERRUP T FLAGS 8-BIT DATA BUS CONVERSION LOGIC VREF VCC 8-BIT DAC - ADC3 ADC2 ADC1 + INPUT MUX S AMP LE & HOLD COMPARATOR ADC0 The analog input channel is selected by writing to the MUX bits in the ADC Multiplexer Selection register (ADMUX.MUX). Any of the ADC input pins can be selected as single ended inputs to the ADC. The ADC is enabled by writing a '1' to the ADC Enable bit in the ADC Control and Status Register A (ADCSRA.ADEN). Voltage reference and input channel selections will not take effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. Related Links PRR on page 45 ADMUX on page 134 ADCL on page 138 15.3. Starting a Conversion A single conversion is started by writing a '0' to the Power Reduction ADC bit in the Power Reduction Register (PRR.PRADC), and writing a '1' to the ADC Start Conversion bit in the ADC Control and Status Register A (ADCSRA.ADSC). ADCS will stay high as long as the conversion is in progress, and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit (ADCSRA.ADATE). The trigger source is selected by setting the ADC Trigger Select bits in the ADC Control and Status Register B (ADCSRB.ADTS). See the description of the ADCSRB.ADTS for a list of available trigger sources. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 125 When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in the AVR Status REgister (SREG.I) is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 15-2 ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . SOURCE n CONVERSION LOGIC EDGE DETECTOR ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a '1' to ADCSRA.ADSC. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag (ADIF) is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADCSRA.ADSC to '1'. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as '1' during a conversion, independently of how the conversion was started. Related Links PRR on page 45 15.4. Prescaling and Conversion Timing By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is selected by the ADC Prescaler Select bits in the ADC Control and Status Register A (ADCSRA.ADPS). The prescaler starts counting from the moment the ADC is switched on by writing the ADC Enable bit ADCSRA.ADEN to '1'. The prescaler keeps running for as long as ADEN=1, and is continuously reset when ADEN=0. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 126 Figure 15-3 ADC Prescaler ADEN START Reset CK/64 CK/128 CK/32 CK/8 CK/16 CK/2 CK/4 7-BIT ADC PRESCALER CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE When initiating a single ended conversion by writing a '1' to the ADC Start Conversion bit (ADCSRA.ADSC), the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (i.e., ADCSRA.ADEN is written to '1') takes 25 ADC clock cycles in order to initialize the analog circuitry, as the figure below. Figure 15-4 ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conve rs ion Firs t Conve rs ion Cycle Numbe r 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADS C ADIF Conve rs ion Re s ult ADCL MUX Upda te Conve rs ion MUX Comple te Upda te S a mple & Hold The actual sample-and-hold takes place 3 ADC clock cycles after the start of a normal conversion and 16 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers (ADCL), and the ADC Interrupt Flag (ADCSRA.ADIF) is set. In Single Conversion mode, ADCSRA.ADSC is cleared simultaneously. The software may then set ADCSRA.ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 15-5 ADC Timing Diagram, Single Conversion One Conve rs ion 1 Cycle Numbe r 2 3 4 5 6 7 8 9 Next Conve rs ion 10 11 12 13 1 2 3 ADC Clock ADS C ADIF ADCL Conve rs ion Re s ult MUX Upda te S a mple & Hold Conve rs ion MUX Comple te Upda te When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as the next figure. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and- Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 127 hold takes place 2 ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 15-6 ADC Timing Diagram, Auto Triggered Conversion One Conve rs ion 1 Cycle Numbe r 2 3 4 5 6 7 8 9 Next Conve rs ion 10 11 12 13 1 2 ADC Clock Trigge r S ource ADATE ADIF ADCL Conve rs ion Re s ult Conve rs ion P re s ca le r Re s e t Comple te S a mple & Hold P re s ca le r MUX Re s e t Upda te In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADCRSA.ADSC remains high. See also the ADC Conversion Time table below. Figure 15-7 ADC Timing Diagram, Free Running Conversion One Conve rs ion Cycle Numbe r 11 12 Next Conve rs ion 13 1 2 3 4 ADC Clock ADS C ADIF ADCL Conve rs ion Re s ult Conve rs ion comple te MUX upda te S a mple & Hold Table 15-1 ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 16.5 25 Normal conversions, single ended 3.5 13 Auto Triggered conversions 4 13.5 15.5. Changing Channel or Reference Selection The Analog Channel Selection bits (MUX) in the ADC Multiplexer Selection Register (ADCMUX.MUX) are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 128 selection is continuously updated until a conversion is started. Once the conversion starts, the channel selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (indicated by ADCSRA.ADIF set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after the ADC Start Conversion bit (ADCRSA.ADSC) was written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both the ADC Auto Trigger Enable (ADCRSA.ADATE) and ADC Enable bits (ADCRSA.ADEN) are written to '1', an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. When ADATE or ADEN is cleared. 1.1. During conversion, minimum one ADC clock cycle after the trigger event. 1.2. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 15.6. ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: * In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. * In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. The user is advised not to write new channel or reference selection values during Free Running mode. 15.7. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range, which in this case is limited to 0V (VGND) and VREF = Vcc. Single ended channels that exceed VREF will result in codes close to 0xFF. 15.8. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. 2. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 129 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note: The ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADCRSA.ADEN before entering such sleep modes to avoid excessive power consumption. 15.9. Analog Input Circuitry The analog input circuitry for single ended channels is illustrated below. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10 k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 15-8 Analog Input Circuitry IIH ADCn 1..100k IIL CS/H= 14pF VCC/2 15.10. Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: * Keep analog signal paths as short as possible. * Make sure analog tracks run over the analog ground plane * Keep analog tracks well away from high-speed switching digital tracks. * If any port pin is used as a digital output, it mustn't switch while a conversion is in progress. * Place bypass capacitors as close to VCC and GND pins as possible. When high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction Mode. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 130 15.11. ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x00 to 0x01) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 15-9 Offset Error Output Code Ideal ADC Actual ADC Offset Error * VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0xFE to 0xFF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 15-10 Gain Error Output Code Gain Error Ideal ADC Actual ADC VREF * Input Voltage Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 131 Figure 15-11 Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF * Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 15-12 Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 * * VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, nonlinearity, and quantization error. Ideal value: 0.5 LSB. 15.12. ADC Conversion Result After the conversion is complete (ADCSRA.ADIF is set), the conversion result can be found in the ADC Data Registers (ADCL). For single ended conversion, the result is ADC = IN 256 where VIN is the voltage on the selected input pin, and VCC the selected voltage reference (see also descriptions of ADMUX.MUX). 0x00 represents analog ground, and 0xFF represents the selected reference voltage minus one LSB. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 132 15.13. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 133 15.13.1. ADC Multiplexer Selection Register Name: ADMUX Offset: 0x1B Reset: 0x00 Property: - Bit 7 6 5 4 3 2 Access Reset 1 0 MUX1 MUX0 R/W R/W 0 0 Bits 1:0 - MUXn: Analog Channel Selection [n = 1:0] The value of these bits selects which analog inputs are connected to the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADCSRA.ADIF is set). Table 15-2 Input Channel Selection MUX[1:0] Single Ended Input Pin 00 ADC0 PB0 01 ADC1 PB1 10 ADC2 PB2 11 ADC3 PB3 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 134 15.13.2. ADC Control and Status Register A Name: ADCSRA Offset: 0x1D Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. Bits 2:0 - ADPSn: ADC Prescaler Select [n = 2:0] These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 15-3 Input Channel Selection ADPS[2:0] Division Factor 000 2 001 2 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 135 ADPS[2:0] Division Factor 010 4 011 8 100 16 101 32 110 64 111 128 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 136 15.13.3. ADC Control and Status Register B Name: ADCSRB Offset: 0x1C Reset: 0x00 Property: - Bit 7 6 5 4 3 Access Reset 2 1 0 ADTS2 ADTS1 ADTS0 R/W R/W R/W 0 0 0 Bits 2:0 - ADTSn: ADC Auto Trigger Source [n = 2:0] If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 15-4 ADC Auto Trigger Source Selection ADTS[2:0] Trigger Source 000 Free Running mode 001 Analog Comparator 010 External Interrupt Request 0 011 Timer/Counter 0 Compare Match A 100 Timer/Counter 0 Overflow 101 Timer/Counter 0 Compare Match B 110 Pin Change Interrupt 0 Request 111 Timer/Counter 0 Capture Event Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 137 15.13.4. ADC Conversion Result Low Byte When an ADC conversion is complete, the result is found in the ADC register. Name: ADCL Offset: 0x19 Reset: 0x00 Property: Bit 7 6 5 4 3 2 1 0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 - ADCn: ADC Conversion Result [7:0] These bits represent the result from the conversion. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 138 15.13.5. Digital Input Disable Register 0 When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Name: DIDR0 Offset: 0x17 Reset: 0x00 Property: - Bit 7 6 5 4 Access Reset 3 2 1 0 ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R/W 0 0 0 0 Bit 3 - ADC3D: ADC3 Digital Input Disable Not apply for AC. Bit 2 - ADC2D: ADC2 Digital Input Disable Not apply for AC. Bit 1 - ADC1D: ADC1 Digital Input Disable Bit 0 - ADC0D: ADC0 Digital Input Disable For AC: When this bit is set, the digital input buffer on pin AIN1 (ADC1) / AIN0 (ADC0) is disabled and the corresponding PIN register bit will read as zero. When used as an analog input but not required as a digital input the power consumption in the digital input buffer can be reduced by writing this bit to logic one. For ADC: When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 139 16. Programming interface 16.1. Features * * 16.2. Physical Layer: - Synchronous Data Transfer - Bi-directional, Half-duplex Receiver And Transmitter - Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits - Parity Error Detection, Frame Error Detection And Break Character Detection - Parity Generation And Collision Detection - Automatic Guard Time Insertion Between Data Reception And Transmission Access Layer: - Communication Based On Messages - Automatic Exception Handling Mechanism - Compact Instruction Set - NVM Programming Access Control - Tiny Programming Interface Control And Status Space Access Control - Data Space Access Control Overview The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memories (NVM). Memory programming is done via the NVM Controller, by executing NVM controller commands as described in Memory Programming. The Tiny Programming Interface (TPI) provides access to the programming facilities. The interface consists of two layers: the access layer and the physical layer. Figure 16-1 The Tiny Programming Interface and Related Internal Interfaces TINY PROGRAMMING INTERFACE (TPI) RESET TPICLK TPIDATA PHYSICAL LAYER ACCESS LAYER NVM CONTROLLER NON-VOLATILE MEMORIES DATA BUS Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET pin as enable, the TPICLK pin as the clock input, and the TPIDATA pin as data input and output. NVM can be programmed at 5V, only. Related Links MEMPROG- Memory Programming on page 152 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 140 16.3. Physical Layer of Tiny Programming Interface The TPI physical layer handles the basic low-level serial communication. The TPI physical layer uses a bi-directional, half-duplex serial receiver and transmitter. The physical layer includes serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error detection, parity error detection, parity generation and collision detection. The TPI is accessed via three pins, as follows: * RESET: Tiny Programming Interface enable input * TPICLK: Tiny Programming Interface clock input * TPIDATA: Tiny Programming Interface data input/output In addition, the VCC and GND pins must be connected between the external programmer and the device. Figure 16-2 Using an External Programmer for In-System Programming via TPI +5V ATtiny4/5/9/10 TPI CONN TP IDATA/P B0 P B3/RES ET GND VCC TP ICLK/P B1 P B2 APPLICATION NVM can be programmed at 5V, only. In some designs it may be necessary to protect components that can not tolerate 5V with, for example, series resistors. 16.3.1. Enabling The following sequence enables the Tiny Programming Interface: * Apply 5V between VCC and GND * Depending on the method of reset to be used: - Either: wait tTOUT (see System and Reset Characteristics) and then set the RESET pin low. This will reset the device and enable the TPI physical layer. The RESET pin must then be kept low for the entire programming session - Or: if the RSTDISBL configuration bit has been programmed, apply 12V to the RESET pin. The RESET pin must be kept at 12V for the entire programming session * * Wait tRST (see System and Reset Characteristics ) Keep the TPIDATA pin high for 16 TPICLK cycles Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 141 Figure 16-3 Sequence for enabling the Tiny Programming Interface t 16 x TPICLK CYCLES RST RESET TPICLK TPIDATA 16.3.2. Disabling Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inactive high state or, alternatively, if VHV is no longer applied to the RESET pin. If the NVM enable bit is not cleared a power down is required to exit TPI programming mode. See NVMEN bit in TPISR - Tiny Programming Interface Status Register. Related Links TPISR on page 151 16.3.3. Frame Format The TPI physical layer supports a fixed frame format. A frame consists of one character, eight bits in length, and one start bit, a parity bit and two stop bits. Data is transferred with the least significant bit first. Figure 16-4 Serial frame format. TPICLK TPIDATA IDLE ST D0 D1 D7 P SP1 SP2 IDLE/ST Symbols used in the above figure: * ST: Start bit (always low) * D0-D7: Data bits (least significant bit sent first) * P: Parity bit (using even parity) * SP1: Stop bit 1 (always high) * SP2: Stop bit 2 (always high) 16.3.4. Parity Bit Calculation The parity bit is always calculated using even parity. The value of the bit is calculated by doing an exclusive-or of all the data bits, as follows: = 0 1 2 3 4 5 6 7 0 where: * P: Parity bit using even parity * D0-D7: Data bits of the character 16.3.5. Supported Characters The BREAK character is equal to a 12 bit long low level. It can be extended beyond a bit-length of 12. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 142 Figure 16-5 Supported characters. DATA CHARACTER TPIDATA IDLE ST D0 D1 D7 P SP1 SP2 IDLE/ST BREAK CHARACTER TPIDATA 16.3.6. IDLE IDLE/ST Operation The TPI physical layer operates synchronously on the TPICLK provided by the external programmer. The dependency between the clock edges and data sampling or data change is shown in the figure below. Data is changed at falling edges and sampled at rising edges. Figure 16-6 Data changing and Data sampling. TPICLK TPIDATA SAMPLE SETUP The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive mode, waiting for a start bit. The mode of operation is controlled by the access layer. 16.3.7. Serial Data Reception When the TPI physical layer is in receive mode, data reception is started as soon as a start bit has been detected. Each bit that follows the start bit will be sampled at the rising edge of the TPICLK and shifted into the shift register until the second stop bit has been received. When the complete frame is present in the shift register the received data will be available for the TPI access layer. There are three possible exceptions in the receive mode: frame error, parity error and break detection. All these exceptions are signalized to the TPI access layer, which then enters the error state and puts the TPI physical layer into receive mode, waiting for a BREAK character. * * * Frame Error Exception. The frame error exception indicates the state of the stop bit. The frame error exception is set if the stop bit was read as zero. Parity Error Exception. The parity of the data bits is calculated during the frame reception. After the frame is received completely, the result is compared with the parity bit of the frame. If the comparison fails the parity error exception is signalized. Break Detection Exception. The Break detection exception is given when a complete frame of all zeros has been received. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 143 16.3.8. Serial Data Transmission When the TPI physical layer is ready to send a new frame it initiates data transmission by loading the shift register with the data to be transmitted. When the shift register has been loaded with new data, the transmitter shifts one complete frame out on the TPIDATA line at the transfer rate given by TPICLK. If a collision is detected during transmission, the output driver is disabled. The TPI access layer enters the error state and the TPI physical layer is put into receive mode, waiting for a BREAK character. 16.3.9. Collision Detection Exception The TPI physical layer uses one bi-directional data line for both data reception and transmission. A possible drive contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a collision detection mechanism is supported. The collision detection is based on the way the TPI physical layer drives the TPIDATA line. The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver is always enabled when a logical zero is sent. When sending successive logical ones, the output is only driven actively during the first clock cycle. After this, the output driver is automatically tri-stated and the TPIDATA line is kept high by the internal pull-up. The output is re-enabled, when the next logical zero is sent. The collision detection is enabled in transmit mode, when the output driver has been disabled. The data line should now be kept high by the internal pull-up and it is monitored to see, if it is driven low by the external programmer. If the output is read low, a collision has been detected. There are some potential pit-falls related to the way collision detection is performed. For example, collisions cannot be detected when the TPI physical layer transmits a bit-stream of successive logical zeros, or bit-stream of alternating logical ones and zeros. This is because the output driver is active all the time, preventing polling of the TPIDATA line. However, within a single frame the two stop bits should always be transmitted as logical ones, enabling collision detection at least once per frame (as long as the frame format is not violated regarding the stop bits). The TPI physical layer will cease transmission when it detects a collision on the TPIDATA line. The collision is signalized to the TPI access layer, which immediately changes the physical layer to receive mode and goes to the error state. The TPI access layer can be recovered from the error state only by sending a BREAK character. 16.3.10. Direction Change In order to ensure correct timing of the half-duplex operation, a simple guard time mechanism has been added to the physical layer. When the TPI physical layer changes from receive to transmit mode, a configurable number of additional IDLE bits are inserted before the start bit is transmitted. The minimum transition time between receive and transmit mode is two IDLE bits. The total IDLE time is the specified guard time plus two IDLE bits. The guard time is configured by dedicated bits in the TPIPCR register. The default guard time value after the physical layer is initialized is 128 bits. The external programmer looses control of the TPIDATA line when the TPI target changes from receive mode to transmit. The guard time feature relaxes this critical phase of the communication. When the external programmer changes from receive mode to transmit, a minimum of one IDLE bit should be inserted before the start bit is transmitted. 16.3.11. Access Layer of Tiny Programming Interface The TPI access layer is responsible for handling the communication with the external programmer. The communication is based on message format, where each message comprises an instruction followed by one or more byte-sized operands. The instruction is always sent by the external programmer but Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 144 operands are sent either by the external programmer or by the TPI access layer, depending on the type of instruction issued. The TPI access layer controls the character transfer direction on the TPI physical layer. It also handles the recovery from the error state after exception. The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control and status registers in the TPI access Layer. The CSS consist of registers directly involved in the operation of the TPI itself. These register are accessible using the SLDCS and SSTCS instructions. The access layer can also access the data space, either directly or indirectly using the Pointer Register (PR) as the address pointer. The data space is accessible using the SLD, SST, SIN and SOUT instructions. The address pointer can be stored in the Pointer Register using the SLDPR instruction. 16.3.11.1. Message format Each message comprises an instruction followed by one or more byte operands. The instruction is always sent by the external programmer. Depending on the instruction all the following operands are sent either by the external programmer or by the TPI. The messages can be categorized in two types based on the instruction, as follows: * Write messages. A write message is a request to write data. The write message is sent entirely by the external programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions. * Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte operands. This message type is used with the SLDCS, SLD and SIN instructions. All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY instruction requires 8 byte operands. For more information, see the TPI instruction set. 16.3.11.2. Exception Handling and Synchronisation Several situations are considered exceptions from normal operation of the TPI. When the TPI physical layer is in receive mode, these exceptions are: * The TPI physical layer detects a parity error. * The TPI physical layer detects a frame error. * The TPI physical layer recognizes a BREAK character. When the TPI physical layer is in transmit mode, the possible exceptions are: * The TPI physical layer detects a data collision. All these exceptions are signalized to the TPI access layer. The access layer responds to an exception by aborting any on-going operation and enters the error state. The access layer will stay in the error state until a BREAK character has been received, after which it is taken back to its default state. As a consequence, the external programmer can always synchronize the protocol by simply transmitting two successive BREAK characters. 16.4. Instruction Set The TPI has a compact instruction set that is used to access the TPI Control and Status Space (CSS) and the data space. The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte operand following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 145 Table 16-1 Instruction Set Summary Mnemonic Operand Description Operation SLD data, PR Serial LoaD from data space using indirect addressing data DS[PR] SLD data, PR+ Serial LoaD from data space using indirect addressing and data DS[PR] post-increment PR PR+1 SST PR, data Serial STore to data space using indirect addressing DS[PR] data SST PR+, data Serial STore to data space using indirect addressing and post-increment DS[PR] data PR PR+1 16.4.1. SSTPR PR, a Serial STore to Pointer Register using direct addressing PR[a] data SIN data, a Serial IN from data space data I/O[a] SOUT a, data Serial OUT to data space I/O[a] data SLDCS data, a Serial LoaD from Control and Status space using direct addressing data CSS[a] SSTCS a, data Serial STore to Control and Status space using direct addressing CSS[a] data SKEY Key, {8{data}} Serial KEY Key {8{data}} SLD - Serial LoaD from data space using indirect addressing The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-register for serial read-out. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before data is accessed. The Pointer Register is either left unchanged by the operation, or post-incremented. Table 16-2 The Serial Load from Data Space (SLD) Instruction 16.4.2. Operation Opcode Remarks Register data DS[PR] 0010 0000 PR PR Unchanged data DS[PR] 0010 0100 PR PR + 1 Post increment SST - Serial STore to data space using indirect addressing The SST instruction uses indirect addressing to store into data space the byte that is shifted into the physical layer shift register. The data space location is pointed by the Pointer Register (PR), where the address must have been stored before the operation. The Pointer Register can be either left unchanged by the operation, or it can be post-incremented. Table 16-3 The Serial Store to Data Space (SST) Instruction Operation Opcode Remarks Register DS[PR] data 0110 0000 PR PR Unchanged DS[PR] data 0110 0000 PR PR + 1 Post increment Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 146 16.4.3. SSTPR - Serial STore to Pointer Register The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer Register is accessed. Table 16-4 The Serial Store to Pointer Register (SSTPR) Instruction 16.4.4. Operation Opcode Remarks PR[a] data 0110 100a Bit `a' addresses Pointer Register byte SIN - Serial IN from i/o space using direct addressing The SIN instruction loads data byte from the I/O space to the shift register of the physical layer for serial read-out. The instuction uses direct addressing, the address consisting of the 6 address bits of the instruction. Table 16-5 The Serial IN from i/o space (SIN) Instruction 16.4.5. Operation Opcode Remarks data I/O[a] 0aa1 aaaa Bits marked `a' form the direct, 6-bit address SOUT - Serial OUT to i/o space using direct addressing The SOUT instruction stores the data byte that is shifted into the physical layer shift register to the I/O space. The instruction uses direct addressing, the address consisting of the 6 address bits of the instruction. Table 16-6 The Serial OUT to i/o space (SOUT) Instruction 16.4.6. Operation Opcode Remarks I/O[a] data 1aa1 aaaa Bits marked `a' form the direct, 6-bit address SLDCS - Serial LoaD data from Control and Status space using direct addressing The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physical layer shift register for serial read-out. The SLDCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction. Table 16-7 The Serial Load Data from Control and Status space (SLDCS) Instruction 16.4.7. Operation Opcode Remarks data CSS[a] 1000 aaaa Bits marked `a' form the direct, 4-bit address SSTCS - Serial STore data to Control and Status space using direct addressing The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift register to the TPI Control and Status Space. The SSTCS instruction uses direct addressing, the direct address consisting of the 4 address bits of the instruction. Table 16-8 The Serial STore data to Control and Status space (SSTCS) Instruction Operation Opcode Remarks CSS[a] data 1100 aaaa Bits marked `a' form the direct, 4-bit address Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 147 16.4.8. SKEY - Serial KEY signaling The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key. Table 16-9 The Serial KEY signaling (SKEY) Instruction 16.5. Operation Opcode Remarks Key {8[data}} 1110 0000 Data bytes follow after instruction Accessing the Non-Volatile Memory Controller By default, NVM programming is not enabled. In order to access the NVM Controller and be able to program the non-volatile memories, a unique key must be sent using the SKEY instruction. Table 16-10 Enable Key for Non-Volatile Memory Programming Key Value NVM Program Enable 0x1289AB45CDD888FF After the key has been given, the Non-Volatile Memory Enable (NVMEN) bit in the TPI Status Register (TPISR) must be polled until the Non-Volatile memory has been enabled. NVM programming is disabled by writing a logical zero to the NVMEN bit in TPISR. 16.6. Control and Status Space Register Descriptions The control and status registers of the Tiny Programming Interface are mapped in the Control and Status Space (CSS) of the interface. These registers are not part of the I/O register map and are accessible via SLDCS and SSTCS instructions, only. The control and status registers are directly involved in configuration and status monitoring of the TPI. Table 16-11 Summary of Control and Status Registers Offset Name 0x0F TPIIR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Tiny Programming Interface Identification Code 0x0E ... Reserved - - - - - - - - 0x02 TPIPCR - - - - - GT2 GT1 GT0 0x01 Reserved - - - - - - - - 0x00 TPISR - - - - - - NVMEN - 0x03 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 148 16.6.1. Tiny Programming Interface Identification Register Name: TPIIR Offset: Reset: 0x00 Property: CSS: 0x0F Bit 7 6 5 4 3 2 1 0 TPIIC[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TPIIC[7:0]: Tiny Programming Interface Identification Code These bits give the identification code for the Tiny Programming Interface. The code can be used be the external programmer to identify the TPI. Table 16-12 Identification Code for Tiny Programming Interface Code Value Interface Identification 0x80 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 149 16.6.2. Tiny Programming Interface Physical Layer Control Register Name: TPIPCR Offset: Reset: 0x00 Property: CSS: 0x02 Bit 7 6 5 4 3 Access Reset 2 1 0 GT2 GT1 GT0 R/W R/W R/W 0 0 0 Bits 2:0 - GTn: Guard Time [n=2:0] These bits specify the number of additional IDLE bits that are inserted to the idle time when changing from reception mode to transmission mode. Additional delays are not inserted when changing from transmission mode to reception. The total idle time when changing from reception to transmission mode is Guard Time plus two IDLE bits. Table 16-13 Identification Code for Tiny Programming Interface GT2 GT1 GT0 Guard Time (Number of IDLE bits) 0 0 0 +128 (default value) 0 0 1 +64 0 1 0 +32 0 1 1 +16 1 0 0 +8 1 0 1 +4 1 1 0 +2 1 1 1 +0 The default Guard Time is 128 IDLE bits. To speed up the communication, the Guard Time should be set to the shortest safe value. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 150 16.6.3. Tiny Programming Interface Status Register Name: TPISR Offset: Reset: 0x00 Property: CSS: 0x00 Bit 7 6 5 4 3 2 1 0 NVMEN Access R/W Reset 0 Bit 1 - NVMEN: Non-Volatile Memory Programming Enabled NVM programming is enabled when this bit is set. The external programmer can poll this bit to verify the interface has been successfully enabled. NVM programming is disabled by writing this bit to zero. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 151 17. MEMPROG- Memory Programming 17.1. Features * * * * * * 17.2. Two Embedded Non-Volatile Memories: - Non-Volatile Memory Lock bits (NVM Lock bits) - Flash Memory Four Separate Sections Inside Flash Memory: - Code Section (Program Memory) - Signature Section - Configuration Section - Calibration Section Read Access to All Non-Volatile Memories from Application Software Read and Write Access to Non-Volatile Memories from External programmer: - Read Access to All Non-Volatile Memories - Write Access to NVM Lock Bits, Flash Code Section and Flash Configuration Section External Programming: - Support for In-System and Mass Production Programming - Programming Through the Tiny Programming Interface (TPI) High Security with NVM Lock Bits Overview The Non-Volatile Memory (NVM) Controller manages all access to the Non-Volatile Memories. The NVM Controller controls all NVM timing and access privileges, and holds the status of the NVM. During normal execution the CPU will execute code from the code section of the Flash memory (program memory). When entering sleep and no programming operations are active, the Flash memory is disabled to minimize power consumption. All NVM are mapped to the data memory. Application software can read the NVM from the mapped locations of data memory using load instruction with indirect addressing. The NVM has only one read port and, therefore, the next instruction and the data can not be read simultaneously. When the application reads data from NVM locations mapped to the data space, the data is read first before the next instruction is fetched. The CPU execution is here delayed by one system clock cycle. Internal programming operations to NVM have been disabled and the NVM therefore appears to the application software as read-only. Internal write or erase operations of the NVM will not be successful. The method used by the external programmer for writing the Non-Volatile Memories is referred to as external programming. External programming can be done both in-system or in mass production. The external programmer can read and program the NVM via the Tiny Programming Interface (TPI). In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections which are read-only. NVM can be programmed at 5V, only. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 152 17.3. Non-Volatile Memories (NVM) The device has the following, embedded NVM: * Non-Volatile Memory Lock Bits * Flash memory with four separate sections 17.3.1. Non-Volatile Memory Lock Bits The device provides two Lock Bits. Table 17-1 Lock Bit Byte Lock Bit Byte Bit No. Description Default Value 7 1 (unprogrammed) 6 1 (unprogrammed) 5 1 (unprogrammed) 4 1 (unprogrammed) 3 1 (unprogrammed) 2 1 (unprogrammed) NVLB2 1 Non-Volatile Lock Bit 1 (unprogrammed) NVLB1 0 Non-Volatile Lock Bit 1 (unprogrammed) The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security. Lock Bits can be erased to "1" with the Chip Erase command, only. Table 17-2 Lock Bit Protection Modes Memory Lock Bits(1) Protection Type LB Mode NVLB2(2) NVLB1(2) 1 1 1 No memory lock features enabled. 2 1 0 Further Programming of the Flash memory is disabled in the external programming mode. The configuration section bits are locked in the external programming mode 3 0 0 Further programming and verification of the flash is disabled in the external programming mode. The configuration section bits are locked in the external programming mode Note: 1. Program the configuration section bits before programming NVLB1 and NVLB2. 2. "1" means unprogrammed, "0" means programmed 17.3.2. Flash Memory The embedded Flash memory has four separate sections. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 153 Table 17-3 Number of Words and Pages in the Flash (ATtiny9/10) Section Size (Bytes) Page Size (Words) Pages WADDR PADDR Code (program memory) 1024 8 64 [3:1] [9:4] Configuration 8 8 1 [3:1] - Signature (1) 16 8 2 [3:1] [4:4] Calibration(1) 8 8 1 [3:1] - Note: 1. This section is read-only. Table 17-4 Number of Words and Pages in the Flash (ATtiny4/5) Section Size (Bytes) Page Size (Words) Pages WADDR PADDR Code (program memory) 512 8 32 [3:1] [9:4] Configuration 8 8 1 [3:1] - Signature (1) 16 8 2 [3:1] [4:4] Calibration(1) 8 8 1 [3:1] - Note: 1. This section is read-only. 17.3.3. Configuration Section ATtiny4/5/9/10 have one configuration byte, which resides in the configuration section. Table 17-5 Configuration bytes Configuration word address Configuration word data High byte Low byte 0x00 Reserved Configuration Byte 0 0x01 ... 0x07 Reserved Reserved The next table briefly describes the functionality of all configuration bits and how they are mapped into the configuration byte. Table 17-6 Configuration Byte 0 Bit Description Default Value 7:3 - Reserved 1 (unprogrammed) 2 CKOUT System Clock Output 1 (unprogrammed) 1 WDTON Watchdog Timer always on 1 (unprogrammed) 0 RSTDISBL External Reset disable 1 (unprogrammed) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 154 Configuration bits are not affected by a chip erase but they can be cleared using the configuration section erase command (see Erasing the Configuration Section in this chapter). Note that configuration bits are locked if Non- Volatile Lock Bit 1 (NVLB1) is programmed. 17.3.3.1. Latching of Configuration Bits All configuration bits are latched either when the device is reset or when the device exits the external programming mode. Changes to configuration bit values have no effect until the device leaves the external programming mode. 17.3.4. Signature Section The signature section is a dedicated memory area used for storing miscellaneous device information, such as the device signature. Most of this memory section is reserved for internal use. Table 17-7 Signature bytes Signature word address Configuration word data High byte Low byte 0x00 Device ID 1 Manufacturer ID 0x01 Reserved for internal use Device ID 2 0x02 ... 0x0F Reserved for internal use Reserved for internal use ATtiny4/5/9/10 have a three-byte signature code, which can be used to identify the device. The three bytes reside in the signature section, as shown in the above table. The signature data for ATtiny4/5/9/10 is given in the next table. Table 17-8 Signature codes Part 17.3.5. Signature Bytes Manufacturer ID Device ID 1 Device ID 2 ATtiny4 0x1E 0x8F 0x0A ATtiny5 0x1E 0x8F 0x09 ATtiny9 0x1E 0x90 0x08 ATtiny10 0x1E 0x90 0x03 Calibration Section ATtiny4/5/9/10 have one calibration byte. The calibration byte contains the calibration data for the internal oscillator and resides in the calibration section. During reset, the calibration byte is automatically written into the OSCCAL register to ensure correct frequency of the calibrated internal oscillator. Table 17-9 Calibration byte Calibration word address Configuration word data High byte Low byte 0x00 Reserved Internal oscillator calibration value 0x01 ... 0x07 Reserved Reserved Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 155 17.3.5.1. Latching of Calibration Value To ensure correct frequency of the calibrated internal oscillator the calibration value is automatically written into the OSCCAL register during reset. 17.4. Accessing the NVM NVM lock bits, and all Flash memory sections are mapped to the data space as shown in Data Memory. The NVM can be accessed for read and programming via the locations mapped in the data space. The NVM Controller recognizes a set of commands that can be used to instruct the controller what type of programming task to perform on the NVM. Commands to the NVM Controller are issued via the NVM Command Register. See NVMCMD - Non-Volatile Memory Command Register. After the selected command has been loaded, the operation is started by writing data to the NVM locations mapped to the data space. When the NVM Controller is busy performing an operation it will signal this via the NVM Busy Flag in the NVM Control and Status Register. See NVMCSR - Non-Volatile Memory Control and Status Register. The NVM Command Register is blocked for write access as long as the busy flag is active. This is to ensure that the current command is fully executed before a new command can start. Programming any part of the NVM will automatically inhibit the following operations: * All programming to any other part of the NVM * All reading from any NVM location ATtiny4/5/9/10 support only external programming. Internal programming operations to NVM have been disabled, which means any internal attempt to write or erase NVM locations will fail. Related Links SRAM Data Memory on page 25 NVMCMD on page 161 NVMCSR on page 160 17.4.1. Addressing the Flash The data space uses byte accessing but since the Flash sections are accessed as words and organized in pages, the byte-address of the data space must be converted to the word-address of the Flash section. The most significant bits of the data space address select the NVM Lock bits or the Flash section mapped to the data memory. The word address within a page (WADDR) is held by bits [WADDRMSB:1], and the page address (PADDR) by bits [PADDRMSB:WADDRMSB+1]. Together, PADDR and WADDR form the absolute address of a word in the Flash section. The least significant bit of the Flash section address is used to select the low or high byte of the word. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 156 Figure 17-1 Addressing the Flash Memory 16 PADDRMS B WADDRMS B+1 WADDRMS B PADDR WADDR 1 0/1 ADDRES S P OINTER LOW /HIGH BY TE S ELECT FLAS H S ECTION FLAS H PAGE 00 00 01 01 02 ... ... ... PAGE PAGE ADDR ES S W ITHIN A FLAS H S ECTION WORD WOR D ADDR ES S W ITHIN A FLAS H PAGE ... ... ... PAGEEND S ECTIONEND 17.4.2. Reading the Flash The Flash can be read from the data memory mapped locations one byte at a time. For read operations, the least significant bit (bit 0) is used to select the low or high byte in the word address. If this bit is zero, the low byte is read, and if it is one, the high byte is read. 17.4.3. Programming the Flash The Flash can be written word-by-word. Before writing a Flash word, the Flash target location must be erased. Writing to an un-erased Flash word will corrupt its content. The Flash is word-accessed for writing, and the data space uses byte-addressing to access Flash that has been mapped to data memory. It is therefore important to write the word in the correct order to the Flash, namely low bytes before high bytes. First, the low byte is written to the temporary buffer. Then, writing the high byte latches both the high byte and the low byte into the Flash word buffer, starting the write operation to Flash. The Flash erase operations can only performed for the entire Flash sections. The Flash programming sequence is as follows: 1. Perform a Flash section erase or perform a Chip erase 2. Write the Flash section word by word 17.4.3.1. Chip Erase The Chip Erase command will erase the entire code section of the Flash memory and the NVM Lock Bits. For security reasons, the NVM Lock Bits are not reset before the code section has been completely erased. Configuration, Signature and Calibration sections are not changed. Before starting the Chip erase, the NVMCMD register must be loaded with the CHIP_ERASE command. To start the erase operation a dummy byte must be written into the high byte of a word location that resides inside the Flash code section. The NVMBSY bit remains set until erasing has been completed. While the Flash is being erased neither Flash buffer loading nor Flash reading can be performed. The Chip Erase can be carried out as follows: 1. Write the 0x10 (CHIP_ERASE) to the NVMCMD register Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 157 2. 3. Start the erase operation by writing a dummy byte to the high byte of any word location inside the code section Wait until the NVMBSY bit has been cleared Related Links NVMCMD on page 161 17.4.3.2. Erasing the Code Section The algorithm for erasing all pages of the Flash code section is as follows: 1. Write the 0x14 (SECTION_ERASE) to the NVMCMD register 2. Start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. Wait until the NVMBSY bit has been cleared Related Links NVMCMD on page 161 17.4.3.3. Writing a Code Word The algorithm for writing a word to the code section is as follows: 1. Write the 0x1D (WORD_WRITE) to the NVMCMD register 2. Write the low byte of the data into the low byte of a word location 3. Write the high byte of the data into the high byte of the same word location. This will start the Flash write operation 4. Wait until the NVMBSY bit has been cleared Related Links NVMCMD on page 161 17.4.3.4. Erasing the Configuration Section The algorithm for erasing the Configuration section is as follows: 1. Write the 0x14 (SECTION_ERASE) to the NVMCMD register 2. Start the erase operation by writing a dummy byte to the high byte of any word location inside the configuration section 3. Wait until the NVMBSY bit has been cleared Related Links NVMCMD on page 161 17.4.3.5. Writing a Configuration Word The algorithm for writing a Configuration word is as follows: 1. Write the 0x1D (WORD_WRITE) to the NVMCMD register 2. Write the low byte of the data to the low byte of a configuration word location 3. Write the high byte of the data to the high byte of the same configuration word location. This will start the Flash write operation. 4. Wait until the NVMBSY bit has been cleared Related Links NVMCMD on page 161 17.4.4. Reading NVM Lock Bits The Non-Volatile Memory Lock Byte can be read from the mapped location in data memory. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 158 17.4.5. Writing NVM Lock Bits The algorithm for writing the Lock bits is as follows: 1. Write the WORD_WRITE command to the NVMCMD register. 2. Write the lock bits value to the Non-Volatile Memory Lock Byte location. This is the low byte of the Non- Volatile Memory Lock Word. 3. Start the NVM Lock Bit write operation by writing a dummy byte to the high byte of the NVM Lock Word location. 4. Wait until the NVMBSY bit has been cleared. Related Links NVMCMD on page 161 17.5. Self programming The ATtiny4/5/9/10 don't support internal programming. 17.6. External Programming The method for programming the Non-Volatile Memories by means of an external programmer is referred to as external programming. External programming can be done both in-system or in mass production. The Non-Volatile Memories can be externally programmed via the Tiny Programming Interface (TPI). For details on the TPI, see Programming interface. Using the TPI, the external programmer can access the NVM control and status registers mapped to I/O space and the NVM memory mapped to data memory space. Related Links Programming interface on page 140 17.6.1. Entering External Programming Mode The TPI must be enabled before external programming mode can be entered. The following procedure describes, how to enter the external programming mode after the TPI has been enabled: 1. Make a request for enabling NVM programming by sending the NVM memory access key with the SKEY instruction. 2. Poll the status of the NVMEN bit in TPISR until it has been set. Refer to the Programming Interface description for more detailed information of enabling the TPI and programming the NVM. Related Links Programming interface on page 140 17.6.2. Exiting External Programming Mode Clear the NVM enable bit to disable NVM programming, then release the RESET pin. See NVMEN bit in TPISR - Tiny Programming Interface Status Register. Related Links TPISR on page 151 17.7. Register Description Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 159 17.7.1. Non-Volatile Memory Control and Status Register Name: NVMCSR Offset: 0x32 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 NVMBSY Access Reset R/W 0 Bit 7 - NVMBSY: Non-Volatile Memory Busy This bit indicates the NVM memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 160 17.7.2. Non-Volatile Memory Command Register Name: NVMCMD Offset: 0x33 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 NVMCMD[5:0] Access Reset R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 5:0 - NVMCMD[5:0]: Non-Volatile Memory Command These bits define the programming commands for the flash. Table 17-10 NVM Programming commands Operation Type NVMCMD Mnemonic Description Binary Hex 0b000000 0x00 NO_OPERATION No operation 0b010000 0x10 CHIP_ERASE Chip erase Section 0b010100 0x14 SECTION_ERASE Section erase Word 0b011101 0x1D WORD_WRITE Word write General Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 161 18. Electrical Characteristics 18.1. Absolute Maximum Ratings* Operating Temperature -55C to +125C Storage Temperature -65C to +150C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0 mA DC Current VCC and GND Pins 200.0 mA Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 18.2. DC Characteristics Table 18-1 DC Characteristics. TA = -40C to +85C Symbol Parameter Condition Min. VIL VCC = 1.8V - 2.4V -0.5 Input Low Voltage VCC = 2.4V - 5.5V VIH Typ. Max. Units 0.2VCC V 0.3VCC Input High-voltage VCC = 1.8V - 2.4V 0.7VCC(1) Except RESET pin VCC = 2.4V - 5.5V 0.6VCC(1) Input High-voltage VCC = 1.8V to 5.5V 0.9VCC(1) VCC +0.5(2) V VCC +0.5(2) V RESET pin VOL Output Low Voltage(3) 0.6 0.5 IOL = 10 mA, VCC = 5V IOL V = 5 mA, VCC = 3V Except RESET pin(5) VOH Output High-voltage(4) Except RESET pin(5) IOH = -10 mA, VCC = 5 4.3 V 2.5 V IOH = -5 mA, VCC = 3V Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 162 Symbol Parameter Condition Min. Typ. Max. Units ILIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) <0.05 1 A ILIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) <0.05 1 A RRST Reset Pull-up Resistor VCC = 5.5V, input low 30 60 k RPU I/O Pin Pull-up Resistor VCC = 5.5V, input low 20 50 k IACLK Analog Comparator Input Leakage Current VCC = 5V -50 50 nA Vin = VCC/2 ICC Power Supply Current(6) Power-down mode(7) Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 0.8 1.2 mA Active 8MHz, VCC = 5V 2.7 4 mA Idle 1MHz, VCC = 2V 0.02 0.2 mA Idle 4MHz, VCC = 3V 0.13 0.5 mA Idle 8MHz, VCC = 5V 0.6 1.5 mA WDT enabled, VCC = 3V 4.5 10 A WDT disabled, VCC = 3V 0.15 2 A Note: 1. "Min" means the lowest value where the pin is guaranteed to be read as high. 2. "Max" means the highest value where the pin is guaranteed to be read as low. 3. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum of all IOL (for all ports) should not exceed 60 mA. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum of all IOH (for all ports) should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular I/O pins. See Figure 19-25 Reset Pin as I/O, Output Voltage vs. Sink Current on page 182, and Figure 19-26 Reset Pin as I/O, Output Voltage vs. Source Current on page 182. 6. Values are with external clock using methods described in Minimizing Power Consumption. Power Reduction is enabled (PRR = 0xFF) and there is no I/O drive. 7. BOD Disabled. Related Links Minimizing Power Consumption on page 42 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 163 18.3. Speed The maximum operating frequency of the device depends on VCC . The relationship between supply voltage and maximum operating frequency is piecewise linear. Figure 18-1 Maximum Frequency vs. VCC 12 MHz 8 MHz 4 MHz 1.8V 2.7V 4.5V 5.5V 18.4. Clock Characteristics 18.4.1. Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 19-39 Calibrated Oscillator Frequency vs. VCC on page 189 and Figure 19-40 Calibrated Oscillator Frequency vs. Temperature on page 189 Table 18-2 Calibration Accuracy of Internal RC Oscillator Calibration Target Frequency Method VCC Temperature Accuracy at given Voltage & Temperature(1) Factory Calibration 8.0 MHz 3V 25C 10% User Calibration Fixed frequency within: Fixed voltage 7.3 - 8.1 MHz within: 1.8V - 5.5V Fixed temp. within: 1% -40C - 85C Note: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 164 18.4.2. External Clock Drive Figure 18-2 External Clock Drive Waveform VIH1 VIL1 Table 18-3 External Clock Drive Characteristics Symbol Parameter 18.5. VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Units Min. Max. Min. Max. Min. Max. 4 0 8 0 12 1/tCLCL Clock Frequency 0 MHz tCLCL Clock Period 250 125 83 ns tCHCX High Time 100 50 33 ns tCLCX Low Time 100 50 33 ns tCLCH Rise Time 2.0 1 0.6 s tCHCL Fall Time 2.0 1 0.6 s tCLCL Change in period from one clock cycle to the next 2 2 2 % System and Reset Characteristics Table 18-4 Reset, VLM, and Internal Voltage Characteristics Symbol Parameter Condition VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin Min(1) Typ(1) 0.2 VCC VCC = 1.8V Max(1) Units 0.9VCC V ns 2000 VCC = 3V 700 VCC = 5V 400 tTOUT Time-out after reset 32 64 128 ms Note: 1. Values are guidelines, only Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 165 18.5.1. Power-On Reset Table 18-5 Characteristics of Enhanced Power-On Reset. TA = -40 - 85C Symbol Parameter Min(1) Typ(1) Max(1) Units VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V SRON Power-On Slope Rate 0.01 V/ms Note: 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3. The Power-on Reset will not work unless the supply voltage has been below VPOA 18.5.2. VCC Level Monitor Table 18-6 Voltage Level Monitor Thresholds Parameter Min Typ (1) Max Units Trigger level VLM1L 1.1 1.4 1.6 V Trigger level VLM1H 1.4 1.6 1.8 Trigger level VLM2 2.0 2.5 2.7 Trigger level VLM3 3.2 3.7 4.5 Settling time VMLM2,VLM3 (VLM1H,VLM1L) 5 (50) s Note: 1. Typical values at room temperature 18.6. Analog Comparator Characteristics Table 18-7 Analog Comparator Characteristics, TA = -40C - 85C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 tAPD Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.5 1 tDPD Min Typ Max Units < 10 40 mV 50 nA -50 ns 2 CLK Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 166 18.7. ADC Characteristics (ATtiny5/10, only) Table 18-8 ADC Characteristics. T = -40C - 85C. VCC = 2.5V - 5.5V Symbol Parameter Condition Min Typ Max Units Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) 8 Bits VREF = VCC = 4V, ADC clock = 200 kHz 1.0 LSB VREF = VCC = 4V, ADC clock = 200 kHz 1.0 LSB 1.0 LSB Differential Non-linearity (DNL) VREF = VCC = 4V, ADC clock = 200 kHz 0.5 LSB Gain Error VREF = VCC = 4V, ADC clock = 200 kHz 1.0 LSB Offset Error VREF = VCC = 4V, ADC clock = 200 kHz 1.0 LSB Conversion Time Free Running Conversion Noise Reduction Mode Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) VIN RAIN VREF = VCC = 4V, ADC clock = 200 kHz 65 260 s Clock Frequency 50 200 kHz Input Voltage GND VREF V Input Bandwidth 7.7 kHz Analog Input Resistance 100 M ADC Conversion Output 18.8. 0 255 LSB Serial Programming Characteristics Figure 18-3 Serial Programming Timing Re ce ive Mode Tra ns mit Mode TP IDATA tIVCH tCHIX tCLOV TP ICLK tCLCH tCHCL tCLCL Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 167 Table 18-9 Serial Programming Characteristics, TA = -40C to 85C, VCC = 5V 5% (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units 1/tCLCL Clock Frequency 2 MHz tCLCL Clock Period 500 ns tCLCH Clock Low Pulse Width 200 ns tCHCH Clock High Pulse Width 200 ns tIVCH Data Input to Clock High Setup Time 50 ns tCHIX Data Input Hold Time After Clock High 100 ns tCLOV Data Output Valid After Clock Low Time 200 ns Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 168 19. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. During characterisation devices are operated at frequencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. Current consumption is a function of several factors such as operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. A sine wave generator with rail-to-rail output is used as clock source but current consumption in PowerDown mode is independent of clock selection. The difference between current consumption in PowerDown mode with Watchdog Timer enabled and Power-Down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. The current drawn from pins with a capacitive load may be estimated (for one pin) as follows: ICP VCC x CL x f SW where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin. 19.1. Supply Current of I/O Modules Tables and formulas below can be used to calculate additional current consumption for the different I/O modules in Active and Idle mode. Enabling and disabling of I/O modules is controlled by the Power Reduction Register. See Power Reduction Register for details. Table 19-1 Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, f = 1MHz VCC = 3V, f = 4MHz VCC = 5V, f = 8MHz PRTIM0 6.6 uA 40.0 uA 153.0 uA PRADC (1) 29.6 uA 88.3 uA 333.3 uA Note: 1. The ADC is available in ATtiny5/10, only The table below can be used for calculating typical current consumption for other supply voltages and frequencies than those mentioned in the table above. Table 19-2 Additional Current Consumption (percentage) in Active and Idle mode PRR bit Current consumption additional to active mode with external clock (see Figure 17-1 and Figure 17-2) Current consumption additional to idle mode with external clock (see Figure 17-7 and Figure 17-8) PRTIM0 2.3 % 10.4 % PRADC (1) 6.7 % 28.8 % Note: 1. The ADC is available in ATtiny5/10, only Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 169 Related Links Power Reduction Register on page 41 Active Supply Current Figure 19-1 Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY ICC (mA) (P RR=0xFF) 0.7 5.5 V 0.6 5.0 V 0.5 4.5 V 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 19-2 Active Supply Current vs. frequency (1 - 12 MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY (P RR=0xFF) 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V 3 ICC (mA) 19.2. 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 Fre que ncy (MHz) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 170 Figure 19-3 Active Supply Current vs. VCC (Internal Oscillator, 8 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL OS CILLATOR, 8 MHz 3.5 -40 C 25 C 85 C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-4 Active Supply Current vs. VCC (Internal Oscillator, 1 MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL OS CILLATOR, 1 MHz 1 0.9 -40 C 25 C 85 C 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 171 Figure 19-5 Active Supply Current vs. VCC (Internal Oscillator, 128 kHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL OS CILLATOR, 128 KHz 0.12 -40 C 25 C 85 C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-6 Active Supply Current vs. VCC (External Clock, 32 kHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL OS CILLATOR, 32 KHz 0.04 -40 C 85 C 25 C 0.035 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 172 Idle Supply Current Figure 19-7 Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0,1 0,09 5.5 V ICC (mA) 0,08 0,07 5.0 V 0,06 4.5 V 0,05 4.0 V 0,04 3.3 V 0,03 2.7 V 0,02 1.8 V 0,01 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 19-8 Idle Supply Current vs. Frequency (1 - 12 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 1 5.5 V 5.0 V 0,8 4.5 V 0,6 ICC (mA) 19.3. 4.0 V 0,4 3.3 V 0,2 2.7 V 1.8 V 0 0 2 4 6 8 10 12 Frequency (MHz) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 173 Figure 19-9 Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 0,7 85 C 25 C -40 C 0,6 ICC (mA) 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 19-10 Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0,7 0,6 ICC (mA) 0,5 0,4 0,3 85 C 25 C -40 C 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 174 Power-down Supply Current Figure 19-11 Power-down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 0.5 85 C 0.45 0.4 0.35 ICC (uA) 0.3 0.25 0.2 0.15 25 C 0.1 -40 C 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-12 Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 9 -40 C 8 25 C 85 C 7 6 ICC (uA) 19.4. 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 175 Pin Pull-up Figure 19-13 I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 60 50 IOP (uA) 40 30 20 10 25 C 85 C -40 C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 19-14 I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 80 70 60 50 IOP (uA) 19.5. 40 30 20 10 25 C 85 C -40 C 0 0 0,5 1 1,5 2 2, 5 3 VOP (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 176 Figure 19-15 I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 140 120 IOP (uA) 100 80 60 40 20 25 C 85 C -40 C 0 0 1 2 3 4 5 6 VOP (V) Figure 19-16 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 40 35 30 IRESET (uA) 25 20 15 10 5 25 C -40 C 85 C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 177 Figure 19-17 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 50 IRESET (uA) 40 30 20 10 25 C -40 C 85 C 0 0 0,5 1 1,5 2, 5 2 3 VRESET (V) Figure 19-18 Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 100 IRESET (uA) 80 60 40 20 25 C -40 C 85 C 0 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 VRESET (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 178 Pin Driver Strength Figure 19-19 I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT VCC = 1.8V 0.8 0.7 85 C 0.6 VOL (V) 0.5 25 C 0.4 -40 C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL (mA) Figure 19-20 I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT VCC = 3V 0.8 0.7 85 C 0.6 0.5 VOL (V) 19.6. 25 C -40 C 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 179 Figure 19-21 I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT VCC = 5V 1 85 C 0.8 -40 C 25 C VOL (V) 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 19-22 I/O Pin Output Voltage vs. Source Current (VCC = 1.8V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT VCC = 1.8V 2 1.8 1.6 VOH (V) 1.4 1.2 -40 C 1 25 C 0.8 85 C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (mA) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 180 Figure 19-23 I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT VCC = 3V 3.1 2.9 VOH (V) 2.7 2.5 -40 C 25 C 2.3 85 C 2.1 1.9 1.7 1.5 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 19-24 I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT VCC = 5V 5.2 5 VOH (V) 4.8 4.6 4.4 -40 C 25 C 4.2 85 C 4 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 181 Figure 19-25 Reset Pin as I/O, Output Voltage vs. Sink Current OUTP UT VOLTAGE vs . S INK CURRENT RES ET P IN AS I/O 1 3.0 V 1.8 V 0.9 0.8 0.7 5.0 V VOL (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IOL (mA) Figure 19-26 Reset Pin as I/O, Output Voltage vs. Source Current OUTP UT VOLTAGE vs . S OURCE CURRENT RES ET P IN AS I/O 5 4 VOH (V) 3 5.0 V 2 1 3.0 V 1.8 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOH (mA) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 182 Pin Threshold and Hysteresis Figure 19-27 I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as `1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3,5 85 C 25 C -40 C 3 Threshold (V) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 19-28 I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as `0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 C 25 C -40 C 2,5 2 Threshold (V) 19.7. 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 183 Figure 19-29 I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 1 0,9 0,8 Input Hysteresis (V) 0,7 0,6 -40 C 0,5 25 C 0,4 85 C 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 19-30 Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as `1') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIH, RESET READ AS '1' 3 -40 C 25 C 85 C 2,5 Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 184 Figure 19-31 Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as `0') RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2,5 85 C 25 C -40 C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4,5 5 5,5 VCC (V) Figure 19-32 Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O) RESET PIN AS I/O, INPUT HYSTERESIS vs. VCC VIL, PIN READ AS "0" 1 0,9 0,8 Input Hysteresis (V) 0,7 -40 C 25 C 0,6 0,5 85 C 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 185 Figure 19-33 Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as `1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 Threshold (V) 2 1,5 -40 C 25 C 1 85 C 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 19-34 Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as `0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2,5 85 C 25 C -40 C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 186 Figure 19-35 Reset Pin, Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 Input Hysteresis (V) 0,8 0,6 -40 C 0,4 25 C 85 C 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Analog Comparator Offset Figure 19-36 Analog Comparator Offset ANALOG COMP ARATOR OFFS ET VCC = 5V 0.006 -40 0.004 Offs e t 19.8. 25 0.002 85 0 0 1 2 3 4 5 VIN Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 187 Internal Oscillator Speed Figure 19-37 Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 110 109 108 107 Fre que ncy (kHz) -40 C 106 105 25 C 104 103 102 101 85 C 100 99 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-38 Watchdog Oscillator Frequency vs. Temperature WATCHDOG OS CILLATOR FREQUENCY vs . TEMP ERATURE 110 109 108 107 Fre que ncy (kHz) 19.9. 106 105 104 1.8 V 103 2.7 V 102 3.3 V 101 4.0 V 5.5 V 100 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 188 Figure 19-39 Calibrated Oscillator Frequency vs. VCC CALIBRATED 8.0MHz OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 8.4 -40 C 8.2 Fre que ncy (MHz) 25 C 85 C 8 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-40 Calibrated Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.3 8.2 Fre que ncy (MHz) 8.1 8 7.9 5.0 V 7.8 3.0 V 7.7 1.8 V 7.6 -40 -20 0 20 40 60 80 100 Te mpe ra ture Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 189 Figure 19-41 Calibrated Oscillator Frequency vs. OSCCAL Value CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE VCC = 3V 16 25 C 85 C -40 C 14 Fre que ncy (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OS CCAL (X1) 19.10. VLM Thresholds Figure 19-42 VLM1L Threshold of VCC Level Monitor VLM THRES HOLD vs . TEMP ERATURE VLM2:0 = 001 1.42 1.41 Thre s hold (V) 1.4 1.39 1.38 1.37 1.36 1.35 1.34 -40 -20 0 20 40 60 80 100 Te mpe ra ture (C) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 190 Figure 19-43 VLM1H Threshold of VCC Level Monitor VLM THRES HOLD vs . TEMP ERATURE VLM2:0 = 010 1.7 Thre s hold (V) 1.65 1.6 1.55 1.5 1.45 1.4 -40 -20 0 20 40 60 80 100 60 80 100 Te mpe ra ture (C) Figure 19-44 VLM2 Threshold of VCC Level Monitor VLM THRES HOLD vs . TEMP ERATURE VLM2:0 = 011 2.48 Thre s hold (V) 2.47 2.46 2.45 2.44 2.43 -40 -20 0 20 40 Te mpe ra ture (C) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 191 Figure 19-45 VLM3 Threshold of VCC Level Monitorr2 VLM THRES HOLD vs . TEMP ERATURE VLM2:0 = 100 3.9 Thre s hold (V) 3.8 3.7 3.6 3.5 3.4 -40 -20 0 20 40 60 80 100 Te mpe ra ture (C) 19.11. Current Consumption of Peripheral Units Figure 19-46 ADC Current vs. VCC (ATtiny5/10, only) ADC CURRENT vs . VCC 4.0 MHz FREQUENCY 700 600 ICC (uA) 500 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 192 Figure 19-47 Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . VCC 140 120 ICC (uA) 100 25 C 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 19-48 VCC Level Monitor Current vs. VCC VLM S UP P LY CURRENT vs . VCC 0.35 0.3 VLM2:0 = 001 VLM2:0 = 010 VLM2:0 = 011 0.25 ICC (mA) VLM2:0 = 100 0.2 0.15 0.1 0.05 0 VLM2:0 = 000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 193 Figure 19-49 Temperature Dependence of VLM Current vs. VCC VLM S UP P LY CURRENT vs . VCC VLM2:0 = 001 350 -40 C 300 25 C 85 C ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 19-50 Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 9 -40 C 25 C 85 C 8 7 ICC (uA) 6 5 4 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 194 19.12. Current Consumption in Reset and Reset Pulsewidth Figure 19-51 Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,5 0,4 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V ICC (mA) 0,3 0,2 1.8 V 0,1 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Note: The default clock source for the device is always the internal 8 MHz oscillator. Hence, current consumption in reset remains unaffected by external clock signals. Figure 19-52 Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85 C 25 C -40 C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 195 20. Register Summary Offset Name Bit Pos. 0x00 PINB 7:0 0x01 DDRB 7:0 DDRB3 DDRB2 DDRB1 DDRB0 0x02 PORTB 7:0 PORTB3 PORTB2 PORTB1 PORTB0 0x03 PUEB 7:0 PUEB3 PUEB2 PUEB1 PUEB0 PINB3 PINB2 PINB1 PINB0 0x04 ... Reserved 0x0B 0x0C PORTCR 7:0 BBMB 0x0D ... Reserved 0x0F 0x10 PCMSK 7:0 0x11 PCIFR 7:0 PCINT3 PCIF0 0x12 PCICR 7:0 PCIE0 0x13 EIMSK 7:0 INT0 0x14 EIFR 7:0 0x15 EICRA 7:0 0x16 Reserved PCINT1 PCINT0 INTF0 ISC0[1:0] 0x17 DIDR0 0x18 Reserved 7:0 0x19 ADCL 0x1A Reserved 0x1B ADMUX 7:0 0x1C ADCSRB 7:0 0x1D ADCSRA 7:0 ADEN 0x1E Reserved 0x1F ACSR 7:0 ACD 7:0 PCINT2 ADC7 ADC6 ADSC ADC5 ADC4 ADC3D ADC2D ADC1D ADC0D ADC3 ADC2 ADC1 ADC0 MUX1 MUX0 ADTS2 ADTS1 ADTS0 ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ACO ACI ACIE ACIC ACIS1 ACIS0 0x20 ... Reserved 0x21 0x22 ICR0L 7:0 (ICR0[7:0]) ICR0L[7:0] 0x23 ICR0H 7:0 (ICR0[15:8]) ICR0H[7:0] 0x24 OCR0BL 7:0 (OCR0B[7:0]) OCR0BL[7:0] 0x25 OCR0BH 7:0 (OCR0B[15:8]) OCR0BH[7:0] 0x26 OCR0AL 7:0 (OCR0A[7:0]) OCR0AL[7:0] 0x27 OCR0AH 7:0 (OCR0A[15:8]) OCR0AH[7:0] 0x28 TCNT0L 7:0 (TCNT0[7:0]) TCNT0L[7:0] 0x29 TCNT0H 7:0 0x2A TIFR0 7:0 ICF0 (TCNT0[15:8]) TCNT0H[7:0] OCF0B OCF0A TOV0 0x2B TIMSK0 7:0 ICIE0 OCIE0B OCIE0A TOIE0 0x2C TCCR0C 7:0 FOC0A 0x2D TCCR0B 7:0 ICNC0 FOC0B ICES0 0x2E TCCR0A 7:0 COM0A1 COM0A0 0x2F GTCCR 7:0 TSM WGM03 COM0B1 COM0B0 WGM02 CS0[2:0] WGM01 WGM00 PSR Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 196 Offset Name Bit Pos. 0x30 Reserved 0x31 WDTCSR 7:0 WDIF 0x32 NVMCSR 7:0 NVMBSY 0x33 NVMCMD 7:0 0x34 VLMCSR 7:0 0x35 PRR 7:0 0x36 CLKPSR 7:0 0x37 CLKMSR 7:0 0x38 Reserved 0x39 OSCCAL 7:0 0x3A SMCR 7:0 0x3B RSTFLR 7:0 0x3C CCP 7:0 0x3D SPL 7:0 (SP[7:0]) SPL[7:0] 0x3E SPH 7:0 (SP[15:8]) SPH[7:0] 0x3F SREG 7:0 20.1. WDIE WDP3 WDE WDP2 WDP1 WDP0 NVMCMD[5:0] VLMF VLMIE VLM[2:0] PRADC PRTIM0 CLKPS[3:0] CLKMS[1:0] CAL[7:0] SM[2:0] WDRF SE EXTRF PORF Z C CCP[7:0] I T H S V N Note 1. 2. 3. 4. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The ADC is available in ATtiny5/10, only. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 197 21. Instruction Set Summary ARITHMETIC AND LOGIC INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks ADD Rd, Rr Add two Registers without Carry Rd Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add two Registers with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract two Registers with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Constant from Reg with Carry. Rd Rd - K - C Z,C,N,V,S,H 1 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V,S 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V,S 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V,S 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V,S 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V,S 1 INC Rd Increment Rd Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V,S 1 CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1 SER Rd Set Register Rd 0xFF None 1 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks RJMP k Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC(15:0) Z, PC(21:16) 0 None 2 Relative Subroutine Call PC PC + k + 1 None 3/4 ICALL Indirect Call to (Z) PC(15:0) Z, PC(21:16) 0 None 3/4 RET Subroutine Return PC STACK None 4/5 RETI Interrupt Return PC STACK I 4/5 IJMP RCALL k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,S,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,S,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 198 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b)=1) PC PC + 2 or 3 None 1/2/3 SBIS A, b Skip if Bit in I/O Register is Set if (I/O(A,b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V,H 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V,S 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0...6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 199 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Two's Complement Overflow. V1 V 1 CLV Clear Two's Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 CLH Clear Half Carry Flag in SREG H0 H 1 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks MOV Rd, Rr Move Between Registers Rd Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 1/2 LD Rd, X+ Load Indirect and Post-Increment Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Decrement X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Increment Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Decrement Y Y - 1, Rd (Y) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Increment Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Decrement Z Z - 1, Rd (Z) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Increment (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Decrement X X - 1, (X) Rr None 2 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 200 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Increment (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Decrement Y Y - 1, (Y) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Increment (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1, (Z) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 IN Rd, A In from I/O Location Rd I/O (A) None 1 OUT A, Rr Out to I/O Location I/O (A) Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks NOP No Operation No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 201 22. Packaging Information 22.1. 6ST1 Figure 21-1 6ST1 D 5 6 E E1 A 4 A2 Pin #1 ID 1 b 0.10 C SEATING PLANE A 3 2 A A1 C S ide View e To p View A2 A 0.10 C SEATING PLANE c 0.25 O C L A1 C View A-A SEATING PLANE SEE VIEW B View B COMMON DIMENS IONS (Unit of Me a s ure = mm) S YMBOL MIN A Notes: 1. This package is compliant with JEDEC specif cation MO-178 Variation AB 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end. 3. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm 4. Die is facing down after trim/form. NOM MAX - - 1.45 A1 0 - 0.15 A2 0.90 - 1.30 D 2.80 2.90 3.00 E 2.60 2.80 3.00 E1 1.50 1.60 1.75 L 0.30 0.45 0.55 e NOTE 2 0.95 BS C b 0.30 - 0.50 c 0.09 - 0.20 0 - 8 3 6/30/08 Packag e Drawing Co ntac t: pa cka ge drawings @a tme l.com TITLE 6S T1, 6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23) GPC TAQ DRAWING NO. REV. 6S T1 A Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 202 22.2. 8MA4 Figure 21-2 8MA4 8x 8 7 6 0.05 c 5 c 0.05 c S IDE VIEW E P in 1 ID 1 2 D 3 4 A1 A TOP VIEW D2 e 8 5 COMMON DIMENS IONS (Unit of Me a s ure = mm) K E2 S YMBOL MIN NOM MAX A - - 0.60 C0.2 4 1 L b BOTTOM VIEW Note : 1. ALL DIMENS IONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS COPLANARITY SHALL NOT EXCEED 0.05 mm. 3. WARPAGE SHALL NOT EXCEED 0.05 mm. 4. REFER JEDEC MO-236/MO-252 0.00 - 0.05 0.20 - 0.30 D 1.95 2.00 2.05 D2 1.40 1.50 1.60 E 1.95 2.00 2.05 E2 0.80 0.90 1.00 e - 0.50 - L 0.20 0.30 0.40 K 0.20 - - GPC TITLE Packag e Drawing Co ntac t: pa cka ge drawings @a tme l.com A1 b 8PAD, 2x2x0.6 mm bo dy, 0.5 mm pitch, 0.9x1.5 mm expo s e d pad, S aw s ing ulate d The rmally e nhanc e d plas tic ultra thin dual flat no le ad packag e (UDFN/US ON) YAG NOTE 12/17/09 DRAWING NO. REV. 8MA4 Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 A 203 23. Errata 23.1. ATtiny4 23.1.1. Rev. E * Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.1.2. Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.1.3. Rev. A - C Not sampled. 23.2. ATtiny5 23.2.1. Rev. E * Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 204 23.2.2. Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.2.3. Rev. A - C Not sampled. 23.3. ATtiny9 23.3.1. Rev. E * Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.3.2. Rev. D * ESD HBM (ESD STM 5.1) level 1000V * Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 205 23.3.3. Rev. A - C Not sampled. 23.4. ATtiny10 23.4.1. Rev. E * Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.4.2. Rev. C - D * ESD HBM (ESD STM 5.1) level 1000V * Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level 1000V The device meets ESD HBM (ESD STM 5.1) level 1000V. Problem Fix / Workaround Always use proper ESD protection measures (Class 1C) when handling integrated circuits before and during assembly. 2. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 23.4.3. Rev. A - B Not sampled. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 206 24. Datasheet Revision History 24.1. Rev. 8127F - 02/13 1. 24.2. Rev. 8127E - 11/11 1. 24.3. 2. 3. 4. 5. 6. Added UDFN package in Feature on page 1, Pin Configurations on page 7, Ordering Information on page 9, and in Packaging Information on page 202 Updated Figures in Section Power-on Reset on page 47 Updated Section External Reset on page 48 Updated Figure 19-36 Analog Comparator Offset on page 187 and Figure 19-51 Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) on page 195 in "Typical Characteristics" Updated notes in Section Ordering Information on page 9 Added device Rev. E in Section Errata on page 204 Rev. 8127C - 10/09 1. 2. 3. 4. 5. 6. 24.5. Updated: - Device status from Preliminary to Final - Ordering Information on page 9 Rev. 8127D - 02/10 1. 24.4. Updated: - Ordering Information on page 9 Updated values and notes: - Table 18-1 DC Characteristics. TA = -40C to +85C on page 162 in Section "DC Characteristics" - Table 18-3 External Clock Drive Characteristics on page 165 in Section "Clock Characteristics" - Table 18-6 Voltage Level Monitor Thresholds on page 166 in Section "VCC Level Monitor" - Serial Programming Characteristics on page 167 in Section "Serial Programming Characteristics" Updated Figure 18-1 Maximum Frequency vs. VCC on page 164 in Section "Speed" Added Typical Characteristics Figure 19-36 Analog Comparator Offset on page 187 in Section "Analog Comparator Offset". Also, updated some other plots in Typical Characteristics. Added topside and bottomside marking notes in Section Ordering Information on page 9 Added ESD errata, see Section Errata on page 204 Added Lock bits re-programming errata, see Section Errata on page 204 Rev. 8127B - 08/09 1. Updated document template Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 207 2. 3. 4. 5. 6. 7. 8. 24.6. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9 Added section: - Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 on page 13 Updated sections: - ADC Clock - clkADC on page 32 - Starting from Idle / ADC Noise Reduction / Standby Mode on page 35 - ADC Noise Reduction Mode on page 41 - Analog to Digital Converter on page 42 - SMCR on page 44 - PRR on page 45 - Alternate Functions of Port B on page 72 - Overview on page 124 - Physical Layer of Tiny Programming Interface on page 141 - Overview on page 152 - ADC Characteristics (ATtiny5/10, only) on page 167 - Supply Current of I/O Modules on page 169 - Register Summary - Ordering Information on page 9 Added figure: - Figure 16-2 Using an External Programmer for In-System Programming via TPI on page 141 Updated figure: - Figure 6-1 Data Memory Map (Byte Addressing) on page 26 Added table: - Table 17-4 Number of Words and Pages in the Flash (ATtiny4/5) on page 154 Updated tables: - Table 9-1 Active Clock Domains and Wake-up Sources in the Different Sleep Modes. on page 40 - Table 11-1 Reset and Interrupt Vectors on page 56 - Table 17-3 Number of Words and Pages in the Flash (ATtiny9/10) on page 154 - Table 17-8 Signature codes on page 155 Rev. 8127A - 04/09 1. Initial revision Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 [DATASHEET] Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 208 Atmel Corporation (c) 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2015 Atmel Corporation. / Rev.: Atmel-8127G-ATiny4/ ATiny5/ ATiny9/ ATiny10_Datasheet_Complete-09/2015 (R) (R) (R) Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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