MOTOROLA SC {TELECOM} O1 MS b3b7253 08043 1 ff =) PE Je 7S-1/-/7 MC3419-1L eee eg TELEPHONE LINE-FEED CIRCUIT SUBSCRIBER LOOP ... designed as the heart of a circuit to provide BORSHT functions INTERFACE CIRCUIT . for telephone service in Central Office, PABX, and Subscriber Car- (SLIC) | rier equipment. This circuit provides dc power for the telephone (Battery), Overvoltage protection, Supervision features such as BIPOLAR LASER-TRIMMED hook status and dial pulsing, two-wire differential to four-wire INTEGRATED CIRCUIT * single-ended conversions and suppression of longitudinal signals at the two-wire input (Hybrid), and facilitates ringing insertion, Ring trip detection and Testing. Totally Upward Compatible with the MC3419 @ Ail Key Parameters Externally Programmable Current Sensing Outputs Monitor Status of Both Tip and Ring Leads for Auxiliary Functions such as: Ground Key, Ring Trip, Message Waiting Lamp, etc. @ On-Hook Power Below 5.0 mW @ Digital Hook Status Output @ Powerdown Input e@ Ground Fault Protection L SUFFIX Operates from Single 20 V to 56 V Power Source CERAMIC PACKAGE e Size and Weight Reduction Over Conventional Approaches : ; @ The sale of this product is licensed under Patent No. 4,004,109. All royalties related to this patent are included in the unit price. FUNCTIONAL BLOCK DIAGRAM Vcc B1 Mirror | | YF | Analog Ground rocco fsecc- S boso ' VAG 9 EP 3 g: 3 | [ata Ses = \ 1 | Al Mirror L A4 . I BP LT rT < toe {| - RSO | 4 NI ry TSO asp reer wi | ~ 1 I oct N Tip | ry tsi} --4--4--4------- 1 ad Rx1 RRX Receiye Input LH vv C WA + y > 5 Circuit CRX RX cc << t Hook oHSO & ls = 4 Status PDI @ N 3 a Bias Control Balance = RR hd Circuit aor Network = Ring | ___ Tay [ | B2 Mirror! SR Transmit i BN 7 ' 3 RTX1 0 io < { } c > utput . EN | TXO TX pee i t o WA {eA Z VTX Locos Ld. 2383 | AM aa | Bias RTX2 7 4 4 irror . > ~ 3 Ry RvTx Lf J . T VEE Vas a | . @MOTOROLA INC., 1988 DS9605R1MOTOROLA S MC3419-1L.; ss bab?es4s J-915-N-1i9 C {TELECOM}, O1 : goso4a? 3 | eS See MAXIMUM RATINGS (Voltages Referenced to Vcc.) Rating Symbol Value Unit Voltage VEE ~60 Vdc 2 Vos Vege 1.0V A Powerdown Input Voltage Range _ VPDpI +15 to 15 Vdc PIN CONNECTIONS : Sense Current ITs IRS! mAdc Steady State 100 Pulse Figure 4 200 VS Storage Temperature Range Tstg 65 to +150 C Vcc ie ig} VAG . Operating Junction Temperature Ty 150 i (ja = 100C/W Typ) EP[2| 17] RX! OPERATING CONDITIONS (Voltages Referenced to Vcc.) BP[ 3) Hie] TXO Rating Symbol Value Unit tsi [7 5] POI : Operating Ambient Ta 0 to +70 C Temperature Range ce [5] 4] HSO Loop Current IL 10 to 120 mA RSI [6 13] TSO Voltage VEE -20 to 56 Vde BN VoB 20 to Veg G7 12] RSO Analog Ground VAG Vde EN [s] i HST (IL = 0 to 60 mA) Oto 12 (lL = 0 to 120 mA) 2.5 to 12 Vee [9 0] Vas Supervisory Output Voltage Vaso. VTSO 2.0 to 20 Vde Compliance Range Hook Status Output VHSO +15 to 20 Vdc Loop Resistance RL 0 to 2500 2 TRANSMISSION CHARACTERISTICS (Ri = 600 2 unless otherwise noted.) @ Characteristic Figure Symbol Min Typ Max Unit Transmit and Receive Gain Variation 1 VIXVL 0.3 0 +0.3 dB (Insertion Loss) VL/VRX (1.0 kHz @ 0 dBm Input) . Transhybrid Rejection 1 VIx/VRx dB (Input 1.0 kHz @ 0 dBm) Fixed (1%) Resistor Balance Network 23 35 _ Trimmed Balance Network All Types _ 55 _ Level Linearity (48 to +3.0 dBm, referenced to 1 . dB 0 dBm @ 1.0 kHz) Transmission ; VIXML -0.1 0 +0.1 Reception ViVRX -0.1 0 +0.1 Frequency Response (200-3400 Hz referenced to 1 dB 1.0 kHz @ 0 dBm) Transmission VIXMVL -0.1 0 +0.1 Reception VL/VRx 0.1 0 +0.1 Tota! Distortion @ 1.0 kHz, 0 dBm 1 VLVRX _ 60 _ dB (C-Message Filtered) VIXVL -60 _ < t = oc | () MOTOROLA Semiconductor Products Inc. | 2 :MOTORO ; MC3419-1L = LA SC {TELE RS TRANSMISSION CHARACTERISTICS (continued) (RL = 600 2 unless otherwise noted.) Characteristic Figure Symbol Min Typ Max Unit idle Channel Noise (Vax = 0 V) 1 VTx. VL _ 3.0 10 dBrnc Return Loss (referenced to 600 ohms) @ 1.0 kHz, 1 20 Lo Ro 600 30 _ _ dB 0 dBm 9 | Ro +600 Longitudinal Induction (60 Hz) 2 VT _ 5.0 _ dBrnC (LON = 35 mA RMS) Longitudinal Balance (200-3000 Hz) 2 VTIXVLON: 45 _ _ dB VLVLON ELECTRICAL CHARACTERISTICS (Vee = 48 V, Vop = VEE: VAG = OV, RL = 600 2, Ta = 25C unless otherwise noted.) Characteristic Figure Symbol! Min Typ Max Unit Propagation Delay 1 Tp, Vax to Vi _ 750 _ ns Vrx to Itx _ 1.2 - BS Supply Current On-Hook 3 lvec _ 40 200 rN (Vee = Vop = 56 V, RL > 100 MQ) On-Hook Power Dissipation 3 Pp _ 1.0 _ mW (RL > 100 MQ) Power Supply Noise Rejection 3 VixNee -40 _ _ dB (1.0 kHz @ 1.0 Vams) Quiet Battery Noise Rejection 3 VTxVab _ -6.0 _ dB (1.0 kHz @ 1.0 Vams) Sense Current 4 mA/mA Tip Itso/lts1 0.15 0.17 0.19 Ring IRso'IRSI 0.15 0.17 0.19 Fault Currents 1 mA Tip to Vcc ITip _ 0 _ Ring to Vcc IRing _ 2.5 _ Tip to Ring lLoop _ 120 _ Tip and Ring to Vcc ITip and IRing _ 2.5 _ Analog Ground Current 1 IVAG _ 0.1 2.0 LA Powerdown Logic Levels IPDI 1:0 ~10 pA VIH -1.2 _ _ Vdc VIL _ _ 4.0 Vdc Hook Status Output Current 1 lHsO (RL < 2.5 kQ, VHSO = +0.4 Vdc) +1.0 +3.0 _ mA VHSO = 0.4 Vdc} 0.4 -1.5 mA (RL > 10 kO, VHso = +12 Vdc) _ 0 +50 pA VHso = ~12 Vdc) _ 0 2.0 pA {_____ (S) MOTOROLA Semiconductor Products Inc. 36367253 MOTOROLA SC (TELECOM) 2MC3419-1L O1E 80439 D T~75-11-17 MOTOROLA SC {TELECOM} OF} DEM 6367253 0080439 ? FIGURE 1 AC TEST CIRCUIT Vcc VAG MJE271 = 9 EP RxI BP TXO TSI PDI cc HSO RSI TSO 12 BN RSO --0 g EN HST u 9 10 ( VEE Vas 43k 3 232 k -48V (Tip & Ring) AC Termination Impedance, Ro = 600 2 Transmit and Receive Gain = 0 dB DC Feed Resistance, RF = 400 2 Ai = MC1741N or Equivalent FIGURE 2 LONGITUDINAL BALANCE TEST CIRCUIT 1.0 nF 1 18 Veco = VAG MJE271 = 28.5 k 2 ep rxi (7 = BP TXO 16 51.46k 1.0 yF TSI PDI a 14 = cc HSO ->_ 13 RSI TSO O 12 BN RSO ->--- 11 EN HST 0.002 uF AR MJE270 9 10 = . VeE Vos 43k2 232 k as (Tip & Ring) AC Termination Impedance, Ro = 6009 Transmit and Receive Gain = 0 dB DC Feed Resistance, Rr = 400 2 Al = MC1741N or Equivalent () MOTOROLA Semiconductor Products Inc. 4 .6367253 MOTOROLA SC TELECOM) | _ ee ae a: peg E 80440 D _\i occ amas seemed Uivec ~ vac MJE271 = 4, EP RXI BP TXO TSI PDI cc HSO | 13 RSI TSO Lo 0.005 pF T 7 12 4 BN RSO L4 8 1 EN HST | y 0.002 nf Ax MJE270 232 k qb 9 10 3 Vv V -48V 43k3 | EE QB > VOB y, YL (Tip & Ring) AC Termination Impedance, Ro = 600 2 DC Feed Resistance, Rp = 400 9 Transmit and Receive Gain = 0 dB A1 = MC1741N or Equivalent FIGURE 4 TSO AND RSO SUPERVISORY OUTPUT TEST CIRCUIT 1 18 Lv NAST o2 EP RXI 7, o 4 pp TXO Pe : itsI 4 ; 7 -8.0V aw TSI Pb! 17.4k L 1200 { 5 14 20w2 A CC HSO - Inst ) ; 6 13 'TSO -40 V w RSI TSO -12V | 17.4k } o18N RSO a | -12V 3 > ipso . L_O____; EN HST u 261k 9 10 VEE VoB -48V (S) MOTOROLA Semiconductor Products Inc.8367253, MOTOROLA SC_CTELECOM) OTE 80441 iD T-78-\I-19 Ditedheleeliee MOTOROLA SC {TELECOM} 02 DE b3b7253 coao4Na 7 FIGURE 5 QUIET BATTERY CURRENT lyog versus LOOP CURRENT IL FIGURE 6 LONGITUDINAL CAPACITY 100 Typical 80 MC3419-1| Minimum . 4 60 REA 40 lopima) = 0.0285 IL 20 lyop, QUIET BATTERY CURRENT (mA) ILon, 60 Hz PEAK LONGITUDINAL CURRENT (mA) 20 40 60 80 100 0 20 40 60 80 100 i, LOOP CURRENT (mA) (See Figure 3) IL, DC LOOP CURRENT (mA) OUTLINE DIMENSIONS | NOTES: _ LEADS, TRUE POSITIONED WITHIN 0.25 mm orTONA LEAD (0.010) DIA, AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION, _ G . CONF. (18.10.18 . DIM L TO CENTER OF LEADS WHEN FORMED A PARALLEL. rT DIM "A" & B" INCLUDES MENISCUS. \ ! K]- I al <<] J al eK] x Jo no Poo F" DIMENSION IS FOR FULL LEADS. HALE LEADS ARE OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. ls F lL. FE hes eM CASE 726-04 Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola and@) are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/ Affirmative Action Employer. (S) MOTOROLA Semiconductor Products Inc. 6_ MOTOROL LY Tee GE PIN DESCRIPTIONS Pin Name Function Vcc The positive supply voltage. This point is ground in typical applications. EP & EN Loop current sensing inputs. These are connected to the emitters of the PNP and NPN Darlington transistors. They are tied through 10 resistors to Vcc and Vee, respectively. The maximum continuous current through these inputs is 240 mA. 3,7 BP & BN Base drive outputs. These pins drive the bases of the PNP and NPN transistors and are abje to sink or source, respectively, up to 5.0 mA. 4,6 TSI & RSI Tip and Ring voltage Sensing Inputs. They are low impedance inputs (approximately 600 2 each i.e., 400 0 + 3 diodes) that translate the voltages on Tip and Ring to a current through resistors Ry and Rp. TSI is referenced to Vcc and RSI is referenced to Vqp. These pins have 6.0 V zener diodes (to their respective reference) for protection against overvoltage line surges. cc Compensation Capacitor pin. This pin is used to stabilize the longitudinal or common mode circuitry. VEE Negative supply voltage. This pin ties to the chip substrate. Its operating voltage range is 20 V to 56 V. It can withstand 60 V without damage and can sustain a voltage surge to 75 V for less than 4.0.ms without significant degradation of performance. Most of the loop current and bias currents flow through this pin. 10 VoB Quiet Battery Voltage reference. This is the voltage reference for the RSI pin. Its voltage must not go more negative than Veg. The current through this pin, while powered up, is proportional to the loop current, allowing it to be used for loop current limiting. The voltage on this pin, less 4 volts, is the effective battery feed voltage for the 2-wire lines even though most of the power comes from the Veg supply. 11 HST Hook Status Threshold programming resistor input. Ry determines the value of loop resistance at which on-hook and off-hook status is switched. 12 RSO Ring Sense current Output. This output reflects the voltage status of the Ring terminal for voltages more positive than Vgg. The current is sourced from this output, it is one-sixth IRs}, its voltage range is 0 to 20 V and its saturation voltage is approximately ~2.0 V. 13 TSO Tip Sense current Output. This output reflects the voltage status of the Tip terminal for voltages more negative than Vcc. The current is sourced from this output, it is one-sixth ITg|, its voltage ~ range is 0 V to 20 V and its saturation voltage is approximately 2.0 V. 14 HSO/HS oO Hook Status Output. This is a digital output that reflects the condition of the loop resistance. If loop resistance is less than a predetermined value established by Ry, usually Ry < 2.5 kQ, the HSO pin will be active, i.e., with positive voltage logic (a resistor tied from a +5.0 V or +12 V supply to HSO), this pin will sink current to Vcc (VHSO = 0 V); with negative voltage logic (a resistor tied from a 12 V supply to HSO), this pin will source current from Vcc (Vso = 0 V}. If loop resistance is greater than a predetermined value again established by the same resistor Ry, usually Rt > 10 kO, the HSO pin is inactive, i.e, Vuso = logic supply voltage. 15 Jv Powerdown Input pin. This pin is used to deny service to the subscriber. A logic leve! O (Vi_ < ~ 4,0 V) powers down the MC3419-1 except for HSO, TSO and RSO. The voltage range of this high impedance input pin is +15 V. 16 Transmit current Output. This output sinks current to Vgp and is proportional to ITs| + IRsj by a ratio of K1 where: K1 = 0.51. Its saturation voltage is Vop + 2.5 V typ. (+3.5 V over the temperature range). This pin is only active during the off-hook power-up condition. 17 RXI Receive Input. This input sums ac currents from TXO and the receive voltage input (VRx) and sources all the de current to TXO. It has a low input impedance (15 ) typically biased 4.5 V below the Vac pin voltage during off-hook power-up conditions. During powerdown conditions, the voltages on RXI and TXO can drift up to Vag. 18 VAG Analog Ground Voltage reference input. The input impedance of this pin is much greater than 1.0 MQ. It should be ac coupled to system ground and could be direct coupled if system ground is between 0 V and 12 V. AC coupling requires 300 kQ. to Vcc and 0.1 uF to system ground. If Vcc and system ground are common, tie Vag directly to Vcc. If de foop currents are allowed to go higher than 60 mA, Vag should be biased from 2.5 V to 12 V to avoid problems at high ambient temperatures. Le (S) MOTOROLA Semiconductor Products Inc. 7MOTOROLA SC {TELECO o Lee eae FUNCTIONAL DESCRIPTION Referring to the functiona! block diagram on page 1, line sensing resistors (RR and RT) at the TSI and RSI pins convert voltages at the Tip and Ring terminals into currents which are fed into current mirrors* A1 and A2. An output of A1 is mirrored by A3 and summed together with an output of A2 at the TXO terminal. Thus, a dif- ferential to single-ended conversion is performed from the ac line signals to the TXO output. All the dc current at the TXO output is fed back through the RX! terminals to the B1 mirror input. The inputs to B1 and B2 are made equal by mirroring the B1 input current to the B2 input through a unity gain output of the B1 mirror. Both B1 and B2 mirrors have high gain outputs (x95) which drive the subscriber lines with balanced currents that are equal in amplitude and 180 out of phase. The feedback from the TXO output, through the B-Circuit mirrors, to the subscriber line produces a dc feed resistance significantly less, but proportional to the loop sensing resistors. In most line-interface systems, the ac termination impedance is desired to be greater than the dc feed impedance. A differential ac generator on the subscriber loop would be terminated by the dc feed impedance if the total ac current at the TXO output were returned to the B1 input along with the dc current. Instead, the MC3419-1 system diverts part of the ac current from the B-Circuit mirrors. This decreases the ac feedback cur- rent, causing the ac termination impedance at the line interface to be greater than the dc feed impedance. The ac current that is diverted from the B1 mirror input is coupled to a current-to-voltage converter circuit that has a low input impedance. This circuit consists of an op amp (external to the MC3419-1) and a feedback resistor which produces the transmit output voltage (VTx) at the 4-wire interface. Transmission gain is pro- grammed by the op amp feedback resistor (RyT x). Reception gain is realized by converting the ac cou- pled receive input voltage (Vpjx) to a current through an external resistor (RRx) at the low impedance RxXl terminal. This current is summed at RXI with the de and ac feedback current from the A-Circuit mirrors and drives the B1 mirror input. The B-Circuit mirror outputs drive the 2-wire port with balanced ac current propor- tional to the receive input voltage. Reception gain is programmed by the Rprx resistor. Since receive input signals are transmitted through the MC3419-1 to the 2-wire port, and the 2-wire port signals are returned to the 4-wire transmit output, a means of cancellation must be provided to maintain 4-wire signal separation (transhybrid rejection}. Can- cellation is complicated because the gain from the re- ceive port to the transmit port depends on the impedance *A current mirror is a circuit which behaves as a current controlled current source. It has a single low-impedance input terminal with re- spect to a reference point and one or more high impedance outputs. of the subscriber loop. A passive balance network is used to achieve transhybrid rejection by cancelling, at the low impedance input to the transmit op amp, the current reflected by the loop impedance to the 4-wire transmit output. For a resistive loop impedance, a single resistor provides the cancellation. For reactive loops, the balance network should be reactive. Longitudinal (common-mode) currents that may be present on the subscriber lines are suppressed in the MC3419-1 by two methods. The first is inherent in the mirror configuration. Positive-going longitudinal cur- rents into Tip and Ring create common-mode voltages that cause a decreasing current through the Tip Sensing resistor and an increasing current through the Ring Sensing resistor. When these equal and opposite signal currents are reflected through the A-Circuit mirrors and summed together at TXO, the total current at TXO re- mains unchanged. Therefore, the ac currents due to the common-mode signal are cancelled before reaching the transmit output. The second longitudinal suppression method is more dominant, since it limits the amplitude of common- mode voltages that appear at the Tip and Ring terminals. A common-mode suppression circuit detects com- mon-mode inputs and drives the loop with balanced currents to reduce the input amplitude. Subtracting cur- rents from outputs of the A1 and A2 mirrors produces a signal current at the CC terminal in response to the common-mode voltage at Tip and Ring. A transcon- ductance amplifier (C-Circuit) generates a current pro- portional to the CC terminal voltage which is summed with the current from the RXI terminal at the inputs of current mirrors B1 and B2. The weighting and polarity of the summing networks produce common-mode B41 and B2 mirror output currents at the 2-wire port. The common-mode input impedance is inversely propor- tional to the gain of the longitudinal suppression circuit. Rc and Cc compensate the common-mode feedback loop. At 60 Hz with typical component values, the 2-wire common-mode impedance is less than 5 . The longitudinal suppression circuit output currents are generated by modulating dc current fed to the loop by the B1 and B2 current mirrors. This configuration avoids the increased power dissipation attributed to current mode loop drive because dc and longitudinal currents are not cumulatively sourced to the loop. However, driving common-mode currents through the B-circuit current mirrors in this manner limits the long- itudinal suppression capability. The suppression circuit is unable to reverse 2-wire current polarities to maintain a low-impedance termination when longitudinal cur- rents exceed the de loop current. At low dc loop cur- rents, the common-mode signal capability, known as longitudinal capacity, is limited by the loop current (Fig- ure 6). At high-loop currents, longitudinal capacity is limited by the maximum voltage swing of the CC ter- minal and is therefore independent of de loop current. (A) MOTOROLA Semiconductor Products Inc. : .MOTOROLA SC {TELECOM} O1 DE es eRe CEST: 63b?259 OO4044y Q T-15--17 FIGURE 7 BASIC SLIC CIRCUIT * <g Gnd MDA220 1| Vec Lt Le MJE271 2 . cr 1 CR EP Vag U8 * <t VAG | R CRx Le | | 17 RX = t ; cr 3 RXI I VRX i BP R RvTX g@ Tip Ret | B = + 16 it 1| . ! 4 TXO a } o> t TX2 c M0 V ast oR, | | i= | Pe : esr | 21 cc SAL | = Power > R | [ 14 = RI i 'RSI 6 RSI HSO <@ Down | 13 Hook , a TSO ~~ Status Ring Rpr | i N 7] BN Output | , | rso [2 Tip i 3 4 Sense | I EN HST Ring LH_}| _ I MJE270 Sense 9 10/V Cc r VEE OB sry > Re q ro g -48 V The hook status control circuit supplies the bias cur- rents to activate the B-Circuit op amps and other sec- tions of the MC3419-1. To activate the bias currents, the control circuit compares the current through the sense resistors, Rp and Rt, and the load resistance Ry with the current through the hook status threshold program- ming resistor, Ry, by using outputs from both A1 and A2 mirrors. The A1 mirror output sources current to the Ry resistor. (This reduces all internal currents to near zero during the on-hook state in order to eliminate un- necessary power consumption.) If this current is large enough the voltage on the HST pin will trip an internal comparator, then another circuit compares the current from the A1 output with that of an A2 output. These currents must match within + 15%. If so, HSO will be activated and the bias circuits will turn on provided the voltage on PDI is greater than 1.2 V. The HSO pin can have either a pull-up resistor or a pull-down resistor and when activated it will switch to Vcc (0 volts). Once the MC3419-1 is powered up, a circuit with a gain of 20 feeds current to the Ry resistor in order to keep the bias circuitry active. (The sense resistors are paralleled with the Darlington transistors which reduces the sense input currents.) Should the sense input cur- rents drop below one-twentieth of the required power- up current, the bias currents -will be removed, forcing a power-down condition. Current mode analog signal processing is critically dependent on voltage to current conversion at the 2-wire and 4-wire inputs. Precise, low-noise voltage sensing through resistors Rt, RR and Rrx requires quiet, low impedance terminations at terminals TSI, RSI and RXI respectively. For 2-wire signals, terminal Vgop isolates the loop-sensing resistors and current mirrors _ from noise at the high-current Veg terminal. External filtering from Vcc to Vogp (quiet battery terminal) ensures loop voltages are sensed without interference from system supply noise. Veg noise rejection at audio frequencies is typically 60 dB or greater. Receive input terminal RXI is referenced to the VAG terminal which references the 4-wire input to the analog ground of the 4-wire signal source, thus isolat- ing the input from power ground voltage transients. This isolation offers 70 dB of noise rejection at audio frequencies. SYSTEM EQUATIONS K1 The current gain from Ilys; + IRs} to TXO only during an off-hook power-up condition. K1 = 0.51 + 1%. K2 The current gain from RXI to the collectors of the off-chip Dartington transistors only during an off-hook power-up condition. K2 = 95 + 1%. For simplicity, the following equations do not use K1 or K2. Instead the actual numerical value is used, for instance (1 + [2]K1K2) = 1 + 1.02 x 95 = 97.9 is ap- proximately 98. Ri Loop resistance. This is a load resistance from Tip to Ring and can be either ac or dc depending on context. (A) MOTOROLA Semiconductor Products Inc.LOOP CURRENT REGULATIONS FIGURE 8(a) FIGURE 9(a) Gnd Gnd Vcc Vcc Tip Tip Ring =~ CoB Ring 7 CoB HST HST +o Vee Vos Vee Vos IcR Ros VEE CR VEE FIGURE 8(b) FIGURE 9(b) 130 130 120 120 = 00 < 00 Standard 400 0 Feed Resistance 80 80 Ss 70 sS 70 oOo oO 8 60 S 50 = 4 = 40 30 30 20 20 10 10 0 0 10 100 1.0k : 10k 10 100 1.0k 10k Ry, LOOP RESISTANCE {Q) Ri, LOOP RESISTANCE () SYSTEM EQUATIONS (continued) ZL Loop impedance. This is used only to connote a ignoring the effects of Ry complex impedance loading on Tip and Ring. \Vopi(RR + Rr + 1200 0) |, Loop current. The dc current flow through R_. RF = 98 (|Vqp| -4.0 V) 3) Re De feed resistance. The synthesized resistance So: . from which battery (Vcc and Vee) current is fed to R_. Rp = RT = 49RF (Vol -4.0 V) _ 600 (4) The battery feed resistance is balanced differential feed. Vapi See Figure 7. (This assumes Vgp = Vee.) The first order The minimum value for Rp and Rr is 5.0 kQ. equation is: The first order value of Rr can not be greater than the _ Art Ry + 12000 desired value of the termination impedance (usually Rp (1) 98 600 or 900 2). To achieve dc feed resistances that are Because of the diode voltage drops on TSI and RSI, the greater, a resistor can be placed between Vg and Veg actual de feed resistance is higher. The second order along with a filter capacitor Cqg which restores the equation is: desired termination impedance and filters power supply noise. A diode should also be placed between Vgp and Rr = Vopi98 RL + Rp + Rt + 12000) RL (2) Veg to prevent damage in case a catastrophic power o 98 (|(Vap] -4.0 V) supply failure occurs. (S) MOTOROLA Semiconductor Products Inc. -- . 10 RN ne ee ee. Ce welyoB This is the current that is sourced from the Vqgg pin and is proportional to the currents into and out of RSI and TSI. When the SLIC is in the off-hook power-up mode, lyqg is also proportional to IL. lyoB = 2.15 IRs} + 0.7 ITs) (5) lyoB = 0.029 IL (6) RFro Dc feed resistance. The synthesized resistance from which battery current is fed to R,, see Figure 8. (This assumes Vqp is tied to Veg through a resistor Ras-) Rog synthesizes additional dc feed resistance to the Rp value previously stated. When using Rop, the dc feed is effectively balance fed from Vcc and Vog instead of Veg. The sense resistors (Rp and Ry) should be selected to make Rr (first order) less than the termination impedance. \Vegl(98R_ + RR + Ry + 1200 + 2.85RqQpR) RFQ = 98(\VEE| 4.0 V) ~ AL (7) Ignoring R,, this simplifies to: _ Weel(RR + Rp + 1200 + 2.8529) Rra = 98(|VEE] 4.0 V) (8) Therefore: Ror = 98RFQ(VeEE| 4.0 V) [VeEKRR + RT + 1200 0) QB ~ 2.85|VEE| (9) Cop Power supply noise filter capacitor. 2.85 R + Rp + Rp + 12000 Cop = OB A I (10) 2nf Rog (RR + RT + 1200 0) Figure 9B shows Rop replaced with a current regulating device such as Motorolas 1N5283 family. !cRoB The current that is sourced to a current reg- ulating device from the Vos pin. When this current reaches the regulated value, the voltage differential be- tween Veg and Vp increases causing the effective bat- tery voltage to decrease which limits IL to a maximum value as determined below: IL = 34.5 crop (11) The graph, Figure 9B, shows loop current versus loop resistance using several values of IcRqp. The closest current regulating diode part number to that value is also shown. A typical value for Cqp in this case is 10 bF, 60 Vde. Figure 10 shows how power can be conserved on the shorter loop lengths by utilizing current limiting techniques. Overvoltage protection on the 2-wire port is achieved with the MDA220 diode bridge and the protection re- sistors RpR and Rpyt. Whenever the voltage on the 2-wire port exceeds the power supply rails (Vcc and Vee), the MDA220 diodes will forward bias and clamp to the rail voltage. The current is limited by the protec- FIGURE 10 TOTAL SLIC POWER DISSIPATION versus LOOP RESISTANCE > > > So an oa 400 Battery > 2 wo Oo 50 mA Current Limit Lad = Pp, POWER DISSIPATION (WATTS} = o o 10 100 10k 10k Ri, LOOP RESISTANCE (Q) tion resistors. These resistors should be as large in value as possible. However, if they are too large, they will interfere with the performance of the SLIC under worst case conditions. Rpt < R7/196 15 (12) Using the voltage of Vgp when I, is at its minimum off- hook value (Typ. 20 mA): Rpr < RA/196 + 25\Vee Vapi 15 (13) The tolerance of these resistors is not critical due to placement inside a closed loop. Positive temperature co-efficient resistors (PTC) may be considered here. Consult resistor manufacturers for component selec- tions that will meet the surge current and peak voltage requirements. Because the MC3419-1 is a broadband device it re- quires compensation components to keep its circuits stable. Cr & Cy Compensates the longitudinal gain of the A and the B circuit mirrors. Their values range from 2000 pF to 5000 pF. Rc & Cc Compensates the longitudinal C circuitry. Their values can be ratioed according to: Rox Cc = Rr x Cr. (14) Two off-chip power Darlington transistors are used with the MC3419-1. These transistors reduce any tem- perature gradiant problems with the precision matched devices on-chip and they alleviate thermal stress con- ditions that could occur for every on-hook and off-hook transition. The power dissipation in these devices is: Pot = IL2(R7/98 Rpt 4) + (2.0 VIL (15) Por = IL [Vee] 2 IL(R7/98 + RL + RpR + 16)} = (16) where IL = |Veg\/REQ or Iy(max) in current limited designs. (S) KIOTOROLA Semiconductor Products Inc.WN? SYSTEM EQUATIONS (continued) Ry The resistor that determines the hook status threshold values of R,. Ry is selected from a graph of the following two equations: Off-hook threshold Ry = 6(RL + RR + RT) (17) On-hook threshold Ry = 27.25 [RL + 0.01(RR + Rq)I (18) FIGURE 11 HOOK STATUS DETECTION Threshold +0.01(Rp + Off-Hook Threshold Ry = 6(RL+RR+ RL, LOOP RESISTANCE (kQ) Typical Off-Hook Limit 200 220 240 260 280 300 320 340 Ry, HOOK STATUS THRESHOLD RESISTANCE (kQ) Figure 11 shows such a graph using 17.4 kQ as the values for Rp and Rr. Note the oscillatory condition to the right of the crossing point. Selection of Ry in this region is usually not a problem since the majority of telephone lines do not fall into this resistance range. Ry always ties to Vgg and HST and will give reliable hook status information regardless of power supply voltages and PDI. Ro Termination impedance of the 2-wire port. This impedance is greater than the dc feed resistance Rr because of a current splitting network in the feedback loop, Rtx7 and RTx2. K3 A constant, formed by RTx 1 and RTx2, between 0 and 1, which determines the ratio of the first order value of Rr to Rg. _ Ra + Rr + 12000 Ro 1 + 97K3 (19) So: _ RR + Rr + 12000 - Ro K3 = ~~ 87Rg (20) and K3 ___Rrx2 + Zin (21) ~ RIX1 + RTX2 + Zin Zin The input impedance of the current to voltage converter op amp. This impedance is usually negligible, it can be used to sway the selection of a 1% component value. (S) FAOTOROLA Semiconductor Products Inc. Zi, = (Ra + Rp + 1200 0) Gtx _ Rytx in 1020 (1 K3) ~ 1000 Rrx1 Feeds most of the TXO de current to the RXI pin. To keep TXO from saturation the maximum value of Rtx7 is as follows: (RR + RT + 12000) (\Vopimin Vagimax 6.5 V) (22) RTx1 < iVogimin 5.4V (23) Where: Voaimin = (Ra + RT + 1200 0) (\VEE|min 4) (24) (RR + Rt + 12009 + 2.8 Rop) or if a current regulator diode is used: < 0.01 IL{max) (RR + Ry + 600 0) ~ [Vacimax - 3.9 V R TxA 0.07 IL(max) (28) It is beneficial to make Ry as large as possible. Typical values range from 15 k to 24 kQ. K3 R RTX2 = 5 os Zin (26) _ BR + RT + 1200 0 7RTX2Q Gtx The voltage gain from the 2-wire port to VTx which is adjustable by Ryt x. _ 1,02 (1 K3) Rytx SIX = Re + Ry + 1200 0 _ Grx(RR + Rt + 1200 9) 7 1.02 (1 K3) Grx The voltage gain from the Vpx input to the 2- wire port which is adjustable by Rrx. 95 Ry (RR + Rt + 1200 0) CTx The result isin nF. (27) {28) Rytx (29) GRX = Bex Tin # Rp + 12000) + R17 + o7Ka) FO) _ 795 RL Ro GRx = Rrx(RL + Ro) (31) _ __95 RL Ro RRX = GrxiRL + Ro) (32) Crx > Rrx + Re (33) 2n f RaxRpB Where f is the minimum passband frequency, usually 200 Hz. Transhybrid Rejection The voltage gain from Vpx to Vx. It is expressed in dB, the number should be neg- ative and the larger the value the better. Transhybrid rejection is achieved by summing a current from the Vex input (Rg) with the TXO current that flows to the current to voltage converter. Rp balances a resistive load, RL. _ Rpx(1 + 97K3) (Ro + RL) Rp = Q7R, (1K3) (34)MOTOROLA SC {TELECOM} Ol pe b3b?253 O08044a & FIGURE 12 BALANCE NETWORK FOR CAPACITIVE LINES MJE271 EP VAG BP Tip RXI [ TSI Cc L T TXO RSI MJE270 Ring BN EN NI | vv alt @ Rax Crx ] vax Hvac Rp c B RvTx RTXx1 Rp2 RTX2 Ctx | VIX FIGURE 13 BALANCE NETWORK FOR COMPLEX LOAD IMPEDANCES Rrx ERX MJE271 5 I {_] vex EP VAG ? +] vac lean, | R 1 pe Bl | . | { Tip | 2 | RXI | @2BL- RT Rvtx Ar TsI | 2 LS _! Rr TXO NWA- RSI ] VIX MJE270 Ring Ch To scale Zp to its maximum values Rx (1 + 97K3) BN Rp = Rpg = A 35 b1 = Mb2 * "194 (1 K3) (35) _ Rbi EN 2b = pAgtt) (36) When the 2-wire port has a paralle! R and C load, then (see Figure 12): _ Rrx(RR + Rt + 1200 9) Rot Q7RL (1 K3) (37) _ RrxiRp + Rt + 1200 2) Rb2 = 97RO(1 K3) (38) Rie Cp = Roo (39) When it is desirable to balance complex load imped- ances using component values that are equal to the load values (see Figure 13) then: _ Rax(1 + 97K3) Rb1 = ~i94(7 K3) Rrax(t + 97K3)|* RoRRX(1 + 97K3) (20) 194(1 K3) 97(1 K3) Rrx(1 + 97K3) Rbo = TS Ka) Kg) Rt (41) Zp = ZL (42) Rp and Rpg values are interchangeable. (AA) MOTOROLA Semiconductor Products Inc. YSNMOTOROLA SC {TELECOM} Ol DE 6367253 00804445 QO Tas Nea 3 The Tip and Ring Sense Output currents are propor- tional to the currents out of and into TSI and RSI, respectively. _ Ts! itso = - (43) I IRSO = SI (44) _ \VTip Vec| 2.0 V ; Tso = ~5 (Ry + 600 0) for VTip <Vcc (48) _ \VRing Vapi -2.0 V . IRSO = 6(RR + 600 A) for VRing > VoB (46) Digital interfacing to the MC3419-1 PDI pin and the HSO pin is shown in Figures 14a, 14b and 14c. If the PDI pin is not used it should be terminated to Vcc and if HSO is not used, it can be left open. SYSTEM EQUATIONS (continued) Figure 15 is an application circuit showing solid state ringing insertion using an MOC3030 zero-crossing de- tector optocoupled triac to replace the conventional electromechanical relay. This device inserts the ringing signal on a zero voltage crossing which eliminates noise in adjacent cable pairs and removes the signal on a zero current crossing which eliminates inductive voltage spikes that commonly destroy relay contacts. The ring- ing generator provides a continuous 40 V to 120 V RMS signal from 15 to 66 Hz superimposed upon 48 Vdc. Ringing cadencing is inserted with the Ring Enable Input. The 2N6558 and MPSA42 replace the MJE270 for systems that use ringing generator voltages greater than 70 Vams. The MDA220 diode bridge is replaced with a series 1N4007 on the Tip lead and a shunting 1N4004 to Veg and to allow ringing voltage FIGURE 14 INTERFACE-TO-DIGITAL LOGIC Vcc MC14xxx _ MC14xxx PDI HSO > MC3419 MC74LSxxx V 62 Vss or -12V T k MC74HCxxx -48V -12V (a) Interface-to-Negative Supply CMOS Logic: MC14xxx : +5.0V 10 kSyp5 MC74LSxxx MC74HCxxx Vcc Vss PDI HSO ; MC3419-1 750 k VEE (b) Interface-to-LSTTL +12V 62k Vpp MC14xxx Vss PDI 1.0 MQ VEE HSO MC3419-1 48V (c) Interface-to-Positive Supply CMOS Logic {________ (S) MOTOROLA Semiconductor Products Inc. -- 14MOTOROLA SC {TELECOM} Oh \7 - 15-1 DE) e367253 oosouso 4 ff 7- Asayeg aanebay [ } sjuauodwog jeuondg sayesipu; minding WwsuelL T L-3} a05 eXLy bLXLy ? \ EOESNL O a WN Hy te vt GL 9L ynduy aaladay {+ Xdy db punoiy Bojeuy } gL DA ISH OSH OSL OSH Idd OXL IXY DVA "a3 daa Na Q NS IL Jy ISH S ZPVSdN Hy Udy -W--- | Buly WN 29 ISL dq Lcarn IIA punoin [ } yndino SNCS, JOO} loyesouey Burbuly } ajqeug Bury [J MW ddy 2Dy S90VSdIN Jamog 91607 [ ] 9SVSdW Of0eD0W LINDUID 3NIT Xad SL IYNDI 41_ diy 15 Sa ) MOTOROLA Semiconductor Products Inc.SYSTEM EQUATIONS (continued) on the Ring lead to exceed the power supply voltages, a 1N4007 and an MK1V-135 (Sidac) are used for pro- tection. The forward voltage drop across the 1N4007, during normal operation, wil! not affect the parametric characteristics of the MC3419-1 since it is inside a feedback circuit. If the MJE270 is used, the MK1V-135 should be replaced with a lower voltage Sidac or MO+sorb transient suppressor. An optocoupled transistor circuit is used for ring trip detection on long lines. It samples only the ac and dc ringing signal current and uses a simple one pole filter to eliminate the low level ac signal. Under worst case conditions this circuit will ring trip in 1% to 4 cycles. In systems serving only short loops (<700 Q), if Rg1 and Rg? are 620 2 or greater, the optotransistor circuit is not needed, the Hook Status Output will perform ring trip on a Zero Crossing. The Ring Enable input and the Hook Status Output interface with standard CMOS and TTL logic. The op amp in this circuit is an integral part of the following codecs, filters or combos: MC3417/8 MC145414 MC14404/6/7 MC14413/4 MC14401/2/3/5 LONG LINES OFF-PREMISE LINES Specifications Re 2000 Roc 6000 {L(max) 60 mA Rx Gain 0OdB 200-3400 Hz Ry (max) 190092 TxGain 0dB 200-3400 Hz. Parts List MPSA56 RR _ 9.09k 1% Matched 2N3905 RT _ 9.09k 1% if desired 2N6558 RpeT 472 5% MPSA42 RpR _ 752 5% MJE271 Roi 6202 5% 1N4007 Rag 1002 5% MK1V135 Rei _ 910 5% 1N4007 Rep - 3.0k 5% 4N4007 - Reto 20k 5% 1N5303 Rc _ 24k 5% 1N4004 Ry _ 127 k 1-3% MC3419-1 Ruso 10k 5% SHORT LINES ON-PREMISE LINES Specifications Re _ 500 2 RL(max) _ 700 2 Ring Trip _ <50 ms Ringer Equivalent _ 2.5 Ro _ 600 2 Parts List MJE271 RR _ 19.6k 1% MJE270 RT _ 19.6k 1% MPSA56 Rgi _ 6202 5% 2N3905 Rg2 6200 5% 1N4007 Re1 _ 912 5% 1N4007 Re2 _ 3.0k 5% a (S) MOTOROLA Semiconductor Products Inc. BOX 20912 e PHOENIX, ARIZONA 85036 e A SUBSIDIARY OF MOTOROLA INC. 1655-2 PRINTED IN USA 4-88 DMPERIAL LITHO (55985 15,000 YCARAA Off-Hook <25000 VLogic +5.0V On-Hook >10k2 VEE 42to 56 Volts Protection 1000 V VRinging (40 V to 120 VRMs) + VEE Ringer Equivalent- 5 MOC3030 Rt1 121k 1% 4N25 Rts2. B.76k 1% RRxX 28.7k 1% Rapa ~= 280k 1% Rvtx 286k 1% CT 0.004 pF CR _ 0.004 pF Cc 0.001 pF CRx 1.0 pF/20 V Cx 2.0 wF/40 V Cet 20 pF/5.0 V Cop 10 uF/60 V Rx Gain _ -5.0 dB Tx Gain _ 0 dB VLogic _ +5.0 Volts VEE _ -20 to 56 Volts VRinging _ (40 V to 70 Vams}+ VEE MOC3030 RHso 10k 5% RTX1. 19.6k 1% CT 0,004 pF RTx2 42.2k 1% CR 0.004 pF RRxX 69.8k 1% Cc 0.004 pF Rp _ 301k 1% CRx 0.1 wF RvTxX 127k 1% Crx 05 uF Rc _ 56k 5%