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tm
74VHC112 Dual J-K Flip-Flops with Preset and Clear
May 2007
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2
74VHC112
Dual J-K Flip-Flops with Preset and Clear
Features
■
High speed: f
MAX
= 200MHz (Typ.) at V
CC
= 5.0V
■
Low power dissipation: I
CC
= 2µA (Max.) at T
A
= 25°C
■
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(Min.)
■
Power down protection is provided on all inputs
■
Pin and function compatible with 74HC112
General Description
The VHC112 is an advanced high speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The VHC112 contains two independent, high-speed JK
flip-flops with Direct Set and Clear inputs. Synchronous
state changes are initiated by the falling edge of the
clock. Triggering occurs at a voltage level of the clock
and is not directly related to transition time. The J and K
inputs can change when the clock is in either state with-
out affecting the flip-flop, provided that they are in the
desired state during the recommended setup and hold
times relative to the falling edge of the clock. The LOW
signal on PR or CLR prevents clocking and forces Q and
Q HIGH, respectively. Simultaneous LOW signals on PR
and CLR force both Q and Q HIGH.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Order Number
Package
Number Package Description
74VHC112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 2
Connection Diagram
Pin Description
Truth Table
H (h)
=
HIGH Voltage Level
L (l)
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Clock Transition
Q
0
(Q
0
)
=
Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced
input or output one setup time prior to the HIGH-to-LOW
clock transition.
Logic Diagram
(One Half Shown)
Pin Names Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CLK
1
, CLK
2
Clock Pulse Inputs (Active Falling
Edge)
CLR
1
, CLR
2
Direct Clear Inputs (Active LOW)
PR
1
, PR
2
Direct Preset Inputs (Active LOW)
Q
1
, Q
2
, Q
1
, Q
2
Outputs
Inputs Outputs
PR CLR CP JK Q Q
LHXXXHL
HLXXXLH
LLXXXHH
HH hhQ
0
Q
0
HH lhLH
HH hlHL
HH llQ
0
Q
0
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
V
IN
DC Input Voltage –0.5V to +7.0V
V
OUT
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
IK
Input Diode Current –20mA
I
OK
Output Diode Current ±20mA
I
OUT
DC Output Current ±25mA
I
CC
DC V
CC
/ GND Current ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
L
Lead Temperature (Soldering, 10 seconds) 260°C
Symbol Parameter Rating
V
CC
Supply Voltage 2.0V to +5.5V
V
IN
Input Voltage 0V to +5.5V
V
OUT
Output Voltage 0V to V
CC
T
OPR
Operating Temperature –40°C to +85°C
t
r
, t
f
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 4
DC Electrical Characteristics
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
T
A
=
–40°C to
+85°C
UnitsMin. Typ. Max. Min. Max.
V
IH
HIGH Level Input
Voltage
2.0 1.50 1.50 V
3.0–5.5 0.7 x V
CC
0.7 x V
CC
V
IL
LOW Level Input
Voltage
2.0 0.50 0.50 V
3.0–5.5 0.3 x V
CC
0.3 x V
CC
V
OH
HIGH Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OH
=
–50µA 1.9 2.0 1.9 V
3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 I
OH
=
–4mA 2.58 2.48
4.5 I
OH
=
–8mA 3.94 3.80
V
OL
LOW Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OL
=
50µA 0.0 0.1 0.1 V
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 I
OL
=
4mA 0.36 0.44
4.5 I
OL
=
8mA 0.36 0.44
I
IN
Input Leakage
Current
0–5.5 V
IN
=
5.5V or GND ±0.1 ±1.0 µA
I
CC
Quiescent
Supply Current
5.5 V
IN
=
V
CC
or GND 2.0 20.0 µA
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 5
AC Electrical Characteristics
Note:
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
I
CC
(opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per F/F), and the total C
PD
when n pcs of the Flip-Flop operate can be calculated
by the following equation: C
PD
(total)
=
30 + 14 • n
AC Operating Requirements
Note:
3. V
CC is 3.3 ± 0.3V or 5.0 ± 0.5V.
Symbol Parameter VCC (V) Conditions
TA = 25°C
TA = –40°C
to +85°C
UnitsMin. Typ. Max. Min. Max.
fMAX Maximum Clock
Frequency
3.3 ± 0.3 CL = 15pF 110 150 100 MHz
CL = 50pF 90 120 80
5.0 ± 0.5 CL = 15pF 150 200 135 MHz
CL = 50pF 120 185 110
tPLH, tPHL Propagation Delay Time
(CP to Qn or Qn)
3.3 ± 0.3 CL = 15pF 8.5 11.0 1.0 13.4 ns
CL = 50pF 10.0 15.0 1.0 16.5
5.0 ± 0.5 CL = 15pF 5.1 7.3 1.0 8.8 ns
CL = 50pF 6.3 10.5 1.0 12.0
tPLH, tPHL Propagation Delay Time
(PR or CLR to Qn or Qn)
3.3 ± 0.3 CL = 15pF 6.7 10.2 1.0 11.7 ns
CL = 50pF 9.7 13.5 1.0 15.0
5.0 ± 0.5 CL = 15pF 4.6 6.7 1.0 8.0 ns
CL = 50pF 6.4 9.5 1.0 11.0
CIN Input Capacitance VCC = Open 4 10 10 pF
CPD Power Dissipation
Capacitance
(2) 18 pF
Symbol Parameter VCC (V)(3)
TA = 25°C TA = –40°C to +85°C
Units Typ. Guaranteed Minimum
tWMinimum Pulse Width
(CP or CLR or PR)
3.3 5.0 5.0 ns
5.0 5.0 5.0
tSMinimum Setup Time
(Jn or Kn to CPn)
3.3 5.0 5.0 ns
5.0 4.0 4.0
tHMinimum Hold Time
(Jn or Kn to CPn)
3.3 1.0 1.0 ns
5.0 1.0 1.0
tREC Minimum Recovery Time
(CLR or PR to CP)
3.3 6.0 6.0 ns
5.0 5.0 5.0
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 6
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
0.65
4.4±0.1
MTC16rev4
0.11
4.55
5.00
5.00±0.10
12°
7.354.45
1.45
5.90
74VHC112 Dual J-K Flip-Flops with Preset and Clear
©1995 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC112 Rev. 1.2 9
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HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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As used herein:
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which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
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development. Specifications may change in any manner without notice.
Preliminary This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
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reference information only.
Rev. I26
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regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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