1 Publication Order Number :
LE25S40AMC/D
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© Semiconductor Components Industries, LLC, 2014
November 2014 - Rev. 2
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of this data sheet.
LE25S40AMC
Overview
The LE25S40A is a SPI bus flash memory device with a 4M bit (512K
8-bit) configuration that adds a high performance Dual output and Dual I/O
function. It uses a single 1.8V power supply. While making the most of the
features inhere nt to a serial flash m emory device, the LE25S40A is housed in
an 8-pin ultra- miniat ure package. All these features make this device ideally
suited to storing program in applications such as portable information
devices, which are required to have increasingly more compact dimensions.
The LE25S40A also has a small sector erase capability which makes the
device ideal for storing parameters o r data that have fewer re write cycles and
convention a l EEPROMs cannot handle due to insufficient capacity.
Function
Read/write operations enabled by single 1.8V power supply : 1.65 to 1.95V supply voltage rang e
Operating frequency : 40MHz
Temperature range : –40 to +90C
Serial interface : SPI mode 0, mode 3 supported
Sector size : 4K bytes/small sector, 64K bytes/sector
Small sector erase, sector erase, chip erase functions
Page program function (256 bytes / page)
Block protect function
Data retention period : 20 years
Status functions : Ready/busy information, protect information
Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ.), 150ms (max.)
Sector erase time : 80ms (typ.), 250ms (m ax.)
Chip erase time : 400ms (typ.), 4.0s (max.)
Page program time : 0.8ms/256 bytes (typ.), 1. 0m s/ 25 6 by t e s (max.)
Package : SOP8J / SOIC-8, CASE 751CU
CMOS LSI
4M-bit (512K x 8)
Serial Flash Memory
* This product is licensed from Silicon S torage Technology, Inc. (USA).
SOP8J(200mil)
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Specifications
Absolute Maximum Ratings
Parameter Symbol Conditions Ratings unit
Maximum supply voltage With respect to VSS 0.5 to +2.4 V
DC voltage (all pins) With respect to VSS 0.5 to VDD+0.5 V
Storage temperature Tstg 55 to +150 C
Operating Conditions
Parameter Symbol Conditions Ratings unit
Operating supply voltage 1.65 to 1.95 V
Operating ambient temperature 40 to +90 C
Allowable DC Operating Conditions
Parameter Symbol Conditions Ratings unit
min typ max
Read mode operating current ICCR
SCK = 0.1VDD/0.9VDD,
HOLD = WP = 0.9VDD,
SO = open
Single 30MHz 6 mA
40MHz 8 mA
Dual 40MHz 10 mA
Write mode operating current
(erase+page program) ICCW t
SSE = tSE = tCHE = typ., tPP = max 15 mA
CMOS standby current ISB CS = VDD, HOLD = WP = VDD,
SI = VSS/VDD, SO = open 50 A
Power-down standby current IDSB CS = VDD, HOLD = WP = VDD,
SI = VSS/VDD, SO = open 10 A
Input leakage current ILI 2A
Output leakage current ILO 2A
Input low voltage VIL 0.3 0.3VDD V
Input high voltage VIH 0.7VDD V
DD+0.3 V
Output low voltage VOL I
OL = 100A, VDD = VDD min 0.2 V
IOL = 1.6mA, VDD = VDD min 0.4
Output high voltage VOH I
OH = 100A, VDD = VDD min VCC0.2 V
Data hold, Rewriting frequency
Parameter Conditions min max unit
Rewriting frequency Program/Erase 100,000 times/
Sector
Status resister write 1,000
Data hold 20 year
Pin Capacitance at Ta = 25C, f = 1MHz
Parameter Symbol Conditions Ratings unit
max
Output pin capacitance CSO V
SO = 0V 12 pF
Input pin capacitance CIN V
IN = 0V 6 pF
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather val ues for
some of the sampled devices.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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AC Characteristics
Parameter Symbol
Ratings unit
min typ max
Clock frequency Read instruction (03h) fCLK 30 MHz
All instruction except for read (03h) 40 MHz
Input signal rising/falling time tRF 0.1 V/ns
SCK logic high level pulse width 30MHz tCLHI 14 ns
40MHz 11.5 ns
SCK logic low level pulse width 30MHz tCLLO 14 ns
40MHz 11.5 ns
CS setup time tCSS 10 ns
CS hold time tCSH 10 ns
SCK setup time tCLS 10 ns
SCK hold time tCLH 10 ns
Data setup time tDS 5 ns
Data hold time tDH 5 ns
CS wait pulse width tCPH 25 ns
Output high impedance time from CS t
CHZ 15 ns
Output data time from SCK tV 8 11 ns
Output data hold time tHO 1 ns
Output low impedance time from SCK tCLZ 0 ns
WP setup time tWPS 20 ns
WP hold time tWPH 20 ns
HOLD setup time tHS 5 ns
HOLD hold time tHH 5 ns
Output low impedance time from HOLD t
HLZ 12 ns
Output high impedance time from HOLD t
HHZ 9 ns
Power-down time tDP 5 s
Power-down recovery time tPRB 500 s
Write status register time tSRW 8 10 ms
Page programming cycle time 256Byte tPP
0.8 1.0 ms
nByte 0.15+
n*0.65/256 0.20+
n*0.8/256 ms
Small sector erase cycle time tSSE 0.04 0.15 s
Sector erase cycle time tSE 0.08 0.25 s
Chip erase cycle time tCHE 0.4 4.0 s
AC Test Conditions
Input pulse level ··········· 0.2VDD to 0.8VDD
Input rising/falling time ·· 5n s
Input timing level ········· 0.3VDD, 0.7VDD
Output timing level ······· 1/2VDD
Output load ················ 15pF
Note : As the test conditions for "typ", the measurements are conducted using 1.8V for VDD at room temperature.
0.8VDD
0.2VDD
0.7VDD
0.3VDD
1/2VDD
input level input/output timing level
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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Package Dimensions
unit : mm
SOIC-8 / SOP8J (200 mil)
CASE 751CU
ISSUE O
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Figure 1. Pin Assignments
Table 1. Pin Description
Symbol Pin Name Description
SCK Serial clock This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
SI/SIO0 Serial data input
/ Serial data input output The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
SO/SIO1 Serial data input
/ Serial data input output The data stored inside the device is output from this pin synchronized to the falling edge of the serial clo c k. It
changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
CS Chip select The device becomes a ctive when the lo gic leve l of this pin i s low; it is dese lected and place d in standby status
when the logic level of the pin is high.
WP Write protect The status register write protect (SRWP) takes effect when the logic level of this pin is low.
HOLD Hold Serial communication is suspended when the logic level of this pin is low.
VDD Power supply This pin supplies the 1.65 to 1.95V supply voltage.
VSS Ground This pin supplies the 0V supply voltage.
Figure 2. Block Diagram
4M Bit
Flash EEPROM
Cell Array
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CS SCK SI/SIO0 HOLD
WP
SO/SIO1
X-
DECODER
ADDRESS
BUFFERS
&
LATCHES
SERIAL INTERFACE
CONTROL
LOGIC
Top view
CS
SO/SIO1
WP
VSS
VDD
HOLD
SCK
SI/SIO0
1
2
3
4
8
7
6
5
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Device Operation
The read, erase, program and other required functions of the device are executed through the command registers. The
serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the device is
selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and
taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute
operation according to the command that is input.
The LE25S40A supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the log ic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3. I/O waveforms
Table 2. Command Settings
Command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle Nth bus cycle
Read 03h A23-A16 A15-A8 A7-A0 RD *1 RD *1 RD *1
High Speed Read 0Bh A23-A16 A15-A8 A7-A0 X RD *1 RD *1
Dual Output Read 3Bh A23-A16 A15-A8 A7-A0 Z RD *1 RD *1
Dual I/O Read BBh A23-A8 A7-A0, X, Z RD *1 RD *1 RD *1 RD *1
Small sector erase 20h / D7h A23-A16 A15-A8 A7-A0
Sector erase D8h A23-A16 A15-A8 A7-A0
Chip erase 60h / C7h
Page program 02h A23-A16 A15-A8 A7-A0 PD *2 PD *2 PD *2
Write enable 06h
Write disable 04h
Power down B9h
Status register read 05h
Status register write 01h DATA
JEDEC ID read 9Fh
ID read ABh X X X
power down B9h
Exit power down mode ABh
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input).
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A19 for all commands are "Don't care".
*1: "RD" stands for read data. *2: "PD" stands for page program data.
CS
SCK
SO
SI 1st bus
8CLK
Mode0
Mode3
2nd bus
DATA
MSB
(Bit7) DATA
LSB
(Bit0)
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Table 3. Memory Organization
4M Bit
sector (64KB) small sector (4KB) address space (A23 to A0)
7
127 07F000h 07FFFFh
to
112 070000h 070FFFh
6
111 06F000h 06FFFFh
To
96 060000h 060FFFh
5
95 05F000h 05FFFFh
to
80 050000h 050FFFh
4
79 04F000h 04FFFFh
to
64 040000h 040FFFh
3
63 03F000h 03FFFFh
to
48 030000h 030FFFh
2
47 02F000h 02FFFFh
to
32 020000h 020FFFh
1
31 01F000h 01FFFFh
to
16 010000h 010FFFh
0
15 00F000h 00FFFFh
to
2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
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Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
Ther e are two read commands, the standard SPI read command and High-speed read command .
1-1. Read command
Consisting of the firs t through fourth bus cycles, the 4 bus cycle read co mmand inputs the 24-bit add resses following
(03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read"
shows the timing waveforms.
Figure 4-a. Read
1-2. High-speed read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.
"Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b. High-speed Read
N+2 N+1 N
CS
High Impedance DATA DATA DATA
SCK
SO
SI 03h
A
dd.
A
dd.
A
dd.
15
MSB MSBMSB
0 1 2 3 4 5 6 7 8 2316 24 31 39 47
8CLK
Mode0
Mode3 32 40
N+2 N+1 N
CS
High Impedance DATA DATA DATA
SCK
SO
SI 0Bh
A
dd.
A
dd.
A
dd. X
15
MSB MSB MSB
0 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 47 48 55
Mode3
Mode0
8CLK
MSB
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2. Dual read
There are two Dual read com mands, the Dual Output read command and the Dual I/O read command. They achieve the
twice speed-up from a High-speed read command.
2-1. Dual Output read command
The Dual Output read command changes SI/SIO0 into the output pin function in addition to SO/SIO1, makes the data
output x 2 bit and has achie ved a high-speed output. Consist ing of the first thr ough fifth bu s cycles, the Dual Outp ut read
command inputs the 24-bit addresses and 8 dummy bits following (3Bh). DATA1 (Bit7, BIt5, Bit3 and Bit1) is output
from SI/SIO0 and DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of fifth bus
cycle bit 0 as a reference. "Figure 5-a Dual Output read" shows the timing waveforms.
Figure 5-a. Dual Output read
2-2. Dual I/O read command
The Dual I/O read command changes SI/SIO0 and SO/SIO1 int o the input out put pin fu nction, makes t he data input a nd
output x2 bit and has achieved a high-speed output. Consisting of the first through third bus cycles, the Dual I/O read
command inputs the 24-bit addresses and 4 dummy clocks following (BBh). The format of the address input and the
dummy bit input is t he x2 bit input . A dd1 (A 23, A 21, -, A3 and A1) i s in put from S0/SIO1 a nd A dd0 ( A22, A20 , -, A 2
and A0) is input from SI/SIO0. 2CLK of the latter half of the dummy clock is in the state of high impedance, the
controller can switch I/O for this period. DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and DATA0 (Bit6,
Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of third bus cycle bit 0 as a reference. "Figure 5-b
Dual I/O Read" shows the timing waveforms.
Figure 5-b. Dual I/O Read
When SCK is input continuously after the read co mmand has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest
address (7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting
the logic level of CS to high, t he device is deselected, and the read cy cle ends. While the device is deselected, the output
pin SO is in a high-impedance state.
CS
High Impedance DATA1DATA1
DATA1
SCK
SO/SIO1
SI/SIO0 3Bh
A
dd.
A
dd.
A
dd.
15
MSB MSB
0 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 43 44 47
Mode3
Mode0
8CLK
MSB
MSB
N+2
N+1
N
DATA0DATA0 DATA0
4CLK 4CLK
DATA0
b6,b4,b2,b0
DATA1
b7,b5,b3,b1
dummy
bit
CS
High Impedance DATA1DATA1
DATA1
SCK
SO/SIO1
SI/SIO0 BBh X
A
dd1:A22,A20-A2,A0
MSB MSB
0 1 2 3 4 5 6 7 8 19 22 23 24 27 28 31
Mode3
Mode0
8CLK
MSB
MSB
N+2
N+1
N
DATA0DATA0 DATA0
4CLK
DATA0
b6,b4,b2,b0
DATA1
b7,b5,b3,b1
dummy
bit
20 21
A
dd2:A23,A21-A3,A1 X
2CLK
2CLK
12CLK
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3. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (Status
Register read) and the protect information can be rewritten (Status Register write). There are 8 bits in total, and "Table
4 Status registers" gives the significance of each bit.
Table 4. Status Registers
Bit Name Logic Function Power-on Time Information
Bit0 RDY 0 Ready 0
1 Erase/Program
Bit1 WEN
0 Write disabled 0
1 Write enabled
Bit2 BP0
0
Block protect information
Protecting area switch
Nonvolatile information
1
Bit3 BP1
0 Nonvolatile information
1
Bit4 BP2
0 Nonvolatile information
1
Bit5 TB
0 Block protect
Upper side/Lower side switch Nonvolatile information
1
Bit6 Reserved bits 0
Bit7 SRWP
0 Status register write enabled Nonvolatile information
1 Status register write disabled
3-1. Status register read
The contents of the status r egi sters ca n be rea d usin g t he st atus re gister read comm and. Thi s comm and ca n be exec uted
even during the following operations.
Small sector erase, sector erase, chip erase
Page program
Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first
to be output, a nd eac h ti m e one clock i s in put, al l t he othe r bi ts up t o RDY (bit 0) are o utput i n seque nce , syn chro nized
to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning
to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The
data can be read by the status register read command at any time (even during a program or erase cycle).
Figure 6. Status Register Read
CS
SCK
SI
SO
MSB MSB MSB
05h
DATADATA
High Impedance
83 2 1 0 7654 15 23
Mode 3
Mode 0
8CLK
16
DATA
MSB
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3-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB
and SRWP is stored in the non -volatile memory, and when it is written in these bits, the contents are retained even at
power-down. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20
shows a status regi ster wri te fl owchart . Consi sting of the fi rst and second bus cycles, the status re gister write comm and
initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and
program are performed automatically inside the device by status register write so that erasing or other processing is
unnecessary be fore executin g the comm and. By the operatio n of this com mand, the inf ormation i n bits BP0, B P1, BP2,
TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status register cannot be written, no
problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write
ends can be det ected by RDY of status register read. To initiate status register write, the logic level of the WP pin must
be set high and status register WEN must be set to "1".
Figure 7. Status Register Write
3-3. Contents of each status regis ter
RDY (Bit0)
The RDY register is for detecting th e write (program, erase and status register write) end. When it is "1", the device is in
a busy state, and when it is "0", it means that write is completed.
WEN (Bit1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable an d write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by i nputting the write disable command (04h), it can be set to "0." In the following states,
WEN is automatically set to "0" in orde r to protect against unintentional writing.
At power-on
Upon completion of small sector erase, sector erase or chip erase
Upon completion of page program
Upon completion of status register write
* If a wri te operati on has not been perform ed inside the LE2 5S40A becaus e, for instance , the comm and input f or any of
the write operations (small sector e rase, sector erase, chi p erase, page program , or status regist er write) has failed or a
write operation has been performed for a protected address, WEN will retain the status established prior to the issue of
the command concerned. Furthermore, its state will not be changed by a read operation.
tSRW
Self-timed
Write Cycle
SCK
SI
High Impedance
SO
CS
DATA01h
150 1 2 3 4 5 6 7 8
Mode3
Mode0
8CLK
WP
tWPH
tWPS
MSB
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BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)
Block protect BP0, BP1, BP2 and TB are status register bits that ca n be rewritten, and th e memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the highe r-order address
area or lower-order address area.
Table 5. Protect Level Setting Conditions
Protect Level Status Register Bits Protected Area
TB BP2 BP1 BP0
0 (Whole area unprotected) X 0 0 0 None
T1 (Upper side 1/8 protected) 0 0 0 1 07FFFFh to 070000h
T2 (Upper side 1/4 protected) 0 0 1 0 07FFFFh to 060000h
T3 (Upper side 1/2 protected) 0 0 1 1 07FFFFh to 040000h
B1 (Lower side 1/8 protected) 1 0 0 1 00FFFFh to 000000h
B2 (Lower side 1/4 protected) 1 0 1 0 01FFFFh to 000000h
B3 (Lower side 1/2 protected) 1 0 1 1 03FFFFh to 000000h
4 (Whole area protected) X 1 X X 07FFFFh to 000000h
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers
are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting
conditions".
Table 6. SRWP Setting Conditions
WP Pin SRWP Status Register Protect State
0 0 Unprotected
1 Protected
1 0 Unprotected
1 Unprotected
Bit 6 are reserved bits, and have no significance.
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4. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is perfo rmed. The write enable
command consists on ly of the first bus cycle, and it is initiated by inputting (06h).
Small sector erase, sector erase, chip erase
Page program
Status register write
5. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable"
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h). Th e write disable state (WEN "0") is exited by setting WEN to "1 " using the write enable command
(06h).
Figure 8. Write Enable Figure 9. Write Disable
6. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows
the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputtin g
(B9h). However, a power-dow n command issu ed during an internal wr ite operation will be ignor ed. The power- down
state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the
silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of
the power-down exit command.
Figure 10. Power-down Figure 11. Exiting from Power-down
SCK
SI
High Impedance
SO
CS
06h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
04h
012 3 4 5 6 7
Mode3
Mode0
8CLK
MSB MSB
SCK
SI
High Impedance
SO
CS
B9h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
SCK
SI
High Impedance
SO
CS
A
Bh
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
tPRB
tDP
Power down
mode Power down
mode
MSB MSB
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7. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting
the 24-bit addresses fo llowing (20h) or (D7h ). Addresses A18 to A12 are v alid, and Addresses A23 to A19 are "don't
care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends
automatically by the control exercised by the internal timer. Erase end can also be det ect ed using status regi st er RDY .
Figure 12. Small Sector Erase
8. Sector Erase
Sector erase is an operation that sets t he memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 13
Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command
consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h).
Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the
internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal
timer. Erase end can also be detected using status register RDY.
Figure 13. Sector Erase
Self-timed
Erase Cycle
SCK
SI
High Impedance
SO
CS
tSSE
Add.20h / D7h Add. Add.
15
0 1 2 3 4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
MSB
SCK
SI
High Impedance
SO
CS
tSE
Self-timed
Erase Cycle
Add.D8h Add. Add.
15
0 1 2 3 4 5 6 7 8 2316 24 31
Mode3
Mode0
8CLK
MSB
LE25S40AMC
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9. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the
timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus
cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase operation
starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can
also be detected using status register RDY.
Figure 14. Chip Erase
10. Page Program
Page program i s an operati on that prog rams any n umber of b ytes from 1 to 256 bytes wit hin the sam e sector page (page
addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using small
sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and
Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the
24-bit addresses. Addr esses A18 to A0 are valid. The pro gram data is then loaded at each rising clock edge until the
rising CS edge, and data loading is continu ed until the rising CS edge. If the data loaded has exceeded 256 bytes, the
256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program
operation is not performed at the rising CS edge occurring at any other timing.
Figure 15. Page Program
SCK
SI
High Impedance
SO
CS
tCHE
Self-timed
Erase Cycle
60h / C7h
0 1 2 3 4 5 6 7
Mode3
Mode0
8CLK
MSB
tPP
Self-timed
Program Cycle
SCK
SI
High Impedance
SO
CS
PD
A
dd.
A
dd.02h
A
dd. PD
15
0 1 2 3 4 5 6 7 8 2316 24 31 32 39 40 47
Mode3
Mode0
8CLK
PD
2079
MSB
LE25S40AMC
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11. ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is not
accepted during writing. There are t wo m ethods of rea ding the silicon ID, each of which is assigned a de vice ID. In the
first met hod, the read command sequence co n s is t s onl y o f th e fi rst b us cycle in which ( 9F h) is input. In the s ubsequent
bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory type, memory
capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as clock inputs are
present, "Table 7-1 JEDEC ID codes table" lists the silicon ID codes and "Figure 16-a JEDEC ID read" shows the
JEDEC ID read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read wh en 24 dummy bits are in put after (ABh). "Table 7-2 ID codes table"
lists the silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling ed ge of the clock for bit 0 in the four th bus cycle and the silico n ID read seq uence is
finished by setting CS high.
Table 7-1. JEDEC ID read Table 7-2. ID read
Output code Output Code
Manufacturer code 62h 1 byte device ID 3Eh
(LE25S40A)
2 byte device ID Memory type 16h
Memory capacity code 13h (4M Bit)
Device code 1 00h
Figure 16-a. Silicon ID Read 1
Figure 16-b. Silicon ID Read 2
CS
High Impedance 13h16h62h
SCK
SO
SI 9Fh
15
MSBMSBMSB
0 1 2 3 4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3 32
00h
MSB
62h
MSB
CS
High Impedance 3Eh3Eh
SCK
SO
SI
A
Bh X X
15
MSBMSB
0 1 2 3 4 5 6 7 8 2316 24 31 39
8CL
Mode0
Mode3 32
X
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12. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic
level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,
HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited
and serial comm unication is reset at the rising CS edge. In the hold stat us, the S O output is in the high-im pedance state,
and SI and SCK are "don't care".
Figure 17. HOLD
13. Power-on
In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After
power-on, t he supply voltage has st abilized at VDD m in. or higher, waits for tPU before inputting the command to start
a device operation. The device is in the standby state and not in the power-down state after power is turned on. To put
the device into the power-down state, it is necessary to enter a power-down command.
Figure 18. Power-on Timing
CS
HOLD
SCK
SO
A
ctive HOLD
A
ctive
tHH
tHS
tHLZ
tHHZ
High Impedance
tHH
tHS
VDD(Max)
VDD(Min)
VDD
0V
tPU
CS = VDD level Full Access Allowed
LE25S40AMC
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14. Hardware Data Protection
LE25S40A incorporates a power-on reset function. The following conditions must be met in order to ensure that the
power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19. Power-down Timing
Power-on timing
Parameter Symbol
spec unit
min max
power-on to operation time tPU 500 s
power-down time tPD 10 ms
power-down voltage VBOT 0.2 V
15. Software Data Protection
The LE25S40A eliminates the possib ility of unintentional operations by not recognizing commands under the
following conditions .
When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
When the page program data is not in 1-byte increments
When the status register write command is input for 2 bus cycles or more
16. Decoupling Capacitor
A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure
that the device will operate stably.
VDD(Max)
VDD(Min)
VDD
0V vBOT
tPD
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19
Timing waveforms
Serial Input Timing
Serial Output Timing
Hold Timing
Status register write Timing
tHO tCHZ tCLZ
SI
tV
CS
SO
SCK
DATA VALID
CS
SO
SCK
HOLD
tHH tHS t
HH tHS
tHHZ tHLZ
High Impedance
WP
CS tWPS tWPH
High Impedance
tDH
tCPH
tDS
tCSH tCSS
CS
DATA VALID
SO
SI
SCK
High Impedance
tCLH tCLS tCLHI tCLLO
LE25S40AMC
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Figure 20. Status Register Write Flowchart
Status register write
Start
05h Set status register read
command
Set status register write
command
Program start on rising
edge of CS
End of status register
write
YES
Bit 0= “0” ?
06h Write enable
01h
NO
* Automatically placed in write disabled state
at the end of the status register write
Data
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21
Figure 21. Erase Flowcharts
Start
05h Set status register read
command
Set small sector erase
command
Address 1
Address 2
Start erase on rising
edge of CS
End of erase
Bit 0 = “0” ?
YES
Small sector erase
Address 3
06h Write enable
20h / D7h
NO
* Automatically placed in write disabled
state at the end of the erase
Start
05h Set status register read
command
Set sector erase
command
Address 1
Address 2
Start erase on rising
edge of CS
End of erase
Bit 0 = “0” ?
YES
Sector erase
Address 3
06h Write enable
D8h
NO
* Automatically placed in write disabled
state at the end of the erase
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Figure 22. Page Program Flowchart
Start
05h Set status register read
command
Set chip erase
command
Start erase on rising edge
of CS
End of erase
Bit 0 = “0” ?
YES
Chip erase
06h Write enable
60h / C7h
NO
* Automatically placed in write disabled state at
the end of the erase
Page program
Start
05h Set status register read
command
Set page program
command
Address 1
Address 2
Start program on rising
edge of CS
End of
programming
YES
Bit 0= “0” ?
Address 3
06h Write enable
02h
NO
* Automatically placed in write disabled state at
the end of the programming operation.
Data 0
Data n
LE25S40AMC
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ON Semiconductor and the ON logo are registered trademarks of SemiconductorComponents Industries, LLC (SCILLC) or its subsidiariesin the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representationor guarantee regarding the suitabilityof its products for any particularpurpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specificationscan
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as componentsin systemsintended for surgical implant into the body, or other applicationsintended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject toall
applicable copyright laws and is not for resale in any manner.
Figure 23. Making Diagrams
ORDERING INFORMATION
Device Package Shipping (Qty / Packing)
LE25S40AMCTWG SOIC-8/SOP8J(200mil)
(Pb-Free / Halogen Free) 2000 / Tape &Reel
25S40A
ALYW
00
SOP8J / SOIC8, CASE 751CU
25S40A = Specific Device Code
00 = Blank Data (entire memory cell data ar e FFh)
A = Assembly Location
L = Wafer Lot Traceability
YW = Two Digits Year and Wo rk Week Date coding
