CAT25C128U14A-TE13 - Catalyst Semiconductor, Inc.

1

CAT25C128/256

128K/256K-Bit SPI Serial CMOS E2PROM

FEATURES

■ 5 MHz SPI Compatible

■1.8 to 6.0 Volt Operation

■Hardware and Software Protection

■Zero Standby Current

■Low Power CMOS Technology

■SPI Modes (0,0 &1,1)

■Commercial, Industrial and Automotive

Temperature Ranges

■100,000 Program/Erase Cycles

■100 Year Data Retention

■Self-Timed Write Cycle

■8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP

and 20-Pin TSSOP

■64-Byte Page Write Buffer

■Block Write Protection

– Protect 1/4, 1/2 or all of E2PROM Array

PIN CONFIGURATION DIP Package (P)

PIN FUNCTIONS

Pin Name Function

SO Serial Data Output

SCK Serial Clock

WP Write Protect

VCC +1.8V to +6.0V Power Supply

VSS Ground

CS Chip Select

SI Serial Data Input

HOLD Suspends Serial Input

NC No Connect

BLOCK DIAGRAM

Characteristics subject to change without notice

DESCRIPTION

The CAT25C128/256 is a 128K/256K-Bit SPI Serial

CMOS E2PROM internally organized as 16Kx8/32Kx8

bits. Catalyst’s advanced CMOS Technology substan-

tially reduces device power requirements. The

CAT25C128/256 features a 64-byte page write buffer.

The device operates via the SPI bus serial interface and

is enabled though a Chip Select (CS). In addition to the

Chip Select, the clock input (SCK), data in (SI) and data

out (SO) are required to access the device. The HOLD

pin may be used to suspend any serial communication

without resetting the serial sequence. The CAT25C128/

256 is designed with software and hardware write pro-

tection features including Block Lock protection. The

device is available in 8-pin DIP, 8-pin SOIC, 16-pin

SOIC, 14-pin TSSOP and 20-pin TSSOP packages.

TSSOP Package (U20)

SENSE AMPS

SHIFT REGISTERS

SPI

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

I/O

CONTROL

E

2

PROM

ARRAY

COLUMN

DECODERS

XDEC

HIGH V OL TAGE/

TIMING CONTROL

SO

25C128 F02

STATUS

REGISTER

BLOCK

PROTECT

LOGIC

CONTROL LOGIC

DATA IN

STORAGE

SI

CS

WP

HOLD

SCK

SOIC Package (S, K)

VSS

SO

WP

VCC

HOLD

SCK

SI

1

2

3

4

8

7

6

5

CS

SO

WP

CS VCC

HOLD

SCK

SI

1

2

3

4

8

7

6

5

VSS

Doc. No. 25088-00 1/01

CS

WP

HOLD

VCC

NC

NC NC

SO

NC

V

SS

SCK

SI

1

2

3

4

5

6

78

9

10

11

12

13

14

SOIC Package (S16)

NC NC

CS

WP

HOLD

VCC

NC

NC NC

NC

SO

NC

SO

VSS SCK

SI

1

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

19

20

TSSOP Package (U14)

CS

NC

1

2

3

414

13

12

11 NC

NC

5

6

710

98

NC

SCK

VSS SI

NC

WP

VCC

HOLDSO 15

16

NCNC

Note: CAT25C256 not available in 8-Lead S or U packages.

2

CAT25C128/256

Doc. No. 25088-00 1/01

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

ICC1 Power Supply Current 10 mA VCC = 5V @ 5MHz

(Operating Write) SO=open; CS=Vss

ICC2 Power Supply Current 2 mA VCC = 5.5V

(Operating Read) FCLK = 5MHz

ISB Power Supply Current 0 µACS = VCC

(Standby) VIN = VSS or VCC

ILI Input Leakage Current 2 µA

ILO Output Leakage Current 3 µAV

OUT = 0V to VCC,

CS = 0V

VIL(3) Input Low Voltage -1 VCC x 0.3 V

VIH(3) Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Low Voltage 0.4 V

VOH1 Output High Voltage VCC - 0.8 V

VOL2 Output Low Voltage 0.2 V 1.8V≤VCC<2.7V

VOH2 Output High Voltage VCC-0.2 V IOL = 150µA

IOH = -100µA

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to VSS(1) .................. –2.0V to +VCC +2.0V

VCC with Respect to VSS................................ –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current(2) ........................ 100 mA

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

NEND(3) Endurance 100,000 Cycles/Byte MIL-STD-883, Test Method 1033

TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008

VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

4.5V≤VCC<5.5V

IOL = 3.0mA

IOH = -1.6mA

3

CAT25C128/256

Doc. No. 25088-00 1/01

Figure 1. Sychronous Data Timing

Limits

Vcc= VCC =V

CC =

1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions

tSU Data Setup Time 100 70 35 ns

tHData Hold Time 100 70 35 ns

tWH SCK High Time 250 150 80 ns

tWL SCK Low Time 250 150 80 ns

fSCK Clock Frequency DC 1 DC 3 DC 5 MHz

tLZ HOLD to Output Low Z 50 50 50 ns

tRI(1) Input Rise Time 2 2 2 µs

tFI(1) Input Fall Time 2 2 2 µs

tHD HOLD Setup Time 250 250 40 ns

tCD HOLD Hold Time 250 250 40 ns

tWC Write Cycle Time 10 10 5 ms

tVOutput Valid from Clock Low 250 250 80 ns

tHO Output Hold Time 0 0 0 ns

tDIS Output Disable Time 250 250 100 ns

tHZ HOLD to Output High Z 150 150 50 ns

tCS CS High Time 1000 250 100 ns

tCSS CS Setup Time 1000 250 100 ns

tCSH CS Hold Time 1000 250 100 ns

tWPS WP Setup Time 50 50 50 ns

tWPH WP Hold Time 50 50 50 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

A.C. CHARACTERISTICS (CAT25C128)

VALID IN

VIH

VIL t

CSS

VIH

VIL

VIH

VIL

VOH

VOL

HI-Z

t

SU

t

H

t

WH

t

WL

t

V

t

CS

t

CSH

t

HO

t

DIS

HI-Z

CS

SCK

SI

SO

t

RI

tFI

Note: Dashed Line= mode (1, 1) — — — —

CL = 50pF

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CAT25C128/256

Doc. No. 25088-00 1/01

Limits

Vcc= VCC= VCC= VCC =

1.8V-6.0V 2.5V-6.0V 2.7V-6.0V 4.5V-5.5V

SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. Min. Max. UNITS

tSU Data Setup Time 500 100 70 35 ns

tHData Hold Time 500 100 70 35 ns

tWH SCK High Time 2500 250 200 80 ns

tWL SCK Low Time 2500 250 200 80 ns

fSCK Clock Frequency DC 0.2 DC 2.0 DC 2.5 DC 5 MHz

tLZ HOLD to Output Low Z 100 50 50 50 ns

tRI(1) Input Rise Time 2 2 2 2 µs

tFI(1) Input Fall Time 2 2 2 2 µs

tHD HOLD Setup Time 250 100 100 40 ns

tCD HOLD Hold Time 250 100 100 40 ns

tWC Write Cycle Time 10 10 10 5 ms

tVOutput Valid from Clock Low 250 200 200 80 ns

tHO Output Hold Time 0 0 0 0 ns

tDIS Output Disable Time 250 200 200 100 ns

tHZ HOLD to Output High Z 150 100 100 50 ns

tCS CS High Time 100 100 100 100 ns

tCSS CS Setup Time 100 100 100 100 ns

tCSH CS Hold Time 100 100 100 100 ns

tWPS WP Setup Time 50 50 50 50 ns

tWPH WP Hold Time 50 50 50 50 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

A.C. CHARACTERISTICS (CAT25C256)

Test

Conditions

CL = 50pF

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CAT25C128/256

Doc. No. 25088-00 1/01

FUNCTIONAL DESCRIPTION

The CAT25C128/256 supports the SPI bus data trans-

mission protocol. The synchronous Serial Peripheral

Interface (SPI) helps the CAT25C128/256 to interface

directly with many of today’s popular microcontrollers.

The CAT25C128/256 contains an 8-bit instruction regis-

ter. (The instruction set and the operation codes are

detailed in the instruction set table)

After the device is selected with CS going low, the first

byte will be received. The part is accessed via the SI pin,

with data being clocked in on the rising edge of SCK.

The first byte contains one of the six op-codes that define

the operation to be performed.

PIN DESCRIPTION

SI: Serial Input

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses, and data to be written to the

25C128/256. Input data is latched on the rising edge of

the serial clock.

SO: Serial Output

SO is the serial data output pin. This pin is used to

transfer data out of the 25C128/256. During a read cycle,

data is shifted out on the falling edge of the serial clock.

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchro-

nize the communication between the microcontroller

and the 25C128/256. Opcodes, byte addresses, or data

present on the SI pin are latched on the rising edge of the

SCK. Data on the SO pin is updated on the falling edge

of the SCK.

CSCS

CS: Chip Select

CS is the Chip select pin. CS low enables the CAT25C128/

256 and CS high disables the CAT25C128/256. CS high

takes the SO output pin to high impedance and forces

the device into a Standby Mode (unless an internal write

operation is underway) The CAT25C128/256 draws

ZERO current in the Standby mode. A high to low

transition on CS is required prior to any sequence being

initiated. A low to high transition on CS after a valid write

sequence is what initiates an internal write cycle.

WPWP

WP: Write Protect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.

When WP is tied low and the WPEN bit in the status

register is set to “1”, all write operations to the status

register are inhibited. WP going low while CS is still low

will interrupt a write to the status register. If the internal

write cycle has already been initiated, WP going low will

have no effect on any write operation to the status

register. The WP pin function is blocked when the WPEN

bit is set to 0.

HOLDHOLD

HOLD: Hold

HOLD is the HOLD pin. The HOLD pin is used to pause

transmission to the CAT25C128/256 while in the middle

of a serial sequence without having to re-transmit entire

sequence at a later time. To pause, HOLD must be

brought low while SCK is low. The SO pin is in a high

impedance state during the time the part is paused, and

transitions on the SI pins will be ignored. To resume

communication, HOLD is brought high, while SCK is low.

(HOLD should be held high any time this function is not

being used.) HOLD may be tied high directly to Vcc or tied

to Vcc through a resistor. Figure 9 illustrates hold timing

sequence.

Instruction Opcode Operation

WREN 0000 0110 Enable Write Operations

WRDI 0000 0100 Disable Write Operations

RDSR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register

READ 0000 0011 Read Data from Memory

WRITE 0000 0010 Write Data to Memory

INSTRUCTION SET

6

CAT25C128/256

Doc. No. 25088-00 1/01

Status Register Bits Array Address Protection

BP1 BPO Protected

25C128 25C256

0 0 None None No Protection

0 1 3000-3FFF 6000-7FFF Quarter Array Protection

1 0 2000-3FFF 4000-7FFF Half Array Protection

1 1 0000-3FFF 0000-7FFF Full Array Protection

BLOCK PROTECTION BITS

Protected Unprotected Status

WPEN WPWP

WPWP

WP WEL Blocks Blocks Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

WRITE PROTECT ENABLE OPERATION

76543210

WPEN X X X BP1 BP0 WEL RDY

STATUS REGISTER

The Status Register indicates the status of the device.

The RDY (Ready) bit indicates whether the CAT25C128/

256 is busy with a write operation. When set to 1 a write

cycle is in progress and when set to 0 the device

indicates it is ready. This bit is read only

The WEL (Write Enable) bit indicates the status of the

write enable latch . When set to 1, the device is in a Write

Enable state and when set to 0 the device is in a Write

Disable state. The WEL bit can only be set by the WREN

instruction and can be reset by the WRDI instruction.

The BPO and BP1 (Block Protect) bits indicate which

blocks are currently protected. These bits are set by the

user issuing the WRSR instruction. The user is allowed

to protect quarter of the memory, half of the memory or

the entire memory by setting these bits. Once protected

the user may only read from the protected portion of the

array. These bits are non-volatile.

The WPEN (Write Protect Enable) is an enable bit for the

WP pin. The WP pin and WPEN bit in the status register

control the programmable hardware write protect fea-

ture. Hardware write protection is enabled when WP is

low and WPEN bit is set to high. The user cannot write

to the status register (including the block protect bits and

the WPEN bit) and the block protected sections in the

memory array when the chip is hardware write pro-

tected. Only the sections of the memory array that are

not block protected can be written. Hardware write

protection is disabled when either WP pin is high or the

WPEN bit is zero.

7

CAT25C128/256

Doc. No. 25088-00 1/01

After the correct read instruction and address are sent,

the data stored in the memory at the selected address is

shifted out on the SO pin. The data stored in the memory

at the next address can be read sequentially by continu-

ing to provide clock pulses. The internal address pointer

is automatically incremented to the next higher address

after each byte of data is shifted out. When the highest

address (7FFFh for 25C256 and 3FFFh for 25C128) is

reached, the address counter rolls over to 0000h allow-

ing the read cycle to be continued indefinitely. The read

operation is terminated by pulling the CS high. To read

the status register, RDSR instruction should be sent.

The contents of the status register are shifted out on the

SO line. The status register may be read at any time

even during a write cycle.Read sequence is illustrated in

figure 4. Reading status register is illustrated in figure 5.

Figure 2. WREN Instruction Timing

Figure 3. WRDI Instruction Timing

DEVICE OPERATION

Write Enable and Disable

The CAT25C128/256 contains a write enable latch. This

latch must be set before any write operation. The device

powers up in a write disable state when Vcc is applied.

WREN instruction will enable writes (set the latch) to the

device. WRDI instruction will disable writes (reset the

latch) to the device. Disabling writes will protect the

device against inadvertent writes.

READ Sequence

The part is selected by pulling CS low. The 8-bit read

instruction is transmitted to the CAT25C128/256, fol-

lowed by the 16-bit address (the Most Significant Bit is

don’t care for 25C256 and the two most significant bits

are don't care for the 25C128).

SK

SI

CS

SO

00000 110

HIGH IMPEDANCE

SK

SI

CS

SO

00000 100

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — — — —

8

CAT25C128/256

Doc. No. 25088-00 1/01

Figure 5. RDSR Timing

Byte Write

Once the device is in a Write Enable state, the user may

proceed with a write sequence by setting the CS low,

issuing a write instruction via the SI line, followed by the

16-bit address (the most significant bit is don't care for

25C256 and the two most significant bits are don't care

for the 25C128), and then the data to be written. Pro-

gramming will start after the CS is brought high. The low

to high transition of the CS pin must occur during the

SCK low time, immediately after clocking the least

significant bit of the data. Figure 6 illustrates byte write

sequence.

WRITE Sequence

The CAT25C128/256 powers up in a Write Disable

state. Prior to any write instructions, the WREN instruc-

tion must be sent to CAT25C128/256. The device goes

into Write enable state by pulling the CS low and then

clocking the WREN instruction into CAT25C128/256.

The CS must be brought high after the WREN instruction

to enable writes to the device. If the write operation is

initiated immediately after the WREN instruction without

CS being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set. Also, for a successful write operation the

address of the memory location(s) to be programmed

must be outside the protected address field location

selected by the block protection level.

Figure 4. Read Instruction Timing

SK

SI

SO

00000011 BYTE ADDRESS*

012345678910 2021222324252627282930

7 6 5 4 3 2 1 0

*Please check the instruction set table for address

CS

OPCODE

DATA OUT

MSB

HIGH IMPEDANCE

012345678 10911121314

SCK

SI

DATA OUT

MSB

HIGH IMPEDANCE

OPCODE

SO 7 6 54 3 2 1 0

CS

00000 1 01

Note: Dashed Line= mode (1, 1) — — — —

9

CAT25C128/256

Doc. No. 25088-00 1/01

Figure 7. WRSR Timing

address will remain constant.The only restriction is that

the 64 bytes must reside on the same page. If the

address counter reaches the end of the page and clock

continues, the counter will “roll over” to the first address

of the page and overwrite any data that may have been

written. The CAT25C128/256 is automatically returned

to the write disable state at the completion of the write

cycle. Figure 8 illustrates the page write sequence.

To write to the status register, the WRSR instruction

should be sent. Only Bit 2, Bit 3 and Bit 7 of the status

register can be written using the WRSR instruction.

Figure 7 illustrates the sequence of writing to status

register.

During an internal write cycle, all commands will be

ignored except the RDSR (Read Status Register) in-

struction.

The Status Register can be read to determine if the write

cycle is still in progress. If Bit 0 of the Status Register is

set at 1, write cycle is in progress. If Bit 0 is set at 0, the

device is ready for the next instruction

Page Write

The CAT25C128/256 features page write capability.

After the initial byte the host may continue to write up to

64 bytes of data to the CAT25C128/256. After each byte

of data is received, six lower order address bits are

internally incremented by one; the high order bits of

Figure 6. Write Instruction Timing

Figure 8. Page Write Instruction Timing

SK

SI

SO

0 0 0 0 0 0 1 0 ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

012345678 2122232425262728293031

CS

OPCODE DATA IN

HIGH IMPEDANCE

012345678 10911121314

SCK

SI

MSB

HIGH IMPEDANCE

DATA IN

15

SO

CS

7 6 54 3 2 10

0000000 1

OPCODE

SK

SI

SO

0 0 0 0 0 0 1 0 ADDRESS

Data

Byte 1

012345678 212223

24-31 32-39

Data

Byte 2 Data

Byte 3 Data Byte N

CS

OPCODE

7..1 0

24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

DATA IN

HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — — — —

10

CAT25C128/256

Doc. No. 25088-00 1/01

Figure 9. HOLDHOLD

HOLDHOLD

HOLD Timing

DESIGN CONSIDERATIONS to start an internal write cycle. Access to the array during

an internal write cycle is ignored and programming

is continued. On power up, SO is in a high impedance.

If an invalid op code is received, no data will be shifted

into the CAT25C128/256, and the serial output pin (SO)

will remain in a high impedance state until the falling

edge of CS is detected again.

The CAT25C128/256 powers up in a write disable state

and in a low power standby mode. A WREN instruction

must be issued to perform any writes to the device after

power up. Also,on power up CS should be brought low

to enter a ready state and receive an instruction. After

a successful byte/page write or status register write the

CAT25C128/256 goes into a write disable mode. CS

must be set high after the proper number of clock cycles

CS

SCK

HOLD

SO

tCD

tHD

tCD

tLZ

tHZ HIGH IMPEDANCE

Note: Dashed Line= mode (1, 1) — — — —

t

CSH

CS

SCK

WP

t

WPS

t

WPH

Figure 10. WP WP

WP WP

WP Timing

Note: Dashed Line= mode (1, 1) — — — —

11

CAT25C128/256

Doc. No. 25088-00 1/01

Notes:

(1) The device used in the above example is a 25C256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

Voltage, Tape & Reel)

ORDERING INFORMATION

Package

P = 8-Pin PDIP

S = 8-Pin SOIC (JEDEC)

S16 = 16-Pin SOIC (JEDEC)

K = 8-Pin SOIC (EIAJ)

U14 = 14-Pin TSSOP

U20 = 20-Pin TSSOP

Prefix Device # Suffix

25C256 KITE13

Product

Number

25C128: 128K

25C256: 256K

Tape & Reel

TE13: 2000/Reel

Operating V oltage

Blank (Vcc=2.5 to 6.0V)

1.8 (Vcc=1.8 to 6.0V)

- 1.8

CAT

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

A = Automotive (-40˚ to +105˚C)*

* -40˚C to +125˚C is available upon request

Optional

Company ID