LC05732ARA Battery Protection IC, Integrated Power MOSFET, 1-Cell Lithium-Ion Battery Overview The LC05732ARA is a protection IC for 1-cell lithium-ion batteries with integrated power MOS FET. Also it integrates highly accurate detection circuits and detection delay circuits to prevent batteries from over-charging, over-discharging, over-current discharging and over-current charging. In addition, main system can execute the power-on reset of itself by turning off the charge FET and discharge FET of LC05732ARA for a certain time period, with a reset signal. A battery protection system can be made by only LC05732ARA and few external parts. Features * Charge-and-Discharge Power MOSFET are Integrated at TA = 25C, * * * * * * * VCC = 4.0 V ON Resistance (Total of Charge and Discharge ) 4.8 mW (typ) Highly Accurate Detection Voltage/Current at TA = 25C, VCC = 3.7 V Over-Charge Detection 25 mV Over-Discharge Detection 50 mV Charge Over-Current Detection 0.7 A Discharge Over-Current Detection 0.7 A Delay Time for Detection and Release (Fixed Internally) Discharge/Charge Over-Current Detection is Compensated for Temperature Dependency of Power FET 0 V Battery Charging: "Inhibit" Auto Wake-up Function Battery Charging: "Inhibit" Forcible Charge-FET and Discharge-FET OFF Mode RSTB>VDD*0.9: Charge-FET and Discharge-FET = ON RSTB<VDD*0.1: Charge-FET and Discharge-FET = OFF These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAM XXXXX AYYWW ECP30, 1.97x4.01 SUFFIX CASE 971BC A = Assembly Location YY = Year WW = Work Week ORDERING INFORMATION Device Package Shipping LC05732A02RATBG ECP30 (Pb-Free) 5000 / Tape & Reel LC05732A03RATBG ECP30 (Pb-Free) 5000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Typical Applications * Smart Phone * Tablet * Wearable Device (c) Semiconductor Components Industries, LLC, 2017 March, 2018 - Rev. 3 1 Publication Order Number: LC05732ARA/D LC05732ARA SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS at TA = 25C (Notes 1, 2, 3, 5) Parameter Symbol Conditions Ratings Unit Between PAC+ and VCC : R1 = 680 W Supply voltage VCC -0.3 to 12.0 V S1 - S2 voltage VS1-S2 20.0 V CS terminal Input voltage CS VCC-20.0 to VCC+0.3 V RSTB input voltage RSTB -0.3 to 7 V Storage temperature Tstg -55 to +125 C Operating ambient temperature Topr -40 to +100 C Allowable power dissipation Pd 800 mW Junction temperature TJ 125 C (Note 4) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Absolute maximum ratings represent the values which cannot be exceeded at any given time 2. If you intend to use this IC continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for confirmation 3. This device is made for power applications. 4. JESD 51-3 (1S) 5. Please execute appropriate test and take safety measures on your board. PAC+ R1 VCC VCC RSTB R3 RSTB Controller IC Battery C1 S1 S2 CS R2 PAC- Figure 1. Example of Application Circuit Components Min Recommended Value Max Unit R1 330 680 1k W R2 680 1k 2k W R3 680 1k 2k W C1 0.1m 1.0m 2.2m F *We don't guarantee the characteristics of the circuit shown above. www.onsemi.com 2 Description LC05732ARA ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9) Parameter Symbol Conditions Min Typ Max Unit mV DETECTION VOLTAGE R1 = 680 W Over-charge detection voltage Vov Over-charge release voltage Vovr R1 = 680 W Over-discharge detection voltage Vuv R1 = 680 W Over-discharge release voltage Vuvr Discharge over-current detection current Ioc Discharge over-current detection current2 (Short circuit) Ioc2 Charge over-current detection current Ioch R1=680 W CS =0V R2 = 1 kW R2 = 1 kW R2 = 1 kW TA = 25C Vov_set -25 Vov_set Vov_set +25 TA = -30 to 70C Vov_set -30 Vov_set Vov_set +30 TA = 25C Vovr_set -40 Vovr_set Vovr_set +40 TA = -30 to 70C Vovr_set -70 Vovr_set Vovr_set +70 TA = 25C Vuv_set -50 Vuv_set Vuv_set +50 TA = -30 to 70C Vuv_set -80 Vuv_set Vuv_set +80 TA = 25C Vuvr_set -100 Vuvr_set Vuvr_set +100 TA = -30 to 70C Vuvr_set -120 Vuvr_set Vuvr_set +120 TA = 25C VCC = 3.7 V Ioc_set -0.7 Ioc_set Ioc_set +0.7 TA = -30 to 70C VCC = 3.7 V Ioc_set -1.2 Ioc_set Ioc_set +1.2 TA = 25C VCC = 3.7 V Ioc2_set*0.8 Ioc2_set Ioc2_set*1.2 TA = -30 to 70C VCC = 3.7 V Ioc2_set*0.6 Ioc2_set Ioc2_set*1.8 TA = 25C VCC = 3.7 V Ioch_set -0.7 Ioch_set Ioch_set +0.7 TA = -30 to 90C VCC = 3.7 V Ioch_set -1.2 Ioch_set Ioch_set +1.2 0.9*VCC mV mV mV A A A RESET TERMINAL High-Level Input Voltage VIH TA = -30 to 90C Low-Level Input Voltage VIL TA = -30 to 90C 0.1*VCC V High-Level Input Leakage Current IIH VCC = RSTB TA = -30 to 90C 1 mA Low-Level Input Leakage Current IIL VCC = 3.7 V RSTB = 0 V TA = -30 to 90C 20 34 48 mA Reset pulse width Tw_res VCC = 2.2 to 4.3 V TA = -30 to 90C 10 20 30 ms TA = 25C 0.4 0.9 1.4 V 3 6 mA 0.1 mA V INPUT VOLTAGE 0 V battery charging inhibition battery voltage Vinh CURRENT CONSUMPTION Operating current ICC At normal state TA = 25C VCC = 3.7 V Shut down current Ishut At shut down state TA = 25C VCC = 2.0 V ON resistance 1 of integrated power MOSFET Ron1 VCC = 3.1 V TA = 25C 4.4 5.4 6.9 mW ON resistance 2 of integrated power MOS FET Ron2 TA = 25C 4 4.9 5.8 mW ON resistance 3 of integrated power MOSFET Ron3 TA = 25C 3.9 4.8 5.7 mW RESISTANCE I = 2.0 A VCC = 3.8 V I = 2.0 A VCC = 4.0 V I = 2.0 A www.onsemi.com 3 LC05732ARA ELECTRICAL CHARACTERISTICS (Notes 6, 7, 8, 9) Parameter Symbol Conditions Min Typ Max Unit 3.8 4.7 5.6 mW RESISTANCE VCC = 4.5V ON resistance 4 of integrated power MOSFET Ron4 Internal resistance (VCC-CS) Rcsu VCC = Vuv_set CS = 0 V TA = 25C 300 kW Internal resistance (VSS-CS) Rcsd VCC = 3.7 V CS = 0.1 V TA = 25C 10 kW Forward Source to Source Voltage Vf(s-s) VCC = 2.0 V Is = 0.25 A TA = 25C 0.67 1.06 V s TA = 25C I = 2.0 A DETECTION AND RELEASE DELAY TIME Over-charge detection delay time Tov Over-charge release delay time Tovr Over-discharge detection delay time Tuv Over-discharge release delay time Tuvr Discharge over-current detection delay time 1 Toc1 Discharge over-current release delay time 1 Tocr1 Discharge over-current detection delay time 2 (Short circuit) Toc2 Charge Over-current detection delay time Toch Charge Over-current release delay time Tochr VCC = 3.7 V Reset release time Tres VCC = 3.7 V VCC = 3.7 V VCC = 3.7 V VCC = 3.7 V VCC = 3.7 V TA = 25C 0.8 1 1.2 TA = -30 to 70C 0.6 1 1.5 TA = 25C 12.8 16 19.2 TA = -30 to 70C 9.6 16 24 TA = 25C 14 20 26 TA = -30 to 70C 12 20 30 TA = 25C 0.9 1.1 1.3 TA = -30 to 70C 0.6 1.1 1.5 TA = 25C 9.6 12 14.4 TA = -30 to 70C 7.2 12 18 TA = 25C 3.2 4 4.8 TA = -30 to 70C 2.4 4 6 TA = 25C 230 300 420 TA = -30 to 70C 200 300 450 TA = 25C 12.8 16 19.2 TA = -30 to 90C 9.6 16 24 TA = 25C 3.2 4 4.8 TA = -30 to 90C 2.4 4 6 TA = 25C 0.8 1 1.2 TA = -30 to 70C 0.6 1 1.5 ms ms ms ms ms ms ms ms s 6. This device is made for power applications. 7. Please execute appropriate test and take safety measures on your board. 8. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 9. The specification in this parameter and all specification at high and low temperature are guaranteed by design. www.onsemi.com 4 LC05732ARA SELECTION GUIDE Vov (V) Vovr (V) Vuv (V) Vuvr (V) Ioc (A) Ioch (A) Ioc2 (A) Tuv (ms) Reset Function LC05732A02RATBG Device 4.475 4.475 2.1 2.1 7.0 9.0 25.0 20 Enable LC05732A03RATBG 4.500 4.300 2.3 2.3 9.0 6.0 15.0 20 Disable 1 2 3 4 5 6 7 8 S1 S1 S1 S1 S1 S1 S1 VCC B S1 S1 S1 S1 S1 S1 NC C S2 S2 S2 S2 S2 S2 NC D S2 S2 S2 S2 S2 S2 RSTB A CS TOP VIEW Figure 2. Pin Functions Pin No. Symbol A1-7 B1-6 S1 Pin Function Description Source 1 Negative power input A8 VCC C1-6 D1-6 S2 VCC terminal D7 RSTB D8 CS Charger minus voltage input terminal B7,C7 NC Non connection Source 2 Charge and discharge off control terminal ("L" = Reset ) www.onsemi.com 5 Connected to VCC with 100 kW LC05732ARA VCC Power Control OSC Level Shifter Control Circuit Rcsu Over-discharge Detector Discharge Over- current Detector Rcsd 1.2V Short-circuit Detector Over- charge Detector Charge Over- current Detector OTP VSS RSTB Figure 3. Block Diagram Figure 4. Pdmax vs TA www.onsemi.com 6 S1 S2 CS LC05732ARA Figure 5. Thermal Resistance vs Time www.onsemi.com 7 LC05732ARA DESCRIPTION OF OPERATION 1. Normal mode LC05732ARA controls charging and discharging by detecting cell voltage (VCC) and controls S2-S1 current. In case that cell voltage is between over-discharge detection voltage (Vuv) and over-charge detection voltage (Vov), and S2-S1 current is between charge over-current detection current (Ioch) and discharge over-current detection current (Ioc), internal power MOS FETs as CHG_SW, DCHG_SW are both turned ON. This is the normal mode, and it is possible to be charged and discharged. 2. Over-charging mode Internal power MOSFET CHG_SW turns off if cell voltage becomes greater than or equal to over-charge detection voltage (Vov) over the delay time of over-charging (Tov). This is the over-charging detection mode. The recovery from over-charging will be made after the following two conditions are satisfied. 1. Charger is removed from IC. 2. Cell voltage decreases under over-charge release voltage (Vovr) over the delay time of over-charging releasing (Tovr) due to discharging through a load. Consequently, internal power MOS FET as CHG_SW will be turned on and normal mode will be resumed. In over-charging mode, discharging over-current detection is made only when CS pin increases more than discharging over-current detection current 2(Ioc2), because discharge current flows through parasitic diode of CHG_SW FET. If CS pin voltage increases more than discharging over-current detection current 2 (Ioc2) over the delay time of discharging over-current 2 (Toc2), discharging will be shut off, because internal power FETs as DCHG_SW is turned off. (short-circuit detection mode) After detecting short-circuit, CS pin will be pulled down to VSS by internal resistor Rcsd. The recovery from short circuit detection in over-charging mode will be made after the following two conditions are satisfied. 1. Load is removed from IC. 2. CS pin voltage becomes less than or equal to discharging over-current detection current 2 (Ioc2) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and over-charging detection mode will be resumed. 3. Over-discharging mode without Auto Wake Up function If cell voltage drops lower than over-discharge detection voltage (Vuv) over the delay time of over-discharging (Tuv), discharging will be shut off, internal power FETs as DCHG_SW is turned off. This is the over-discharging mode. After detecting over-discharging, CS pin will be pulled up to VCC by an internal resistor Rcsu and the bias of internal circuits will be shut off. (Shut-down mode) In shut-down mode, operating current is suppressed under 0.1 uA (max). The recovery from stand-by mode will be made by internal circuits biased after the connecting charger. By continuing to be charged, if cell voltage increases more than over-discharge detection voltage (Vuvr) over the delay time of over-discharging (Tuvr), internal power MOS FETs as DCHG_SW is turned on and normal mode will be resumed. In over-discharge detection mode, charging over-current detection does not operate. By continuing to be charged, charging over-current detection starts to operate after cell voltage goes up more than over-discharge release voltage (Vuvr). 4. Discharging over-current detection mode 1 Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage becomes greater than or equal to discharging over-current detection current (Ioc) over the delay time of discharging over-current (Toc1). This is the discharging over-current detection mode 1. In discharging over-current detection mode 1, CS pin will be pulled down to VSS with internal resistor Rcsd. The recovery from discharging over-current detection mode will be made after the following two conditions are satisfied. 1. Load is removed from IC. 2. CS pin voltage becomes less than or equal to discharging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed. 5. Discharging over-current detection mode 2 (short circuit detection) Internal power MOS FET as DCHG_SW will be turned off and discharging current will be shut off if CS pin voltage becomes greater than or equal to discharging over-current detection current2 (Ioc2) over the delay time of discharging over-current 2 (Toc2). This is the short circuit detection mode. www.onsemi.com 8 LC05732ARA In short circuit detection mode, CS pin will be pulled down to VSS by internal resistor Rcsd. The recovery from short circuit detection mode will be made after the following two conditions are satisfied. a. Load is removed from IC. b. CS pin voltage becomes less than or equal to discharging over-current release current (Iocr) over the delay time of discharging over-current release (Tocr1) due to CS pin pulled down through Rcsd. Consequently, internal power MOS FET as DCHG_SW will be turned on, and normal mode will be resumed. 6. Charging over-current detection mode Internal power MOS FET as CHG_SW will be turned off and charging current will be shut off if CS pin voltage becomes less than or equal to charging over-current detection current (Ioch) over the delay time of charging over-current (Toch). This is the charging over-current detection mode. The recoveries from charging over-current detection mode will be made after the following two conditions are satisfied. 1. Charger is removed from IC and CS pin will increase by load connection. 2. CS pin voltage becomes greater than or equal to charging over-current release current (Iochr) over the delay time of charging over-current release (Tocrh). Consequently, internal power MOS FET as CHG_SW will be turned on, and normal mode will be resumed. *Internal current flows out through CS and S2 terminals. After charger is removed, it flows through parasitic diode of CHG_SW FET. Therefore, CS pin voltage will go up more than charging over-current release current (Iochr). So CS pin voltage is not an indispensable condition for recovery from charging over-current detection. 7. 0 V Battery Protection Function This function protects the battery when a short circuit in the battery (0 V battery) is detected, at which point charging will be prohibited. When the voltage of a battery is below 1.4 V (max), the gate of the charging control FET is fixed to the PAC-Terminal voltage, at which point charging will be prohibited. If the voltage of the battery is greater than the 0 V battery prohibit voltage (Vinh), charging will be enabled. 8. Reset mode In case of normal mode, internal power MOS FET as CHG_SW and DCHG_SW will be turned off and charging and discharging current will be shut off if RSTB pin voltage becomes less than or equal to low-level input voltage (VIL) over the delay time of reset pulse width(Tw_res). This is the reset mode. The recovery from reset mode will be made itself after the reset release time (Tres). Consequently, internal power MOS FET as CHG_SW and DCHG_SW will be turned on, and normal mode will be resumed. www.onsemi.com 9 LC05732ARA TIMING CHART Charger connection Load connection Charger connection VCC Vov Vovr Vuv/Vuvr DCHG_SW (Gate) VCC S1 CHG_SW (Gate) VCC S2 CS VCC S1 Tov Tovr Tuv Figure 6. Over-charge Detection/Release, Over-discharge Detection/Release (Connect Charger) www.onsemi.com 10 LC05732ARA Charger connection Load connection VCC Vov Vovr Vuv DCHG_SW (Gate) VCC S1 CHG_SW (Gate) VCC S2 CS VCC S1 Tov Tovr Figure 7. Over-charge Detection/Release, Over-discharge Detection/Release (Non-connect Charger) www.onsemi.com 11 LC05732ARA Load connection Load connection VCC Vov Vuv DCHG_SW (Gate) VCC S1 CHG_SW (Gate) VCC S2 CS VCC S1 Discharge Current Ioc Toc1 Toc2 Tocr1 Tocr1 Figure 8. Discharge Over-Current Detection1, Discharge Over-current Detection2 (Short Circuit) www.onsemi.com 12 LC05732ARA Charger connection Load connection VCC Vov Vuv DCHG_SW (Gate) VCC S1 CHG_SW (Gate) VCC S2 CS VCC S1 Charge/Discharge Current 0 Ioch Toch Tochr Figure 9. Charge Over-current Detection www.onsemi.com 13 LC05732ARA Load connection Load connection RSTB VCC Vov Vuv DCHG_SW (Gate) VCC S1 CHG_SW (Gate) VCC S2 Discharge Current Tw _res Tres Figure 10. Reset Function www.onsemi.com 14 LC05732ARA PACKAGE DIMENSIONS ECP30, 1.97x4.01 CASE 971BC ISSUE A EEE EEE EEE ORIENTATION MARK 2X 0.05 C 2X 0.05 C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. DIMENSION b IS MEASURED AT THE MAXIMUM BALL DIAMETER PARALLEL TO DATUM C. A B D DIM A A1 A2 b D E E2 E3 E4 e SUPPORT SI ENCAPSULATION TOP VIEW A2 DETAIL A A 0.15 C DETAIL A 0.05 C NOTE 3 A1 C SIDE VIEW e E2 E4 E3 e SEATING PLANE e e/2 D e C B A 30X 1 2 IC DIE 3 4 5 6 7 8 b 0.05 C A B 0.03 C IC DIE BOTTOM VIEW RECOMMENDED SOLDERING FOOTPRINT* 30X 0.24 0.40 PITCH 0.10 A1 PACKAGE OUTLINE 0.40 PITCH 0.96 0.505 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 15 MILLIMETERS MIN MAX 0.625 0.545 0.165 0.205 0.380 0.420 0.245 0.285 1.970 BSC 4.010 BSC 0.860 BSC 0.100 BSC 1.405 BSC 0.400 BSC LC05732ARA ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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