F4052/34052 DUAL 4-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER DESCRIPTION The F4052 is a Dual 4-Channel Analog Multiplexer/Demultiplexer with common channel select logic. Each Multiplexer/Demultiplexer has four Independent Inputs/Outputs (Yo-Y3) and a Common Input/Output (Z). The common channel select logic includes two Address Inputs (Ag, A4) and an active LOW Enable Input (E). Both multiplexer/demultiplexers contain four bidirectional analog switches, each with one side connected to an Independent Input/Output (Yg-Y3) and the other side connected to a Common Input/Output (Z). With the Enable Input LOW, one of the four switches is selected (low impedance, ON state) by the two Address Inputs. With the Enable Input HIGH, ail switches are in the high impedance OFF state, independent of the Address Inputs. Vpp and Vgg are the two supply voltage connections for the digital control inputs (Ag, A1, E). Their voltage limits are the same as for all other digital CMOS. The analog inputs/outputs (Yo-Y3, Z) can swing between Vpp as 2 positive limit and Veg as a negative limit. Vop-VEE May not exceed 15 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to Vss {typically ground). DIGITAL OR ANALOG MULTIPLEXER/DEMULTIPLEXER COMMON ENABLE INPUT (ACTIVE LOW) PIN NAMES Yoa-Y 3a Independent Inputs/Outputs Yob-Y 3b Independent Inputs/Outputs Ao, A1 Address Inputs E Enable Input (Active LOW) Za: 2b Common Input/Output TRUTH TASLE INPUTS CHANNELS E | Ay | Ag | Yo-z | Yi-Z2 | Yo-Z | Y3~2 L L L ON OFF OFF OFF L L H OFF ON OFF OFF L H L OFF OFF ON OFF L H H OFF OFF OFF ON H | x | x | OFF OFF OFF OFF L = LOW Level, H = HIGH Level, X = Dont care. F4052 FUNCTIONAL LOGIC DIAGRAM Q@@@Q OOO@ Yaa |Y20 {Y1a 1 Yoa Yap [Y2b |[Y1b |] Yop BIDIRECTIONAL ANALOG SWITCHES Ao %9 A % 1G E 02 TG E 03 1G E 1-0F -4 DECODER 2b AND LEVEL CONVERTER 7 Te | } (3) T Sie Vop = Pin 16 1G Vsg = Pin 8 E Veg = Pin7 O = Pin Number LOGIC SYMBOL. 12:14 16 110610=* fiLLLELL Yoa Y1s Y2a 3a Yob Y1b 2b Y3b 10 ae Ag 9a F4052 6OlE Za 2b 13 3 Vop = Pin 16 Vsg = Pin 8 Vee = Pin7 CONNECTION DIAGRAM DIP (TOP VIEW) 1 Yoo Vo PJ ie 2) va You] 15 30] Via LJ 4 4] va zi [13 5 EI Yw Yoa [J 12 6 Yga LJ" 7 [ver Ao LJ] 10 8 (] vss Ay 9 mi NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-line Package. 13-76FAIRCHILD INTEGRATED CIRCUIT * F4052/34052 CMOS F4052/34052 OC CHARACTERISTICS: Vpp as shown, Veg = O V (See Note 1} LIMITS SYMBOL | PARAMETER Vpp = 5 V Vop = 10 V Vop = 15V uNiTs | TEMP TEST CONDITIONS MIN | TYP | MAX] MIN | TYP | MAX | MIN | TYP | MAX 95 55 35 MIN Vis = Vop 100 65 40 2 25C Note 2 125 100 65 MAX 95 55 35 MIN Vis = Vee XC 100 65 40 a 25C Note 2 125 100 65 MAX 1600 110 55 MIN 1000 125 60 2 25C Note 3 Ron ON 850 200 95 MAX Resistance 390 50 30 MIN Vig = Vpp 100 65 40 2 25C Note 2 150 110 70 MAX 90 50 30 MIN Vis = VEE XM 100 65 40 n 25C Note 2 150 110 70 MAX 1750 100 50 MIN 1000 125 60 2 25C Note 3 700 220 100 MAX a ON Resist- ARon _ | ance Between Any 10 5 2 25C Note 2 Two Channels OFF State | . 800 E=Vpp. Leakage Vss = Vpp/2 Current, All Vis = Vop F Vee Channels orrX 80 iz nA 25C |} Any xc 100 E =Vss =Vop/2 Channel XM 10 Vis = Vop F Vee OFF , Quiescent xc 20 40 8 yA MIN,25C| Vgg = Vee ' Power 700 1400 280 MAX All Inputs Common oD ' 3 Supp ly XM 2 4 0.8 yA MIN,25C | and at O V or Von Dissipation 70 140 28 MAX Notes on following page. 13-77FAIRCHILD INTEGRATED CIRCUIT * F4052/34052 CMOS F4052/34052 AC CHARACTERISTICS AND SET-UP REQUIREMENTS: Vpp as shown, Veg = 0 V. Ta = 25C (See Note 4) LIMITS SYMBOL | PARAMETER Vop = V Vop = 10.V Yop = 18 V UNITS TEST CONDITIONS MIN | TYP | MAX] MIN | TYP] MAX] MIN| TYP | MAX tPLH Propagation Delay, 20 7 4 ns_ | C_ = 15 pF, E = Vgg = Veg. tPHL Input to Output 8 4 3 ns Ap oF Vis = Vpp OF VEE tpLy Propagation Delay, 160 90 75 ns Note 6 tpHL Address to Output 200 120 90 ns tpzi Output Enabie Time 180 90 70 ns C. = 15 pF tpz2H 200 100 80 ns E or An = Vgs = VEE tpLz Output Disable Time 41000 g00 860 ns Vis = Vpp F Vee tpyz 1000 900 850 ns Note 6 teLH Propagation Delay, 25 10 6 ns Cc. = 50 pF tPHL input to Output 10 6 4 ns | E=Vgg = Veg, teLy Propagation Delay, 170 95 80 ns | Ay or Vig = Vpp oF Veg tpHL Address to Output 210 125 95 ns Note 6 tez, Output Enable Time 185 95 75 ns CL = 50 pF tezH 205 105 85 ns E or Ang = Vss = Vee tpiz Output Disable Time 1250 1130 1080 ns Vis = Yop F Vee tpHz 1240 1120 1070 ns Note 6 Distortion, Sine 0.2 0.2 0.2 % Cy = 15 pF Wave Response RL =10k2 Vgg= Vpp/2 E= Vee. Vig = Vpp/2 (sine wave) fig = 1 kHz Crosstalk Between 1 MHz | Ry =1k2,E=V_eg Any Two Channels Vis = Vpp/2 (sine wave) at -40 dB Vss = Vpp/2. 20 Logi9 (Vos/Vis) = ~40 dB OFF State 1 MHz Ry =ilka, Vss = Vpp/2 Feedthrough E=Voo Vis = Vpp72 (sine wave) 20 Logg (Vog/Vis) = -40 4B fmax | ON State 13 40 70 MHz | RL=1k92, E=Vgg Frequency Response Vig = Vpp72 (sine wave) Vgs = VYop2 20 Logi 9 (Vo5/Vig} = -3 dB NOTES: 1. Additional DC Characteristics for the Address and Enable Inputs are listed in this section under F4000 Series CMOS Family Characteristics. 2. E=Vgs, RL = 10 kQ, any channel selected and Vss = Veg OF Vpp/2. 3. Vig = 8.6V for Vop = 15V Vig = 5.1V for Vpp = 10V Vis = 1.9V for Vop = 5V Onn . Propagation Delays and Output Transition Times are graphically described in this section under F4000 Series CMOS Family Characteristics. - Vig/Vog is the voltage signal at an Input/Output Terminal (Y _/Zy). - VIN = Vop (Square Wave), Input Transition Times <20 ns and Ry = 10 k&. 13-78