HY57V283220T-I/ HY5V22F-I
4 Banks x 1M x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6/Nov. 02
DESCRIPTION
The Hynix HY57V283220T-I / HY5V22F-I is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the mem-
ory applications which require wide data I/O and high bandwidth. HY57V283220T-I / HY5V22F-I is organized as
4banks of 1,048,576x32.
HY57V283220T-I / HY5V22F-I is offering fully synchronous operation referenced to a positive edge of the clock. All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to
achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• JEDEC standard 3.3V power supply
• All device pins are compatible with LVTTL interface
• 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by DQM0,1,2 and 3
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Burst Read Single Write operation
ORDERING INFORMATION
Part No. Clock Frequency Organization Interface Package
HY57V283220(L)T-5I
HY5V22(L)F-5I 200MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-55I
HY5V22(L)F-55I 183MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-6I
HY5V22(L)F-6I 166MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-7I
HY5V22(L)F-7I 143MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-8I
HY5V22(L)F-8I 125MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-PI
HY5V22(L)F-PI 100MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
HY57V283220(L)T-SI
HY5V22(L)F-SI 100MHz 4Banks x 1Mbits
x32 LVTTL 86TSOP-II
90Ball FBGA
Rev. 0.6/Nov. 02 2
HY57V283220T-I / HY5V22F-I
PIN CONFIGURATION ( HY57V283220T-I Series)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
86pin TSOP II
400m il x 875m il
0.5mm pin pitch
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
/W E
/C A S
/R A S
/C S
A11
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
86pin TSOP II
400m il x 875m il
0.5mm pin pitch
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Rev. 0.6/Nov. 02 3
HY57V283220T-I / HY5V22F-I
Ball CONFIGURATION ( HY5V22F-ISeries)
Ball DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1 Bank Address Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3 Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4 A5 A6
A7 A8 NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CA S /W E DQ M0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
123 789456
Top View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4 A5 A6
A7 A8 NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CA S /W E DQ M0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
123 789456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4 A5 A6
A7 A8 NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CA S /W E DQ M0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4 A5 A6
A7 A8 NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CA S /W E DQ M0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4 A5 A6
A7 A8 NC
CLK CKE A9
DQM1 NC NC
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CA S /W E DQ M0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
123 789456
Rev. 0.6/Nov. 02 4
HY57V283220T-I / HY5V22F-I
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
X decoder
State Machine
A0
A1
A11
BA0
BA1
Address buffers
Address
Register
Mode Register
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Row Active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Refresh
Counter
DQ0
DQ1
DQ30
DQ31
Self Refresh Logic
& Timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
x32 Bank 3
X decoder
X decoder
Memory
Cell
Array
Y decoder
X decoder
1M x32 Bank 0
1M x32 Bank 1
1M x32 Bank 2
1M
X decoderX decoder
State Machine
A0
A1
A11
BA0
BA1
Address buffers
Address
Register
Mode Register
Row
Pre
Decoder
Column
Pre
Decoder
Column Add
Counter
Row Active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Refresh
Counter
DQ0
DQ1
DQ30
DQ31
Self Refresh Logic
& Timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
x32 Bank 3
X decoderX decoder
X decoderX decoder
Memory
Cell
Array
Y decoder
X decoder
Memory
Cell
Array
Y decoder
X decoder
1M x32 Bank 0
1M x32 Bank 1
1M x32 Bank 2
1M
Rev. 0.6/Nov. 02 5
HY57V283220T-I / HY5V22F-I
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=-40 to 85°C)
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=-40 to 85°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Parameter Symbol Rating Unit
Ambient Temperature TA-40 ~ 85 °C
Storage Temperature TSTG -55 ~ 125 °C
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD1W
Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 °C ⋅ Sec
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD, VDDQ 3.135 3.3 3.6 V 1
Input high voltage VIH 2.0 3.0 VDDQ + 0.3 V 1,2
Input low voltage VIL VSSQ - 0.3 0 0.8 V 1,3
Parameter Symbol Value Unit Note
AC input high / low level voltage VIH / VIL 2.4/0.4 V
Input timing measurement reference level voltage Vtrip 1.4 V
Input rise / fall time tR / tF 1 ns
Output timing measurement reference level Voutref 1.4 V
Output load capacitance for access time measurement CL 30 pF 1
Rev. 0.6/Nov. 02 6
HY57V283220T-I / HY5V22F-I
CAPACITANCE ( HY57V283220T-I Series) (TA=25°C, f=1MHz, VDD=3.3V)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Parameter Pin Symbol Min Max Unit
Input capacitance CLK CI1 2.5 4.0 pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI22.5 4.0 pF
Data input / output capacitance DQ0 ~ DQ31 CI/O 4.0 6.5 pF
Parameter Symbol Min. Max Unit Note
Input leakage current ILI -1 1 uA 1
Output leakage current ILO -1 1 uA 2
Output high voltage VOH 2.4 - V IOH = -2mA
Output low voltage VOL -0.4VIOL = +2mA
Vtt=1.4V
RT=500 Ω
30pF
Output
DC Output Load Circuit AC Output Load Circuit
Vtt=1.4V
RT=50 Ω
30pF
Output Z0 = 50Ω
Rev. 0.6/Nov. 02 7
HY57V283220T-I / HY5V22F-I
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V283220T(HY5V22F)-5I/55I/6I/7I/8I/PI/SI
4.HY57V283220LT(HY5V22LF)-5I/55I/6I/7I/8I/PI/SI
Parameter Symbol Test Condition
Speed
Unit Note
-5 -55 -6 -7 -8 -P S
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 120 120 110 100 100 90 90 mA 1
Precharge Standby
Current
in power down mode
IDD2P CKE ≤ VIL(max), tCK = 10ns 2
mA
IDD2PS CKE ≤ VIL(max), tCK = ∞1
Precharge Standby
Current
in non power down mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
14
mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 9
Active Standby Current
in power down mode
IDD3P CKE ≤ VIL(max), tCK = 10ns 7
mA
IDD3PS CKE ≤ VIL(max), tCK = ∞6
Active Standby Current
in non power down mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 10ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
17
mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 13
Burst Mode Operating
Current IDD4 ttCK ≥ tCK(min), IOL=0mA
All banks active
CL=3 230 220 200 180 150 130 130
mA 1
CL=2 - - - - - 130 130
Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 170 160 150 140 140 140 140 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V
2
mA
3
0.8 4
Rev. 0.6/Nov. 02 8
HY57V283220T-I / HY5V22F-I
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Parameter Symbol
-5 -55 -6 -7 -8 -P -S
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
System clock
cycle time
CAS Latency = 3 tCK3 5
1000
5.5
1000
6
1000
7
1000
8
1000
10
1000
10
1000
ns
CAS Latency = 2 tCK2 10 10 10 10 -10 10 12 ns
Clock high pulse width tCHW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1
Clock low pulse width tCLW 2 - 2.25 - 2.5 - 3 - 3 - 3 - 3 - ns 1
Access time from
clock
CAS Latency = 3 tAC3 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns
2
CAS Latency = 2tAC2 -6-6-6-6-6-6-6ns
Data-out hold time tOH 1.5 - 2 - 2 - 2 - 2 - 2 - 2 - ns 3
Data-Input setup time tDS 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1
Data-Input hold time tDH 1 - 1 - 1 - 1 - 1 - 1 - 1 - ns 1
Address setup time tAS 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1
Address hold time tAH 1-1-1-1-1-1-1-ns1
CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1
CKE hold time tCKH 1-1-1-1-1-1-1-ns1
Command setup time tCS 1.5 - 1.5 - 1.5 - 1.75 - 2 - 2 - 2 - ns 1
Command hold time tCH 1-1-1-1-1-1-1-ns1
CLK to data output in low Z-time tOLZ 1-1-1-1-1-1-1-ns
CLK to data output
in high Z-time
CAS Latency = 3 tOHZ3 - 4.5 - 5 - 5.5 - 5.5 - 6 - 6 - 6 ns
CAS Latency = 2tOHZ2 -6-6-6-6-6-6-6ns
Rev. 0.6/Nov. 02 9
HY57V283220T-I / HY5V22F-I
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter Symbol
-5 -55 -6 -7 -8 -P -S
Unit Not
e
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
RAS cycle time
Operation tRC 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns
Auto Refresh tRRC 55 - 55 - 60 - 63 - 64 - 70 - 70 - ns
RAS to CAS delay tRCD 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns
RAS active time tRAS 38.7 100
K38.7 100
K42 100
K42 100
K48 100
K50 100
K50 100
Kns
RAS precharge time tRP 15 - 16.5 - 18 - 20 - 20 - 20 - 20 - ns
RAS to RAS bank active delay tRRD 2 - 2 - 2 - 2 - 2 - 20 - 20 - CLK
CAS to CAS delay tCCD 1-1-1-1-1-1-1-CLK
Write command to data-in delay tWTL 0 - 0 - 0 - 0 - 0 - 0 - 0 - CLK
Data-in to precharge command tDPL 1 - 1 - 1 - 1 - 1 - 1 - 1 - CLK
Data-in to active command tDAL 4-4-4-4-4-4-4-CLK
DQM to data-out Hi-Z tDQZ 2 - 2 - 2 - 2 - 2 - 2 - 2 - CLK
DQM to data-in mask tDQM 0-0-0-0-0-0-0-CLK
MRS to new command tMRD 2-2-2-2-2-2-2-CLK
Precharge to
data output Hi-Z
CAS Latency = 3tPROZ33-3-3-3-3-3-3-CLK
CAS Latency = 2tPROZ22-2-2-2-2-2-2-CLK
Power down exit time tPDE 1-1-1-1-1-1-1-CLK
Self refresh exit time tSRE 1-1-1-1-1-1-1-CLK1
Refresh Time tREF -64-64-64-64-64-64-64ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.6/Nov. 02 10
HY57V283220T-I / HY5V22F-I
DEVICE OPERATING OPTION TABLE
HY5xxxxxxxxx-5I
HY5xxxxxxxxx-55I
HY5xxxxxxxxx-6I
HY5xxxxxxxxx-7I
HY5xxxxxxxxx-8I
HY5xxxxxxxxx-PI
CAS Latency tRCD tRAS tRC tRP tAC tOH
200MHz(5ns) 3CLKs 3CLKs 8CLKs 11CLKs 3CLKs 4.5ns 1.5ns
183MHz(5.5ns) 3CLKs 3CLKs 8CLKs 10CLKs 3CLKs 5ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
183MHz(5.5ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5ns 2ns
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
166MHz(6ns) 3CLKs 3CLKs 7CLKs 10CLKs 3CLKs 5.5ns 2ns
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2.5ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
143MHz(7ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 5.5ns 2ns
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
125MHz(8ns) 3CLKs 3CLKs 6CLKs 9CLKs 3CLKs 6ns 2ns
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns
83MHz(12ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns
Rev. 0.6/Nov. 02 11
HY57V283220T-I / HY5V22F-I
CAS Latency tRCD tRAS tRC tRP tAC tOH
100MHz(10ns) 3CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2ns
83MHz(12ns) 2CLKs 2CLKs 5CLKs 7CLKs 2CLKs 6ns 2.5ns
66MHz(15ns) 2CLKs 2CLKs 4CLKs 6CLKs 2CLKs 6ns 2.5ns
HY5xxxxxxxxx-SI
Rev. 0.6/Nov. 02 12
HY57V283220T-I / HY5V22F-I
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/
AP BA Note
Mode Register Set H X L L L L X OP code
No Operation H X
HXXX
XX
LHHH
Bank Active H X L L H H X RA V
Read
H X LHLHXCA
L
V
Read with Autoprecharge H
Write
HXLHLLXCA
L
V
Write with Autoprecharge H
Precharge All Banks
HXLLHLXX
HX
Precharge selected Bank LV
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Burst-Read-Single-
WRITE H X LLLLX A9 Pin High
(Other Pins OP code) 3
Self Refresh1
Entry H L L L L H X
X
Exit L H
HXXX
X
LHHH
Precharge
power down
Entry H L
HXXX
X
X
LHHH
Exit L H
HXXX
X
LHHH
Clock
Suspend
Entry H L
HXXX
X
XLVVV
Exit L H X X
Rev. 0.6/Nov. 02 13
HY57V283220T-I / HY5V22F-I
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.058(0.3960)
22.327(0.8790)
22.149(0.8720)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
1.194(0.0470)
0.991(0.0390)
Unit : mm(inch)
0.150(0.0059)
0.050(0.0020)
0.50(0.0197) 0.21(0.008)
0.18(0.007)
PACKAGE INFORMATION (HY57V283220T-I Series)
400mil 86pin Thin Small Outline Package
Rev. 0.6/Nov. 02 14
HY57V283220T-I / HY5V22F-I
PACKAGE INFORMATION (HY5V22F-I Series)
90Ball FBGA with 0.8mm of pin pitch
8.00±.108.00±.10
