EProClock® Generator for Intel Calpella Chipset
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 1 of 19
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
Features
•Intel CK505 Clock Revision 1.0 Compliant
• Hybrid Video Support - Simultaneous DOT96,
27MHz_SS and 27MHz_NSS video clocks
• PCI-Express Gen 2 Compliant
• Low power pus h-p ull type differential output buffers
• Integrated voltage regulator
• Integrate d resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.05V)
• Wireless friendly 3-bits slew rate control on
single-ended clocks.
• Differential CPU clocks with selectable frequency
• 100MHz Differential SRC clocks
• 100MHz Differential SATA clocks
• 96MHz Differential DOT clock
• 27MHz Vide o c loc k
• Buffered Reference Clock 14.318MHz
• 14.318MHz Crystal Input or Clock input
• EProClock® Programmable Technology
•I
2C support with readback capabilities
• Triangular Spread Spectrum profile for maximum
electromagnetic interferen ce (EMI) reduction
• Industrial Temperature -40oC to 85oC
• 3.3V Power supply
• 32-pin QFN package
CPU SRC SATA DOT96 REF 27M
x2 x1 x 1 x 1 x1 x2
Block Diagram Pin Configuration
** Internal 100K-ohm Pull-Down Resistor
SCLK
SDATA
REF0/ FS**
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/ PD#
32 31 30 29 28 27 26 25
VDD_DOT 124
VDD_CPU
VSS_DOT 223
CPU0
DOT96 322
CPU#0
DOT96# 421
VSS_CPU
VDD_27 520
CPU1
27_NSS 619
CPU#1
27_SS 718
VDD_CPU_IO
VSS_27 817
VDD_SRC
9 10111213141516
VSS_SATA
SRC0 / SATA
SRC0# / SATA#
VSS_SRC
SRC1
SRC1#
VDD_SRC_IO
CPU_STP#
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 2 of 19
32-QFN Pin Definitions
Pin No. Name Type Description
1 VDD_DOT PWR 3.3V Power supply for outputs and PLL
2 VSS_DOT GND Ground for outputs
3 DOT96 O, DIF Fixed true 96MHz clock output
4 DOT96# O, DIF Fixed complement 96MHz clock output
5 VDD_27 PWR 3.3V Power supply for 27MHz PLL
6 27M_NSS O,SE Non-spread 27MHz video clock output
7 27M_SS O, SE Spread 27MHz video clock output
8 VSS_27 GND Ground for 27MHz PLL
9 VSS_SATA GND Ground for outputs
10 SRC0 / SATA O, DIF 100MHz True differential serial reference clock
11 SRC0# / SATA# O, DIF 100MHz Complement differential serial reference clock
12 VSS_SRC GND Ground for PLL
13 SRC1 O, DIF 100MHz True differential serial reference clock
14 SRC1# O, DIF 100MHz Complement differential serial reference clock
15 VDD_SRC_IO PWR Scalable 3.3V to 1.05V power supply for output buffer
16 CPU_STP# I 3.3V tolerance input to stop the CPU clock
17 VDD_SRC PWR 3.3V Power supply for PLL
18 VDD_CPU_IO PWR Scalable 3.3V to 1.05V power supply for output buffer
19 CPU1# O, DIF Complement differential CPU clock output
20 CPU1 O, DIF True differential CPU clock output
21 VSS_CPU GND Ground for PLL
22 CPU0# O, DIF Complement differential CPU clock output
23 CPU0 O, DIF True differential CPU clock output
24 VDD_CPU PWR 3.3V Power supply for CPU PLL
25 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW)
26 VSS_REF GND Ground for outputs
27 XOUT O, SE 14.318MHz Crystal output
28 XIN I 14.318MHz Crystal input
29 VDD_REF PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power-down
30 REF/FS** PD, I/O 3.3V tolerant input for Graphic clock selection/fixed 14.318MHz clock output.
(Internal 100K-ohm pull-down resi stor on FS pin)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
31 SDATA I/O SMBus compatible SDATA
32 SCLK I SMBus compatible SCLOCK
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 3 of 19
EProClock® Programmable Technology
EProClock® is the world’s first non-volatile programmable
clock. The EProClock® technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock® technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Serial Dat a Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
Frequency Select Pin (FS)
FS CPU Power On SRC SATA DOT96 27MHz REF
0 133MHz Default
100MHz 100MHz 96MHz 27MHz 14.318MHz
1 100MHz
Tab le 1. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Byte Count–8 bits 20 Repeat start
28 Acknowledge from slave 27:21 Slave address–7 bits
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 4 of 19
36:29 Data byte 1–8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave–8 bits
.... Data Byte N–8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave–8 bits
.... NOT Acknowledge
.... Stop
Tab le 3. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 5 of 19
Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 HW FS CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz
6 0 RESERVED RESERVED
5 1 RESERVED RESERVED
4 0 iAMT_EN iAMT Enable
0 = Legacy Mode, 1 = iAMT Enabled
3 0 RESERVED RESERVED
2 0 SRC_Main_SEL Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
1 0 SATA_SEL Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL4
0 1 PD_Restore Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 0 PLL1_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
5 0 PLL3_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
4 0 PLL3_CFB3 CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0)
See Table 4 on page 9 for Configuration.
3 0 PLL3_CFB2
2 1 PLL3_CFB1
1 0 PLL3_CFB0
0 1 RESERVED RESERVED
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 REF_OE Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6 1 RESERVED RESERVED
5 1 RESERVED RESERVED
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 RESERVED RESERVED
5 1 RESERVED RESERVED
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 6 of 19
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Byte 4: Control Register 4
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 SATA_OE Output enable for SATA
0 = Output Disabled, 1 = Output Enabled
5 1 SRC_OE Output enable for SRC
0 = Output Disabled, 1 = Output Enabled
4 1 DOT96_OE Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
3 1 CPU1_OE Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2 1 CPU0_OE Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1 1 PLL1_SS_EN Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0 1 PLL3_SS_EN Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 REF Bit1 REF slew rate control (see Byte 13 for Sle w Rate Bit 0 a nd Bit 2 )
0 = High, 1 = Low
4 0 RESERVED RESERVED
3 0 27MHz Bit 1 27MHz slew rate control (see Byte 1 3 fo r Sl ew Ra te Bit 0 an d Bi t 2)
0 = High, 1 = Low
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 7 of 19
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Rev Code Bit 3 Revision Code Bit 3
6 1 Rev Code Bit 2 Revision Code Bit 2
5 0 Rev Code Bit 1 Revision Code Bit 1
4 0 Rev Code Bit 0 Revision Code Bit 0
3 1 Vendor ID bit 3 Vendor ID Bit 3
2 0 Vendor ID bit 2 Vendor ID Bit 2
1 0 Vendor ID bit 1 Vendor ID Bit 1
0 0 Vendor ID bit 0 Vendor ID Bit 0
Byte 8: Control Register 8
Bit @Pup Name Description
7 1 Device_ID3 RESERVED
6 0 Device_ID2 RESERVED
5 0 Device_ID1 RESERVED
4 0 Device_ID0 RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 1 27M_non-SS_OE Output enable for 27M_non-SS
0 = Output Disabled, 1 = Output Enabled
0 1 27M_SS_OE Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 1 RESERVED RESERVED
4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state
0 = All outputs tri-state, 1 = All output REF/N
3 0 TEST_MODE_ENTRY Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
2 1 I2C_VOUT<2> Amplitude configurations differential clocks
I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 0.60V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
1 0 I2C_VOUT<1>
0 1 I2C_VOUT<0>
Byte 10: Control Register 10
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 RESERVED RESERVED
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 8 of 19
Byte 13: Control Register 13
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 1 CPU1_STP_CTRL Enable CPU_STP# control of CPU1
0 = Free running, 1= Stoppable
0 1 CPU0_STP_CTRL Enable CPU_STP# control of CPU0
0 = Free running, 1= Stoppable
Byte 10: Control Register 10 (continued)
Bit @Pup Name Description
Byte 11: Control Register 11
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 1 CPU1_iAMT_EN CPU1 iAMT Clock Enabled
0 = Disabled, 1 = Enabled
1 1 PCI-e_GEN2 PCI-e_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
0 1 RESERVED RESERVED
Byte 12: Byte Count
Bit @Pup Name Description
7 0 BC7 Byte count register for block read operation.
The default value for Byte count is 15.
In order to read beyond Byte 15, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
60 BC6
50 BC5
40 BC4
31 BC3
21 BC2
11 BC1
01 BC0
Bit @Pup Name Description
7 1 REF_Bit2 Drive Strength Control - Bit[2:0], Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and
Byte 6 Bit 3 for 27MHz Slew Rate Bit 1
Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
61 REF_Bit0
5 1 27MHz_NSS_Bit2
4 1 27MHz_NSS_Bit0
3 1 27MHz_SS_Bit2
2 1 27MHz_SS_Bit0
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 9 of 19
Byte 14: Control Register 14
Table 4. Pin 6 and 7 Configu r ation Table
.
.
1 0 RESERVED RESERVED
0 0 Wireless Friendly mode Wireless Friendly Mode
0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’
1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 0 RESERVED RESERVED
5 1 RESERVED RESERVED
40 OTP_4 OTP_ID
Identification for programmed device
30 OTP_3
20 OTP_2
10 OTP_1
00 OTP_0
B1b4 B1b3 B1b2 B1b1 Pin7 Pin 8 Spread
(%)
0000 N/A N/AN/A
0001 N/A N/AN/A
0 0 1 0 27M_NSS 27M_SS -0.5%
0 0 1 1 27M_NSS 27M_SS -1%
0 1 0 0 27M_NSS 27M_SS -1.5%
0 1 0 1 27M_NSS 27M_SS -2%
0 1 1 0 27M_NSS 27M_SS -0.75V
0 1 1 1 27M_NSS 27M_SS -1.25%
1 0 0 0 27M_NSS 27M_SS -1.75%
1 0 0 1 27M_NSS 27M_SS +/-0.5%
1 0 1 0 27M_NSS 27M_SS +/-0.75%
1011 N/A N/AN/A
1100 N/A N/AN/A
1101 N/A N/AN/A
1110 N/A N/AN/A
1111 N/A N/AN/A
Table 5. Output Driver Status during CPU_STP#
CPU_STP# Asserted SMBus OE Disabled
Single-ended Clocks Stoppable Running Driven low
Non stoppable Running
Differential Clocks Stoppable Clock driven high Clock driven low
Clock# driven low
Non stoppable Running
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 10 of 19
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10 s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300 s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 2
is an example showing the relationship of clocks coming up.
Table 6. Output Driver Status
All Single-ended Clocks All Differential Clocks
w/o Strap w/ Strap Clock Clock#
PD# = 0 (Power down) Low Hi-z Low Low
Figure 1. Power Down Assertion Timing Waveform
Figure 2. Power Do wn Deassertion Timing Waveform
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 11 of 19
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
Figure 3. CKPWRGD Timing Diagram
CPU_STP#
CPUT
CPUC
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 12 of 19
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD_3.3V Main Supply Voltage Functional – 4.6 V
VDD_IO IO Supply Voltage Functional 4.6 V
VIN Input Voltage Relative to VSS –0.5 4.6 VDC
TSTemperature, Storage Non-functional –65 150 °C
TATemperature, Operating
Ambient (Commercial)
Functional 0 85 °C
TATemperature, Operating
Ambient (Industrial)
Functional -40 85 °C
TJTemperature, Junction Functional – 150 °C
ØJC Dissipation, Junction to Case Functional – 20 °C/
W
ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/
W
ESDHBM ESD Protection (Human Body
Model)
JEDEC (JESD 51) 2000 – V
UL-94 Flammability Rating JEDEC (JESD 22 - A114) V–0
MSL Moisture Sensitivity Level UL (Class) 1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VDD core 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
VIH 3.3V Input High Voltage (SE) 2.0 VDD + 0.3 V
VIL 3.3V Input Low Voltage (SE) VSS – 0.3 0.8 V
VIHI2C Input High Voltage SDATA, SCLK 2.2 – V
VILI2C Input Low Voltage SDATA, SCLK – 1.0 V
VIH_FS FS Input High Voltage 0.7 VDD+0.3 V
VIL_FS FS Input Low Voltage VSS – 0.3 0.35 V
IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD –5A
IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A
VOH 3.3V Output High Voltage (SE) IOH = –1 mA 2.4 – V
VOL 3.3V Output Low Voltage (SE) IOL = 1 mA – 0.4 V
VDD IO Low Voltage IO Supply Voltage 1 3.465 V
IOZ High-impedance Output
Current
–10 10 A
CIN Input Pin Capacitance 1.5 5 pF
COUT Output Pin Capacitance 6pF
LIN Pin Inductance – 7 nH
VXIH Xin High Voltage 0.7VDD VDD V
VXIL Xin Low Voltage 0 0.3VDD V
IDD_PD Power Down Current – 1 mA
IDD_3.3V Dynamic Supply Current All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–65mA
IDD_VDD_IO Dynamic Supply Current All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–25mA
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 13 of 19
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
Crystal
TDC XIN Duty Cycle The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5 52.5 %
TPERIOD XIN Period When XIN is driven from an external
clock source
69.841 71.0 ns
TR/TFXIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD –10.0ns
TCCJ XIN Cycle to Cycle Jitter As an average over 1-s duration – 500 ps
LACC Long-term Accuracy Measured at VDD/2 differential – 250 ppm
Clock Input
TDC CLKIN Duty Cycle Measured at VDD/2 47 53 %
TR/TFCLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns
TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps
TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps
VIL Input Low Voltage XIN / CLKIN pin – 0.8 V
VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V
IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN <0.8 – 20 uA
IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA
CPU at 0.7V
TDC CPUT and CPUC Duty Cycle Measured at 0V differential 45 55 %
TPERIOD 100 MHz CPUT and CPUC Period Measured at 0V differential at 0.1s 9.99900 10.00100 ns
TPERIOD 133 MHz CPUT and CPUC Period Measured at 0V differential at 0.1s 7.49925 7.50075 ns
TPERIODSS 100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns
TPERIODSS 133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s 7.51804 7.51955 ns
TPERIODAbs 100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock 9.91400 10.0860 ns
TPERIODAbs 133 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock 7.41425 7.58575 ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock 9.914063 10.1362 ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock 7.41430 7.62340 ns
TCCJ CPU Cycle to Cycle Jitter Measured at 0V differential – 85 ps
Skew CPU0 to CPU1 skew Measured at 0V differential – 100 ps
LACC Long-term Accuracy Measured at 0V differential – 100 ppm
TR / TFCPU Rising/Falling Slew rate Measured differentially from ±150 mV 2.5 8 V/ns
TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 %
VHIGH Voltage High 1.15 V
VLOW Voltage Low –0.3 – V
VOX Crossing Point Voltage at 0.7V Swing 300 550 mV
SRC at 0.7V
TDC SRC Duty Cycle Measured at 0V differential 45 55 %
TPERIOD 100 MHz SRC Period Measured at 0V differential at 0.1s 9.99900 10.0010 ns
TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential at 0.1s 10.02406 10.02607 ns
TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential at 1 clock 9.87400 10.1260 ns
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Measured at 0V differential at 1 clock 9.87406 10.1762 ns
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 14 of 19
TSKEW(window) Any SRC Clock Skew from the earliest
bank to the latest bank
Measured at 0V differential – 3.0 ns
TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 125 ps
RMSGEN1 Output PCIe* Gen1 REFCLK phase
jitter
BER = 1E-12 (including PLL BW 8 - 16
MHz, ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz) 0108ps
RMSGEN2 Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz 03.0ps
RMSGEN2 Output PCIe* Gen2 REFCLK phase
jitter
Includes PLL BW 8 - 16 MHz, Jitter
Peaking = 3dB, ζ = 0.54, Td=10 ns),
Low Band, F < 1.5MHz 03.1ps
LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm
TR / TFSRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns
TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 %
VHIGH Voltage High 1.15 V
VLOW Voltage Low –0.3 – V
VOX Crossing Point Voltage at 0.7V Swing 300 550 mV
DOT96 at 0.7V
TDC DOT96 Duty Cycle Measured at 0V differential 45 55 %
TPERIOD DOT96 Period Measured at 0V differential at 0.1s 10.4156 10.4177 ns
TPERIODAbs DOT96 Absolute Period Measured at 0V differential at 0.1s 10.1656 10.6677 ns
TCCJ DOT96 Cycle to Cycle Jitter Measured at 0V differential at 1 clock – 250 ps
LACC DOT96 Long Term Accuracy Measured at 0V differential at 1 clock – 100 ppm
TR / TFDOT96 Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns
TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 %
VHIGH Voltage High 1.15 V
VLOW Voltage Low –0.3 – V
VOX Crossing Point Voltage at 0.7V Swing 300 550 mV
27M_NSS/27_SS at 3.3V
TDC Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread 27M Period Measurement at 1.5V 37.03594 37.03813 ns
Spread Enabled 27M Period Measurement at 1.5V 37.12986 37.13172 ns
TR / TFRising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 300 ps
LACC 27_M Long Term Accuracy Measured at crossing point VOX –50ppm
REF
TDC REF Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD REF Period Measurement at 1.5V 69.82033 69.86224 ns
TPERIODAbs REF Absolute Period Measurement at 1.5V 68.83429 70.84826 ns
THIGH REF High time Measurement at 2V 29.97543 38.46654 ns
TLOW REF Low time Measurement at 0.8V 29.57543 38.26654 ns
TR / TFREF Rising and Falling Edge Rate Measured between 0.8V and 2.0V 1.0 4.0 V/ns
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 15 of 19
TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps
LACC Long Term Accuracy Measurement at 1.5V – 100 ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up – 1.8 ms
TSS Stopclock Set-up Time 10.0 – ns
AC Electrical Specifications (continued)
Parameter Description Condition Min. Max. Unit
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 16 of 19
Test and Measurement Set-up
For Reference Clock
The following diagram shows the test load configurations for
the single-ended REF output signal.
For Differential Clock Signals
This diagram shows the test load configuration for the differential clock signals
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 17 of 19
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 18 of 19
Ordering Information
Part Number Package Type Product Flow
Lead-free
SL28748ELC 32-pin QFN Commercial, 0 to 85C
SL28748ELCT 32-pin QFN–Tape and Reel Commercial, 0 to 85C
SL28748ELI 32-pin QFN Industrial, -40 to 85C
SL28748ELIT 32-pin QFN–Tape and Reel Industrial, -40 to 85C
This device is Pb free and RoHS compliant.
Package Diagrams 32-Lead QFN 5x 5mm (Saw Version )
SL 28 748 EL C - T
Temperature Designator
Package Designator
L : QFN
Revision Number
A = 1st Silicon
Generic Part Number
Designated Family Number
Company Initials
Packaging Designator for Tape and Reel
SL28748
DOC#: SP-AP-0017 (Rev. AA) Page 19 of 19
Document History Page
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon
Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of
information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or param-
eters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental
damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or
for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Silicon Laboratories harmless against all claims and damages.
Document Title: SL28748 PC EProClock® Generator for Intel Calpella Chipset
DOC#: SP-AP-0017 (Rev. AA)
REV. ECR# Issue
Date Orig. of
Change Description of Ch ange
1.0 10/09/08 JMA Initial Release
1.1 10/23/08 JMA 1. Changed operating temperature to 0-85C
2. Re-aligned ordering part number description
1.2 1/27/09 JMA 1. Updated Rev. ID
2. Updated definition of Byte 6 bit 5 and 3
3. Updated Byte 13 and single-ended slew rate table
4. Updated Byte 14
5. Updated Feature description
6. Added less than symbol in power consumption value
7. Updated ordering part number
8. Changed package information
9. Changed Wireless Friendly Mode to 111
1.3 3/16/09 JMA 1. Added PC EProClock® Programmed Technology in Feature section
2. Updated Block Diagram
3. Updated 27MHz slew rate measurement window
4. Updated power consumption
1.4 3/25/09 JMA 1. Updated Package information removed punch version with saw version
2. Updated Period at 100MHz for CPU clocks
3. Updated Revision ID
4. Added Power down Spec
5. Added PC EProClock® Technology description
6. Added CPU Skew
1.5 6/03/09 JMA 1. Updated Revision ID
2. Removed 3-bit differential slew rate
3. Removed 0.1s from CPU duty cycle spec
4. Changed SATA PLL2 to PLL4
5. Updated IDD measurement condition
1.6 10/16/09 JMA 1. Removed the word “Preliminary”
2. Added Note in package diagram
3. Updated text content
4. Added information on trace length in Figure 8
5. Removed CPU Driven Figures
6. Edited CK_PWRGD to CKPWRGD
AA 1456 05/18/10 JMA 1. Updated MIL-STD to Jedec Standard
2. Updated VDD_IO spec to 4.6V maximum value
3. Combined Commercial and Industrial
4. Changed Revision to be ISO compliant
5. Removed refernce to Application Note#25.
6. Added feature for clock input
7. Removed skew data on REF clock