FEBRUARY 2009
DSC-5310/07
1
©2007 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆256K x 36, 512K x 18 memory configurations
◆◆
◆◆
◆Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
◆◆
◆◆
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O supply (VDDQ)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V67603/7803 are high-speed SRAMs organized as
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67603/Z
IDT71V67803/Z
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67603/7803 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
A
0
-A
18
Address Inputs Input Synchronous
CE Chip Enable Input Synchronous
CS
0
, CS
1
Chip Sele cts Input Sy nchronous
OE Output Enable Input Asynchronous
GW Global Write Enable Input Synchronous
BWE By te Write E nab le Input Sy nc hro nous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV Burst Address Advance Input Synchronous
ADSC Ad dress Status (Cache Co ntroller) Input Sy nc hro nous
ADSP Address Status (Processor) Input Synchronous
LBO Linear / Interleaved Burst Order Input DC
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/O Sy nc hro no us
V
DD
, V
DDQ
Co re Po we r, I/O Po we r Sup p l y N/A
V
SS
Ground Supply N/A
5310 tbl 01
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
6.42
2
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Pin Function I/O Active Description
A
0
-A
18
Address Inputs I N/A Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK and ADSC Low o r ADSP Lo w and CE Lo w.
ADSC Address Status
(Cache Co ntrolle r) I LOW Synchronous Address Status from Cache Controller. ADSC is an acti v e LOW inp ut that is
used to load the address registers with new addresses.
ADSP Address Status
(Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance I LOW Synchronous Address Advance. ADV i s an ac tiv e LOW inp ut that is use d to ad vanc e the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW
1
-BW
4
Individual Byte
Write E nab le s I LOW Synchronous byte write enables. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc
.
Any active byte write causes all outputs to be disabled.
CE Chip Enable I LOW Sync hrono us chip enab le . CE i s us e d wi th CS
0
and CS
1
to enab le the IDT71V67603/7803.
CE also gates ADSP.
CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS
0
Chip Select 0 I HIGH Synchronous activ e HIGH chip select. CS
0
is use d with CE and CS
1
to enable the chip .
CS
1
Chip Select 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to enable the chip.
GW Global Write
Enable I LOW Synchronous global write enable. This input will write all fo ur 9-bit data bytes when LOW
on the ris ing edge of CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output I/O N/A Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Line ar burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE Outp ut Enab le I LOW As ync hro no us o utp ut enable. Whe n OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Po we r Supply N/A N/A 3.3V I/O Supply.
V
SS
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
ZZ Sleep Mode I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67603/7803 to its lowest p ower consumption level. Data retention is guaranteed in
Sleep Mode.
5 310 t b l 02
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A
0–
A
17/18
ADDRESS
REGISTER
CLR
A1*
A0*
18/19
2
18/19
A
2
–A
18
256K x 36/
512K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BWE
LBO
I/O
0
–I/O
31
I/O
P1
–I/O
P4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
OUTPUT
REGISTER
DQ
DQ
Enable
Register
Enable
Delay
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
5301 drw 01
ZZ
Powerdown
,
6.42
4
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100 Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTE:
1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial Unit
V
TERM
(2)
Terminal Vo ltage with
Re sp e c t to GND -0.5 to +4.6 V
V
TERM
(3,6)
Terminal Vo ltage with
Re sp e c t to GND -0.5 to V
DD
V
V
TERM
(4,6)
Terminal Vo ltage with
Re sp e c t to GND -0. 5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Vo ltage with
Re sp e c t to GND -0.5 to V
DDQ
+0.5 V
T
A
(7)
Operating Temperature -0 to +70
o
C
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -55 to +125
o
C
P
T
Po we r Di s si p atio n 2. 0 W
I
OUT
DC Output Current 50 mA
5310 t b l 03
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0°C to +70° C 0V 3.3V± 5% 3.3V±5%
Industrial -40°C to +85° C 0V 3.3V± 5% 3.3V± 5%
5310 tbl 04
Symbol Parameter Min. Typ. Max. Uni
t
V
DD
Core Sup ply Vo ltag e 3.135 3.3 3.465 V
V
DDQ
I/ O S up p l y Vo ltag e 3. 135 3. 3 3 .465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
DDQ
+0.3 V
V
IL
Inp ut Lo w Vo ltag e -0.3
(1)
____
0.8 V
5310 t bl 05
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap acitance V
IN
= 3dV 5 pF
C
I/O
I/O Capac itanc e V
OUT
= 3dV 7 pF
5310 t bl 07
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap acitanc e V
IN
= 3dV 7 p F
C
I/O
I/ O Capac itanc e V
OUT
= 3dV 7 pF
5310 tbl 07a
NOTE:
1. TA is the "instant on" case temperature.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap acitance V
IN
= 3dV 7 p F
C
I/O
I/O Capac itance V
OUT
= 3dV 7 p F
5310 t bl 07b
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
6.42
5
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 36, 100-Pin TQFP
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
17
NC
NC
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5301 drw 02
V
DD
/NC
(1)
I/O
15
I/O
P3
NC
I/O
P4
A
15
A
16
I/O
P1
NC
I/O
P2
ZZ
(2)
,
Top View
6.42
6
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 512K x 18, 100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5310 drw 03
V
DD
/NC
(1)
NC
NC
NC
NC
A
16
A
17
NC
NC
A
10
ZZ(2)
,
A
18
Top View
NOTES:
1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
7
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 512K x 18, 119 BGA
Pin Configuration – 256K x 36, 119 BGA
Top View
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
4. On future 18M device CS0 will be removed, B2 will be used for address expansion.
1234567
AV
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
BNC CS
0
(4)
A
3
ADSC A
9
A
17
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
CE V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
ADV BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
GW V
SS
I/O
9
I/O
8
JV
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
BWE V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
A
13
TNC NC A
10
A
11
A
14
NC ZZ
UV
DDQ
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
DNU
(3)
V
DDQ
5310 drw 04
V
DD
/NC
NC
NC
,
(1)
(2)
1234567
AV
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
BNC CS
0
(4)
A
3
ADSC A
9
A
18
NC
CA
7
A
2
V
DD
A
13
A
17
NC
DI/O
8
NC V
SS
NC V
SS
I/O
P1
NC
ENC I/O
9
V
SS
CE V
SS
NC I/O
7
FV
DDQ
NC V
SS
OE V
SS
I/O
6
V
DDQ
GNC I/O
10
BW
2
ADV NC I/O
5
HI/O
11
NC V
SS
GW V
SS
I/O
4
NC
JV
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
KNC I/O
12
V
SS
CLK V
SS
NC I/O
3
LI/O
13
NC NC BW
1
I/O
2
NC
MV
DDQ
I/O
14
V
SS
BWE V
SS
NC V
DDQ
NI/O
15
NC V
SS
A
1
V
SS
I/O
1
NC
PNC I/O
P2
V
SS
A
0
V
SS
NC I/O
0
RNC A
5
LBO V
DD
A
12
TNC A
10
A
15
NC A
14
A
11
ZZ
UV
DDQ
DNU(3) DNU(3) DNU(3) DNU(3) DNU(3) V
DDQ
5310 drw 05
NC
V
DD
/NC NC
V
SS
V
SS
,
(1)
(2)
6.42
8
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
1234567891011
ANC
(3)
A
7
CE BW
3
BW
2
CS
1
BWE ADSC ADV A
8
NC
BNC A
6
CS
0
BW
4
BW
1
CLK GW OE ADSP A
9
NC
(3)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
DD
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(2)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS
NC NC
(3)
NC V
SS
V
DDQ
NC I/O
P1
PNCNC
(3)
A
5
A
2
DNU
(4)
A
1
DNU
(4)
A
10
A
13
A
14
A
17
RLBO NC
(3)
A
4
A
3
DNU
(4)
A
0
DNU
(4)
A
11
A
12
A
15
A
16
5310 tb l 17a
Pin Configuration – 512K x 18, 165 fBGA
Pin Configuration – 256K x 36, 165 fBGA
1234567891011
ANC
(3)
A
7
CE BW
2
NC CS
1
BWE ADSC ADV A
8
A
10
BNC A
6
CS
0
NC BW
1
CLK GW OE ADSP A
9
NC
(3)
CNC NCV
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P1
DNC I/O
8
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
7
ENC I/O
9
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
6
FNCI/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
5
GNC I/O
11
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
4
HV
DD
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(2)
JI/O
12
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
KI/O
13
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
NC
LI/O
14
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
NC
MI/O
15
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
NC
NI/O
P2
NC V
DDQ
V
SS
NC NC
(3)
NC V
SS
V
DDQ
NC NC
PNC NC
(3)
A
5
A
2
DNU
(4)
A
1
DNU
(4)
A
11
A
14
A
15
A
18
RLBO NC
(3)
A
4
A
3
DNU
(4)
A
0
DNU
(4)
A
12
A
13
A
16
A
17
5310 tb l 17b
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. H11 can be left unconnected and the device will always remain in active mode.
3. Pin N6, B11, A1, R2 and P2 are reserved for 18M, 36M, 72M, and 144M and 288M respectively.
4. DNU= Do not use; these signals can either be left unconnected or tied to Vss.
6.42
9
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Symbol Parameter Test Conditi ons Min. Max. Unit
|I
LI
| Inp ut Leakag e Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|ZZ and LBO Inp ut Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Le ak age Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut Hig h Voltag e I
OH
= -8mA, V
DD
= Min. 2.4
___
V
5310 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
5310 d rw 06
,
1
2
3
4
20 30 50 100 200
∆t
CD
(Typical, ns)
Capacitance (pF)
80
5
6
5310 drw 07
,
S ym bol P arame ter Test Cond iti ons 166MHz 150MHz 133MHz Unit
Co m'l o nly Co m'l Ind Com' l Ind
I
DD
Operating Power Supply
Current Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
340 305 325 260 280 mA
I
SB1
CMOS Stand by P owe r
Sup ply Current De vice Deselected , Outp uts Ope n, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
50 50 70 50 70 mA
I
SB2
Clock Running Po wer
Sup ply Current De vice Deselected , Outp uts Ope n, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
160 155 175 150 170 mA
I
ZZ
Full Sleep Mode Supply
Current ZZ > V
HD,
V
DD
= Max. 50 50 70 50 70 mA
5310 tb l 09
Inp ut Pul s e Le v e ls
Inp ut Ris e /F al l Ti me s
Inp ut Ti ming Re fe re nc e Le v e ls
Output Timing Refe renc e Leve ls
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5310 t b l 10
6.42
10
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,3)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used CE CS
0
CS
1
ADSP ADSC ADV GW BWE BWxOE
(2) CLK I/O
De s e le c te d Cy cle, P o we r Do wn No ne H X X X L X X X X X - HI-Z
De s e le c te d Cy cle, P o we r Do wn No ne L X H L X X X X X X - HI-Z
De s e le c te d Cy cle, P o we r Do wn No ne L L X L X X X X X X - HI-Z
De s e le c te d Cy cle, P o we r Do wn No ne L X H X L X X X X X - HI-Z
De s e le c te d Cy cle, P o we r Do wn No ne L L X X L X X X X X - HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L - D
OUT
Read Cycle, Begin Burst External L H L L X X X X X H - HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Re ad Cycle , Continue Burst Ne xt X X X H H L H H X L - D
OUT
Re ad Cycle , Continue Burst Ne xt X X X H H L H H X H - HI-Z
Re ad Cycle , Continue Burst Ne xt X X X H H L H X H L - D
OUT
Re ad Cycle , Continue Burst Ne xt X X X H H L H X H H - HI-Z
Re ad Cycle , Continue Burst Ne xt H X X X H L H H X L - D
OUT
Re ad Cycle , Continue Burst Ne xt H X X X H L H H X H - HI-Z
Re ad Cycle , Continue Burst Ne xt H X X X H L H X H L - D
OUT
Re ad Cycle , Continue Burst Ne xt H X X X H L H X H H - HI-Z
Write Cycle , Continue Burst Next X X X H H L H L L X - D
IN
Write Cycle , Continue Burst Next X X X H H L L X X X - D
IN
Write Cycle , Continue Burst Next H X X X H L H L L X - D
IN
Write Cycle , Continue Burst Next H X X X H L L X X X - D
IN
Re ad Cycle , Sus pe nd B urst Current X X X H H H H H X L - D
OUT
Re ad Cycle , Sus pe nd B urst Current X X X H H H H H X H - HI-Z
Re ad Cycle , Sus pe nd B urst Current X X X H H H H X H L - D
OUT
Re ad Cycle , Sus pe nd B urst Current X X X H H H H X H H - HI-Z
Re ad Cycle , Sus pe nd B urst Current H X X X H H H H X L - D
OUT
Re ad Cycle , Sus pe nd B urst Current H X X X H H H H X H - HI-Z
Re ad Cycle , Sus pe nd B urst Current H X X X H H H X H L - D
OUT
Re ad Cycle , Sus pe nd B urst Current H X X X H H H X H H - HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspend Burst Current X X X H H H L X X X - D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X - D
IN
5310 tbl 11
6.42
11
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table(1, 2)
Asynchronous Truth Table(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V67803.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes L X X X X X
Write all Bytes H L L L L L
Write B y te 1
(3)
HLLHHH
Write B y te 2
(3)
HLHLHH
Write B y te 3
(3)
HLHHLH
Write B y te 4
(3)
HLHHHL
5310 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5310 tbl 15
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
5310 tbl 14
Operation
(2)
OE ZZ I/O Status Power
Re ad L L Data Out Active
Read H L High-Z Active
Write X L Hig h-Z – Data In Ac ti ve
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sle ep
5310 tbl 13
6.42
12
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
166MHz 150MHz 133MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CYC
Clo ck Cycle Time 6 ____ 6.7 ____ 7.5 ____ ns
t
CH
(1)
Clock High Pulse Width 2.4 ____ 2.6 ____ 3____ ns
t
CL
(1)
Clock Low Pulse Width 2.4 ____ 2.6 ____ 3____ ns
Outpu t Parameters
t
CD
Clock High to Valid Data ____ 3.5 ____ 3.8 ____ 4.2 ns
t
CDC
Clock High to Data Change 1.5 ____ 1.5 ____ 1.5 ____ ns
t
CLZ
(2)
Clock High to Output Active 0 ____ 0____ 0____ ns
t
CHZ
(2)
Cl o ck Hig h to Data Hi g h-Z 1. 5 3 .5 1. 5 3.8 1. 5 4. 2 ns
t
OE
Output Enable Access Time ____ 3.5 ____ 3.8 ____ 4.2 ns
t
OLZ
(2)
Outp u t Enab le Lo w to O utp ut Ac ti ve 0 ____ 0____ 0____ ns
t
OHZ
(2)
Outp ut Enab l e Hi g h to Outp ut Hig h-Z ____ 3.5 ____ 3.8 ____ 4.2 ns
Set Up Times
t
SA
Address Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SS
Address Status Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SD
Da ta In S e tu p Ti m e 1 . 5 ____ 1.5 ____ 1.5 ____ ns
t
SW
Write S e tup Time 1. 5 ____ 1.5 ____ 1.5 ____ ns
t
SAV
Address Advance Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
t
SC
Chip Enable/Select Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns
Hold Times
t
HA
Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HS
Address Status Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HD
Data In Hold Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HW
Write Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HAV
Address Advance Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HC
Chip Enable/Select Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
S lee p Mode an d Config uration Param eters
t
ZZPW
ZZ Pulse Width 100 ____ 100 ____ 100 ____ ns
t
ZZR
(3)
ZZ Recovery Time 100 ____ 100 ____ 100 ____ ns
t
CFG
(4)
Config uration Set-up Time 24 ____ 27 ____ 30 ____ ns
5 310 t bl 16
6.42
13
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in
the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Pipelined Read Cycle(1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O3(Ay)O2(Ay)
O2(Ay)
t
CLZ
ADV
CE,CS
1
(Note3)
Pipelined
ReadBurstPipelinedRead
Output
Disabled
AxAy
t
SS
O1(Ay)
(Burstwrapsaround
toitsinitialstate)
O4(Ay)
5310drw08
ADSP
ADVHIGHsuspends
burst
,
6.42
14
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address
Az; O2 (Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state
of the LBO input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
CLK
ADSP
ADDRESS
GW
ADV
OE
DAT
A
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DAT
A
IN
(2)
t
OE
O1(Az)
O1(Az)
SingleReadPipelinedBurstRead
Pipelined
Write
O1(Ax)
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)
5310drw09
t
CD
,
6.42
15
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2 . O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing W av eform of Write Cyc le No. 1 — GW Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DAT
A
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O3(Aw)O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note3)
I2(Az)
BurstWrite
BurstReadBurstWrite
Single
Write
I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVHIGHsuspendsburst)
I1(Ay)
GWisignoredwhenADSPinitiatesacycleandissampledonthenextclockrisingedge
t
SC
5310drw10
,
6.42
16
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa vef orm of Write Cyc le No. 2 — Byte Controlled(1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DAT
A
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)
(ADVsuspendsburst)
I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
t
HW
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
BWxisignoredwhenADSPinitiatesacycleandissampledonnextclockrisingedge
I3(Az)
O3(Aw)
5310drw11
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2 . O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input
from the external address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the
sequence defined by the state of the LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
17
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
SingleReadSnoozeMode
tZZPW
5310drw12
O1(Ax)
Ax
(Note4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
18
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
CLK
ADSP
GW,BWE,BWx
CE, CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
5310 drw 14
,
Non-Burst Read Cycle Timing Waveform
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
Non-Burs t Write Cy cle Timing W av eform
CLK
ADSP
GW
CE, CS1
CS0
ADDRESS
ADSC
DATAIN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
5310 drw 15
,
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19
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
20
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
21
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
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IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
100-pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array(BGA)
165 fine Pitch Ball Grid Array
S
Power
X
Speed
XX
Package
PF
BG
BQ
XXX
166*
150
133 Frequency in Megahertz
5310 drw 13
Device
Type
71V67603
71V67803 256K x 36 Pipelined Burst Synchronous SRAM
512K x 18 Pipelined Burst Synchronous SRAM
,
X
Process/Temperature Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
* Industrial temperature not available on 166MHz devices
X
GRestricted hazardous substance device
Z
Z Current generation die step optional
Blank First generation or current die step
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23
IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
12/31/99 Created datasheet from 71V676 and 71V678 datasheets.
I/O voltage and speed grade offerings have been split into separate part numbers.
See the following datasheets for:
3.3V I/O, 133–166MHz 71V67603
2.5V I/O, 133–166MHz 71V67602
3.3V I/O, 183–200MHz 71V67613
2.5V I/O, 183–200MHz 71V67612
04/26/00 Pg. 4 Add capacitance for BGA package; Insert clarification note to Absolute Max Ratings and Recommended
Operating Temperature tables.
Pg. 7 Replace Pin U6 with TRST pin in BGA pin configuration; Add pin description note in pinout
Pg. 18 Inserted 100 pin TQFP Package Diagram Outline
05/24/00 Pg. 1,8,4,21 Add new package offering, 13 x 15 fBGA
22
Pg. 5,6,7,8 Correct note 2 in BGA and TQFP pinouts
Pg. 20 Correction in the119BGA Package Diagram Outline
07/12/00 Pg. 5,6 Remove note from TQFP pinout
Pg. 7 Add/Remove reference note from BG119 pinout
Pg. 9 Remove note from BQ165 pinout
Pg. 20 Update BG119 Package Diagram Outline dimensions
12/18/00 Pg. 9 Updated ISB2 levels for F=133-166MHz
10/29/01 Pg. 1,2 Remove 166MHz and JTAG pins
Pg. 7,8 Updated pins U2-U6 to DNU and P5,P7,R5 & R7 to DNU
Pg. 9 Remove 166MHz and raise range by 10mA on 150Mhz and 133MHz
Pg. 12,22 Remove 166MHz
10/22/02 Pg.1-22 Changed datasheet from Advanced to final release.
Pg. 4,9,12, Added I temp to datasheet.
22
11/19/02 Pg.1,9,12,22 Added 166MHz to datasheet.
04/15 /03 Pg.4 Updated165fBGA table from TBD to 7.
09/30/04 Pg.7 Updated 119BGA pin configurations-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Pg.22 Added "Restricted hazardous substance device" to ordering information.
02/21/07 Pg.22 Added Z generation die step to ordering information.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
