M93S66, M93S56 M93S46 4Kbit, 2Kbit and 1Kbit (16-bit wide) MICROWIRE Serial Access EEPROM with Block Protection FEATURES SUMMARY Industry Standard MICROWIRE Bus Single Supply Voltage: - 4.5 to 5.5V for M93Sx6 - 2.5 to 5.5V for M93Sx6-W - 1.8 to 5.5V for M93Sx6-R Single Organization: by Word (x16) Programming Instructions that work on: Word or Entire Memory Self-timed Programming Cycle with AutoErase User Defined Write Protected Area Page Write Mode (4 words) Ready/Busy Signal During Programming Speed: - 1MHz Clock Rate, 10ms Write Time (Current product, identified by process identification letter F or M) - 2MHz Clock Rate, 5ms Write Time (New Product, identified by process identification letter W or G) Sequential Read Operation Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention Figure 1. Packages 8 1 PDIP8 (BN) 8 1 SO8 (MN) 150 mil width TSSOP8 (DS) 3x3mm body size TSSOP8 (DW) 169 mil width April 2004 1/34 M93S66, M93S56, M93S46 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 POWER-ON DATA PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Instruction Set for the M93S46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Instruction Set for the M93S66, M93S56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. READ, WRITE, WEN and WDS Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. PAWRITE and WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. PREAD, PRWRITE and PREN Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. PRCLEAR and PRDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE PROTECTION AND THE PROTECTION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection Register Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Table 6. Table 7. Table 8. Table 9. 2/34 Operating Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions (M93Sx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Conditions (M93Sx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Conditions (M93Sx6-W and M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . 17 M93S66, M93S56, M93S46 Figure 9. AC Testing Input Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. DC Characteristics (M93Sx6, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. DC Characteristics (M93Sx6, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. DC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. DC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. DC Characteristics (M93Sx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. AC Characteristics (M93Sx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. AC Characteristics (M93Sx6-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. AC Characteristics (M93Sx6-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10.Synchronous Timing (Start and Op-Code Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 13.PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 28 Table 20. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 28 Figure 14.SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 29 Table 21. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 29 Figure 15.TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline 30 Table 22. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data 30 Figure 16.TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 31 Table 23. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 31 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 32 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3/34 M93S66, M93S56, M93S46 SUMMARY DESCRIPTION This specification covers a range of 4K, 2K, 1K bit serial Electrically Erasable Programmable Memory (EEPROM) products (respectively for M93S66, M93S56, M93S46). In this text, these products are collectively referred to as M93Sx6. Figure 2. Logic Diagram VCC D C S Q M93Sx6 PRE W VSS AI02020 Table 1. Signal Names S Chip Select Input D Serial Data Input Q Serial Data Output C Serial Clock PRE Protection Register Enable W Write Enable VCC Supply Voltage VSS Ground The M93Sx6 is accessed through a serial input (D) and output (Q) using the MICROWIRE bus protocol. The memory is divided into 256, 128, 64 x16 bit words (respectively for M93S66, M93S56, M93S46). The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write, Write All 4/34 and instructions used to set the memory protection. These are summarized in Table 2. and Table 3.). A Read Data from Memory (READ) instruction loads the address of the first word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the M93S66), or continuously as the address counter automatically rolls over to 00h when the highest address is reached. Within the time required by a programming cycle (tW), up to 4 words may be written with help of the Page Write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the Write All instruction. Within the memory, a user defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protection Register, located outside of the memory array. As a final protection step, data may be permanently protected by programming a One Time Programming bit (OTP bit) which locks the Protection Register content. Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driven High. Figure 3. DIP, SO and TSSOP Connections M93Sx6 S C D Q 1 2 3 4 8 7 6 5 VCC PRE W VSS AI02021 Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1. M93S66, M93S56, M93S46 An internal Power-on Data Protection mechanism in the M93Sx6 inhibits the device when the supply is too low. POWER-ON DATA PROTECTION To prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming circuitry, and sets the device in the Write Disable mode. - At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supply voltage reaches the operating value VCC specified in Table 5. to Table 6.. - When VCC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incoming instructions. For the M93Sx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Sx6W (3V range) and M93Sx6-R (2V range) the POR threshold voltage is around 1.5V. INSTRUCTIONS The instruction set of the M93Sx6 devices contains seven instructions, as summarized in Table 2. to Table 3.. Each instruction consists of the following parts, as shown in Figure 4.: Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock (C) being held Low. A start bit, which is the first `1' read on Serial Data Input (D) during the rising edge of Serial Clock (C). Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code). The address bits of the byte or word that is to be accessed. For the M93S46, the address is made up of 6 bits (see Table 2.). For the M93S56 and M93S66, the address is made up of 8 bits (see Table 3.). The M93Sx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in Table 16. to Table 19.. 5/34 M93S66, M93S56, M93S46 Table 2. Instruction Set for the M93S46 Required Clock Cycles Additional Comments 25 Write is executed if the address is not inside the Protected area Description W PRE Start bit OpCode Address1 Data READ Read Data from Memory X 0 1 10 A5-A0 Q15-Q0 WRITE Write Data to Memory 1 0 1 01 A5-A0 D15-D0 PAWRITE Page Write to Memory 1 0 1 11 A5-A0 Nx D15-D0 WRAL Write All Memory with same Data 1 0 1 00 01 XXXX D15-D0 WEN Write Enable 1 0 1 00 11 XXXX 9 WDS Write Disable X 0 1 00 00 XXXX 9 PRREAD Protection Register Read X 1 1 10 XXXXXX PRWRITE Protection Register Write 1 1 1 01 A5-A0 9 Data above specified address A5-A0 are protected PRCLEAR Protection Register Clear 1 1 1 11 111111 9 Protect Flag is also cleared (cleared Flag = 1) PREN Protection Register Enable 1 1 1 00 11XXXX 9 PRDS Protection Register Disable 1 1 1 00 000000 9 Instruction Note: 1. X = Don't Care bit. 6/34 Write is executed if all the N addresses 9 + N x 16 are not inside the Protected area 25 Write all data if the Protection Register is cleared Data Output = Protection Register content + Protection Flag bit Q5-Q0 + Flag OTP bit is set permanently M93S66, M93S56, M93S46 Table 3. Instruction Set for the M93S66, M93S56 Required Clock Cycles Additional Comments 27 Write is executed if the address is not inside the Protected area Description W PRE Start bit OpCode Address1,2 Data READ Read Data from Memory X 0 1 10 A7-A0 Q15-Q0 WRITE Write Data to Memory 1 0 1 01 A7-A0 D15-D0 Write is executed if all the N Nx 11 + N x 16 addresses are not D15-D0 inside the Protected area Instruction PAWRITE Page Write to Memory 1 0 1 11 A7-A0 WRAL Write All Memory with same Data 1 0 1 00 01XXXXXX WEN Write Enable 1 0 1 00 11XXXXXX 11 WDS Write Disable X 0 1 00 00XXXXXX 11 PRREAD Protection Register Read X 1 1 10 XXXXXXXX PRWRITE Protection Register Write 1 1 1 01 A7-A0 11 Data above specified address A7-A0 are protected PRCLEAR Protection Register Clear 1 1 1 11 11111111 11 Protect Flag is also cleared (cleared Flag = 1) PREN Protection Register Enable 1 1 1 00 11XXXXXX 11 PRDS Protection Register Disable 1 1 1 00 00000000 11 D15-D0 27 Write all data if the Protection Register is cleared Data Output = Protection Register content + Protection Flag bit Q7-Q0 + Flag OTP bit is set permanently Note: 1. X = Don't Care bit. 2. Address bit A7 is not decoded by the M93S56. 7/34 M93S66, M93S56, M93S46 Figure 4. READ, WRITE, WEN and WDS Sequences READ PRE S D 1 1 0 An A0 Q Qn ADDR Q0 DATA OUT OP CODE WRITE PRE W S CHECK STATUS D 1 0 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE WRITE ENABLE WRITE DISABLE PRE PRE W S S D D 1 0 0 1 1 Xn X0 1 0 0 0 0 Xn X0 OP CODE OP CODE AI00889D Note: For the meanings of An, Xn, Qn and Dn, see Table 2. and Table 3.. 8/34 M93S66, M93S56, M93S46 Read The Read Data from Memory (READ) instruction outputs serial data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0 bit is output first, followed by the 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Sx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read. Write Enable and Write Disable The Write Enable (WEN) instruction enables the future execution of write instructions, and the Write Disable (WDS) instruction disables it. When power is first applied, the M93Sx6 initializes itself so that write instructions are disabled. After an Write Enable (WEN) instruction has been executed, writing remains enabled until an Write Disable (WDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from accidental corruption, it is advisable to issue the Write Disable (WDS) instruction after every write cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable (WEN) or Write Disable (WDS) instructions. Write The Write Data to Memory (WRITE) instruction is composed of the Start bit plus the op-code followed by the address and the 16 data bits to be written. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle. 9/34 M93S66, M93S56, M93S46 Figure 5. PAWRITE and WRAL Sequence PAGE WRITE PRE W S CHECK STATUS D 1 1 1 An A0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE WRITE ALL PRE W S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0 Q ADDR DATA IN BUSY READY OP CODE AI00890C Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3.. Page Write A Page Write to Memory (PAWRITE) instruction contains the first address to be written, followed by up to 4 data words. After the receipt of each data word, bits A1-A0 of the internal address register are incremented, the high order bits remaining unchanged (A7-A2 for M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over. 10/34 The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words addresses the protected area. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not M93S66, M93S56, M93S46 be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle. Write All The Write All Memory with same Data (WRAL) instruction is valid only after the Protection Register has been cleared by executing a Protection Register Clear (PRCLEAR) instruction. The Write All Memory with same Data (WRAL) instruction simultaneously writes the whole memory with the same data word given in the instruction. Write Enable (W) must be held High before and during the instruction. Input address and data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C). After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. While the M93Sx6 is performing a write cycle, but after a delay (tSLSH) before the status information becomes available, Chip Select Input (S) can be driven High to monitor the status of the write cycle: Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit is decoded or the Chip Select Input (S) is brought Low. Programming is internally self-timed, so the external Serial Clock (C) may be disconnected or left running after the start of a write cycle. 11/34 M93S66, M93S56, M93S46 Figure 6. PREAD, PRWRITE and PREN Sequences Protect Register READ PRE S D 1 1 0 Xn X0 Q An ADDR OP CODE Protect Register WRITE A0 F F = Protect Flag DATA OUT PRE W S CHECK STATUS D 1 0 1 An A0 Q ADDR BUSY READY OP CODE Protect Register ENABLE PRE W S D 1 0 0 1 1 Xn X0 OP CODE Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3.. 12/34 AI00891D M93S66, M93S56, M93S46 Figure 7. PRCLEAR and PRDS Sequences Protect Register CLEAR PRE W S CHECK STATUS D 111 111 Q ADDR BUSY READY OP CODE Protect Register DISABLE PRE W S CHECK STATUS D 100 000 Q ADDR BUSY READY OP CODE AI00892C Note: For the meanings of An, Xn and Dn, please see Table 2. and Table 3.. 13/34 M93S66, M93S56, M93S46 WRITE PROTECTION AND THE PROTECTION REGISTER The Protection Register on the M93Sx6 is used to adjust the amount of memory that is to be write protected. The write protected area extends from the address given in the Protection Register, up to the top address in the M93Sx6 device. Two flag bits are used to indicate the Protection Register status: - Protection Flag: this is used to enable/disable protection of the write-protected area of the M93Sx6 memory - OTP bit: when set, this disables access to the Protection Register, and thus prevents any further modifications to the value in the Protection Register. The lower-bound memory address is written to the Protection Register using the Protection Register Write (PRWRITE) instruction. It can be read using the Protection Register Read (PRREAD) instruction. The Protection Register Enable (PREN) instruction must be executed before any PRCLEAR, PRWRITE or PRDS instruction, and with appropriate levels applied to the Protection Enable (PRE) and Write Enable (W) signals. Write-access to the Protection Register is achieved by executing the following sequence: - Execute the Write Enable (WEN) instruction - Execute the Protection Register Enable (PREN) instruction - Execute one PRWRITE, PRCLEAR or PRDS instructions, to set a new boundary address in the Protection Register, to clear the protection address (to all 1s), or permanently to freeze the value held in the Protection Register. Protection Register Read The Protection Register Read (PRREAD) instruction outputs, on Serial Data Output (Q), the content of the Protection Register, followed by the Protection Flag bit. The Protection Enable (PRE) signal must be driven High before and during the instruction. As with the Read Data from Memory (READ) instruction, a dummy 0 bit is output first. Since it is not possible to distinguish between the Protection Register being cleared (all 1s) or having been written with all 1s, the user must check the Protection Flag status (and not the Protection Register content) to ascertain the setting of the memory protection. Protection Register Enable The Protection Register Enable (PREN) instruction is used to authorize the use of instructions that modify the Protection Register (PRWRITE, PRCLEAR, PRDS). The Protection Register En- 14/34 able (PREN) instruction does not modify the Protection Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protection Register Enable (PREN) instruction. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Protection Register Clear The Protection Register Clear (PRCLEAR) instruction clears the address stored in the Protection Register to all 1s, so that none of the memory is write-protected by the Protection Register. However, it should be noted that all the memory remains protected, in the normal way, using the Write Enable (WEN) and Write Disable (WDS) instructions. The Protection Register Clear (PRCLEAR) instruction clears the Protection Flag to 1. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Clear (PRCLEAR) instruction. Protection Register Write The Protection Register Write (PRWRITE) instruction is used to write an address into the Protection Register. This is the address of the first word to be protected. After the Protection Register Write (PRWRITE) instruction has been executed, all memory locations equal to and above the specified address are protected from writing. The Protection Flag bit is set to 0, and can be read with Protection Register Read (PRREAD) instruction. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Write (PRWRITE) instruction, but it is not necessary to execute first a Protection Register Clear (PRCLEAR). Protection Register Disable The Protection Register Disable (PRDS) instruction sets the One Time Programmable (OTP) bit. This instruction is a ONE TIME ONLY instruction which latches the Protection Register content, this content is therefore unalterable in the future. Both the Protection Enable (PRE) and Write Enable (W) signals must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Protection Register, using the Protection Register Read (PRREAD) instruction, then by writing this same value back into the Protection Register, us- M93S66, M93S56, M93S46 COMMON I/O OPERATION ing the Protection Register Write (PRWRITE) instruction. When the OTP bit is set, the Ready/Busy status cannot appear on Serial Data Output (Q). When the OTP bit is not set, the Busy status appears on Serial Data Output (Q). Note: A Protection Register Enable (PREN) instruction must immediately precede the Protection Register Disable (PRDS) instruction. Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a current limiting resistor, to form a common, single-wire data bus. Some precautions must be taken when operating the memory in this way, mostly to prevent a short circuit current from flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output (Q). Please see the application note AN394 for details. Figure 8. Write Sequence with One Clock Glitch S C D An START "0" "1" WRITE An-1 An-2 Glitch D0 ADDRESS AND DATA ARE SHIFTED BY ONE BIT AI01395 CLOCK PULSE COUNTER In a noisy environment, the number of pulses received on Serial Clock (C) may be greater than the number delivered by the Bus Master (the microcontroller). This can lead to a misalignment of the instruction of one or more bits (as shown in Figure 8.) and may lead to the writing of erroneous data at an erroneous address. To combat this problem, the M93Sx6 has an onchip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of clock pulses received is not the number expected, the WRITE, PAWRITE, WRALL, PRWRITE or PRCLEAR instruction is aborted, and the contents of the memory are not modified. The number of clock cycles expected for each instruction, and for each member of the M93Sx6 family, are summarized in Table 2. to Table 3.. For example, a Write Data to Memory (WRITE) instruction on the M93S56 (or M93S66) expects 27 clock cycles from the start bit to the falling edge of Chip Select Input (S). That is: 1 Start bit + 2 Op-code bits + 8 Address bits + 16 Data bits 15/34 M93S66, M93S56, M93S46 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute Maximum Ratings Symbol Parameter Min. Max. Unit -65 150 C TSTG Storage Temperature TLEAD Lead Temperature during Soldering VOUT Output range (Q = VOH or Hi-Z) -0.50 VCC+0.5 V VIN Input range -0.50 VCC+1 V VCC Supply Voltage -0.50 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) 2 -4000 4000 V See note 1 (R) C Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 16/34 M93S66, M93S56, M93S46 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 5. Operating Conditions (M93Sx6) Symbol VCC Parameter Min. Max. Unit Supply Voltage 4.5 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Ambient Operating Temperature (Device Grade 3) -40 125 C Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Min. Max. Unit Supply Voltage 1.8 5.5 V Ambient Operating Temperature (Device Grade 6) -40 85 C Min. Max. Unit TA Table 6. Operating Conditions (M93Sx6-W) Symbol VCC TA Parameter Table 7. Operating Conditions (M93Sx6-R) Symbol VCC TA Parameter Table 8. AC Measurement Conditions (M93Sx6) Symbol CL Parameter Load Capacitance 100 Input Rise and Fall Times pF 50 Input Pulse Voltages ns 0.4 V to 2.4 V V Input Timing Reference Voltages 1.0 V and 2.0 V V Output Timing Reference Voltages 0.8 V and 2.0 V V Note: Output Hi-Z is defined as the point where data out is no longer driven. Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R) Symbol CL Parameter Load Capacitance Input Rise and Fall Times Min. Max. 100 Unit pF 50 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input Timing Reference Voltages 0.3VCC to 0.7VCC V Output Timing Reference Voltages 0.3VCC to 0.7VCC V Note: Output Hi-Z is defined as the point where data out is no longer driven. 17/34 M93S66, M93S56, M93S46 Figure 9. AC Testing Input Output Waveforms M93SXX 2.4V 2V 2.0V 1V 0.8V 0.4V INPUT OUTPUT M93SXX-W & M93SXX-R 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02791 Table 10. Capacitance Symbol Parameter Test Condition COUT Output Capacitance VOUT = 0V CIN Input Capacitance VIN = 0V Note: Sampled only, not 100% tested, at TA=25C and a frequency of 1 MHz. 18/34 Min Max Unit 5 pF 5 pF M93S66, M93S56, M93S46 Table 11. DC Characteristics (M93Sx6, Device Grade 6) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current Test Condition Min. Max. Unit 0V VIN VCC 2.5 A 0V VOUT VCC, Q in Hi-Z 2.5 A 1.5 mA 2 mA 50 A 15 A VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 ICC Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, New Product 2 VIL Input Low Voltage VCC = 5V 10% -0.45 0.8 V VIH Input High Voltage VCC = 5V 10% 2 VCC + 1 V VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V VOH Output High Voltage VCC = 5V, IOH = -400A 2.4 V Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G. Table 12. DC Characteristics (M93Sx6, Device Grade 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Test Condition Min. Max. Unit 0V VIN VCC 2.5 A 0V VOUT VCC, Q in Hi-Z 2.5 A VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 1.5 mA 2 mA 50 A 15 A Supply Current VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 5V, S = VSS, C = VSS, New Product 2 VIL Input Low Voltage VCC = 5V 10% -0.45 0.8 V VIH Input High Voltage VCC = 5V 10% 2 VCC + 1 V VOL Output Low Voltage VCC = 5V, IOL = 2.1mA 0.4 V VOH Output High Voltage VCC = 5V, IOH = -400A 2.4 V Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G. 19/34 M93S66, M93S56, M93S46 Table 13. DC Characteristics (M93Sx6-W, Device Grade 6) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current Test Condition Min. Max. Unit 0V VIN VCC 2.5 A 0V VOUT VCC, Q in Hi-Z 2.5 A 1.5 mA 1 mA 2 mA 1 mA 10 A 5 A VCC = 5V, S = VIH, f = 1 MHz, Current Product 1 VCC = 2.5V, S = VIH, f = 1 MHz, Current ICC Supply Current (CMOS Inputs) Product 1 VCC = 5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VIH, f = 2 MHz, New Product 2 VCC = 2.5V, S = VSS, C = VSS, Current Product 1 ICC1 Supply Current (Stand-by) VCC = 2.5V, S = VSS, C = VSS, New Product 2 VIL Input Low Voltage (D, C, S) -0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V VCC = 5V, IOL = 2.1mA 0.4 V VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A 0.2 V VOH VCC = 5V, IOH = -400A 2.4 V VCC = 2.5V, IOH = -100A VCC-0.2 V Output High Voltage (Q) Note: 1. Current product: identified by Process Identification letter F or M. 2. New product: identified by Process Identification letter W or G. 20/34 M93S66, M93S56, M93S46 Table 14. DC Characteristics (M93Sx6-W, Device Grade 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC ICC1 Supply Current (CMOS Inputs) Supply Current (Stand-by) Max. 1 Unit 0V VIN VCC 2.5 A 0V VOUT VCC, Q in Hi-Z 2.5 A VCC = 5V, S = VIH, f = 2 MHz 2 mA VCC = 2.5V, S = VIH, f = 2 MHz 1 mA VCC = 2.5V, S = VSS, C = VSS 5 A Test Condition Min 1. VIL Input Low Voltage (D, C, S) -0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.7 VCC VCC + 1 V VCC = 5V, IOL = 2.1mA 0.4 V VOL Output Low Voltage (Q) VCC = 2.5V, IOL = 100A 0.2 V VOH VCC = 5V, IOH = -400A 2.4 V VCC = 2.5V, IOH = -100A VCC-0.2 V Output High Voltage (Q) Note: 1. New product: identified by Process Identification letter W or G. Table 15. DC Characteristics (M93Sx6-R) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC ICC1 Supply Current (CMOS Inputs) Supply Current (Stand-by) Max. 1 Unit 0V VIN VCC 2.5 A 0V VOUT VCC, Q in Hi-Z 2.5 A VCC = 5V, S = VIH, f = 2 MHz 2 mA VCC = 1.8V, S = VIH, f = 1 MHz 1 mA VCC = 1.8V, S = VSS, C = VSS 2 A Test Condition Min. 1 VIL Input Low Voltage (D, C, S) -0.45 0.2 VCC V VIH Input High Voltage (D, C, S) 0.8 VCC VCC + 1 V VOL Output Low Voltage (Q) VCC = 1.8V, IOL = 100A 0.2 V VOH Output High Voltage (Q) VCC = 1.8V, IOH = -100A VCC-0.2 V Note: 1. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office. 21/34 M93S66, M93S56, M93S46 Table 16. AC Characteristics (M93Sx6, Device Grade 6 or 3) Test conditions specified in Table 8. and Table 5. Max.3 Min.4 Max.4 Unit D.C. 1 D.C. 2 MHz Alt. fC fSK tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns tWVCH tPES Write Enable Valid to Clock High 50 50 ns tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns tSLWX tPEH Chip Select Low to Write Enable Transition 250 250 ns Chip Select Low to Clock High 250 50 ns Chip Select Set-up Time M93C46, M93C56, M93C66 50 50 ns Chip Select Set-up time M93C76, M93C86 100 50 ns tSLCH tSHCH tCSS Parameter Min.3 Symbol Clock Frequency tSLSH2 tCS Chip Select Low to Chip Select High 250 200 ns tCHCL1 tSKH Clock High Time 250 200 ns tCLCH1 tSKL Clock Low Time 250 200 ns tDVCH tDIS Data In Set-up Time 100 50 ns tCHDX tDIH Data In Hold Time 100 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns tCLSL tCSH Chip Select Hold Time 0 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns tCHQL tPD0 Delay to Output Low 400 200 ns tCHQV tPD1 Delay to Output Valid 400 200 ns tW tWP Erase/Write Cycle time 10 5 ms Note: 1. 2. 3. 4. 22/34 tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W or G. M93S66, M93S56, M93S46 Table 17. AC Characteristics (M93Sx6-W, Device Grade 6) Test conditions specified in Table 9. and Table 6. Max.3 Min.4 Max.4 Unit D.C. 1 D.C. 2 MHz Alt. fC fSK tPRVCH tPRES Protect Enable Valid to Clock High 50 50 ns tWVCH tPES Write Enable Valid to Clock High 50 50 ns tCLPRX tPREH Clock Low to Protect Enable Transition 0 0 ns tSLWX tPEH Chip Select Low to Write Enable Transition 250 250 ns Chip Select Low to Clock High 250 50 ns 100 50 ns 1000 200 ns tSLCH Parameter Min.3 Symbol Clock Frequency tSHCH tCSS Chip Select Set-up Time tSLSH2 tCS Chip Select Low to Chip Select High tCHCL1 tSKH Clock High Time 350 200 ns tCLCH1 tSKL Clock Low Time 250 200 ns tDVCH tDIS Data In Set-up Time 100 50 ns tCHDX tDIH Data In Hold Time 100 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 50 ns tCLSL tCSH Chip Select Hold Time 0 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 100 ns tCHQL tPD0 Delay to Output Low 400 200 ns tCHQV tPD1 Delay to Output Valid 400 200 ns tW tWP Erase/Write Cycle time 10 5 ms Note: 1. 2. 3. 4. tCHCL + tCLCH 1 / fC. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W or G. 23/34 M93S66, M93S56, M93S46 Table 18. AC Characteristics (M93Sx6-W, Device Grade 3) Test conditions specified in Table 9. and Table 6. Max.3 Unit D.C. 2 MHz Alt. fC fSK tPRVCH tPRES Protect Enable Valid to Clock High 50 ns tWVCH tPES Write Enable Valid to Clock High 50 ns tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns Chip Select Low to Clock High 50 ns tSLCH Parameter Min.3 Symbol Clock Frequency tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH2 tCS Chip Select Low to Chip Select High 200 ns tCHCL1 tSKH Clock High Time 200 ns tCLCH1 tSKL Clock Low Time 200 ns tDVCH tDIS Data In Set-up Time 50 ns tCHDX tDIH Data In Hold Time 50 ns tCLSH tSKS Clock Set-up Time (relative to S) 50 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 200 ns tSLQZ tDF Chip Select Low to Output Hi-Z 100 ns tCHQL tPD0 Delay to Output Low 200 ns tCHQV tPD1 Delay to Output Valid 200 ns tW tWP Erase/Write Cycle time 5 ms Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. New product: identified by Process Identification letter W or G. 24/34 M93S66, M93S56, M93S46 Table 19. AC Characteristics (M93Sx6-R) Test conditions specified in Table 9. and Table 7. Max.3 Unit D.C. 1 MHz Alt. fC fSK tPRVCH tPRES Protect Enable Valid to Clock High 50 ns tWVCH tPES Write Enable Valid to Clock High 50 ns tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns Chip Select Low to Clock High 250 ns tSLCH Parameter Min.3 Symbol Clock Frequency tSHCH tCSS Chip Select Set-up Time 50 ns tSLSH2 tCS Chip Select Low to Chip Select High 250 ns tCHCL1 tSKH Clock High Time 250 ns tCLCH1 tSKL Clock Low Time 250 ns tDVCH tDIS Data In Set-up Time 100 ns tCHDX tDIH Data In Hold Time 100 ns tCLSH tSKS Clock Set-up Time (relative to S) 100 ns tCLSL tCSH Chip Select Hold Time 0 ns tSHQV tSV Chip Select to Ready/Busy Status 400 ns tSLQZ tDF Chip Select Low to Output Hi-Z 200 ns tCHQL tPD0 Delay to Output Low 400 ns tCHQV tPD1 Delay to Output Valid 400 ns tW tWP Erase/Write Cycle time 10 ms Note: 1. tCHCL + tCLCH 1 / fC. 2. Chip Select Input (S) must be brought Low for a minimum of tSLSH between consecutive instruction cycles. 3. Preliminary Data: this product is under development. For more infomation, please contact your nearest ST sales office. 25/34 M93S66, M93S56, M93S46 Figure 10. Synchronous Timing (Start and Op-Code Input) PRE tPRVCH W tWVCH tCHCL C tCLSH tSHCH tCLCH S tDVCH START D tCHDX OP CODE OP CODE OP CODE INPUT START AI02025 Figure 11. Synchronous Timing (Read or Write) C tCLSL S tDVCH tCHDX A0 An D Hi-Z tSLSH tCHQV tSLQZ tCHQL Q15 Q ADDRESS INPUT Q0 DATA OUTPUT AI002026 26/34 M93S66, M93S56, M93S46 Figure 12. Synchronous Timing (Read or Write) PRE tCLPRX W tSLWX C tSLCH tCLSL S tSLSH tDVCH D tCHDX An A0/D0 tSHQV tSLQZ Hi-Z BUSY Q READY tW ADDRESS/DATA INPUT WRITE CYCLE AI02027 27/34 M93S66, M93S56, M93S46 PACKAGE MECHANICAL Figure 13. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Note: Drawing is not to scale. Table 20. PDIP8 - 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm inches Symb. Typ. Min. A Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 D 9.27 9.02 10.16 0.365 0.355 0.400 E 7.87 7.62 8.26 0.310 0.300 0.325 E1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 - - 0.100 - - eA 7.62 - - 0.300 - - eB L 28/34 Max. 10.92 3.30 2.92 3.81 0.430 0.130 0.115 0.150 M93S66, M93S56, M93S46 Figure 14. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Outline h x 45 A C B CP e D N E H 1 A1 L SO-a Note: Drawing is not to scale. Table 21. SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data mm inches Symb. Typ. Min. Max. A 1.35 A1 Min. Max. 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 - - - - H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 0.90 0.016 0.035 0 8 0 8 N 8 e CP 1.27 Typ. 0.050 8 0.10 0.004 29/34 M93S66, M93S56, M93S46 Figure 15. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Package Outline D 8 5 c E1 1 E 4 L A1 A A2 L1 CP b e TSSOP8BM Note: Drawing is not to scale. Table 22. TSSOP8 3x3mm - 8 lead Thin Shrink Small Outline, 3x3mm body size, Mechanical Data mm inches Symbol Typ. Min. A 0.050 0.150 0.750 0.950 b 0.250 c A2 Typ. Min. 1.100 A1 0.850 Max. 0.0433 0.0020 0.0059 0.0295 0.0374 0.400 0.0098 0.0157 0.130 0.230 0.0051 0.0091 0.0335 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 E 4.900 4.650 5.150 0.1929 0.1831 0.2028 E1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - CP 0.100 L 0.550 L1 0.950 30/34 Max. 0.400 0.700 0.0039 0.0217 0.0157 0.0276 0 6 0.0374 0 6 M93S66, M93S56, M93S46 Figure 16. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 1 E 4 L A1 A A2 L1 CP b e TSSOP8AM Note: Drawing is not to scale. Table 23. TSSOP8 - 8 lead Thin Shrink Small Outline, Package Mechanical Data mm inches Symbol Typ. Min. A Max. Min. 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ. 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0 8 0.0394 0 8 31/34 M93S66, M93S56, M93S46 PART NUMBERING Table 24. Ordering Information Scheme Example: M93S66 - W MN 6 T P Device Type M93 = MICROWIRE serial access EEPROM (x16) with Block Protection Device Function 66 = 4 Kbit (256 x 16) 56 = 2 Kbit (128 x 16) 46 = 1 Kbit (64 x 16) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) DS2 = TSSOP8 (3x3mm body size) Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C 3 = Automotive: device tested with High Reliability Certified Flow 1 over -40 to 125 C Option blank = Standard Packing T = Tape & Reel Packing Plating Technology blank = Standard SnPb plating P = Lead-Free and RoHS compliant G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Available only on new products: identified by the Process Identification letter W or G. Devices are shipped from the factory with the memory content set at all 1s (FFh). For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. Table 25. How to Identify Current and New Products by the Process Identification Letter Markings on Current Products1 Markings on New Products1 M93S46W6 AYWWF (or AYWWM) M93S46W6 AYWWW (or AYWWG) Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0059 (PCEE0059). 32/34 M93S66, M93S56, M93S46 REVISION HISTORY Table 26. Document Revision History Date Rev. Description of Revision 07-Mar-2002 2.0 Document reformatted, and reworded, using the new template. Temperature range 1 removed. TSSOP8 (3x3mm) package added. New products, identified by the process letter W, added, with fc(max) increased to 1MHz for -R voltage range, and to 2MHz for all other ranges (and corresponding parameters adjusted). 26-Mar-2003 2.1 Value of standby current (max) corrected in DC characteristics tables for -W and -R ranges VOUT and VIN separated from VIO in the Absolute Maximum Ratings table 14-Apr-2003 2.2 Values corrected in AC characteristics tables for -W range (tSLSH, tDVCH, tCLSL) for devices with Process Identification Letter W. 23-May-2003 2.3 Standby current corrected for -R range. Four missing parameters restored to all AC Characteristics tables 24-Nov-2003 3.0 Table of contents, and Pb-free options added. VIL(min) improved to -0.45V. 19-Apr-2004 4.0 Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to HRCF and automotive environments. Process identification letter "G" information added 33/34 M93S66, M93S56, M93S46 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 34/34