GS1560ACFE3 - SEMTECH INTERNATIONAL

1 of 79GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

www.gennum.com

Key Features

• SMPTE 292M and SMPTE 259M-C compliant

descrambling and NRZI → NRZ decoding (with bypass)

• DVB-ASI 8b/10b decoding

• auto-configuration for HD-SDI and SD-SDI

• serial loop-through cable driver output selectable as

reclocked or non-reclocked (GS1560A only)

• dual serial digital input buffers with 2 x 1 mux

• integrated serial digital signal termination

• integrated reclocker

• automatic or manual rate selection / indication

(HD/SD)

• descrambler bypass option

• user selectable additional processing features

including:

• CRC, TRS, ANC data checksum, line number and EDH

CRC error detection and correction

• programmable ANC data detection

• illegal code remapping

• internal flywheel for noise immune H, V, F extraction

• FIFO load Pulse

• 20-bit / 10-bit CMOS parallel output data bus

• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel

digital output

• automatic standards detection and indication

• Pb-free and RoHS Compliant

• 1.8V core power supply and 3.3V charge pump power

supply

• 3.3V digital I/O supply

• JTAG test interface

• small footprint compatible with GS9060, GS1532, and

GS9062

Applications

• SMPTE 292M Serial Digital Interfaces

• SMPTE 259M-C Serial Digital Interfaces

• DVB-ASI Serial Digital Interfaces

Description

The GS1560A/GS1561 is a reclocking deserializer. When

used in conjunction with the GS1524 Automatic Cable

Equalizer and the GO1555/GO1525* Voltage Controlled

Oscillator, a receive solution can be realized for HD-SD,

SD-SDI and DVB-ASI applications.

In addition to reclocking and deserializing the input data

stream, the GS1560A/GS1561 performs NRZI-to-NRZ

decoding, descrambling as per SMPTE 259M-C/292M, and

word alignment when operating in SMPTE mode. When

operating in DVB-ASI mode, the device will word align the

data to K28.5 sync characters and 8b/10b decode the

received stream.

Two serial digital input buffers are provided with a 2x1

multiplexer to allow the device to select from one of two

serial digital input signals.

The integrated reclocker features a very wide Input Jitter

Tolerance of ±0.3 UI (total 0.6 UI), a rapid asynchronous

lock time, and full compliance with DVB-ASI data streams.

The GS1560A includes an integrated cable driver is for

serial input loop-through applications. It can be selected to

output either buffered or reclocked data. The cable driver

also features an output mute on loss of signal, high

impedance mode, adjustable signal swing, and automatic

dual slew-rate selection depending on HD/SD operational

requirements.

The GS1560A/GS1561 also includes a range of data

processing functions such as error detection and

correction, automatic standards detection, and EDH

support. The device can also detect and extract SMPTE

352M payload identifier packets and independently

identify the received video standard. This information is

read from internal registers via the host interface port.

Line-based CRC errors, line number errors, TRS errors, EDH

CRC errors and ancillary data checksum errors can all be

detected.

Finally, the device can correct detected errors and insert

new TRS ID words, line-based CRC words, ancillary data

checksum words, EDH CRC words, and line numbers.

Illegal code re-mapping is also available. All processing

functions may be individually enabled or disabled via host

interface control.

The GS1560A/GS1561 is Pb-free and the encapsulation

compound does not contain halogenated flame retardant.

This component and all homogeneous subcomponents are

RoHS compliant.

*For new designs use GO1555

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

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Functional Block Diagrams

GS1560A Functional Block Diagram

GS1561 Functional Block Diagram

DDI_1

TERM 1

TERM 2

DDI_1

DDI_2

Reclocker

SDO

SDO_EN/DIS

RSET

S->P

SMPTE De-

scramble, Word

alignment and

flywheel

DOUT[19:0]

IP_SEL

carrier_detect

RC_BYP

(o/p mute)

pll_lock

RESET_TRST

asi_sync_det

HOST Interface / JTAG

test

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

FIFO_LD

DATA_ERROR

YANC

CANC

Reset

JTAG/HOST

IOPROC_EN/DIS

CRC check

Line number

check

TRS check

CSUM check

ANC data

detection

DVB-ASI

word alignment

and

8b/10b decode

CRC correct

Line number

correct

TRS correct

CSUM correct

EDH check &

correct

Illegal code re-

map

20bit/10bit

I/O

Buffer

& mux

FW_EN/DIS

CP_CAP

DVB_ASI

pll_lock

VCO

LB_CONT

VCO_VCC

VCO_GND

SD/HD

MASTER/SLAVE

PCLK

LOCKED

LOCK detect

CD1

CD2

SMPTE_BYPASS

smpte_sync_det

rclk_ctrl

rclk_bypass

DDI_1

TERM 1

TERM 2

DDI_1

DDI_2

Reclocker

S->P

SMPTE De-

scramble, Word

alignment and

flywheel

DOUT[19:0]

IP_SEL

carrier_detect

RESET_TRST

asi_sync_det

HOST Interface / JTAG

test

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

FIFO_LD

DATA_ERROR

YANC

CANC

Reset

JTAG/HOST

IOPROC_EN/DIS

CRC check

Line number

check

TRS check

CSUM check

ANC data

detection

DVB-ASI

word alignment

and

8b/10b decode

CRC correct

Line number

correct

TRS correct

CSUM correct

EDH check &

correct

Illegal code re-

map

20bit/10bit

I/O

Buffer

& mux

FW_EN/DIS

CP_CAP

DVB_ASI

pll_lock

VCO

LB_CONT

VCO_VCC

VCO_GND

SD/HD

MASTER/SLAVE

PCLK

LOCKED

LOCK detect

CD1

CD2

SMPTE_BYPASS

smpte_sync_det

rclk_ctrl

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Data Sheet

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Revision History

Contents

Key Features ........................................................................................................................................................1

Applications.........................................................................................................................................................1

Description...........................................................................................................................................................1

Functional Block Diagrams ............................................................................................................................2

1. Pin Out...............................................................................................................................................................6

1.1 Pin Assignment GS1560A ...............................................................................................................6

1.2 Pin Assignment GS1561 ..................................................................................................................7

1.3 Pin Descriptions .................................................................................................................................8

2. Electrical Characteristics ......................................................................................................................... 19

2.1 Absolute Maximum Ratings........................................................................................................ 19

2.2 DC Electrical Characteristics ...................................................................................................... 19

2.3 AC Electrical Characteristics ...................................................................................................... 21

3. Input/Output Circuits ............................................................................................................................... 24

3.1 Host Interface Map......................................................................................................................... 26

3.1.1 Host Interface Map (R/W Configurable Registers) ................................................. 27

3.1.2 Host Interface Map (Read Only Registers) ................................................................ 28

4. Detailed Description.................................................................................................................................. 29

Version ECR PCN Date Changes and / or Modifications

12 152053 – June 2009 Removed ‘Proprietary & Confidential’ from the footer.

11 150195 50711 July 2008 DVB_ASI operation specification change in Master mode.

10 143666 42774 January 2007 Recommended the new GO1555 VCO for new designs.

9 140423 39452 May 2006 Corrected minor typing errors in Functional Block Diagram. Modified

video format numbers for system 1125 on Table 4-4: Switch Line

Position for Digital Systems.

8 137405 – September 2005 Conversion to Data Sheet. Added note on max device power and

current to Table 2-1: DC Electrical Characteristics. Corrected Solder

Reflow Profile labels.

7 136978 – June 2005 Restored missing overlines to pin names. Corrected missing TERM pin

in Serial Digital Input connection diagram. Rephrased RoHS

compliance statement.

6 134906 – April 2005 Added Solder Reflow Profile description. Clarified setting of

VD_STD[4:0], INT_PROG and STD_LOCK bits following a reset and/or

removal of input. Minor correction to Typical Application Circuits for

both parts. Added DVB-ASI Packet Counter information. Added

Packaging Data section. Changed ‘Green’ references to RoHS

Compliant.

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

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4.1 Functional Overview..................................................................................................................... 29

4.2 Serial Digital Input ......................................................................................................................... 30

4.2.1 Input Signal Selection ...................................................................................................... 30

4.2.2 Carrier Detect Input.......................................................................................................... 30

4.2.3 Single Input Configuration ............................................................................................. 30

4.3 Serial Digital Reclocker ................................................................................................................ 31

4.3.1 External VCO...................................................................................................................... 31

4.3.2 Loop Bandwidth................................................................................................................. 31

4.4 Serial Digital Loop-Through Output (GS1560A only)......................................................... 31

4.4.1 Output Swing ...................................................................................................................... 32

4.4.2 Reclocker Bypass Control ............................................................................................... 33

4.4.3 Serial Digital Output Mute.............................................................................................. 33

4.5 Serial-To-Parallel Conversion .................................................................................................... 34

4.6 Modes Of Operation ...................................................................................................................... 34

4.6.1 Lock Detect .......................................................................................................................... 34

4.6.2 Master Mode........................................................................................................................ 35

4.6.3 Slave Mode........................................................................................................................... 36

4.7 SMPTE Functionality ..................................................................................................................... 36

4.7.1 SMPTE Descrambling and Word Alignment ............................................................ 37

4.7.2 Internal Flywheel .............................................................................................................. 37

4.7.3 Switch Line Lock Handling............................................................................................. 38

4.7.4 HVF Timing Signal Generation ..................................................................................... 42

4.8 DVB-ASI Functionality ................................................................................................................. 44

4.8.1 Transport Packet Format................................................................................................. 44

4.8.2 DVB-ASI 8b/10b Decoding and Word Alignment.................................................. 44

4.8.3 Status Signal Outputs ....................................................................................................... 45

4.9 Data Through Mode ....................................................................................................................... 45

4.10 Additional Processing Functions ............................................................................................45

4.10.1 FIFO Load Pulse ............................................................................................................... 46

4.10.2 Ancillary Data Detection and Indication ................................................................ 47

4.10.3 SMPTE 352M Payload Identifier ................................................................................ 51

4.10.4 Automatic Video Standard and Data Format Detection.................................... 51

4.10.5 Error Detection and Indication................................................................................... 55

4.10.6 Error Correction and Insertion ................................................................................... 60

4.10.7 EDH Flag Detection ........................................................................................................ 62

4.11 Parallel Data Outputs.................................................................................................................. 64

4.11.1 Parallel Data Bus Buffers .............................................................................................. 64

4.11.2 Parallel Output in SMPTE Mode................................................................................. 65

4.11.3 Parallel Output in DVB-ASI Mode ............................................................................. 65

4.11.4 Parallel Output in Data-Through Mode................................................................... 65

4.11.5 Parallel Output Clock (PCLK) ...................................................................................... 66

4.12 GSPI Host Interface...................................................................................................................... 67

4.12.1 Command Word Description...................................................................................... 67

4.12.2 Data Read and Write Timing ....................................................................................... 68

4.12.3 Configuration and Status Registers........................................................................... 68

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Data Sheet

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4.13 JTAG.................................................................................................................................................. 69

4.14 Device Power Up.......................................................................................................................... 70

4.15 Device Reset................................................................................................................................... 70

5. Application Reference Design ............................................................................................................... 71

5.1 GS1560A Typical Application Circuit (Part A) ...................................................................... 71

5.2 GS1560A Typical Application Circuit (Part B) ...................................................................... 72

5.3 GS1561 Typical Application Circuit (Part A) ......................................................................... 73

5.4 GS1561 Typical Application Circuit (Part B).......................................................................... 74

6. References & Relevant Standards ......................................................................................................... 75

7. Package & Ordering Information .......................................................................................................... 76

7.1 Package Dimensions...................................................................................................................... 76

7.2 Packaging Data................................................................................................................................ 77

7.3 Solder Reflow Profiles................................................................................................................... 77

7.4 Ordering Information.................................................................................................................... 78

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

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1. Pin Out

1.1 Pin Assignment GS1560A

[

GS1560A

CORE_GND

FW_EN/DIS

CANC

YANC

CORE_VDD

DOUT19

DOUT18

DOUT17

DOUT16

DOUT15

DOUT14

DOUT13

DOUT12

DOUT11

DOUT10

DOUT9

DOUT8

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

IO_GND

IO_VDD

IO_GND

IO_VDD

PCLK

RC_BYP

MASTER/SLAVE

LOCKED

VCO

VCO_GND

VCO_VCC

CP_CAP

LB_CONT

CP_GND

CP_VDD

PDBUFF_GND

PD_VDD

BUFF_VDD

CD1

DDI1

TERM1

DDI1

DVB_ASI

IP_SEL

SD/HD

20bit/10bit

IOPROC_EN/DIS

CD2

DDI2

TERM2

DDI2

SMPTE_BYPASS

RSET

CD_VDD

1234567 8 91011121314151617 18 19 20

59 58 57 5655 54 53 52 51 50 49 48 47 4645 44 43 42 41

CORE_VDD

CORE_GND

FIFO_LD

DATA_ERROR

SCLK_TCK

SDIN_TDI

SDOUT_TDO

CS_TMS

JTAG/HOST

RESET_TRST

SDO

CD_GND

SDO_EN/DIS

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Data Sheet

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1.2 Pin Assignment GS1561

GS1561

CORE_GND

FW_EN/DIS

CANC

YANC

CORE_VDD

DOUT19

DOUT18

DOUT1

DOUT9

DOUT8

DOUT7

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

IO_GND

IO_VDD

IO_GND

IO_VDD

PCLK

MASTER/SLAVE

LOCKED

VCO

VCO_GND

VCO_VCC

CP_CAP

LB_CONT

CP_GND

CP_VDD

PDBUFF_GND

PD_VDD

BUFF_VDD

CD1

DDI1

TERM1

DDI1

DVB_ASI

IP_SEL

SD/HD

20bit/10bit

IOPROC_EN/DIS

CD2

DDI2

TERM2

DDI2

SMPTE_BYPASS

RSV

1234567 8 91011121314151617 18 19 20

59 58 57 5655 54 53 52 51 50 49 48 47 4645 44 43 42 41

CORE_VDD

CORE_GND

FIFO_LD

DATA_ERRO

SCLK_TCK

SDIN_TDI

SDOUT_TDO

CS_TMS

JTAG/HOST

RESET_TRST

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1.3 Pin Descriptions

Table 1-1: Pin Descriptions

Number

Name Timing Typ e Description

1CP_VDD – Power Power supply connection for the charge pump. Connect to +3.3V DC

analog.

2PDBUFF_GND – Power Ground connection for the phase detector and serial digital input

buffers. Connect to analog GND.

3 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC

analog.

4 BUFF_VDD – Power Power supply connection for the serial digital input buffers. Connect

to +1.8V DC analog.

5CD1 Non

Synchronous

Input STATUS SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the presence of a serial digital input signal. Normally

generated by a Gennum automatic cable equalizer.

When LOW, the serial digital input signal received at the DDI1 and

DDI1 pins is considered valid.

When HIGH, the associated serial digital input signal is considered to

be invalid. In this case, the LOCKED signal is set LOW and all parallel

outputs are muted.

6, 8 DDI1, DDI1 AnalogInput Differential input pair for serial digital input 1.

7 TERM1 AnalogInput Termination for serial digital input 1. AC couple to EQ_GND.

9DVB_ASINon

Synchronous

Input /

Output

CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

This pin will be an input set by the application layer in slave mode.

This pin and its function are not supported in Master mode.

Slave Mode (MASTER/SLAVE = LOW)

When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS

= LOW, the device will be configured to operate in DVB-ASI mode.

When set LOW, the device will not support the decoding or word

alignment of received DVB-ASI data.

10 IP_SEL Non

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input

signal, and CD1 or CD2 as the carrier detect input signal.

When set HIGH, DDI1 / DDI1 is selected as the serial digital input and

CD1 is selected as the carrier detect input signal.

When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect

input signal is selected.

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11 SD/HD Non

Synchronous

Input /

Output

CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

This pin will be an input set by the application layer in slave mode, and

will be an output set by the device in master mode.

Master Mode (MASTER/SLAVE = HIGH)

The SD/HD signal will be LOW whenever the received serial digital

signal is 1.485Gb/s or 1.485/1.001Gb/s.

The SD/HD signal will be HIGH whenever the received serial digital

signal is 270Mb/s.

Slave Mode (MASTER/SLAVE = LOW)

When set LOW, the device will be configured for the reception of

1.485Gb/s or 1.485/1.001Gb/s signals only and will not lock to any

other serial digital signal.

When set HIGH, the device will be configured for the reception of

270Mb/s signals only and will not lock to any other serial digital signal.

NOTE: When in slave mode, reset the device after the SD/HD input has

been initially configured, and after each subsequent SD/HD data rate

change.

NOTE: This pin has an internal pull-up resistor of 100K.

12 20bit/10bit Non

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to select the output data bus width in SMPTE or Data-Through

modes. This signal is ignored in DVB-ASI mode.

When set HIGH, the parallel output will be 20-bit demultiplexed data.

When set LOW, the parallel outputs will be 10-bit multiplexed data.

13 IOPROC_EN/DISNon

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable I/O processing features.

When set HIGH, the following I/O processing features of the device are

enabled:

•EDH CRC Error Correction (SD-only)

•ANC Data Checksum Correction

•Line-based CRC Error Correction (HD-only)

•Line Number Error Correction (HD-only)

•TRS Error Correction

• Illegal Code Remapping

To enable a subset of these features, keep IOPROC_EN/DIS HIGH and

disable the individual feature(s) in the IOPROC_DISABLE register

accessible via the host interface.

When set LOW, the I/O processing features of the device are disabled,

regardless of whether the features are enabled in the

IOPROC_DISABLE register.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

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Data Sheet

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14 CD2 Non

Synchronous

Input STATUS SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the presence of a serial digital input signal. Normally

generated by a Gennum automatic cable equalizer.

When LOW, the serial digital input signal received at the DDI2 and

DDI2 pins is considered valid.

When HIGH, the associated serial digital input signal is considered to

be invalid. In this case, the LOCKED signal is set LOW and all parallel

outputs are muted.

15, 17 DDI2, DDI2 AnalogInput Differential input pair for serial digital input 2.

16 TERM2 AnalogInput Termination for serial digital input 2. AC couple to PDBUFF_GND.

18 SMPTE_BYPASS Non

Synchronous

Input /

Output

CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

This pin will be an input set by the application layer in slave mode, and

will be an output set by the device in master mode.

Master Mode (MASTER/SLAVE = HIGH)

The SMPTE_BYPASS signal will be HIGH only when the device has

locked to a SMPTE compliant data stream. It will be LOW otherwise.

Slave Mode (MASTER/SLAVE = LOW)

When set HIGH in conjunction with DVB_ASI = LOW, the device will be

configured to operate in SMPTE mode. All I/O processing features may

be enabled in this mode.

When set LOW, the device will not support the descrambling,

decoding or word alignment of received SMPTE data. No I/O

processing features will be available.

19 RSET AnalogInput GS1560A

Used to set the serial digital loop-through output signal amplitude.

Connect to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended

output swing.

NC––GS1561

No Connect.

20 CD_VDD – Power GS1560A

Power supply connection for the serial digital cable driver. Connect to

+1.8V DC analog.

NC––GS1561

No Connect.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

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21 SDO_EN/DISNon

Synchronous

Input GS1560A

CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable the serial digital output loop-through stage.

When set LOW, the serial digital output signals SDO and SDO are

disabled and become high impedance.

When set HIGH, the serial digital output signals SDO and SDO are

enabled.

NC––GS1561

No Connect.

22 CD_GND – Power GS1560A

Ground connection for the serial digital cable driver. Connect to

analog GND.

NC––GS1561

No Connect.

23, 24 SDO, SDO AnalogOutput GS1560A

Serial digital loop-through output signal operating at 1.485Gb/s,

1.485/1.001Gb/s, or 270Mb/s.

The slew rate of these outputs is automatically controlled to meet

SMPTE 292M and 259M specifications according to the setting of the

SD/HD pin.

NC––GS1561

No Connect.

25 RESET_TRSTNon

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to reset the internal operating conditions to default settings and

to reset the JTAG test sequence.

Host Mode (JTAG/HOST = LOW)

When asserted LOW, all functional blocks will be set to default

conditions and all input and output signals become high

impedance,

including the serial digital outputs SDO and

SDO.

Must be set HIGH for normal device operation.

NOTE: When in slave mode, reset the device after the SD/HD input has

been initially configured, and after each subsequent SD/HD data rate

change.

JTAG Test Mode (JTAG/HOST = HIGH)

When asserted LOW, all functional blocks will be set to default and

the JTAG test sequence will be held in reset.

When set HIGH, normal operation of the JTAG test sequence resumes.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

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26 JTAG/HOSTNon

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to select JTAG Test Mode or Host Interface Mode.

When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are

configured for JTAG boundary scan testing.

When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are

configured as GSPI pins for normal host interface operation.

27 CS_TMSSynchronous

with

SCLK_TCK

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Chip Select / Test Mode Select

Host Mode (JTAG/HOST = LOW)

CS_TMS operates as the host interface chip select, CS, and is active

LOW.

JTAG Test Mode (JTAG/HOST = HIGH)

CS_TMS operates as the JTAG test mode select, TMS, and is active

HIGH.

NOTE: If the host interface is not being used, tie this pin HIGH.

28 SDOUT_TDO Synchronous

with

SCLK_TCK

Output CONTROL SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Output / Test Data Output

Host Mode (JTAG/HOST = LOW)

SDOUT_TDO operates as the host interface serial output, SDOUT, used

to read status and configuration information from the internal

registers of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDOUT_TDO operates as the JTAG test data output, TDO.

29 SDIN_TDI Synchronous

with

SCLK_TCK

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data In / Test Data Input

Host Mode (JTAG/HOST = LOW)

SDIN_TDI operates as the host interface serial input, SDIN, used to

write address and configuration information to the internal registers

of the device.

JTAG Test Mode (JTAG/HOST = HIGH)

SDIN_TDI operates as the JTAG test data input, TDI.

NOTE: If the host interface is not being used, tie this pin HIGH.

30 SCLK_TCKNon

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Serial Data Clock / Test Clock.

Host Mode (JTAG/HOST = LOW)

SCLK_TCK operates as the host interface burst clock, SCLK. Command

and data read/write words are clocked into the device synchronously

with this clock.

JTAG Test Mode (JTAG/HOST = HIGH)

SCLK_TCK operates as the JTAG test clock, TCK.

NOTE: If the host interface is not being used, tie this pin HIGH.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

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Data Sheet

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31 DATA_ERROR Synchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

The DATA_ERROR signal will be LOW when an error within the

received data stream has been detected by the device. This pin is a

logical 'OR'ing of all detectable errors listed in the internal

ERROR_STATUS register.

Once an error is detected, DATA_ERROR will remain LOW until the

start of the next video frame / field, or until the ERROR_STATUS

The DATA_ERROR signal will be HIGH when the received data stream

has been detected without error.

NOTE: It is possible to program which error conditions are monitored

by the device by setting appropriate bits of the ERROR_MASK register

HIGH. All error conditions are detected by default.

32 FIFO_LD Synchronous

with PCLK

Output CONTROL SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used as a control signal for external FIFO(s).

Normally HIGH but will go LOW for one PCLK period at SAV.

33, 68 CORE_GND – Power Ground connection for the digital core logic. Connect to digital GND.

34 F Synchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the ODD / EVEN field of the video signal.

The F signal will be HIGH for the entire period of field 2 as indicated

by the F bit in the received TRS signals.

The F signal will be LOW for all lines in field 1 and for all lines in

progressive scan systems.

35 V Synchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the portion of the video field / frame that is used for

vertical blanking.

The V signal will be HIGH for the entire vertical blanking period as

indicated by the V bit in the received TRS signals.

The V signal will be LOW for all lines outside of the vertical blanking

interval.

36 H Synchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the portion of the video line containing active video

data. H signal timing is configurable via the H_CONFIG bit of the

IOPROC_DISABLE register accessible via the host interface.

Active Line Blanking (H_CONFIG = 0h)

The H signal will be HIGH for the entire horizontal blanking period,

including the EAV and SAV TRS words, and LOW otherwise. This is the

default setting.

TRS Based Blanking (H_CONFIG = 1h)

The H signal will be HIGH for the entire horizontal blanking period as

indicated by the H bit in the received TRS ID words, and LOW

otherwise.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

14 of 79

37, 64 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V

DC digital.

38, 39,

42-48, 50

DOUT[0:9] Synchronous

with PCLK

Output PARALLEL DATA BUS

Signal levels are LVCMOS/LVTTL compatible.

DOUT9 is the MSB and DOUT0 is the LSB.

HD 20-bit mode

SD/HD = LOW

20bit/10bit = HIGH

Chroma data output in SMPTE mode

SMPTE_BYPASS =HIGH

DVB_ASI = LOW

Data output in Data-Through mode

SMPTE_BYPASS

= LOW

DVB_ASI = LOW

HD 10-bit mode

SD/HD = LOW

20bit/10bit = LOW

Forced LOW in all modes.

SD 20-bit mode

SD/HD = HIGH

20bit/10bit = HIGH

Chroma data output in SMPTE mode

SMPTE_BYPASS

= HIGH

DVB_ASI = LOW

Data output in Data-Through mode

SMPTE_BYPASS

= LOW

DVB_ASI = LOW

Forced LOW in DVB-ASI mode

SMPTE_BYPASS

= LOW

DVB_ASI = HIGH

SD 10-bit mode

SD/HD = HIGH

20bit/10bit = LOW

Forced LOW in all modes.

40, 49, 60 IO_GND – Power Ground connection for digital I/O buffers. Connect to digital GND.

41, 53, 61 IO_VDD – Power Power supply connection for digital I/O buffers. Connect to +3.3V DC

digital.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

15 of 79

51, 52,

54-59, 62,

DOUT[19:10] Synchronous

with PCLK

Output PARALLEL DATA BUS

Signal levels are LVCMOS/LVTTL compatible.

DOUT19 is the MSB and DOUT10 is the LSB.

HD 20-bit mode

SD/HD = LOW

20bit/10bit = HIGH

Luma data output in SMPTE mode

SMPTE_BYPASS = HIGH

DVB_ASI = LOW

Data output in Data-Through mode

SMPTE_BYPASS = LOW

DVB_ASI = LOW

HD 10-bit mode

SD/HD = LOW

20bit/10bit = LOW

Multiplexed Luma and Chroma data

output in SMPTE mode

SMPTE_BYPASS = HIGH

DVB_ASI = LOW

Data output in Data-Through mode

SMPTE_BYPASS = LOW

DVB_ASI = LOW

SD 20-bit mode

SD/HD = HIGH

20bit/10bit = HIGH

Luma data output in SMPTE mode

SMPTE_BYPASS = HIGH

DVB_ASI = LOW

Data output in Data-Through mode

SMPTE_BYPASS = LOW

DVB_ASI = LOW

DVB-ASI data in DVB-ASI mode

SMPTE_BYPASS = LOW

DVB_ASI = HIGH

SD 10-bit mode

SD/HD = HIGH

20bit/10bit = LOW

Multiplexed Luma and Chroma data

output in SMPTE mode

SMPTE_BYPASS

= HIGH

DVB_ASI = LOW

Data input in data through mode

SMPTE_BYPASS

= LOW

DVB_ASI = LOW

DVB-ASI data in DVB-ASI mode

SMPTE_BYPASS

= LOW

DVB_ASI = HIGH

65 YANCSynchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the presence of ancillary data in the video stream.

HD Mode (SD/HD = LOW)

The YANC signal will be HIGH when the device has detected VANC or

HANC data in the luma video stream and LOW otherwise.

SD Mode (SD/HD = LOW)

For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal

will be HIGH when VANC or HANC data is detected in the luma video

stream and LOW otherwise.

For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will

be HIGH when VANC or HANC data is detected anywhere in the data

stream and LOW otherwise.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

16 of 79

66 CANCSynchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to indicate the presence of ancillary data in the video stream.

HD Mode (SD/HD = LOW)

The CANC signal will be HIGH when the device has detected VANC or

HANC data in the chroma video stream and LOW otherwise.

SD Mode (SD/HD = LOW)

For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal

will be HIGH when VANC or HANC data is detected in the chroma

video stream and LOW otherwise.

For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will

be HIGH when VANC or HANC data is detected anywhere in the data

stream and LOW otherwise.

67 FW_EN/DISNon

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to enable or disable the noise immune flywheel of the device.

When set HIGH, the internal flywheel is enabled. This flywheel is used

in the extraction and generation of TRS timing signals, in automatic

video standards detection, and in manual switch line lock handling.

When set LOW, the internal flywheel is disabled and TRS correction

and insertion is unavailable.

69 PCLK – Output PARALLEL DATA BUS CLOCK

Signal levels are LVCMOS/LVTTL compatible.

HD 20-bit modePCLK = 74.25MHz or 74.25/1.001MHz

HD 10-bit modePCLK = 148.5MHz or 148.5/1.001MHz

SD 20-bit modePCLK = 13.5MHz

SD 10-bit modePCLK = 27MHz

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

17 of 79

70 RC_BYP Non

Synchronous

Input

/Outpu

GS1560A

CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT

Signal levels are LVCMOS/LVTTL compatible.

This pin will be an input set by the application layer in slave mode, and

will be an output set by the device in master mode.

Master Mode (MASTER/SLAVE = HIGH)

The RC_BYP signal will be HIGH only when the device has successfully

locked to a SMPTE compliant input data stream. In this case, the serial

digital loop-through output will be a reclocked version of the input.

The RC_BYP signal will be LOW whenever the input does not conform

to a SMPTE compliant data stream. In this case, the serial digital

loop-through output will be a buffered version of the input.

Slave Mode (MASTER/SLAVE = LOW)

When set HIGH, the serial digital output will be a reclocked version of

the input signal regardless of whether the device is in SMPTE, DVB-ASI

or Data-Through mode.

When set LOW, the serial digital output will be a buffered version of

the input signal in all modes.

RSV––GS1561

Connect to CORE_VDD through 2.2kΩ.

71 MASTER/SLAVE Non

Synchronous

Input CONTROL SIGNAL INPUT

Signal levels are LVCMOS/LVTTL compatible.

Used to determine the input / output selection for the DVB_ASI,

SD/HD, RC_BYP and SMPTE_BYPASS pins.

When set HIGH, the GS1560A is set to operate in master mode where

SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS become status

signal output pins set by the device. In this mode, the GS1560A will

automatically detect, reclock, deserialize and process SD SMPTE and

HD SMPTE input data.

When set LOW, the GS1560A is set to operate in slave mode where

DVB_ASI, SD/HD, RC_BYP (GS1560A only) and SMPTE_BYPASS become

control signal input pins. In this mode, the application layer must set

these external device pins for the correct reception of either SMPTE or

DVB-ASI data. Slave mode also supports the reclocking and

deserializing of data not conforming to SMPTE or DVB-ASI streams.

72 LOCKED Synchronous

with PCLK

Output STATUS SIGNAL OUTPUT

Signal levels are LVCMOS / LVTTL compatible.

The LOCKED signal will be HIGH whenever the device has correctly

received and locked to SMPTE compliant data in SMPTE mode or

DVB-ASI compliant data in DVB-ASI mode.

It will be LOW otherwise.

73, 74 VCO, VCOAnalogInput Differential inputs for the external VCO reference signal. For single

ended devices such as the GO1555/GO1525*, VCO should be AC

coupled to VCO_GND.

VCO is nominally 1.485GHz.

*For new designs use GO1555

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

18 of 79

75 VCO_GND – Output

Power

Ground reference for the external voltage controlled oscillator.

Connect to pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an

output.

Should be isolated from all other grounds.

*For new designs use GO1555

76 VCO_VCC – Output

Power

Power supply for the external voltage controlled oscillator. Connect to

pin 7 of the GO1555/GO1525*. This pin is an output.

Should be isolated from all other power supplies.

*For new designs use GO1555

77 LF AnalogOutput Control voltage to external voltage controlled oscillator. Nominally

+1.25V DC.

78 CP_CAP AnalogInput PLL lock time constant capacitor connection. Normally connected to

VCO_GND through 2.2nF.

79 LB_CONT AnalogInput Control voltage to set the loop bandwidth of the integrated reclocker.

Normally connected to VCO_GND through 40kΩ.

80 CP_GND – Power Ground connection for the charge pump. Connect to analog GND.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

19 of 79

2. Electrical Characteristics

2.1 Absolute Maximum Ratings

2.2 DC Electrical Characteristics

Parameter Value/Units

Supply Voltage Core -0.3V to +2.1V

Supply Voltage I/O -0.3V to +4.6V

Input Voltage Range (any input) -2.0V to + 5.25V

Ambient Operating Temperature -20°C < TA < 85°C

Storage Temperature -40°C < TSTG < 125°C

Lead Temperature (soldering, 10 sec) 230°C

ESD Protection On All Pins (see Note 2) 1kV

NOTES:

1. See reflow solder profile ( on page 21)

2. HBM, per JESDA-114B

Table 2-1: DC Electrical Characteristics

TA = 0°C to 70°C, unless otherwise specified.

Parameter Symbol Conditions Min Ty p Max Units Te st

Levels

Notes

System

Operation Temperature

Range

TA–0–70°C–1

Digital Core Supply VoltageCORE_VDD – 1.65 1.8 1.95 V 1 1

Digital I/O Supply Voltage IO_VDD – 3.0 3.3 3.6 V 1 1

Charge Pump Supply VoltageCP_VDD – 3.0 3.3 3.6 V 1 1

Phase Detector Supply

Voltage

PD_VDD – 1.65 1.8 1.95 V 1 1

Input Buffer Supply Voltage BUFF_VDD – 1.65 1.8 1.95 V 1 1

Cable Driver Supply VoltageCD_VDD – 1.71 1.8 1.89 V 1 1

External VCO Supply Voltage

Output

VCO_VCC – 2.25 2.50 2.75 V 1 –

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

20 of 79

+1.8V Supply Current

GS1560A

I1V8 – – – 245 mA 1 4

+1.8V Supply Current

GS1561

I1V8 – – – 200 mA 1 –

+3.3V Supply Current I3V3 –––55mA15

Total Device Power

GS1560A

PD– – – 625 mW 5 4, 5

Total Device Power

GS1561

PD– – – 545 mW 5 5

Digital I/O

Input Logic LOW VIL ––– 0.8V1–

Input Logic HIGHV

IH –2.1––V1–

Output Logic LOW VOL 8mA – 0.2 0.4 V 1 –

Output Logic HIGHV

OH 8mA IO_VDD - 0.4 – – V 1 –

Input

Input Bias VoltageV

B– – 1.45 – V 6 2

RSET Voltage

(GS1560A only)

VRSET RSET=281Ω0.54 0.6 0.66 V 1 3

Output (GS1560A only)

Output Common Mode

Voltage

VCMOUT 75Ω load,

RSET=281Ω,

SD and HD

0.8 1.0 1.2 V 1 –

TEST LEVELS

1. Production test at room temperature and nominal supply voltage

with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage

with guardbands for supply and temperature ranges using

correlated test.

3. Production test at room temperature and nominal supply

voltage.

4. QA sample test.

5. Calculated result based on Level 1, 2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of

similar product.

9. Indirect test.

NOTES

1. 6MHz sinewave modulation.

2. HD = 1080i, SD = 525i

3. Serial Digital Output Reclocked (RC_BYP = HIGH).

4. Serial Duty Cycle Distortion is defined here to be the difference

between the width of a ‘1’ bit, and the width of a ‘0’ bit. (GS1560A

only)

5. With 15pF load. (GS1560A only)

6. See Device Reset on page 70, Figure 4-16. (GS1560A only)

Table 2-2: AC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Units Tes t

Levels

Notes

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

24 of 79

3. Input/Output Circuits

All resistors in ohms, all capacitors in farads, unless otherwise shown.

Figure 3-1: Serial Digital Input

Figure 3-2: VCO Input

Figure 3-3: PLL Loop Bandwidth Control

VDD

DDI

45K

150K

TERM

VDD

VCO

1.5K

865mV 7.2K

LB_CONT

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

25 of 79

Figure 3-4: Serial Digital Output (GS1560A only)

Figure 3-5: VCO Control Output & PLL Lock Time Capacitor

SDO

300

CP_CAP

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Data Sheet

27360 - 12 June 2009

26 of 79

3.1 Host Interface Map

ERROR_MASK 01Ah Not UsedNot UsedNot UsedNot UsedNot UsedVD_STD_

ERR_MASK

FF_CRC_

ERR_MASK

AP_CRC_

ERR_MASK

LOCK_ERR_

MASK

CCS_ERR_

MASK

YCS_ERR_

MASK

CCRC_ERR_

MASK

YCRC_ERR_

MASK

LNUM_ERR

_MASK

SAV_ERR_

MASK

EAV_ERR_

MASK

FF_LINE_END_F1 019h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

FF_LINE_START_F1 018h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

FF_LINE_END_F0 017h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

FF_LINE_START_F0 016h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

AP_LINE_END_F1 015h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

AP_LINE_START_F1 014h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

AP_LINE_END_F0 013h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

AP_LINE_START_F0 012h Not UsedNot UsedNot UsedNot UsedNot UsedNot Usedb9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE4 011h Not UsedNot UsedNot UsedNot UsedNot Usedb10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE3 010h Not UsedNot UsedNot UsedNot UsedNot Usedb10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE2 00Fh Not UsedNot UsedNot UsedNot Usedb11 b10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE1 00Eh Not UsedNot UsedNot UsedNot Usedb11 b10 b9b8b7b6b5b4b3b2b1b0

VIDEO_FORMAT_OUT

00Dh VFO4-b7VFO4-b6VFO4-b5VFO4-b4VFO4-b3VFO4-b2VFO4-b1VFO4-b0VFO3-b7VFO3-b6VFO3-b5VFO3-b4VFO3-b3VFO3-b2VFO3-b1VFO3-b0

VIDEO_FORMAT_OUT

00ChVFO2-b7VFO2-b6VFO2-b5VFO2-b4VFO2-b3VFO2-b2VFO2-b1VFO2-b0VFO1-b7VFO1-b6VFO1-b5VFO1-b4VFO1-b3VFO1-b2VFO1-b1VFO1-b0

00Bh

00Ah

ANC_TYPE5 009h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE4 008h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE3 007h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE2 006h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE1 005h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

VIDEO_STANDARD 004h Not UsedVDS-b4VDS-b3VDS-b2VDS-b1VDS-b0INT_PROGSTD_

LOCK

CDF-b3CDF-b2CDF-b1CDF-b0YDF-b3YDF-b2YDF-b1YDF-b0

EDH_FLAG003h Not UsedANC-UESANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UESFF-IDA FF-IDH FF-EDA FF-EDH AP-UESAP-IDA AP-IDH AP-EDA AP-EDH

002h

ERROR_STATUS001h Not UsedNot UsedNot UsedNot UsedNot UsedVD_STD_

ERR

FF_CRC_

ERR

AP_CRC_

ERR

LOCK_ERR CCS_ERR YCS_ERR CCRC_ERR YCRC_ERR LNUM_ERR SAV_ERR EAV_ERR

IOPROC_DISABLE 000h Not UsedNot UsedNot UsedNot UsedNot UsedNot UsedNot UsedH_CONFIGNot UsedNot UsedILLEGAL_

REMAP

EDH_CRC_

INS

ANC_CSUM

_INS

CRC_INSLNUM_ INSTRS_INS

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

27 of 79

3.1.1 Host Interface Map (R/W Configurable Registers)

ERROR_MASK01Ah VD_STD_

ERR_MASK

FF_CRC_

ERR_MASK

AP_CRC_

ERR_MASK

LOCK_ERR_

MASK

CCS_ERR_

MASK

YCS_ERR_

MASK

CCRC_ERR_

MASK

YCRC_ERR_

MASK

LNUM_ERR

_MASK

SAV_ERR_

MASK

EAV_ERR_

MASK

FF_LINE_END_F1 019h b9b8b7b6b5b4b3b2b1b0

FF_LINE_START_F1 018h b9b8b7b6b5b4b3b2b1b0

FF_LINE_END_F0 017h b9b8b7b6b5b4b3b2b1b0

FF_LINE_START_F0 016h b9b8b7b6b5b4b3b2b1b0

AP_LINE_END_F1 015h b9b8b7b6b5b4b3b2b1b0

AP_LINE_START_F1 014h b9b8b7b6b5b4b3b2b1b0

AP_LINE_END_F0 013h b9b8b7b6b5b4b3b2b1b0

AP_LINE_START_F0 012h b9b8b7b6b5b4b3b2b1b0

011h

010h

00Fh

00Eh

00Dh

00Ch

00Bh

00Ah

ANC_TYPE5 009h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE4 008h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE3 007h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE2 006h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

ANC_TYPE1 005h b15 b14 b13 b12 b11 b10 b9b8b7b6b5b4b3b2b1b0

004h

003h

002h

001h

IOPROC_DISABLE 000h H_CONFIGILLEGAL_

REMAP

EDH_CRC_

ANC_CSUM

_INS

CRC_INSLNUM_ INSTRS_INS

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

28 of 79

3.1.2 Host Interface Map (Read Only Registers)

01Ah

019h

018h

017h

016h

015h

014h

013h

012h

RASTER_STRUCTURE4 011h b10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE3 010h b10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE2 00Fh b11 b10 b9b8b7b6b5b4b3b2b1b0

RASTER_STRUCTURE1 00Eh b11 b10 b9b8b7b6b5b4b3b2b1b0

VIDEO_FORMAT_OUT_

00Dh VFO4-b7VFO4-b6VFO4-b5VFO4-b4VFO4-b3VFO4-b2VFO4-b1VFO4-b0VFO3-b7VFO3-b6VFO3-b5VFO3-b4VFO3-b3VFO3-b2VFO3-b1VFO3-b0

VIDEO_FORMAT_OUT_

00ChVFO2-b7VFO2-b6VFO2-b5VFO2-b4VFO2-b3VFO2-b2VFO2-b1VFO2-b0VFO1-b7VFO1-b6VFO1-b5VFO1-b4VFO1-b3VFO1-b2VFO1-b1VFO1-b0

00Bh

00Ah

009h

008h

007h

006h

005h

VIDEO_STANDARD 004h VDS-b4VDS-b3VDS-b2VDS-b1VDS-b0INT_PROGSTD_

LOCK

CDF-b3CDF-b2CDF-b1CDF-b0YDF-b3YDF-b2YDF-b1YDF-b0

EDH_FLAG003h ANC-UESANC-IDA ANC-IDH ANC-EDA ANC-EDH FF-UESFF-IDA FF-IDH FF-EDA FF-EDH AP-UESAP-IDA AP-IDH AP-EDA AP-EDH

002h

ERROR_STATUS001h VD_STD_

ERR

FF_CRC_

ERR

AP_CRC_

ERR

LOCK_ERR CCS_ERR YCS_ERR CCRC_ERR YCRC_ERR LNUM_ERR SAV_ERR EAV_ERR

000h

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

29 of 79

4. Detailed Description

4.1 Functional Overview

The GS1560A/GS1561 is a dual-rate reclocking deserializer. An integrated serial digital

loop-through output is also included on the GS1560A only. When used in conjunction

with the multi-rate GS1524 Adaptive Cable Equalizer and the external

GO1555/GO1525* Voltage Controlled Oscillator, a receive solution at 1.485Gb/s,

1.485/1.001Gb/s or 270Mb/s is realized.

The device has two basic modes of operation which determine precisely how SMPTE or

DVB-ASI compliant input data streams are reclocked and processed.

In master mode, (MASTER/SLAVE = HIGH), the GS1560A/GS1561 will automatically

detect, reclock, deserialize and process SD SMPTE 259M-C or HD SMPTE 292M input

data.

In slave mode, (MASTER/SLAVE = LOW), the application layer must set external device

pins for the correct reception of either SMPTE or DVB-ASI data. Slave mode also

supports the reclocking and deserializing of data not conforming to SMPTE or DVB-ASI

streams.

The GS1560A includes an integrated cable driver is for serial input loop-through

applications. It can be selected to output either buffered or reclocked data. The cable

driver also features an output mute on loss of signal, high impedance mode, adjustable

signal swing, and automatic dual slew-rate selection depending on HD/SD operational

requirements.

In the digital signal processing core, several data processing functions are implemented

including error detection and correction and automatic video standards detection.

These features are all enabled by default, but may be individually disabled via internal

registers accessible through the GSPI host interface.

Finally, the GS1560A/GS1561 contains a JTAG interface for boundary scan test

implementations.

*For new designs use GO1555

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4.2 Serial Digital Input

The GS1560A/GS1561 contains two current mode differential serial digital input

buffers, allowing the device to be connected to two SMPTE 259M-C or 292M compliant

input signals.

Both input buffers have internal 50Ω termination resistors which are connected to

ground via the TERM1 and TERM2 pins. The input common mode level is set by internal

biasing resistors such that the serial digital input signals must be AC coupled into the

device. Gennum recommends using a capacitor value of 4.7uF to accommodate

pathological signals.

The input buffers use a separate power supply of +1.8V DC supplied via the BUFF_VDD

and PDBUFF_GND pins.

4.2.1 Input Signal Selection

A 2x1 input multiplexer is provided to allow the application layer to select between the

two serial digital input streams using a single external pin. When IP_SEL is set HIGH,

serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS1560A/GS1561's

reclocker stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected.

4.2.2 Carrier Detect Input

For each of the differential inputs, an associated carrier detect input signal is included,

(CD1 and CD2). These signals are generated by Gennum's family of automatic cable

equalizers.

When LOW, CDx indicates that a valid serial digital data stream is being delivered to the

GS1560A/GS1561 by the equalizer. When HIGH, the serial digital input to the device

should be considered invalid. If no equalizer precedes the device, the application layer

should set CD1 and CD2 accordingly.

NOTE: If the GS1524 Automatic Cable Equalizer is used, the MUTE/CD output signal

from that device must be translated to TTL levels before passing to the GS1560A/GS1561

CDx inputs. See GS1560A Typical Application Circuit (Part A) on page 71 for a

recommended transistor network that will set the correct voltage levels.

A 2x1 input multiplexer is also provided for these signals. The internal carrier_detect

signal is determined by the setting of the IP_SEL pin and is used by the lock detect block

of the GS1560A/GS1561 to determine the lock status of the device, (see Lock Detect on

page 34).

4.2.3 Single Input Configuration

If the application requires a single differential input, the second set of inputs may be left

unconnected. Tie the associated carrier detect pin HIGH, and leave the termination pin

unconnected.

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4.3 Serial Digital Reclocker

The output of the 2x1 serial digital input multiplexer passes to the GS1560A/GS1561's

internal reclocker stage. The function of this block is to lock to the input data stream,

extract a clean clock, and retime the serial digital data to remove high frequency jitter.

The reclocker was designed with a 'hexabang' phase and frequency detector. That is, the

PFD used can identify six 'degrees' of phase / frequency misalignment between the

input data stream and the clock signal provided by the VCO, and correspondingly signal

the charge pump to produce six different control voltages. This results in fast and

accurate locking of the PLL to the data stream.

In master mode, the operating center frequency of the reclocker is toggled between

270Mb/s and 1.485Gb/s by the lock detect block, (see Lock Detect on page 34). In slave

mode, however, the center frequency is determined entirely by the SD/HD input control

signal set by the application layer.

If lock is achieved, the reclocker provides an internal pll_lock signal to the lock detect

block of the device.

4.3.1 External VCO

The GS1560A/GS1561 requires the external GO1555/GO1525* Voltage Controlled

Oscillator as part of the reclocker's phase-locked loop. This external VCO

implementation was chosen to ensure high quality reclocking.

Power for the external VCO is generated entirely by the GS1560A/GS1561 from an

integrated voltage regulator. The internal regulator uses +3.3V DC supplied via the

CP_VDD / CP_GND pins to provide +2.5V DC on the VCO_VCC / VCO_GND pins.

The control voltage to the VCO is output from the GS1560A/GS1561 on the LF pin and

requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation.

The GO1555/GO1525* produces a 1.485GHz reference signal for the reclocker, input on

the VCO pin of the GS1560A/GS1561. Both LF and VCO signals should be referenced to

the supplied VCO_GND as shown in the recommended application circuit of GS1560A

Typical Application Circuit (Part A) on page 71.

*For new designs use GO1555

4.3.2 Loop Bandwidth

The loop bandwidth of the integrated reclocker is nominally 1.4MHz, but may be

increased or decreased via the LB_CONT pin. It is recommended that this pin be

connected to VCO_GND through 39.2kΩ to maximize the input jitter tolerance of the

device.

4.4 Serial Digital Loop-Through Output (GS1560A only)

The GS1560A contains an integrated current mode differential serial digital cable driver

with automatic slew rate control. When enabled, this serial digital output provides an

active loop-through of the input signal.

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To enable the loop-through output, SDO_EN/DIS must be set HIGH by the application

layer. Setting the SDO_EN/DIS signal LOW will cause the SDO and SDO output pins to

become high impedance, resulting in reduced device power consumption.

With suitable external return loss matching circuitry, the GS1560A's loop-through

outputs will provide a minimum output return loss of -15dB at SD rates. Gennum

recommends using the GS1528 SDI Dual Slew-Rate Cable Driver to meet output return

loss specifications at HD rates.

The integrated cable driver uses a separate power supply of +1.8V DC supplied via the

CD_VDD and CD_GND pins.

4.4.1 Output Swing

Nominally, the voltage swing of the serial digital loop-through output is 800mVp-p

single-ended into a 75Ω load. This is set externally by connecting the RSET pin to

CD_VDD through 281Ω.

The loop-through output swing may be decreased by increasing the value of the RSET

resistor. The relationship is approximated by the curve shown in Figure 4-1.

Alternatively, the serial digital output can drive 800mVp-p into a 50Ω load. Since the

output swing is reduced by a factor of approximately one third when the smaller load is

used, the RSET resistor must be 187Ω to obtain 800mVp-p.

Figure 4-1: Serial Digital Loop-Through Output Swing

300

400

500

600

700

800

900

1000

250 300 350 400 450 500 550 600 650 700 750

RSET(W)

DVSDO(mVp-p)

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4.4.2 Reclocker Bypass Control

The serial digital loop-through output may be either a buffered version of the serial

digital input signal, or a reclocked version of that signal.

When operating in slave mode, the application layer may choose the reclocked output

by setting RC_BYP to logic HIGH. If RC_BYP is set LOW, the data stream will bypass the

internal reclocker and the serial digital output will be a buffered version of the input.

When operating in master mode, the device will assert the RC_BYP pin HIGH only when

it has successfully locked to a SMPTE input data stream, (see Lock Detect on page 34). In

this case, the serial digital loop-through output will be a reclocked version of the input.

4.4.3 Serial Digital Output Mute

The GS1560A will automatically mute the serial digital loop-through output in both

master and slave modes when the internal carrier_detect signal indicates an invalid

serial input.

The loop-through output will also be muted in slave mode when SDO/SDO is selected as

reclocked, (RC_BYP = HIGH), but the lock detect block has failed to lock to the data

stream, (LOCKED = LOW).

Table 4-1 summarizes the possible states of the serial digital loop-through output data

stream.

Table 4-1: Serial Digital Loop-Through Output Status

SLAVE MODE

SDO CD LOCKED

RC_BYP

(INPUT)

RECLOCKED LOW HIGHHIGH

BUFFERED LOW X LOW

MUTED LOW LOW HIGH

MUTED HIGHLOW* X

MASTER MODE

SDO CD LOCKED

RC_BYP

(OUTPUT)

RECLOCKED LOW HIGHHIGH

BUFFERED LOW LOW LOW

MUTED HIGHLOW*LOW

*NOTE: LOCKED = HIGH if and only if CD = LOW

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4.5 Serial-To-Parallel Conversion

The retimed data and phase-locked clock signals from the reclocker are fed to the

serial-to-parallel converter. The function of this block is to extract 10-bit or 20-bit

parallel data words from the reclocked serial data stream and present them to the

SMPTE and DVB-ASI word alignment blocks simultaneously.

4.6 Modes Of Operation

The GS1560A/GS1561 has two basic modes of operation which determine how the lock

detect block controls the integrated reclocker. Master mode is enabled when the

application layer sets the MASTER/SLAVE pin HIGH, and slave mode is enabled when

MASTER/SLAVE is set LOW.

4.6.1 Lock Detect

The lock detect block controls the center frequency of the integrated reclocker to ensure

lock to the received serial digital data stream is achieved, and indicates via the LOCKED

output pin that the device has detected the appropriate sync words. In Data Through

mode, the detection for appropriate sync words is turned off. The LOCKED pin is an

indication of analog lock.

Lock detection is a continuous process, which begins at device power up or after a

system reset, and continues until the device is powered down or held in reset.

The lock detection algorithm first determines if a valid serial digital input signal has

been presented to the device by sampling the internal carrier_detect signal. As

described in Carrier Detect Input on page 30, this signal will be LOW when a good serial

digital input signal has been detected.

If the carrier_detect signal is HIGH, the serial data into the device is considered invalid,

and the VCO frequency will be set to the center of the pull range. The LOCKED pin will

be LOW and all outputs of the device except for the PCLK output will be muted. Instead,

the PCLK output frequency will operate within +/-3% of the rates shown in Table 4-16 of

Parallel Output Clock (PCLK) on page 66.

NOTE: When the device is operating in DVB-ASI slave mode, the parallel outputs will not

mute when the carrier_detect signal is HIGH. The LOCKED signal will function normally.

If a valid input signal has been detected, and the device is in master mode, the lock

algorithm will enter a hunt phase where four attempts are made to detect the presence

of either SMPTE TRS sync words. At each attempt, the center frequency of the reclocker

will be toggled between 270Mb/s and 1.485Gb/s.

Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device,

asynchronous lock times will be as listed in Table 2-2: AC Electrical Characteristics.

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In slave mode, the application layer fixes the center frequency of the reclocker such that

the lock algorithm will attempt to lock within the single data rate determined by the

setting of the SD/HD pin. Asynchronous lock times are also listed in the Table 2-2: AC

Electrical Characteristics.

NOTE: The PCLK output will continue to operate during the lock detection process. The

frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin is set

LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.

For SMPTE inputs, the lock detect block will only assert the LOCKED output signal HIGH

if (1) the reclocker has locked to the input data stream as indicated by the internal

pll_lock signal, and (2) TRS sync words have been correctly identified.

If after four attempts lock has not been achieved, the lock detection algorithm will enter

into PLL lock mode. In this mode, the reclocker will attempt to lock to the input data

stream without detecting SMPTE TRS words. This unassisted process can take up to

10ms to achieve lock.

When reclocker lock as indicated by the internal pll_lock signal is achieved in this mode,

one of the following will occur:

1. In slave mode, data will be passed directly to the parallel outputs without any

further processing taking place and the LOCKED signal will be asserted HIGH if and

only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW; or

2. In master mode, the LOCKED signal will be asserted LOW, the parallel outputs will

be latched to logic LOW, and the SMPTE_BYPASS output signal will also be set LOW.

4.6.2 Master Mode

Recall that the GS1560A/GS1561 is said to be in master mode when the MASTER/SLAVE

input signal is set HIGH. In this case, the following three device pins become output

status signals:

• SMPTE_BYPASS

•SD/HD

•RC_BYP (GS1560A only)

The combined setting of these pins will indicate whether the device has locked to valid

SMPTE data at SD or HD rates. DVB_ASI functionality is not supported in Master mode.

Table 4-2 shows the possible combinations.

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4.6.3 Slave Mode

The GS1560A/GS1561 is said to be in slave mode when the MASTER/SLAVE input signal

is set LOW. In this case, the device pins listed in Master Mode on page 35, in addition to

the DVB_ASI pin, become input control signals.

It is required that the application layer set the inputs to reflect the appropriate input data

format (SMPTE_BYPASS, DVB_ASI, and SD/HD). If just one of these pins is configured

incorrectly, the device will not lock to the input data stream, and the DATA_ERROR pin

will be set LOW.

The input signals, RC_BYP (GS1560A only), allows the application layer to determine

whether the serial digital loop-through output will be a reclocked or buffered version of

the input, Reclocker Bypass Control on page 33. Table 4-3 shows the required settings

for various input formats.

4.7 SMPTE Functionality

The GS1560A/GS1561 is said to be in SMPTE mode once the device has detected SMPTE

TRS sync words and locked to the input data stream as described in Lock Detect on

Table 4-2: Master Mode Output Status Signals

FORMAT

PIN SETTINGS

SMPTE_BYPASS SD/HD RC_BYP

(GS1560A only)

HD SMPTE HIGHLOWHIGH

SD SMPTE HIGHHIGHHIGH

NOT SMPTE* LOW HIGH OR LOW LOW

*NOTE: When the device locks to the data stream in PLL lock mode, the parallel outputs will

be latched LOW, and the serial loop-through output (GS1560A only) will be a buffered version

of the input.

Table 4-3: Slave Mode Control Signals

FORMAT

PIN SETTINGS

SMPTE_BYPASS DVB_ASI SD/HD

HD SMPTE HIGHLOWLOW

SD SMPTE HIGHLOWHIGH

DVB-ASILOWHIGHHIGH

NOT SMPTE OR

DVB-ASI*

LOW LOW HIGH OR LOW

*NOTE: See Data Through Mode on page 45 for a complete description of Data Through

mode.

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page 34. The device will remain in SMPTE mode until such time that SMPTE TRS sync

words fail to be detected.

The lock detect block may also drop out of SMPTE mode under the following conditions:

• RESET_TRST is asserted LOW

•CDx

is HIGH

• SMPTE_BYPASS is asserted LOW in slave mode

• DVB_ASI is asserted HIGH in slave mode

TRS word detection is a continuous process and both 8-bit and 10-bit TRS words will be

identified by the device in both SD and HD modes.

In master mode, the GS1560A/GS1561 sets the SMPTE_BYPASS pin HIGH to indicate

that it has locked to a SMPTE input data stream. When operating in slave mode, the

application layer must assert the DVB_ASI pin LOW and the SMPTE_BYPASS pin HIGH

in order to enable SMPTE operation.

4.7.1 SMPTE Descrambling and Word Alignment

After serial-to-parallel conversion, the internal 10-bit or 20-bit data bus is fed to the

SMPTE descramble and word alignment block. The function of this block is to carry out

NRZI-to-NRZ decoding, descrambling according to SMPTE 259M or 292M, and word

alignment of the data to the TRS sync words.

Word alignment occurs when two consecutive valid TRS words (SAV and EAV inclusive)

with the same bit alignment have been detected.

In normal operation, re-synchronization of the word alignment process will only take

place when two consecutive identical TRS word positions have been detected. When

automatic or manual switch line lock handling is 'actioned', (see Switch Line Lock

Handling on page 38), word alignment re-synchronization will occur on the next

received TRS code word.

4.7.2 Internal Flywheel

The GS1560A/GS1561 has an internal flywheel which is used in the generation of

internal / external timing signals, in the detection and correction of certain error

conditions and in automatic video standards detection. It is only operational in SMPTE

mode.

The flywheel consists of a number of counters and comparators operating at video pixel

and video line rates. These counters maintain information about the total line length,

active line length, total number of lines per field / frame, and total active lines per field

/ frame for the received video stream.

The flywheel 'learns' the video standard by timing the horizontal and vertical reference

information contained in the TRS ID words of the received video stream. Full

synchronization of the flywheel to the received video standard therefore requires one

complete video frame.

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Once synchronization has been achieved, the flywheel will continue to monitor the

received TRS timing information to maintain synchronization.

The FW_EN/DIS input pin controls the synchronization mechanism of the flywheel.

When this input signal is LOW, the flywheel will re-synchronize all pixel and line based

counters on every received TRS ID word.

When FW_EN/DIS is held HIGH, re-synchronization of the pixel and line based counters

will only take place when a consistent synchronization error has been detected. Two

consecutive video lines with identical TRS timing different to the current flywheel

timing must occur to initiate re-synchronization of the counters. This provides a

measure of noise immunity to internal and external timing signal generation.

The flywheel will be disabled should the LOCKED signal or the RESET_TRST signal be

LOW. A LOW to HIGH transition on either signal will cause the flywheel to re-acquire

synchronization on the next received TRS word, regardless of the setting of the

FW_EN/DIS pin.

4.7.3 Switch Line Lock Handling

The principal of switch line lock handling is that the switching of synchronous video

sources will only disturb the horizontal timing and alignment of the stream, whereas the

vertical timing remains in synchronization.

To account for the horizontal disturbance caused by a synchronous switch, it is

necessary to re-synchronize the flywheel immediately after the switch has taken place.

Rapid re-synchronization of the GS1560A/GS1561 to the new video standard can be

achieved by controlling the flywheel using the FW_EN/DIS pin.

At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH

transition at this pin is detected anywhere within the active line, the flywheel will

re-synchronize immediately to the next TRS word. This is shown in Figure 4-2.

To ensure switch line lock handling, the FW_EN/DIS signal should be LOW for a

minimum of one PCLK cycle (maximum one video line) anywhere within the active

portion of the line on which the switch has taken place.

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Figure 4-2: Switch Line Locking

The ability to manually re-synchronize the flywheel is also important when switching

asynchronous sources or to implement other non-standardized video switching

functions.

The GS1560A/GS1561 also implements automatic switch line lock handling. By utilizing

the synchronous switch points defined by SMPTE RP168 for all major video standards

with the automatic video standards detect function, the device automatically

re-synchronizes the flywheel at the switch point.

This function will occur regardless of the setting of the FW_EN/DIS pin.

EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC

ACTIVE PICTURE

SAV

EAV ANC SAV

Video source 1

EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC SAV

ACTIVE PICTURE EAV ANC SAV

Video source 2

EAV ANC ACTIVE PICTURESAV EAV ANC SAV

DATA IN

ACTIVE PICTURE EAV ANC SAVANCACTIVE PICTURE EAV ANC SAV

Switch point

Flywheel TRS

position

EAV ANC ACTIVE PICTURESAV EAV ANC SAV ANCACTIVE PICTURE

DATA OUT

ACTIVE PICTURE EAV ANC SAVEAV ANC SAV

FW_EN/DIS

switch video source 1 to 2

Flywheel re-synch

EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC

ACTIVE PICTURE

SAV

EAV ANC SAV

Video source 1

EAV ANC ACTIVE PICTURE EAV ANCSAV EAV ANC ACTIVE PICTURESAV EAV ANC SAV

ACTIVE PICTURE EAV ANC SAV

Video source 2

EAV ANC ACTIVE PICTURESAV EAV ANC SAV

DATA IN

ACTIVE PICTURE EAV ANC SAVACTIVE PICTURE EAV ANC SAV

Switch point

Flywheel TRS

position

EAV ANC ACTIVE PICTURESAV EAV ANC SAV ACTIVE PICTURE

DATA OUT

switch video source 2 to 1

EAV ANC SAV ACTIVE PICTURE EAV ANC SAV

Flywheel re-synch

FW_EN/DIS

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The switch line is defined as follows:

• For 525 line interlaced systems: re-sync takes place at the end of lines 10 & 273.

• For 525 line progressive systems: re-sync takes place at the end of line 10.

• For 625 line interlaced systems: re-sync takes place at the end of lines 6 & 319.

• For 625 line progressive systems: re-sync takes place at the end of line 6.

• For 750 line progressive systems: re-sync takes place at the end of line 7.

• For 1125 line interlaced systems: re-sync takes place at the end of lines 7 & 568.

• For 1125 line progressive systems: re-sync takes place at the end of line 7.

A full list of all major video standards and switching lines is shown in Table 4-4.

NOTE 1: The flywheel timing will define the line count such that the line numbers shown

in Table 4-4 may not correspond directly to the digital line counts.

NOTE 2: Unless indicated by SMPTE 352M payload identifier packets, the

GS1560A/GS1561 will not distinguish between 50/60 frames PsF and 25/30 frames

interlaced for the 1125 line video systems; 24 PsF will be identified.

Table 4-4: Switch Line Position for Digital Systems

System Video Format Sampling Signal

Standard

Parallel

Interface

Serial

Interface

Switch Line

No.

HD-SDTI 1920x1080 (PsF) 4:2:2 274M 274M + 348M 292M 7

1920x1080 (2:1) 4:2:2 274M 274M + 348M 292M 7, 569

1280x720 (1:1) 4:2:2 296M 296M + 348M 292M 7

SDTI 720x576/50 (2:1) 4:2:2 BT.656 BT.656 + 305M 259M 6, 319

720x483/59.94 (2:1) 4:2:2 125M 125M + 305M 259M 10, 273

750 1280x720/60 (1:1) 4:2:2 296M 296M 296M 7

1280x720/50 (1:1) 4:2:2 296M 296M 296M 7

1280x720/30 (1:1) 4:2:2 296M 296M 296M 7

1280x720/25 (1:1) 4:2:2 296M 296M 296M 7

1280x720/24 (1:1) 4:2:2 296M 296M 296M 7

1125 1920x1080/30 (PsF) 4:2:2 274M + RP211 274M + RP211 292M 7

1920x1080/25 (PsF) 4:2:2 274M + RP211 274M + RP211 292M 7

1920x1080/24 (PsF) 4:2:2 274M + RP211 274M + RP211 292M 7

1920x1080/60 (2:1) 4:2:2 274M + RP211 274M + RP211 292M 7, 569

1920x1080/50 (2:1) 4:2:2 274M + RP211 274M + RP211 292M 7, 569

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525 960x483/59.94 (2:1) 4:2:2 267M 349M 292M 10, 273

960x483/59.94 (2:1) 4:2:2 267M 267M 259M 10, 273

720x483/59.94 (2:1) 4:4:4:4 267M 349M 292M 10, 273

720x483/59.94 (2:1) 4:4:4:4 267M 347M 344M 10, 273

720x483/59.94 (2:1) 4:4:4:4 267M RP174 344M 10, 273

720x483/59.94 (2:1) 4:4:4:4 267M RP175 RP175 10, 273

720x483/59.94 (2:1) 4:2:2 125M 349M 292M 10, 273

720x483/59.94 (2:1) 4:2:2 125M 125M 259M 10, 273

720x483/59.94 (1:1) 4:2:2 293M 349M 292M 10

720x483/59.94 (1:1) 4:2:2 293M 347M 344M 10

720x483/59.94 (1:1) 4:2:2 293M 293M 294M 10

720x483/59.94 (1:1) 4:2:0 293M 349M 292M 10

720x483/59.94 (1:1) 4:2:0 293M 293M 294M 10

625 720x576/50 (1:1) 4:2:2 BT.1358 349M 292M 6

720x576/50 (1:1) 4:2:2 BT.1358 347M 344M 6

720x576/50 (1:1) 4:2:2 BT.1358 BT.1358 BT.1362 6

720x576/50 (1:1) 4:2:0 BT.1358 349M 292M 6

720x576/50 (1:1) 4:2:0 BT.1358 BT.1358 BT.1362 6

960x576/50 (2:1) 4:2:2 BT.601 349M 292M 6, 319

960x576/50 (2:1) 4:2:2 BT.601 BT.656 259M 6, 319

720x576/50 (2:1) 4:4:4:4 BT.799 349M 292M 6, 319

720x576/50 (2:1) 4:4:4:4 BT.799 347M 344M 6, 319

720x576/50 (2:1) 4:4:4:4 BT.799 BT.799 344M 6, 319

720x576/50 (2:1) 4:4:4:4 BT.799 BT.799 – 6, 319

720x576/50 (2:1) 4:2:2 BT.601 349M 292M 6, 319

720x576/50 (2:1) 4:2:2 BT.601 125M 259M 6, 319

Table 4-4: Switch Line Position for Digital Systems

System Video Format Sampling Signal

Standard

Parallel

Interface

Serial

Interface

Switch Line

No.

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4.7.4 HVF Timing Signal Generation

The GS1560A/GS1561 extracts critical timing parameters from either the received TRS

signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator

(FW_EN/DIS = HIGH).

Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F)

timing are all extracted and presented to the application layer via the H:V:F status

output pins.

The H signal timing is configurable via the H_CONFIG bit of the internal

IOPROC_DISABLE register as either active line based blanking, or TRS based blanking,

(see Error Correction and Insertion on page 60).

Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this mode,

the H output is HIGH for the entire horizontal blanking period, including the EAV and

SAV TRS words. This is the default H timing used by the device.

When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H output

will be HIGH for the entire horizontal blanking period as indicated by the H bit in the

received TRS ID words.

The timing of these signals is shown in Figure 4-3.

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Figure 4-3: H, V, F Timing

H:V:F TIMING - HD 20-BIT OUTPUT MODE

PCLK

LUMA DATA OUT

CHROMA DATA OUT

XYZ

(eav)

0000003FF

XYZ

(eav)

0000003FF

XYZ

(sav)

0000003FF

XYZ

(sav)

0000003FF

H;V:F TIMING AT SAV - HD 10-BIT OUTPUT MODE

0000003FF3FF XYZ

(sav)

000000 XYZ

(sav)

PCLK

H:V:F TIMING AT EAV - HD 10-BIT OUTPUT MODE

PCLK

0000003FF3FF XYZ

(eav)

000000 XYZ

(eav)

MULTIPLEXED

Y/Cr/Cb DATA OUT

MULTIPLEXED

Y/Cr/Cb DATA OUT

H:V:F TIMING - SD 20-BIT OUTPUT MODE

PCLK

CHROMA DATA OUT

LUMA DATA OUT

0003FF

XYZ

(eav)

000

0003FF

XYZ

(SAV)

000

H:V:F TIMING - SD 10-BIT OUTPUT MODE

MULTIPLEXED

Y/Cr/Cb DATA OUT

PCLK

XYZ

(eav)

0000003FF XYZ

(sav)

0000003FF

H SIGNAL TIMING:

H_CONFIG = LOW

H_CONFIG = HIGH

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4.8 DVB-ASI Functionality

The GS9060 conforms to DVB-ASI standard EN 50083-9:1998.

The lock detect block may drop out of DVB-ASI mode under the following conditions:

• RESET_TRST is asserted LOW

•CDx

is HIGH

• SMPTE_BYPASS is asserted HIGH in slave mode

• DVB_ASI is asserted LOW in slave mode

DVB_ASI functionality is only supported in Slave mode. To operate in DVB_ASI mode,

the device must be in Slave mode, and the application layer must set the SD/HD pin

HIGH, in addition to setting SMPTE_BYPASS LOW and DVB_ASI HIGH.

4.8.1 Transport Packet Format

Transport packet structure shall conform to the specifications of EN/ISO/IEC 13818-1

and ETS 300 429 for Transport Stream Packets. The packet length can be 188 or 204

bytes.

4.8.2 DVB-ASI 8b/10b Decoding and Word Alignment

After serial-to-parallel conversion, the internal 10-bit data bus is fed to the DVB-ASI

8b/10b decode and word alignment block. The function of this block is to word align the

data to the K28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve

bit alignment with the data outputs.

The extracted 8-bit data will be presented to DOUT[17:10], bypassing all internal SMPTE

mode data processing.

NOTE: When operating in DVB-ASI mode, DOUT[9:0] are forced LOW.

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4.8.3 Status Signal Outputs

In DVB-ASI mode, the DOUT19 and DOUT18 pins will be configured as DVB-ASI status

signals SYNCOUT and WORDERR respectively.

SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output. This

output may be used to drive the write enable signal of an external FIFO, thus providing

a means of removing the K28.5 sync characters from the data stream. Parallel DVB-ASI

data may then be clocked out of the FIFO at some rate less than 27MHz. See Figure 4-4.

WORDERR will be high whenever the device has detected a running disparity error or

illegal code word.

Figure 4-4: DVB-ASI FIFO Implementation Using The GS1560A

4.9 Data Through Mode

The GS1560A/GS1561 may be configured by the application layer to operate as a simple

serial-to-parallel converter. In this mode, the device presents data to the output data bus

without performing any decoding, descrambling or word-alignment.

Data through mode is enabled only when the MASTER/SLAVE, SMPTE_BYPASS, and

DVB_ASI input pins are set LOW. Under these conditions, the lock detection algorithm

enters PLL lock mode, (see Lock Detect on page 34), such that the device may reclock

data not conforming to SMPTE or DVB-ASI streams. The LOCKED pin will indicated

analog lock.

When operating in master mode, the GS1560A/GS1561 will set the SMPTE_BYPASS

signal to logic LOW if presented with a data stream without SMPTE TRS ID words. The

LOCKED and data bus outputs will be forced LOW and the serial digital loop-through

output (GS1560A only) will be a buffered version of the input.

4.10 Additional Processing Functions

The GS1560A/GS1561 contains an additional data processing block which is available

in SMPTE mode only, (see SMPTE Functionality on page 36).

AOUT ~ HOUT

WORDERR

PCLK = 27MHz

SYNCOUT

DDI

CLK_IN

CLK_OUT

FIFO

DDI

READ_CLK

<27MHz

WORDERR

GS1560A / GS1561

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4.10.1 FIFO Load Pulse

To aid in the application-specific implementation of auto-phasing and line

synchronization functions, the GS1560A/GS1561 will generate a FIFO load pulse to

reset line-based FIFO storage.

The FIFO_LD output pin will normally be HIGH but will go LOW for one PCLK period,

thereby generating a FIFO write reset signal.

The FIFO load pulse will be generated such that it is co-timed to the SAV XYZ code word

presented to the output data bus. This ensures that the next PCLK cycle will correspond

to the first active sample of the video line.

Figure 4-5 shows the timing relationship between the FIFO_LD signal and the output

video data.

Figure 4-5: FIFO_LD Pulse Timing

PCLK

LUMA DATA OUT

CHROMA DATA OUT

FIFO_LD

3FF 3FF

3FF

000 000000000 XYZ

(SAV)

000

XYZ

(SAV)

XYZ

(SAV)

XYZ

(SAV)

MULTIPLEXED

Y/Cr/Cb DATA OUT

PCLK

FIFO_LD

FIFO LOAD PULSE - HD 10BIT OUTPUT MODE

FIFO LOAD PULSE - HD 20BIT OUTPUT MODE

3FF

000

000 XYZ

(SAV)

MULTIPLEXED

Y/Cr/Cb DATA OUT

PCLK

LUMA DATA OUT

CHROMA DATA OUT

FIFO_LD

XYZ

(SAV)

FIFO LOAD PULSE - SD 10BIT OUTPUT MODE

FIFO LOAD PULSE - SD 20BIT OUTPUT MODE

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4.10.2 Ancillary Data Detection and Indication

The GS1560A/GS1561 will detect all types of ancillary data in either the vertical or

horizontal blanking spaces and indicate via the status signal output pins YANC and

CANC the position of ancillary data in the output data stream. These status signal

outputs are synchronous with PCLK and can be used as clock enables to external logic,

or as write enables to an external FIFO or other memory device.

When operating in HD mode, (SD/HD = LOW), the YANC signal will be HIGH whenever

ancillary data is detected in the luma data stream, and the CANC signal will be HIGH

whenever ancillary data is detected in the chroma data stream.

In SD mode, (SD/HD = HIGH), the YANC and CANC signal operation will depend on the

output data format. For 20-bit demultiplexed data, (see Parallel Data Outputs on

page 64), the YANC and CANC signals will operate independently. However, for 10-bit

multiplexed data, the YANC and CANC signals will both be HIGH whenever ancillary

data is detected.

The signals will be HIGH from the start of the ancillary data preamble and will remain

HIGH until after the ancillary data checksum.

The operation of the YANC and CANC signals is shown in Figure 4-6.

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Figure 4-6: YANC and CANC Output Signal Timing

ANC DATA DETECTION - HD 20BIT OUTPUT MODE

ANC DATA DETECTION - HD 10BIT OUTPUT MODE

000

000 000

3FF

3FF 3FF3FF 3FF

DID

YDID

DID DBN

DBN

ANC DATA

ANC DATA ANC DATA

BLANK BLANKCSUM

CSUM

CANC YCSUM CCSUM

YANC

CANC

PCLK

LUMA DATA OUT

CHROMA DATA OUT

MULTIPLEXED

Y/Cr/Cb DATA OUT

YANC

CANC

PCLK

BLANK

DID

DBN

ANC DATA

ANC DATA ANC DATA

ANC DATA

BLANK

CSUM

3FF

000

DID

3FF

DBN

3FF

DC ANC DATA

ANC DATA DETECTION - SD 20BIT OUTPUT MODE

ANC DATA DETECTION - SD 10BIT OUTPUT MODE

PCLK

MULTIPLEXED

Y/Cr/Cb DATA OUT

YANC/CANC

PCLK

LUMA DATA OUT

CHROMA DATA OUT

YANC

CANC

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4.10.2.1 Programmable Ancillary Data Detection

Although the GS1560A/GS1561 will detect all types of ancillary data by default, it also

allows the host interface to specifically program up to five different ancillary data types

for detection. This is accomplished via the ANC_TYPE register (Table 4-5).

For each data type to be detected, the host interface must program the DID and/or SDID

of the ancillary data type of interest. The GS1560A/GS1561 will compare the received

DID and/or SDID with the programmed values and assert YANC and CANC only if an

exact match is found.

If any DID or SDID value is set to zero in the ANC_TYPE register, no comparison or match

will be made for that value. For example, if the DID is programmed but the SDID is set to

zero, the device will detect all ancillary data types matching the DID value, regardless of

the SDID.

In the case where all five DID and SDID values are set to zero, the GS1560A/GS1561 will

detect all ancillary data types. This is the default setting after device reset.

Where one or more, but less than five, DID and/or SDID values have been programmed,

then only those matching ancillary data types will be detected and indicated.

NOTE 1: The GS1560A/GS1561 will always detect EDH ancillary data packets for EDH

error detection purposes, regardless of which DID/SDID values have been programmed

for ancillary data indication, (see EDH CRC Error Detection on page 57).

NOTE 2: See SMPTE 291M for a definition of ancillary data terms.

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Table 4-5: Host Interface Description for Programmable Ancillary Data Type Registers

ANC_TYPE1

Address: 005h

15-8 ANC_TYPE1[15:8] Used to program the DID for ancillary data

detection at the YANC and CANC output

R/W 0

7-0 ANC_TYPE1[7:0] Used to program the SDID for ancillary data

detection at the YANC and CANC output.

Should be set to zero if no SDID is present in the

ancillary data packet to be detected.

R/W 0

ANC_TYPE2

Address: 006h

15-8 ANC_TYPE2[15:8] Used to program the DID for ancillary data

detection at the YANC and CANC output

R/W 0

7-0 ANC_TYPE2[7:0] Used to program the SDID for ancillary data

detection at the YANC and CANC output.

Should be set to zero if no SDID is present in the

ancillary data packet to be detected.

R/W 0

ANC_TYPE3

Address: 007h

15-8 ANC_TYPE3[15:8] Used to program the DID for ancillary data

detection at the YANC and CANC output

R/W 0

7-0 ANC_TYPE3[7:0] Used to program the SDID for ancillary data

detection at the YANC and CANC output.

Should be set to zero if no SDID is present in the

ancillary data packet to be detected.

R/W 0

ANC_TYPE4

Address: 008h

15-8 ANC_TYPE4[15:8] Used to program the DID for ancillary data

detection at the YANC and CANC output

R/W 0

7-0 ANC_TYPE4[7:0] Used to program the SDID for ancillary data

detection at the YANC and CANC output.

Should be set to zero if no SDID is present in the

ancillary data packet to be detected.

R/W 0

ANC_TYPE5

Address: 009h

15-8 ANC_TYPE5[15:8] Used to program the DID for ancillary data

detection at the YANC and CANC output

R/W 0

7-0 ANC_TYPE5[7:0] Used to program the SDID for ancillary data

detection at the YANC and CANC output.

Should be set to zero if no SDID is present in the

ancillary data packet to be detected.

R/W 0

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4.10.3 SMPTE 352M Payload Identifier

The GS1560A/GS1561 can receive and detect the presence of the SMPTE 352M payload

identifier ancillary data packet. This four word payload identifier packet may be used to

indicate the transport mechanism, frame rate and line scanning / sampling structure.

Upon reception of this packet, the device will extract the four words describing the

video format being transported and make this information available to the host interface

via the four VIDEO_FORMAT_OUT registers (Table 4-6).

The VIDEO_FORMAT_OUT registers will only be updated if the received checksum is

the same as the locally calculated checksum.

These registers will be cleared to zero, indicating an undefined format, if the device loses

lock to the input data stream (LOCKED = LOW), or if the SMPTE_BYPASS pin is asserted

LOW. This is also the default setting after device reset.

The SMPTE 352M packet should be received once per field for interlaced systems and

once per frame for progressive systems. If the packet is not received for two complete

video frames, the VIDEO_FORMAT_OUT registers will be cleared to zero.

4.10.4 Automatic Video Standard and Data Format Detection

The GS1560A/GS1561 can independently detect the input video standard and data

format by using the timing parameters extracted from the received TRS ID words. This

information is presented to the host interface via the VIDEO_STANDARD register

(Table 4-7).

Total samples per line, active samples per line, total lines per field/frame and active lines

per field/frame are also calculated and presented to the host interface via the

RASTER_STRUCTURE registers (Table 4-8). These line and sample count registers are

updated once per frame at the end of line 12. This is in addition to the information

contained in the VIDEO_STANDARD register.

After device reset, the four RASTER_STRUCTURE registers default to zero.

Table 4-6: Host Interface Description for SMPTE 352M Payload Identifier Registers

VIDEO_FORMAT_OUT_B

Address: 00Dh

15-8 SMPTE352M

Byte 4

Data will be available in this register when Video

Payload Identification Packets are detected in the data

stream.

7-0 SMPTE352M

Byte 3

Data will be available in this register when Video

Payload Identification Packets are detected in the data

stream.

VIDEO_FORMAT_OUT_A

Address: 00Ch

15-8 SMPTE352M

Byte 2

Data will be available in this register when Video

Payload Identification Packets are detected in the data

stream.

7-0 SMPTE352M

Byte 1

Data will be available in this register when Video

Payload Identification Packets are detected in the data

stream.

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4.10.4.1 Video Standard Indication

The video standard codes reported in the VD_STD[4:0] bits of the VIDEO_STANDARD

In addition to the 5-bit video standard code word, the VIDEO_STANDARD register also

contains two status bits. The STD_LOCK bit will be set HIGH whenever the flywheel has

achieved full synchronization. The INT_PROG bit will be set LOW if the detected video

standard is progressive and HIGH if the detected video standard is interlaced.

The VD_STD[4:0], STD_LOCK and INT_PROG bits of the VIDEO_STANDARD register

will default to zero after device reset. The VD_STD[4:0] and INT_PROG bits will also

default to zero if the device loses lock to the input data stream, (LOCKED = LOW), or if

the SMPTE_BYPASS pin is asserted LOW. The STD_LOCK bit will retain its previous

value if the input is removed.

Table 4-7: Host Interface Description for Video Standard and Data Format Register

VIDEO_STANDARD

Address: 004h

15 – Not Used.––

14-10 VD_STD[4:0] Video Data Standard (see Table 4-9). R 0

9INT_PROGInterlace/Progressive: Set LOW if detected video

standard is PROGRESSIVE and is set HIGH if it is

INTERLACED.

8STD_LOCKStandard Lock: Set HIGH when flywheel has

achieved full synchronization.

7-4 CDATA_FORMAT[3:0] Chroma Data Format. Set HIGH in SD mode.

Indicates chroma data format in HD mode (see

Table 4-10).

3-0 YDATA_FORMAT[3:0] Luma Data Format. Indicates Luma data format in

HD mode and data format in SD mode (see

Table 4-10).

Table 4-8: Host Interface Description for Raster Structure Registers

RASTER_STRUCTURE1

Address: 00Eh

15-12 – Not Used.––

11-0 RASTER_STRUCTURE1[11:0] Words Per Active Line. R 0

RASTER_STRUCTURE2

Address: 00Fh

15-12 – Not Used.––

11-0 RASTER_STRUCTURE2[11:0] Words Per Total Line. R 0

RASTER_STRUCTURE3

Address: 010h

15-11 – Not Used.––

10-0 RASTER_STRUCTURE3[10:0] Total Lines Per Frame. R 0

RASTER_STRUCTURE4

Address: 011h

15-11 – Not Used.––

10-0 RASTER_STRUCTURE4[10:0] Active Lines Per Field.R0

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Table 4-9: Supported Video Standards

VD_STD[4:0] SMPTE

Standard

Video Format Length of

HANC

Length of

Active Video

Tota l

Samples

SMPTE352M

Lines

00h 296M (HD) 1280x720/60 (1:1) 358 1280 1650 13

01h 296M (HD) 1280x720/60 (1:1) - EM 198 1440 1650 13

02h 296M (HD) 1280x720/30 (1:1) 2008 1280 3300 13

03h 296M (HD) 1280x720/30 (1:1) - EM 408 2880 3300 13

04h 296M (HD) 1280x720/50 (1:1) 688 1280 1980 13

05h 296M (HD) 1280x720/50 (1:1) - EM 240 1728 1980 13

06h 296M (HD) 1280x720/25 (1:1) 2668 1280 3960 13

07h 296M (HD) 1280x720/25 (1:1) - EM 492 3456 3960 13

08h 296M (HD) 1280x720/24 (1:1) 2833 1280 4125 13

09h 296M (HD) 1280x720/24 (1:1) - EM 513 3600 4125 13

0Ah 274M (HD) 1920x1080/60 (2:1) or

1920x1080/30 (PsF)

268 1920 2200 10, 572

0Bh 274M (HD) 1920x1080/30 (1:1) 268 1920 2200 18

0Ch 274M (HD) 1920x1080/50 (2:1) or

1920x1080/25 (PsF)

708 1920 2640 10, 572

0Dh 274M (HD) 1920x1080/25 (1:1) 708 1920 2640 18

0Eh 274M (HD) 1920x1080/25 (1:1) - EM 324 2304 2640 18

0Fh 274M (HD) 1920x1080/25 (PsF) - EM 324 2304 2640 10, 572

10h 274M (HD) 1920x1080/24 (1:1) 818 1920 2750 18

11h 274M (HD) 1920x1080/24 (PsF) 818 1920 2750 10, 572

12h 274M (HD) 1920x1080/24 (1:1) - EM 338 2400 2750 18

13h 274M (HD) 1920x1080/24 (PsF) - EM 338 2400 2750 10, 572

14h 295M (HD) 1920x1080/50 (2:1) 444 1920 2376 10, 572

15h 260M (HD) 1920x1035/60 (2:1) 268 1920 2200 10, 572

16h 125M (SD) 1440x487/60 (2:1)

(Or dual link

progressive)

268 1440 1716 13, 276

17h 125M (SD) 1440x507/60 (2:1) 268 1440 1716 13, 276

19h 125M (SD) 525-line 487 generic– – 1716 13, 276

1Bh 125M (SD) 525-line 507 generic– – 1716 13, 276

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4.10.4.2 Data Format Indication

The luma and chroma data format codes will be reported in the YDATA_FORMAT[3:0]

and CDATA_FORMAT[3:0] bits of the VIDEO_STANDARD register when the device is

operating in HD mode, (SD/HD = LOW).

In SD or DVB-ASI mode, the data format code will only appear in the

YDATA_FORMAT[3:0] bits. The CDATA_FORMAT[3:0] bits will be set to 'Fh'. These codes

represent the data formats listed in Table 4-10.

The YDATA_FORMAT[3:0] and CDATA_FORMAT[3:0] bits of the VIDEO_STANDARD

device loses lock to the input data stream, (LOCKED = LOW), or if Data-Through mode is

enabled, (see Data Through Mode on page 45).

18h ITU-R BT.656

(SD)

1440x576/50 (2:1)

(Or dual link

progressive)

280 1440 1728 9, 322

1Ah ITU-R BT.656

(SD)

625-line generic (EM) – – 1728 9, 322

1Dh Unknown HD – – – – –

1Eh Unknown SD– – – – –

1Ch, 1Fh Reserved–––––

Table 4-9: Supported Video Standards (Continued)

VD_STD[4:0] SMPTE

Standard

Video Format Length of

HANC

Length of

Active Video

Tota l

Samples

SMPTE352M

Lines

Table 4-10: Data Format Codes

YDATA_FORMAT[3:0] or

CDATA_FORMAT[3:0]

Data Format Applicable

Standards

0h SDTI DVCPRO - No ECC SMPTE 321M

1h SDTI DVCPRO - ECC SMPTE 321M

2h SDTI DVCAM SMPTE 322M

3h SDTI CPSMPTE 326M

4h Other SDTI fixed block size –

5h Other SDTI variable block size –

6h SDI –

7h DVB-ASI–

8h TDM data SMPTE 346M

9h ~ Eh Reserved–

Fh Unknown data format –

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4.10.5 Error Detection and Indication

The GS1560A/GS1561 contains a number of error detection functions to enhance

operation of the device when operating in SMPTE mode. These functions, (except lock

error detection), will not be available in either DVB-ASI or Data-Through operating

modes. See DVB-ASI Functionality on page 44 and Data Through Mode on page 45.

The device maintains an error status register at address 001h called ERROR_STATUS

(Table 4-11). Each type of error has a specific flag or bit in this register which is set HIGH

whenever that error is detected.

The ERROR_STATUS register will be cleared at the start of each video field or when read

by the host interface, which ever condition occurs first.

All bits of the ERROR_STATUS register except the LOCK_ERR bit will also be cleared if a

change in the video standard is detected, or under the following conditions:

• RESET_TRST is held LOW

• LOCKED is asserted LOW

• SMPTE_BYPASS is asserted LOW in slave mode

In addition to the ERROR_STATUS register, a register called ERROR_MASK (Table 4-12)

is included which allows the host interface to select the specific error conditions that

will be detected. There is one bit in the ERROR_MASK register for each type of error

represented in the ERROR_STATUS register.

The bits of the ERROR_MASK register will default to '0' after device reset, thus enabling

all error types to be detected. The host interface may disable individual error detection

by setting the corresponding bit HIGH in this register.

Error conditions are also indicated to the application layer via the status signal pin

DATA_ERROR. This output pin is a logical 'OR'ing of each error status flag stored in the

ERROR_STATUS register. DATA_ERROR is normally HIGH, but will be set LOW by the

device when an error condition that has not been masked is detected.

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Table 4-11: Host Interface Description for Error Status Register

ERROR_STATUS

Address: 001h

15-11 – Not Used.––

10 VD_STD_ERR Video Standard Error Flag. Set HIGH when a

mismatch between the received SMPTE352M

packets and the calculated video standard occurs.

9FF_CRC_ERR Full Field CRC Error Flag. Set HIGH in SD mode when

a Full Field (FF) CRC mismatch has been detected in

Field 1 or 2.

8AP_CRC_ERR Active Picture CRC Error Flag. Set HIGH in SD mode

when an Active Picture (AP) CRC mismatch has been

detected in Field 1 or 2.

7LOCK_ERR Lock Error Flag. Set HIGH whenever the LOCK pin is

LOW (indicating the device not correctly locked).

6CCS_ERR Chroma Checksum Error Flag. Set HIGH when

ancillary data packet checksum error has been

detected in the C channel.

5YCS_ERR Luma Checksum Error Flag. Set HIGH when ancillary

data packet checksum error has been detected in

the Y channel.

4CCRC_ERR Chroma CRC Error Flag. Set HIGH in HD mode when

a mismatch occurs between the calculated and

received CRC values in the C channel.

CRC_ERR Luma CRC Error Flag. Set HIGH in HD mode when a

mismatch occurs between the calculated and

received CRC values in the Y channel.

2 LNUM_ERR Line Number Error Flag. Set HIGH in HD mode when

a mismatch occurs between the calculated and

received line numbers.

1SAV_ERR Start of Active Video Error Flag. Set HIGH when TRS

errors are detected in either 8-bit or 10-bit TRS

words. In HD mode only Y channel TRS codes will be

checked. FW_EN/DIS must be set HIGH.

0EAV_ERR End of Active Video Error Flag. Set HIGH when TRS

errors are detected in either 8-bit or 10-bit TRS

words. In HD mode only Y channel TRS codes will be

checked. FW_EN/DIS must be set HIGH.

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4.10.5.1 Video Standard Error Detection

If a mismatch between the received SMPTE 352M packets and the calculated video

standard occurs, the GS1560A/GS1561 will indicate a video standard error by setting

the VD_STD_ERR bit of the ERROR_STATUS register HIGH.

4.10.5.2 EDH CRC Error Detection

The GS1560A/GS1561 calculates Full Field (FF) and Active Picture (AP) CRC words

according to SMPTE RP165 in support of Error Detection and Handling packets in SD

signals.

These calculated CRC values are compared with the received CRC values. If a mismatch

is detected, the error is flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of the

ERROR_STATUS register. These two flags are shared between fields 1 and 2.

The AP_CRC_ERR bit will be set HIGH when an active picture CRC mismatch has been

detected in field 1 or 2. The FF_CRC_ERR bit will be set HIGH when a full field CRC

mismatch has been detected in field 1 or 2.

EDH CRC errors will only be indicated when the device is operating in SD mode (SD/HD

= HIGH), and when the device has correctly received EDH packets.

SMPTE RP165 specifies the calculation ranges and scope of EDH data for standard 525

and 625 component digital interfaces. The GS1560A/GS1561 will utilize these standard

ranges by default.

If the received video format does not correspond to 525 or 625 digital component video

standards as determined by the flywheel pixel and line counters, then one of two

schemes for determining the EDH calculation ranges will be employed:

Table 4-12: Host Interface Description for Error Mask Register

ERROR_MASK

Address: 01Ah

15-11 – Not Used.––

10 VD_STD_ERR_MASKVideo Standard Error Flag Mask bit. R/W 0

9FF_CRC_ERR_MASK Full Field CRC Error Flag Mask bit. R/W 0

8AP_CRC_ERR_MASKActive Picture CRC Error Flag Mask bit. R/W 0

7LOCK_ERR_MASKLock Error Flag Mask bit. R/W 0

6CCS_ERR_MASKChroma Checksum Error Flag Mask bit. R/W 0

5YCS_ERR_MASKLuma Checksum Error Flag Mask bit. R/W 0

4CCRC_ERR_MASKChroma CRC Error Flag Mask bit. R/W 0

3YCRC_ERR_MASKLuma CRC Error Flag Mask bit. R/W 0

2 LNUM_ERR_MASKLine Number Error Flag Mask bit. R/W 0

1SAV_ERR_MASKStart of Active Video Error Flag Mask bit. R/W 0

0EAV_ERR_MASKEnd of Active Video Error Flag Mask bit. R/W 0

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1. Ranges will be based on the line and pixel ranges programmed by the host

interface; or

2. In the absence of user-programmed calculation ranges, ranges will be determined

from the received TRS timing information.

The registers available to the host interface for programming EDH calculation ranges

include active picture and full field line start and end positions for both fields. Table 4-13

shows the relevant registers, which default to '0' after device reset.

If any or all of these register values are zero, then the EDH CRC calculation ranges will

be determined from the flywheel generated H signal. The first active and full field pixel

will always be the first pixel after the SAV TRS code word. The last active and full field

pixel will always be the last pixel before the start of the EAV TRS code words.

Table 4-13: Host Interface Description for EDH Calculation Range Registers

AP_LINE_START_F0

Address: 012h

15-10 – Not Used.––

9-0 AP_LINE_START_F0[9:0] Field 0 Active Picture start line data used to set

EDH calculation range outside of SMPTE RP 165

values.

R/W 0

AP_LINE_END_F0

Address: 013h

15-10 – Not Used.––

9-0 AP_LINE_END_F0[9:0] Field 0 Active Picture end line data used to set

EDH calculation range outside of SMPTE RP 165

values.

R/W 0

AP_LINE_START_F1

Address: 014h

15-10 – Not Used.––

9-0 AP_LINE_START_F1[9:0] Field 1 Active Picture end line data used to set

EDH calculation range outside of SMPTE RP 165

values.

R/W 0

AP_LINE_END_F1

Address: 015h

15-10 – Not Used.––

9-0 AP_LINE_END_F1[9:0] Field 1 Active Picture end line data used to set

EDH calculation range outside of SMPTE RP 165

values.

R/W 0

FF_LINE_START_F0

Address: 016h

15-10 – Not Used.––

9-0 FF_LINE_START_F0[9:0] Field 0 Full Field start line data used to set EDH

calculation range outside of SMPTE RP 165

values.

R/W 0

FF_LINE_END_F0

Address: 017h

15-10 – Not Used.––

9-0 FF_LINE_END_F0[9:0] Field 0 Full Field start line data used to set EDH

calculation range outside of SMPTE RP 165

values.

R/W 0

FF_LINE_START_F1

Address: 018h

15-10 – Not Used.––

9-0 FF_LINE_START_F1[9:0] Field 1 Full Field start line data used to set EDH

calculation range outside of SMPTE RP 165

values.

R/W 0

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4.10.5.3 Lock Error Detection

The LOCKED pin of the GS1560A/GS1561 indicates the lock status of the reclocker and

lock detect blocks of the device. Only when the LOCKED pin is asserted HIGH has the

device correctly locked to the received data stream, (see Lock Detect on page 34).

The GS1560A/GS1561 will also indicate lock error to the host interface when LOCKED

= LOW by setting the LOCK_ERR bit in the ERROR_STATUS register HIGH.

4.10.5.4 Ancillary Data Checksum Error Detection

The GS1560A/GS1561 will calculate checksums for all received ancillary data and

compare the calculated values to the received checksum words. If a mismatch is

detected, the error is flagged in the CCS_ERR and/or YCS_ERR bits of the

ERROR_STATUS register.

When operating in HD mode, (SD/HD = LOW), the device will make comparisons on

both the Y and C channels separately. If an error condition in the Y channel is detected,

the YCS_ERR bit will be set HIGH. If an error condition in the C channel is detected, the

CCS_ERR bit will be set HIGH.

When operating in SD mode, (SD/HD = HIGH), only the YCS_ERR bit will be set HIGH

when checksum errors are detected.

Although the GS1560A/GS1561 will calculate and compare checksum values for all

ancillary data types by default, the host interface may program the device to check only

certain types of ancillary data checksums.

This is accomplished via the ANC_TYPE register as described in Programmable

Ancillary Data Detection on page 49.

FF_LINE_END_F1

Address: 019h

15-10 – Not Used.––

9-0 FF_LINE_END_F1[9:0] Field 1 Full Field end line data used to set EDH

calculation range outside of SMPTE RP 165

values.

R/W 0

Table 4-13: Host Interface Description for EDH Calculation Range Registers (Continued)

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4.10.5.5 Line Based CRC Error Detection

The GS1560A/GS1561 will calculate line based CRC words for HD video signals for both

the Y and C data channels. These calculated CRC values are compared with the received

CRC values and any mismatch is flagged in the YCRC_ERR and/or CCRC_ERR bits of the

ERROR_STATUS register.

Line based CRC error flags will only be generated when the device is operating in HD

mode, (SD/HD = LOW).

If a CRC error is detected in the Y channel, the YCRC_ERR bit in the error status register

will be set HIGH. If a CRC error is detected in the C channel, the CCRC_ERR bit in the

error status register is set HIGH. Y and C CRC errors will also be generated if CRC values

are not received.

4.10.5.6 HD Line Number Error Detection

When operating in HD mode, the GS1560A/GS1561 will calculate line numbers based

on the timing generated by the internal flywheel. These calculated line numbers are

compared with the received line numbers for the Y channel data and any mismatch is

flagged in the LNUM_ERR bit of the ERROR_STATUS.

Line number errors will also be generated if line number values are not received.

4.10.5.7 TRS Error Detection

TRS errors flags are generated by the GS1560A/GS1561 when:

1. The received TRS timing does not correspond to the internal flywheel timing; or

2. The received TRS hamming codes are incorrect.

Both 8-bit and 10-bit SAV and EAV TRS words are checked for timing and data integrity

errors. These are flagged via the SAV_ERR and/or EAV_ERR bits of the ERROR_STATUS

Timing-based TRS errors will only be generated if the FW_EN/DIS pin is set HIGH.

NOTE: In HD mode, (SD/HD = LOW), only the Y channel TRS codes will be checked for

errors.

4.10.6 Error Correction and Insertion

In addition to signal error detection and indication, the GS1560A/GS1561 may also

correct certain types of errors by inserting corrected code words, checksums and CRC

values into the data stream. These features are only available in SMPTE mode and

IOPROC_EN/DIS must be set HIGH. Individual correction features may be enabled or

disabled via the IOPROC_DISABLE register (Table 4-14).

All of the IOPROC_DISABLE register bits default to '0' after device reset, enabling all of

the processing features. To disable any individual error correction feature, the host

interface must set the corresponding bit HIGH in the IOPROC_DISABLE register.

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4.10.6.1 Illegal Code Remapping

If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS1560A

will remap all codes within the active picture between the values of 3FCh and 3FFh to

3FBh. All codes within the active picture area between the values of 000h and 003h will

be re-mapped to 004h.

In addition, 8-bit TRS and ancillary data preambles will be remapped to 10-bit values if

this feature is enabled.

4.10.6.2 EDH CRC Error Correction

The GS1560A/GS1561 will generate and insert active picture and full field CRC words

into the EDH data packets received by the device. This feature is only available in SD

mode and is enabled by setting the EDH_CRC_INS bit of the IOPROC_DISABLE register

LOW.

EDH CRC calculation ranges are described in EDH CRC Error Detection on page 57.

NOTE: Although the GS1560A/GS1561 will modify and insert EDH CRC words and EDH

packet checksums, EDH error flags will not be updated by the device.

Table 4-14: Host Interface Description for Internal Processing Disable Register

IOPROC_DISABLE

Address: 000h

15-9 – Not Used.––

8H_CONFIGHorizontal sync timing output configuration. Set

LOW for active line blanking timing. Set HIGH for H

blanking based on the H bit setting of the TRS

words. See Figure 4-2.

7-6 – Not Used.––

5ILLEGAL_REMAP Illegal Code re-mapping. Correction of illegal code

words within the active picture. Set HIGH to disable.

The IOPROC_EN/DIS pin must be set HIGH.

R/W 0

4 EDH_CRC_INSError Detection & Handling (EDH) Cyclical

Redundancy Check (CRC) error correction insertion.

In SD mode set HIGH to disable. The IOPROC_EN/DIS

pin must be set HIGH.

R/W 0

3ANC_CSUM_INSAncillary Data Check-sum insertion. Set HIGH to

disable. The IOPROC_EN/DIS pin must be set HIGH.

R/W 0

2CRC_INSY and C line based CRC insertion. In HD mode, inserts

line based CRC words in both the Y and C channels.

Set HIGH to disable. The IOPROC_EN/DIS pin must be

set HIGH.

R/W 0

1LNUM_INSY and C line number insertion. In HD mode set HIGH

to disable. The IOPROC_EN/DIS pin must be set HIGH.

R/W 0

0TRS_INSTiming Reference Signal Insertion. Set HIGH to

disable. The IOPROC_EN/DIS pin must be set HIGH.

R/W 0

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4.10.6.3 Ancillary Data Checksum Error Correction

When ancillary data checksum error correction and insertion is enabled, the

GS1560A/GS1561 will generate and insert ancillary data checksums for all ancillary

data words by default. Where user specified ancillary data has been programmed into

the device, (see Programmable Ancillary Data Detection on page 49), only the

checksums for the programmed ancillary data types will be corrected.

This feature is enabled when the ANC_CSUM_INS bit of the IOPROC_DISABLE register

is set LOW.

4.10.6.4 Line Based CRC Correction

The GS1560A/GS1561 will generate and insert line based CRC words into both the Y and

C channels of the data stream. This feature is only available in HD mode and is enabled

by setting the CRC_INS bit of the IOPROC_DISABLE register LOW.

4.10.6.5 HD Line Number Error Correction

In HD mode, the GS1560A/GS1561 will calculate and insert line numbers into the Y and

C channels of the output data stream.

Line number generation is in accordance with the relevant HD video standard as

determined by the device, (see Automatic Video Standard and Data Format Detection on

page 51).

This feature is enabled when SD/HD = LOW, and the LNUM_INS bit of the

IOPROC_DISABLE register is set LOW.

4.10.6.6 TRS Error Correction

When TRS error correction and insertion is enabled, the GS1560A/GS1561 will generate

and insert 10-bit TRS code words as required.

TRS word generation will be performed in accordance with the timing parameters

generated by the flywheel to provide an element of noise immunity. As a result, TRS

correction will only take place if the flywheel is enabled, (FW_EN/DIS = HIGH).

In addition, the TRS_INS bit of the IOPROC_DISABLE register must be set LOW.

4.10.7 EDH Flag Detection

As described in EDH CRC Error Detection on page 57, the GS1560A/GS1561 can detect

EDH packets in the received data stream. The EDH flags for ancillary data, active picture

and full field areas are extracted from the detected EDH packets and placed in the

EDH_FLAG register of the device (Table 4-15).

One set of flags is provided for both fields 1 and 2. Field 1 flag data will be overwritten

by field 2 flag data.

The EDH_FLAG register may be read by the host interface at any time during the

received frame except on the lines defined in SMPTE RP165 where these flags are

updated.

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NOTE 1: By programming the ANC_TYPE1 register (005h) with the DID word for EDH

ancillary packets, the application layer may detect a high-to-low transition on either the

YANC or CANC output pin of the GS1560A/GS1561 to determine (a) when EDH packets

have been received by the device, and (b) when the EDH_FLAG register can be read by

the host interface. See Ancillary Data Detection and Indication on page 47 for more

information on ancillary data detection and indication.

NOTE 2: The bits of the EDH_FLAG register are sticky and will not be cleared by a read

operation. If the GS1560A/GS1561 is decoding a source containing EDH packets, where

EDH flags may be set, and the source is replaced by one without EDH packets, the

EDH_FLAG register will not be cleared.

NOTE 3: The GS1560A/GS1561 will detect EDH flags, but will not update the flags if an

EDH CRC error is detected. Gennum's GS1532 Multi-Rate Serializer allows the host to

individually set EDH flags.

Table 4-15: Host Interface Description for EDH Flag Register

EDH_FLAG

Address: 003h

15 – Not Used.––

14 ANC-UES out Ancillary Unknown Error Status Flag.R0

13 ANC-IDA out Ancillary Internal device error Detected Already Flag.R0

12 ANC-IDH out Ancillary Internal device error Detected Here Flag.R0

11 ANC-EDA out Ancillary Error Detected Already Flag.R0

10 ANC-EDH out Ancillary Error Detected Here Flag.R0

9FF-UES out Full Field Unknown Error Status Flag.R0

8 FF-IDA out Full Field Internal device error Detected Already Flag.R0

7 FF-IDH out Full Field Internal device error Detected Here Flag.R0

6 FF-EDA out Full Field Error Detected Already Flag.R0

5 FF-EDH out Full Field Error Detected Here Flag.R0

4AP-UES out Active Picture Unknown Error Status Flag.R0

3AP-IDA out Active Picture Internal device error Detected Already

Flag.

2AP-IDH out Active Picture Internal device error Detected Here Flag.R 0

1 AP-EDA out Active Picture Error Detected Already Flag.R0

0 AP-EDH out Active Picture Error Detected Here Flag.R0

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4.11 Parallel Data Outputs

Data outputs leave the device on the rising edge of PCLK as shown in Figure 4-7 and

Figure 4-8.

The data may be scrambled or unscrambled, framed or unframed, and may be presented

in 10-bit or 20-bit format. The output data bus width is controlled independently from

the internal data bus width by the 20bit/10bit input pin.

Likewise, the output data format is defined by the setting of the external SD/HD,

SMPTE_BYPASS and DVB_ASI pins. Recall that in slave mode, these pins are set by the

application layer as inputs to the device. In master mode, however, the GS1560A sets the

SD/HD and SMPTE_BYPASS pins as output status signals.

4.11.1 Parallel Data Bus Buffers

The parallel data outputs of the GS1560A/GS1561 are driven by high-impedance buffers

which support both LVTTL and LVCMOS levels. These buffers use a separate power

supply of +3.3V DC supplied via the IO_VDD and IO_GND pins.

All output buffers, including the PCLK output, may be driven to a high-impedance state

if the RESET_TRST signal is asserted LOW.

Note that the timing characteristics of the parallel data output buffers are optimized for

10-bit HD operation. As shown in Figure 4-7, the output data hold time for HD is 1.5ns.

Due to this optimization, however, the output data hold time for SD data is so small that

the rising edge of the PCLK is nearly incident with the data transition. To improve output

hold time at SD rates, the PCLK output is inverted is SD mode, (SD/HD = HIGH). This is

shown in Figure 4-8.

Figure 4-7: HD PCLK to Data Timing

PCLK

DOUT[19:0] DATA

Control signal

output

HD MODE

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Figure 4-8: SD PCLK to Data Timing

4.11.2 Parallel Output in SMPTE Mode

When the device is operating in SMPTE mode, (see SMPTE Functionality on page 36),

both SD and HD data may be presented to the output bus in either multiplexed or

demultiplexed form depending on the setting of the 20bit/10bit input pin.

In 20-bit mode, (20bit/10bit = HIGH), the output data will be word aligned,

demultiplexed luma and chroma data. Luma words will always appear on DOUT[19:10]

while chroma words will occupy DOUT[9:0].

In 10-bit mode, (20bit/10bit = LOW), the output data will be word aligned, multiplexed

luma and chroma data. The data will be presented on DOUT[19:10], and the device will

force DOUT[9:0] LOW.

4.11.3 Parallel Output in DVB-ASI Mode

When operating in DVB-ASI mode, (see DVB-ASI Functionality on page 44), the

GS1560A/GS1561 automatically configures the output port for 10-bit operation

regardless of the setting of the 20bit/10bit pin.

The extracted 8-bit data words will be presented on DOUT[17:10] such that DOUT17 =

HOUT is the most significant bit of the decoded transport stream data and DOUT10 =

AOUT is the least significant bit.

In addition, DOUT19 and DOUT18 will be configured as the DVB-ASI status signals

SYNCOUT and WORDERR respectively. See Status Signal Outputs on page 45 for a

description of these DVB-ASI specific output signals.

DOUT[9:0] will be forced LOW when the GS1560A/GS1561 is operating in DVB-ASI

mode.

4.11.4 Parallel Output in Data-Through Mode

When operating in Data-Through mode, (see Data Through Mode on page 45), the

GS1560A/GS1561 presents data to the output data bus without performing any

decoding, descrambling or word-alignment.

PCLK

DOUT[19:0] DATA

Control signal

output

SD MODE

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As described in Data Through Mode on page 45, the data bus outputs will be forced to

logic LOW if the device is set to operate in master mode but cannot identify SMPTE TRS

ID words in the input data stream.

4.11.5 Parallel Output Clock (PCLK)

The frequency of the PCLK output signal of the GS1560A/GS1561 is determined by the

output data format. Table 4-16 below lists the possible output signal formats and their

corresponding parallel clock rates. Note that DVB-ASI output will always be in 10-bit

format, regardless of the setting of the 20bit/10bit pin.

Table 4-16: Parallel Data Output Format

Output Data Format DOUT

[19:10]

DOUT

[9:0]

PCLK

Status / Control Signals*

20bit/

10bit

SD/HD SMPTE_BYPASS DVB_ASI

SMPTE MODE

20bit DEMULTIPLEXED SDLUMA CHROMA 13.5MHz HIGHHIGHHIGHLOW

10bit MULTIPLEXED SD LUMA /

CHROMA

FORCED

LOW

27MHz LOW HIGHHIGHLOW

20bit DEMULTIPLEXED HD LUMA CHROMA 74.25 or

74.25/

1.001MHz

HIGHLOWHIGHLOW

10bit MULTIPLEXED HD LUMA /

CHROMA

FORCED

LOW

148.5 or

148.5/

1.001MHz

LOW LOW HIGHLOW

DVB-ASI MODE

10bit DVB-ASIDVB-ASI

DATA

FORCED

LOW

27MHz HIGHHIGHLOW HIGH

DVB-ASI

DATA

FORCED

LOW

27MHz LOW HIGHLOW HIGH

DATA-THROUGH MODE**

20bit DEMULTIPLEXED SD DATA DATA 13.5MHz HIGHHIGHLOW LOW

10bit MULTIPLEXED SDDATA FORCED

LOW

27MHz LOW HIGHLOW LOW

20bit DEMULTIPLEXED HD DATA DATA 74.25 or

74.25/

1.001MHz

HIGH LOW LOW LOW

10bit MULTIPLEXED HD DATA FORCED

LOW

148.5 or

148.5/

1.001MHz

LOW LOW LOW LOW

*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but

the SD/HD and SMPTE_BYPASS pins are output status signals set by the device in master mode.

**NOTE 2: Data-Through mode is only available in slave mode Data Through Mode on page 45.

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4.12 GSPI Host Interface

The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow

the host to enable additional features of the device and /or to provide additional status

information through configuration registers in the GS1560A/GS1561.

The GSPI comprises a serial data input signal SDIN, serial data output signal SDOUT, an

active low chip select CS, and a burst clock SCLK. The burst clock must have a duty cycle

between 40% and 60%.

Because these pins are shared with the JTAG interface port, an additional control signal

pin JTAG/HOST is provided. When JTAG/HOST is LOW, the GSPI interface is enabled.

When operating in GSPI mode, the SCLK, SDIN, and CS signals are provided by the host

interface. The SDOUT pin is a high-impedance output allowing multiple devices to be

connected in parallel and selected via the CS input. The interface is illustrated in

Figure 4-9.

All read or write access to the GS1560A/GS1561 is initiated and terminated by the host

processor. Each access always begins with a 16-bit command word on SDIN indicating

the address of the register of interest. This is followed by a 16-bit data word on SDIN in

write mode, or a 16-bit data word on SDOUT in read mode.

Figure 4-9: Gennum Serial Peripheral Interface (GSPI)

4.12.1 Command Word Description

The command word is transmitted MSB first and contains a read/write bit, nine reserved

bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to write from the GSPI.

Command words are clocked into the GS1560A/GS1561 on the rising edge of the serial

clock SCLK. The appropriate chip select, CS, signal must be asserted low a minimum of

1.5ns (t0 in Figure 4-12 and Figure 4-13) before the first clock edge to ensure proper

operation.

Each command word must be followed by only one data word to ensure proper

operation.

Figure 4-10: Command Word

SCLK

SDOUT

SDIN

SCLK

SDIN

SDOUT

Application Host GS1560A / GS1561

R/W RSV RSV RSV A0A1A2A3A4A5RSVRSVRSVRSVRSV RSV

MSB LSB

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Figure 4-11: Data Word

4.12.2 Data Read and Write Timing

Read and write mode timing for the GSPI interface is shown in Figure 4-12 and

Figure 4-13 respectively. The maximum SCLK frequency allowed is 6.6MHz.

When writing to the registers via the GSPI, the MSB of the data word may be presented

to SDIN immediately following the falling edge of the LSB of the command word. All

SDIN data is sampled on the rising edge of SCLK.

When reading from the registers via the GSPI, the MSB of the data word will be available

on SDOUT 12ns following the falling edge of the LSB of the command word, and thus

may be read by the host on the very next rising edge of the clock. The remaining bits are

clocked out by the GS1560A on the negative edges of SCLK.

Figure 4-12: GSPI Read Mode Timing

Figure 4-13: GSPI Write Mode Timing

4.12.3 Configuration and Status Registers

Table 4-17 summarizes the GS1560A/GS1561's internal status and configuration

registers.

All of these registers are available to the host via the GSPI and are all individually

addressable.

Where status registers contain less than the full 16 bits of information however, two or

more registers may be combined at a single logical address.

D15 D14 D13 D12 D0D1D2

D3D4

D6D7

D11 D10

MSB LSB

SDOUT

R/W RSV RSV A0A1

A2A3

RSV

RSVRSV

D15 D14 D13 D12 D0

D4D5

D11 D10

SCLK

SDIN RSV

t0t2

t3input data

setup time

duty

cycle t4period t5

t6output data

hold time

R/W RSV RSV A0A1

A2A3

RSV

RSVRSV D15 D14 D13 D12 D0

D4D5

D11 D10

SCLK

SDIN RSV

t0t2

t3input data

setup time

duty

cycle t4period

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4.13 JTAG

When the JTAG/HOST input pin of the GS1560A/GS1561 is set HIGH, the host interface

port will be configured for JTAG test operation. In this mode, pins 27 through 30 become

TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate as the test reset

pin.

Boundary scan testing using the JTAG interface will be enabled in this mode.

There are two methods in which JTAG can be used on the GS1560A/GS1561:

1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test

Equipment) during PCB assembly; or

2. Under control of the host for applications such as system power on self tests.

When the JTAG tests are applied by ATE, care must be taken to disable any other devices

driving the digital I/O pins. If the tests are to be applied only at ATE, this can be

accomplished with tri-state buffers used in conjunction with the JTAG/HOST input

signal. This is shown in Figure 4-14.

Figure 4-14: In-Circuit JTAG

Table 4-17: GS1560A Internal Registers

Address Register Name See Section

000h IOPROC_DISABLE Section 4.10.6

001h ERROR_STATUSSection 4.10.5

003h EDH_FLAGSection 4.10.7

004h VIDEO_STANDARD Section 4.10.4

005h - 009h ANC_TYPE Section 4.10.2.1

00Ch - 00Dh VIDEO_FORMAT Section 4.10.3

00Eh - 011h RASTER_STRUCTURE Section 4.10.4

012h - 019h EDH_CALC_RANGESSection 4.10.5.2

01Ah ERROR_MASKSection 4.10.5

Application HOST GS1560A / GS1561

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

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Alternatively, if the test capabilities are to be used in the system, the host may still

control the JTAG/HOST input signal, but some means for tri-stating the host must exist

in order to use the interface at ATE. This is represented in Figure 4-15.

Figure 4-15: System JTAG

Please contact your Gennum representative to obtain the BSDL model for the

GS1560A/GS1561.

4.14 Device Power Up

The GS1560A/GS1561 has a recommended power supply sequence. To ensure correct

power up, power the CORE_VDD pins before the IO_VDD pins.

Device pins may also be driven prior to power up without causing damage.

To ensure that all internal registers are cleared upon power-up, the application layer

must hold the RESET_TRST signal LOW for a minimum of 1ms after the core power

supply has reached the minimum level specified in Table 2-1. See Figure 4-16.

4.15 Device Reset

In order to initialize all internal operating conditions to their default states the

application layer must hold the RESET_TRST signal LOW for a minimum of treset = 1ms.

When held in reset, all device outputs will be driven to a high-impedance state.

Figure 4-16: Reset Pulse

Application HOST GS1560A / GS1561

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

Tri-State

CORE_VDD

RESET_TRST

treset

+1.65V +1.8V

Reset Reset

treset

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5. Application Reference Design

5.1 GS1560A Typical Application Circuit (Part A)

EQ_VCC

GS1524

VEE

VCC

CLI

VCCA

VEEA

SDI

RSVD

SDI

VEEA

MUTE/CD

BYPASS

MCLADJ

VEE

SDO

RSVD

SDO

2N4400

2N4402

37R4

10K

GS1524

VEE

VCC

CLI

VCCA

VEEA

SDI

RSVD

SDI

VEEA

MUTE/CD

BYPASS

MCLADJ

VEE

SDO

RSVD

SDO

HEADER

10n

6.4n

2N4402

2K2

POT

2N4400

10K

6.4n

37R4

POT

10n

HEADER

10n

2K2

DDI2

DDI2b

SDI

CD2b

CD1b

SDI

DDI1b

DDI1

GND_EQ

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5.2 GS1560A Typical Application Circuit (Part B)

LOCK

YANC

CANC

IPSEL

SD/HDb

20bit/10bitb

IOPROC_EN/DISb

DATA0

DATA7

DATA12

DATA1

DATA8

DATA13

DATA14

DATA16

DATA3

DATA6

DATA2

DATA11

DATA4

DATA17

DATA10

DATA15

DATA18

DATA9

DATA5

MASTER/SLAVEb

RC_BYPb

FW_EN/DISb

SDO_EN/DISb

JTAG/HOSTb

DATA19

MASTER/SLAVEb

IOPROC_EN/DISb

20bit/10bitb

DATA_ERRORb

YANC

CANC

+1.8V

+3.3V

+1.8V_A

+1.8V

+3.3V

VCO_VCC

+1.8V_A

+3.3V

VCO_VCC

+1.8V_A

GS1560A

CP_VDD

PDBUFF_GND

PD_VDD

BUFF_VDD

CD1

DDI_1

TERM1

DDI_1

DVB_ASI

IPSEL

SD/HD

20bit/10bit

IOPROC_EN/DIS

CD2

DDI_2

TERM2

DDI_2

SMPTE_BYPASS

RSET

CD_VDD

SDO_EN/DIS

CD_GND

SDO

RESET_TRST

JTAG/HOST

CS_TMS

SDOUT_TDO

SDIN_TDI

SCLK_TCK

DATA_ERROR

FIFO_LD

CORE_GND

CORE_VDD

DOUT0

DOUT1

IO_GND

IO_VDD

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

IO_GND

DOUT9

DOUT10

DOUT11

IO_VDD

DOUT13

DOUT12

DOUT14

DOUT15

DOUT16

DOUT17

IO_GND

IO_VDD

DOUT18

DOUT19

CORE_VDD

YANC

CANC

FW_EN/DIS

CORE_GND

PCLK

RC_BYP

MASTER/SLAVE

LOCKED

VCO

VCO_GND

VCO_VCC

CP_CAP

LB_CONT

CP_GND

GO1555

(GO1525)

4 8

7 1

VCTR

GND GND

GND

VCC O/P

GND

10n

281 +/-1%

BNC

10n

2k2

10n

2k2

100n

2k2

10n

BNC

10n

4u7

10n

39K2

4u7

4K75 +/- 1%

10n

2k2

4u7

2n2

1u 10n

10n

4K75 +/- 1%

10n

PCLK

DATA[19..0]

DDI1

DDI1b

DDI2b

DDI2

CD1b

CD2b

DVB_ASI

SD/HDb

RESET_TRSTb

DATA_ERRORb

LOCK

CANC

FIFO_LDb

YANC

SMPTE_BYPASSb

SCLK_TCK

SDOUT_TDO

SDIN_TDI

CSb_TMS

MASTER/SLAVEb

RC_BYPb

JTAG/HOSTb

IPSEL

FW_EN/DISb

SDO_EN/DISb

20bit/10bitb

IOPROC_EN/DISb

NOTE: To guarantee -15dB Output Return Loss

at HD rates, it is recommended that the GS1528

Multi-Rate Cable Driver be used.

R, L, C form the output return

loss compensation network.

Values are subject to change.

NOTE: SMPTE_BYPASSb, SD/HDb, DVB_ASI, and RC_BYPb

are INPUTS in slave mode (MASTER/SLAVEb = LOW), and

are OUTPUTS in master mode (MASTER/SLAVEb = HIGH).

JTAG/HOSTb

IPSEL

FW_EN/DISb

SDO_EN/DISb

SMPTE_BYPASSb

SD/HDb

DVB_ASI

RC_BYPb

PCLK

DATA_ERRORb

FIFO_LDb

LOCK

FIFO_LDb

DVB_ASI

SMPTE_BYPASSb

GND_EQ

GND_A

GND_D

GND_A

GND_D

GND_VCO

4u7

GND_VCO

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5.3 GS1561 Typical Application Circuit (Part A)

EQ_VCC

GS1524

VEE

VCC

CLI

VCCA

VEEA

SDI

RSVD

SDI

VEEA

MUTE/CD

BYPASS

MCLADJ

VEE

SDO

RSVD

SDO

2N4400

2N4402

37R4

10K

GS1524

VEE

VCC

CLI

VCCA

VEEA

SDI

RSVD

SDI

VEEA

MUTE/CD

BYPASS

MCLADJ

VEE

SDO

RSVD

SDO

HEADER

10n

6.4n

2N4402

2K2

POT

2N4400

10K

6.4n

37R4

POT

10n

HEADER

10n

2K2

DDI2

DDI2b

SDI

CD2b

CD1b

SDI

DDI1b

DDI1

GND_EQ

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5.4 GS1561 Typical Application Circuit (Part B)

LOCK

YANC

CANC

IPSEL

SD/HDb

20bit/10bitb

IOPROC_EN/DISb

DATA0

DATA7

DATA12

DATA1

DATA8

DATA13

DATA14

DATA16

DATA3

DATA6

DATA2

DATA11

DATA4

DATA17

DATA10

DATA15

DATA18

DATA9

DATA5

MASTER/SLAVEb

FW_EN/DISb

JTAG/HOSTb

DATA19

MASTER/SLAVEb

IOPROC_EN/DISb

20bit/10bitb

DATA_ERRORb

YANC

CANC

+1.8V

+3.3V

+1.8V

+3.3V

VCO_VCC

+1.8V_A

+3.3V

VCO_VCC

GS1561

CP_VDD

PDBUFF_GND

PD_VDD

BUFF_VDD

CD1

DDI_1

TERM1

DDI_1

DVB_ASI

IPSEL

SD/HD

20bit/10bit

IOPROC_EN/DIS

CD2

DDI_2

TERM2

DDI_2

SMPTE_BYPASS

RESET_TRST

JTAG/HOST

CS_TMS

SDOUT_TDO

SDIN_TDI

SCLK_TCK

DATA_ERROR

FIFO_LD

CORE_GND

CORE_VDD

DOUT0

DOUT1

IO_GND

IO_VDD

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

IO_GND

DOUT9

DOUT10

DOUT11

IO_VDD

DOUT13

DOUT12

DOUT14

DOUT15

DOUT16

DOUT17

IO_GND

IO_VDD

DOUT18

DOUT19

CORE_VDD

YANC

CANC

FW_EN/DIS

CORE_GND

PCLK

RSV

MASTER/SLAVE

LOCKED

VCO

VCO_GND

VCO_VCC

CP_CAP

LB_CONT

CP_GND

GO1555

(GO1525)

4 8

7 1

VCTR

GND GND

GND

VCC O/P

GND

10n

2k2

10n

2k2

100n

2k2

10n

39K2

4u7

4K7

10n

2n2

1u 10n

10n

4K7

10n

PCLK

DATA[19..0]

DDI1

DDI1b

DDI2b

DDI2

CD1b

CD2b

DVB_ASI

SD/HDb

RESET_TRSTb

DATA_ERRORb

LOCK

CANC

FIFO_LDb

YANC

SMPTE_BYPASSb

SCLK_TCK

SDOUT_TDO

SDIN_TDI

CSb_TMS

MASTER/SLAVEb

JTAG/HOSTb

IPSEL

FW_EN/DISb

SDO_EN/DISb

20bit/10bitb

IOPROC_EN/DISb

NOTE: SMPTE_BYPASSb, SD/HDb, and DVB_ASI are

INPUTS in slave mode (MASTER/SLAVEb = LOW), and

are OUTPUTS in master mode (MASTER/SLAVEb = HIGH).

JTAG/HOSTb

IPSEL

FW_EN/DISb

SDO_EN/DISb

SMPTE_BYPASSb

SD/HDb

DVB_ASI

PCLK

DATA_ERRORb

FIFO_LDb

LOCK

FIFO_LDb

DVB_ASI

SMPTE_BYPASSb

GND_EQ

GND_A

GND_D

GND_A

GND_D

GND_VCO

4u7

2K2

GND_VCO

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6. References & Relevant Standards

SMPTE 125M Component video signal 4:2:2 – bit parallel interface

SMPTE 260M 1125 / 60 high definition production system – digital representation and

bit parallel interface

SMPTE 267M Bit parallel digital interface – component video signal 4:2:2 16 x 9 aspect

ratio

SMPTE 274M 1920 x 1080 scanning analog and parallel digital interfaces for multiple

picture rates

SMPTE 291M Ancillary Data Packet and Space Formatting

SMPTE 292M Bit-Serial Digital Interface for High-Definition Television Systems

SMPTE 293M 720 x 483 active line at 59.94 Hz progressive scan production – digital

representation

SMPTE 296M 1280 x 720 scanning, analog and digital representation and analog

interface

SMPTE 352M Video Payload Identification for Digital Television Interfaces

SMPTE RP165 Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital

Interfaces for Television

SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video

Switching

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7. Package & Ordering Information

7.1 Package Dimensions

TOLERANCES OF FORM AND POSITION

SYMBOL

MIN NOM MAX MIN NOM MAX

MILLIMETER INCH

80L

aaa

ccc

bbb

0.22

0.65 BSC 0.026 BSC

12.35

0.20

0.10

0.008

0.004

0.486

0.48612.35

0.30 0.38 0.009 0.012 0.015

NOTES:

Diagram shown is representative only. Table X is fixed for all pin sizes, and

Table Y is specific to the 80-pin package.

Table Y

ddd 0.13 0.005

Table X

CONTROL DIMENSIONS ARE IN MILLIMETERS.

1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.

ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. D1 AND E1 ARE

MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD

MISMATCH.

2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD

WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN

0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS

OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN

ADJACENT LEAD IS 0.07mm FOR 0.4mm AND 0.5mm PITCH PACKAGES.

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7.2 Packaging Data

7.3 Solder Reflow Profiles

The device is manufactured with Matte-Sn terminations and is compatible with both

standard eutectic and Pb-free solder reflow profiles. The recommended standard

eutectic reflow profile is shown in Figure 7-1. MSL qualification was performed using

the maximum Pb-free reflow profile shown in Figure 7-2.

Figure 7-1: Standard Eutectic Solder Reflow Profile

Parameter Value

Package Type 14mm x 14mm 80-pin LQFP

Package Drawing ReferenceJEDEC MS026

Moisture Sensitivity Level 3

Junction to Case Thermal Resistance, θj-c11.6°C/W

Junction to Air Thermal Resistance, θj-a (at zero airflow) 39.9°C/W

Psi 0.6°C/W

Pb-free and RoHS Compliant Yes

25°C

100°C

150°C

183°C

230°C

220°C

Time

Temperature

6 min. max

120 sec. max

60-150 sec.

10-20 sec.

3°C/sec max

6°C/sec max

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Figure 7-2: Maximum Pb-free Solder Reflow Profile (Pb-free package)

7.4 Ordering Information

25°C

150°C

200°C

217°C

260°C

250°C

Time

Temperature

8 min. max

60-180 sec. max

60-150 sec.

20-40 sec.

3°C/sec max

6°C/sec max

Part Number Pb-free and

RoHS Compliant

Loop-Through Package Temperature Range

GS1560ACF No Yes 80-pin LQFP 0°C to 70°C

GS1560ACFE3 Yes Yes 80-pin LQFP 0°C to 70°C

GS1561-CF No No 80-pin LQFP 0°C to 70°C

GS1561-CFE3 Yes No 80-pin LQFP 0°C to 70°C

OTTAWA

232 Herzberg Road, Suite 101

Kanata, Ontario K2K 2A1

Canada

Phone: +1 (613) 270-0458

Fax: +1 (613) 270-0429

CALGARY

3553 - 31st St. N.W., Suite 210

Calgary, Alberta T2L 2K7

Canada

Phone: +1 (403) 284-2672

UNITED KINGDOM

North Building, Walden Court

Parsonage Lane,

Bishop’s Stortford Hertfordshire, CM23 5DB

United Kingdom

Phone: +44 1279 714170

Fax: +44 1279 714171

INDIA

#208(A), Nirmala Plaza,

Airport Road, Forest Park Square

Bhubaneswar 751009

India

Phone: +91 (674) 653-4815

Fax: +91 (674) 259-5733

SNOWBUSH IP - A DIVISION OF GENNUM

439 University Ave. Suite 1700

Toronto, Ontario M5G 1Y8

Canada

Phone: +1 (416) 925-5643

Fax: +1 (416) 925-0581

E-mail: sales@snowbush.com

Web Site: http://www.snowbush.com

MEXICO

288-A Paseo de Maravillas

Jesus Ma., Aguascalientes

Mexico 20900

Phone: +1 (416) 848-0328

JAPAN KK

Shinjuku Green Tower Building 27F

6-14-1, Nishi Shinjuku

Shinjuku-ku, Tokyo, 160-0023

Japan

Phone: +81 (03) 3349-5501

Fax: +81 (03) 3349-5505

E-mail: gennum-japan@gennum.com

Web Site: http://www.gennum.co.jp

TAI W AN

6F-4, No.51, Sec.2, Keelung Rd.

Sinyi District, Taipei City 11502

Taiwan R.O.C.

Phone: (886) 2-8732-8879

Fax: (886) 2-8732-8870

E-mail: gennum-taiwan@gennum.com

GERMANY

Hainbuchenstraße 2

80935 Muenchen (Munich), Germany

Phone: +49-89-35831696

Fax: +49-89-35804653

E-mail: gennum-germany@gennum.com

NORTH AMERICA WESTERN REGION

Bayshore Plaza

2107 N 1st Street, Suite #300

San Jose, CA 95131

United States

Phone: +1 (408) 392-9454

Fax: +1 (408) 392-9427

E-mail: naw_sales@gennum.com

NORTH AMERICA EASTERN REGION

4281 Harvester Road

Burlington, Ontario L7L 5M4

Canada

Phone: +1 (905) 632-2996

Fax: +1 (905) 632-2055

E-mail: nae_sales@gennum.com

KOREA

8F Jinnex Lakeview Bldg.

65-2, Bangidong, Songpagu

Seoul, Korea 138-828

Phone: +82-2-414-2991

Fax: +82-2-414-2998

E-mail: gennum-korea@gennum.com

DOCUMENT IDENTIFICATION

DATA SHEET

The product is in production. Gennum reserves the right to make changes to

the product at any time without notice to improve reliability, function or

design, in order to provide the best product possible.

GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer

Data Sheet

27360 - 12 June 2009

79 of 79

Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of

the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent

infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

www.gennum.com

GENNUM CORPORATE HEADQUARTERS

4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055

E-mail: corporate@gennum.com www.gennum.com

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A

STATIC-FREE WORKSTATION