General Description
The MAX5141–MAX5144 are serial-input, voltage-output,
14-bit digital-to-analog converters (DACs) in tiny µMAX
packages, 50% smaller than comparable DACs in an
8-pin SO. They operate from low +3V (MAX5143/
MAX5144) or +5V (MAX5141/MAX5142) single supplies.
They provide 14-bit performance (±1LSB INL and DNL)
over temperature without any adjustments. The DAC out-
put is unbuffered, resulting in a low supply current of
120µA and a low offset error of 2LSBs.
The DAC output range is 0V to VREF. For bipolar opera-
tion, matched scaling resistors are provided in the
MAX5142/MAX5144 for use with an external precision op
amp (such as the MAX400), generating a ±VREF output
swing.
A 16-bit serial word is used to load data into the DAC
latch. The 25MHz, 3-wire serial interface is compatible
with SPI™/QSPI™/MICROWIRE™, and can interface
directly with optocouplers for applications requiring isola-
tion. A power-on reset circuit clears the DAC output to
code 0 (MAX5141/MAX5143) or code 8192 (MAX5142/
MAX5144) when power is initially applied.
A logic low on CLR asynchronously clears the DAC out-
put to code 0 (MAX5141/MAX5143) or code 8192
(MAX5142/MAX5144), independent of the serial interface.
The MAX5141/MAX5143 are available in 8-pin µMAX
packages and the MAX5142/MAX5144 are available in
10-pin µMAX packages.
Applications
High-Resolution and Gain Adjustment
Industrial Process Control
Automated Test Equipment
Data-Acquisition Systems
Features
♦Miniature (3mm x 5mm) 8-Pin µMAX Package
♦Low 120µA Supply Current
♦Fast 1µs Settling Time
♦25MHz SPI/QSPI/MICROWIRE-Compatible Serial
Interface
♦VREF Range Extends to VDD
♦+5V (MAX5141/MAX5142) or +3V
(MAX5143/MAX5144) Single-Supply Operation
♦Full 14-Bit Performance Without Adjustments
♦Unbuffered Voltage Output Directly Drives 60kΩ
Loads
♦Power-On Reset Circuit Clears DAC Output to
Code 0 (MAX5141/MAX5143) or Code 8192
(MAX5142/MAX5144)
♦Schmitt-Trigger Inputs for Direct Optocoupler
Interface
♦Asynchronous CLR
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
________________________________________________________________ Maxim Integrated Products 1
19-1849; Rev 1; 5/01
Ordering Information
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART T EM P. RA N G E PIN - PAC K A GE IN L ( L SB ) SU PPL Y
R A NG E ( V) O U TPU T SWING
M A X5 1 4 1E U A-40°C to +85°C 8 µMAX ± 15 U nip ol ar
M A X5 1 4 2E U B-40°C to +85°C 10 µMAX ± 15 Bi pol ar
M A X5 1 4 3E U A-40°C to +85°C 8 µMAX ± 13 U nip ol ar
M A X5 1 4 4E U B-40°C to +85°C 10 µMAX ± 13 Bi pol ar
10
9
8
7
6
1
2
3
4
5
GND
VDD
RFB
INV
DIN
SCLK
CS
REF
TOP VIEW
MAX5142
MAX5144
OUT
CLR
µMAX
OUT
SCLK
CS
1
2
8
7VDD
DIN
REF
MAX5141
MAX5143
3
4
6
5
µMAX
GND
CLR
Pin Configurations
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +3V (MAX5143/MAX5144) or +5V (MAX5141/MAX5142), VREF = +2.5V, TA= TMIN to TMAX, CL= 10pF, GND = 0, RL= ∞,
unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
CS, SCLK, DIN, CLR to GND ...................................-0.3V to +6V
REF to GND................................................-0.3V to (VDD + 0.3V)
OUT, INV to GND .....................................................-0.3V to VDD
RFB to INV ...................................................................-6V to +6V
RFB to GND.................................................................-6V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C)...............362mW
10-Pin µMAX (derate 5.6mW/°C above +70°C).............444mW
Operating Temperature Ranges
MAX514_ EUA ...................................................-40°C to +85°C
MAX514_ EUB ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Die Temperature..............................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
REFERENCE INPUT
STATIC PERFORMANCE—ANALOG SECTION
Integral Nonlinearity INL LSB±0.5 ±1MAX514_
+4.5V ≤VDD ≤+5.5V (MAX5141/MAX5142) ±1
Power-Supply Rejection +2.7V ≤VDD ≤+3.3V (MAX5143/MAX5144) ±1 LSB
Ratio error %
LSB
RFB/RINV
Digital Feedthrough nV-s0.2
Code = 0000 hex; CS = VDD;
SCLK, DIN = 0V to VDD levels
DAC Glitch Impulse nV-s7Major-carry transition
Output Settling Time µs1
To ±1
/2LSB of FS
DYNAMIC PERFORMANCE—ANALOG SECTION
Voltage-Output Slew Rate SR V/µs15(Note 5)
Bipolar Zero Offset Error
Guaranteed monotonic
LSBZSE
PARAMETER SYMBOL MIN TYP MAX UNITS
Zero-Code Offset Error ±2
Differential Nonlinearity DNL LSB
Zero-Code Tempco ZSTC ±0.05 ppm/°C
±10Gain Error (Note 1) LSB
Gain-Error Tempco ±0.1 ppm/°C
Resolution N14 Bits
±0.5 ±1
6.2 kΩDAC Output Resistance ROUT
1
Bipolar Resistor Matching ±0.03
±20
Bipolar Zero Tempco BZSTC ±0.5 ppm/°C
PSR
Reference Input Range VREF 2.0 VDD V
10
Reference Input Resistance
(Note 4) RREF 6kΩ
CONDITIONS
(Note 2)
(Note 3)
Unipolar mode
Bipolar mode
STATIC PERFORMANCE—ANALOG SECTION
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 3
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.3V (MAX5143/MAX5144), VDD = +4.5V to +5.5V (MAX5141/MAX5142), VREF = +2.5V, GND = 0, CMOS inputs,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Figure 1)
Note 1: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V (MAX5143/MAX5144) or VREF = +2.0V, +2.5V, +3.0V, and +5.0V
(MAX5141/MAX5142).
Note 2: ROUT tolerance is typically ±20%.
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 2155 hex in unipolar mode, 1155 hex in bipolar mode.
Note 5: Slew-rate value is measured from 10% to 90%.
Note 6: Guaranteed by design. Not production tested.
Note 7: Guaranteed by power-supply rejection test and Timing Characteristics.
Code = 3FFF hex
All digital inputs at
VDD or GND
All digital inputs at VDD or GND
MAX5143/MAX5144
Code = 0000 hex, VREF = 1VP-P at 100kHz
Code = 0000 hex
Code = 3FFF hex
(Note 6)
CONDITIONS
mW
0.36
PDPower Dissipation
mA0.12 0.20IDD
Positive Supply Current
V
2.7 3.6
VDD
Positive Supply Range (Note 7)
V0.15VH
Hysteresis Voltage
pF310CIN
Input Capacitance
mVP-P
1
MHz1BWReference -3dB Bandwidth
µA±1IIN
Input Current
V0.8VIL
Input Low Voltage
V2.4VIH
Input High Voltage
Reference Feedthrough
dB92SNRSignal-to-Noise Ratio
70 pF
170
CINREF
Reference Input Capacitance
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 6)
CONDITIONS
µs20
VDD High to CS Low
(Power-Up Delay)
ns20tCL
SCLK Pulse Width Low
ns20tCH
MHz25fCLK
SCLK Frequency
SCLK Pulse Width High
ns20tCLW
CLR Pulse Width Low
ns0tDH
DIN to SCLK High Hold
ns15tDS
DIN to SCLK High Setup
ns15tCSS0
CS Low to SCLK High Setup
ns15tCSS1
CS High to SCLK High Setup
ns35tCSH0
SCLK High to CS Low Hold
ns20tCSH1
SCLK High to CS High Hold
UNITSMIN TYP MAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V (MAX5143/MAX5144) or +5V (MAX5141/MAX5142), VREF = +2.5V, TA= TMIN to TMAX, CL= 10pF, GND = 0, RL = ∞,
unless otherwise noted. Typical values are at TA= +25°C.)
0.60MAX5141/MAX5142
MAX5143/MAX5144
MAX5141/MAX5142 4.5 5.5
DYNAMIC PERFORMANCE—REFERENCE SECTION
STATIC PERFORMANCE—DIGITAL INPUTS
POWER SUPPLY
MAX5141–MAX5144
+3V/+5V, Serial-Input, Voltage-Output, 14-Bit
DACs
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = +3V (MAX5143/MAX5144) or +5V (MAX5141/MAX5142), VREF = +2.5V, TA= TMIN to TMAX, GND = 0, RL= ∞, unless otherwise
noted. Typical values are at TA= +25°C.)
0
0.050
0.025
0.100
0.075
0.125
0.150
-40 10-15 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX5141/44 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
V
DD
= +5V
V
DD
= +3V
0.05
0.07
0.06
0.09
0.08
0.11
0.10
0.12
0 1.0 1.50.5 2.0 2.5 3.0 3.5 4.5 5.0
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX5141/44 toc02
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (mA)
4.0
V
DD
= +5V
0 1.0 1.50.5 2.0 2.5 3.0
0.05
0.07
0.06
0.09
0.08
0.11
0.10
0.12
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX5141/44 toc03
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (mA)
V
DD
= +3V
-0.2
0
-0.1
0.2
0.1
0.3
0.4
-40 10-15 35 60 85
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
MAX5141 toc04
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-0.30
-0.20
-0.25
-0.10
-0.15
-0.05
0
-40 10-15 35 60 85
GAIN ERROR vs. TEMPERATURE
MAX5141 toc07
TEMPERATURE (°C)
GAIN ERROR (LSB)
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
0 2.50k 5.00k 7.50k 10.00k 12.50k 15.00k
DIFFERENTIAL NONLINEARITY vs. CODE
MAX5141 toc08
DNL (LSB)
CODE
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
CODE
0 2.50k 5.00k 7.50k 10.00k 12.50k 15.00k
INTEGRAL NONLINEARITY vs. CODE
MAX5141 toc09
INL (LSB)
-0.4
0
-0.2
0.4
0.2
0.6
0.8
-40 10-15 35 60 85
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX5141 toc05
TEMPERATURE (°C)
INL (LSB)
+INL
-INL
-0.4
-0.2
-0.3
0
-0.1
0.1
0.2
-40 10-15 35 60 85
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
MAX5141 toc06
TEMPERATURE (°C)
DNL (LSB)
+DNL
-DNL
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 5
FULL-SCALE STEP RESPONSE
(FALLING)
MAX5141/44 toc11
400ns/div
CS
2V/div
AOUT
2V/div
CL = 20pF
FULL-SCALE STEP RESPONSE
(RISING)
MAX5141/44 toc12
400ns/div
CS
2V/div
AOUT
2V/div
CL = 20pF
MAJOR-CARRY GLITCH
(RISING)
MAX5141/44 toc13
200ns/div
CS
1V/div
AOUT
20mV/div
CL = 20pF
0.40
0.50
0.45
0.60
0.55
0.65
0.70
2.0 3.0 3.52.5 4.0 4.5 5.0
INTEGRAL NONLINEARITY vs.
REFERENCE VOLTAGE
MAX5141 toc16
REFERENCE VOLTAGE (V)
INL (LSB)
MAJOR-CARRY GLITCH
(FALLING)
MAX5141/44 toc14
200ns/div
CS
1V/div
AOUT
20mV/div
CL = 20pF
DIGITAL FEEDTHROUGH
MAX5141/44 toc15
50ns/div
DIN
2V/div
AOUT
10mV/div
0
40
20
80
60
120
100
140
REFERENCE CURRENT
vs. DIGITAL INPUT CODE
MAX5141 toc10
INPUT CODE
REFERENCE CURRENT (µA)
0 5k 10k 15k 20k
Typical Operating Characteristics (continued)
(VDD = +3V (MAX5143/MAX5144) or +5V (MAX5141/MAX5142), VREF = +2.5V, TA= TMIN to TMAX, GND = 0, RL= ∞, unless otherwise
noted. Typical values are at TA= +25°C.)
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
6 _______________________________________________________________________________________
Pin Descriptions
PIN
MAX5141
MAX5143
MAX5142
MAX5144
NAME FUNCTION
1 1 REF Voltage Reference Input
22CS Chip-Select Input
3 3 SCLK Serial Clock Input. Duty cycle must be between 40% and 60%.
4 4 DIN Serial Data Input
55CLR Clear Input. Logic low asynchronously clears the DAC to code 0
(MAX5141/MAX5143) or code 8192 (MAX5142/MAX5144).
6 6 OUT DAC Output Voltage
—7 INV Junction of Internal Scaling Resistors. Connect to external op amp’s inverting input in
bipolar mode.
—8 RFB Feedback Resistor. Connect to external op amp’s output in bipolar mode.
79V
DD Supply Voltage. Use +3V for MAX5143/MAX5144 and +5V for MAX5141/MAX5142.
8 10 GND Ground
;;
;;
;;;
;;
;;;;
;;
;;
tCSHO tCH
tCSSO tCL
tDH
tDS
tCSH1
tCSS1
tLDACS
CS
SCLK
DIN D13 D12 S0
Figure 1. Timing Diagram
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 7
Detailed Description
The MAX5141–MAX5144 voltage-output, 14-bit digital-
to-analog converters (DACs) offer full 14-bit perfor-
mance with less than 1LSB integral linearity error and
less than 1LSB differential linearity error, thus ensuring
monotonic performance. Serial data transfer minimizes
the number of package pins required.
The MAX5141–MAX5144 are composed of two
matched DAC sections, with a 10-bit inverted R-2R
DAC forming the ten LSBs and the four MSBs derived
from 15 identically matched resistors. This architecture
allows the lowest glitch energy to be transferred to the
DAC output on major-carry transitions. It also lowers the
DAC output impedance by a factor of eight compared
MAX5142
MAX5144
MAX400
GND
(GND)
VDD RINV RFB
RFB
INV
OUT
CLR
SCLK
DIN
CS
0.1µF
+3V/+5V
EXTERNAL OP AMP
MC68XXXX
PCS0
MOSI
SCLK
IC1
BIPOLAR
OUT
+5V
-5V
0.1µF
+2.5V
1µF
MAX6166
REF
Figure 2b. Typical Operating Circuit—Bipolar Output
MAX5141
MAX5142
MAX5143
MAX5144
MAX495
(GND)
VDD REF
OUT
SCLK
DIN
CS
GND
0.1µF
0.1µF
+2.5V
EXTERNAL OP AMP
MC68XXXX
PCS0
MOSI
SCLK
UNIPOLAR
OUT
CLR
1µF
IC1
MAX6166
+3V/+5V
Figure 2a. Typical Operating Circuit—Unipolar Output
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
8 _______________________________________________________________________________________
to a standard R-2R ladder, allowing unbuffered opera-
tion in medium-load applications.
The MAX5142/MAX5144 provide matched bipolar offset
resistors, which connect to an external op amp for bipo-
lar output swings (Figure 2b).
Digital Interface
The MAX5141–MAX5144 digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 bits (14 data bits, plus two subbits set
to zero) have been loaded into the serial input register,
it transfers its contents to the DAC latch on CS’s low-to-
high transition (Figure 3). Note that if CS is not kept low
during the entire 16 SCLK cycles, data will be corrupt-
ed. In this case, reload the DAC latch with a new 16-bit
word.
Clearing the DAC
A 20ns (min) logic low pulse on CLR asynchronously
clears the DAC buffer to code 0 in the MAX5141/
MAX5143 and to code 8192 in the MAX5142/MAX5144.
External Reference
The MAX5141–MAX5144 operate with external voltage
references from +2V to VDD. The reference voltage
determines the DAC’s full-scale output voltage.
Power-On Reset
The power-on reset circuit sets the output of the
MAX5141/MAX5143 to code 0 and the output of the
MAX5142/MAX5144 to code 8192 when VDD is first
applied. This ensures that unwanted DAC output volt-
ages will not occur immediately following a system
power-up, such as after a loss of power.
Applications Information
Reference and Ground Inputs
The MAX5141–MAX5144 operate with external voltage
references from +2V to VDD, and maintain 14-bit perfor-
mance if certain guidelines are followed when selecting
and applying the reference. Ideally, the reference’s
temperature coefficient should be less than 0.5ppm/°C to
maintain 14-bit accuracy to within 1LSB over the -40°C to
+85°C extended temperature range. Since this converter
is designed as an inverted R-2R voltage-mode DAC, the
input resistance seen by the voltage reference is code
dependent. In unipolar mode, the worst-case input-resis-
tance variation is from 11.5kΩ(at code 2155 hex) to
200kΩ(at code 0000 hex). The maximum change in load
current for a +2.5V reference is +2.5V / 11.5kΩ= 217µA;
therefore, the required load regulation is 28ppm/mA for a
maximum error of 0.1LSB. This implies a reference out-
put impedance of less than 72mΩ. In addition, the sig-
nal-path impedance from the voltage reference to the
reference input must be kept low because it contributes
directly to the load-regulation error.
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REF and GND provides high-frequency
bypassing. A surface-mount ceramic chip capacitor is
preferred because it has the lowest inductance. An
additional 1µF between REF and GND provides low-fre-
quency bypassing. A low-ESR tantalum, film, or organic
semiconductor capacitor works well. Leaded capaci-
tors are acceptable because impedance is not as criti-
;
;
;;
CS
SCLK
DIN
MSB LSB
D13 D6 D5 D4 D3 D2 D1 D0 S1 S0
SUB-BITS
DAC
UPDATED
D12 D11 D10 D9 D8 D7
Figure 3. MAX5141–MAX5144 3-Wire Interface Timing Diagram
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
_______________________________________________________________________________________ 9
cal at lower frequencies. The circuit can benefit from
even larger bypassing capacitors, depending on the
stability of the external reference with capacitive load-
ing.
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 14-bit performance from +VREF to GND
without degradation at zero scale. The DAC’s output
impedance is also low enough to drive medium loads
(RL> 60kΩ) without degradation of INL or DNL; only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change whether the DAC is used in unipolar or bipolar
operational mode. In unipolar mode, the output amplifi-
er is used in a voltage-follower connection. In bipolar
mode (MAX5142/MAX5144 only), the amplifier operates
with the internal scaling resistors (Figure 2b). In each
mode, the DAC’s output resistance is constant and is
independent of input code; however, the output amplifi-
er’s input impedance should still be as high as possible
to minimize gain errors. The DAC’s output capacitance
is also independent of input code, thus simplifying sta-
bility requirements on the external amplifier.
In bipolar mode, a precision amplifier operating with
dual power supplies (such as the MAX400) provides
the ±VREF output range. In single-supply applications,
precision amplifiers with input common-mode ranges
including GND are available; however, their output
swings do not normally include the negative rail (GND)
without significant degradation of performance. A sin-
gle-supply op amp, such as the MAX495, is suitable if
the application does not use codes near zero.
Since the LSBs for a 14-bit DAC are extremely small
(152.6µV for VREF = +2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25kΩ) contributes to zero-scale error.
Temperature effects also must be taken into considera-
tion. Over the -40°C to +85°C extended temperature
range, the offset voltage temperature coefficient (refer-
enced to +25°C) must be less than 0.95µV/°C to add
less than 1/2LSB of zero-scale error. The external
amplifier’s input resistance forms a resistive divider with
the DAC output resistance, which results in a gain error.
To contribute less than 1/2LSB of gain error, the input
resistance typically must be greater than:
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be sig-
nificantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 10.4 time constants to settle to
within 1/2LSB of the final output voltage. The time con-
stant is equal to the DAC output resistance multiplied
by the total output capacitance. The DAC output
capacitance is typically 10pF. Any additional output
capacitance increases the settling time.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 10.4 = 96ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π(1MHz) = 159ns, then the effective time con-
stant of the combined system is:
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 10.4 ✕186ns = 1.93µs.
Digital Inputs and Interface Logic
The digital interface for the 14-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC.
A 20ns (min) logic low pulse to CLR clears the data in
the DAC buffer.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX5141–
MAX5144 without additional external logic. The digital
inputs are compatible with TTL/CMOS-logic levels.
96ns 159ns 186ns
22
()
+
()
=
6.25k MΩΩ ×=2 205
15
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
10 ______________________________________________________________________________________
Unipolar Configuration
Figure 2a shows the MAX5141–MAX5144 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit. Bipolar MAX5142/MAX5144 can also be used in
unipolar configuration by connecting RFB and INV to
REF. This allows the DAC to power up to midscale.
Bipolar Configuration
Figure 2b shows the MAX5141–MAX5144 configured
for bipolar operation with an external op amp. The op
amp is set for unity gain with an offset of -1/2VREF.
Table 2 shows the offset binary codes for this circuit
(less than 0.25 inches).
Power-Supply Bypassing and
Ground Management
Bypass VDD with a 0.1µF ceramic capacitor connected
between VDD and GND. Mount the capacitor with short
leads close to the device (less than 0.25 inches).
Table 1. Unipolar Code Table
Table 2. Bipolar Code Table
VREF ✕(1 / 16,384)
0000 0000 0000 01
VREF ✕(8192 / 16,384) = 1/2VREF
1000 0000 0000 00
VREF ✕(16,383 / 16,384)
1111 1111 1111 11
ANALOG OUTPUT, VOUT
MSB LSB
DAC LATCH CONTENTS
-VREF ✕(8192 / 8192) = -VREF
0000 0000 0000 00
-VREF ✕(1 / 8192)
0111 1111 1111 11
0V1000 0000 0000 00
+VREF ✕(1 / 8192)
1000 0000 0000 01
+VREF ✕(8191 / 8192)
1111 1111 1111 11
ANALOG OUTPUT, VOUT
MSB LSB
DAC LATCH CONTENTS
Chip Information
TRANSISTOR COUNT: 2800
PROCESS: BiCMOS
Functional Diagrams
GND
VDD
OUT
CLR
DIN
SCLK
CS
REF
MAX5141
MAX5143
14-BIT DAC
CONTROL
LOGIC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
GND
VDD
OUT
CLR
DIN
SCLK
CS
REF
14-BIT DAC
CONTROL
LOGIC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
RFB
INV
MAX5142
MAX5144
MAX5141-MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
______________________________________________________________________________________ 11
________________________________________________________Package Information
8LUMAXD.EPS
MAX5141–MAX5144
+3V/+5V, Serial-Input,
Voltage-Output, 14-Bit DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________12
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
10LUMAX.EPS
MAX5141–MAX5144