MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
19-5981; Rev 3; 4/13
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX17497A.related.
General Description
The MAX17497A/MAX17497B include both a current-
mode fixed-frequency flyback converter and a synchro-
nous step-down regulator. They contain all the control
circuitry required to design wide input-voltage noniso-
lated power supplies to supply multiple output rails for
smart meters, industrial control, and other similar applica-
tions. The MAX17497A has its rising/falling undervoltage
lockout (UVLO) thresholds optimized for universal offline
(85V AC to 265V AC) applications, while the MAX17497B
supports undervoltage lockout (UVLO) thresholds suit-
able to low-voltage DC-DC applications. Both devices
also include a 3.3V fixed-output synchronous step-down
regulator that delivers up to 600mA load current.
The switching frequency of the MAX17497A flyback
converter is 250kHz, while the MAX17497B flyback/
boost converter is 500kHz. The internally compensated
synchronous step-down regulator switches at 1MHz on
both versions. These frequencies allow the use of tiny
magnetic and filter components resulting in compact,
cost-effective power supplies. An EN/UVLO input allows
the user to start the power supply precisely at the desired
input voltage, while also functioning as an on/off pin. The
OVI pin enables implementation of an input overvoltage-
protection scheme that ensures the converter shuts
down when the DC input voltage exceeds the desired
maximum value.
Programmable current limit allows proper sizing and
protection of the primary switching FET. The devices
support a maximum duty cycle greater than 92% and
provides programmable slope compensation to allow
optimization of control-loop performance. The devices
provide an open-drain RESETN pin that serves as a
power-good indicator and enters the high-impedance
state to indicate that the flyback/boost converter and
3.3V step-down regulator outputs are in regulation. An
SSF pin allows programmable soft-start time for the fly-
back/boost converter, while an internal digital soft-start is
employed for the 3.3V step-down regulator to limit inrush
current. Hiccup mode overcurrent protection and thermal
shutdown are provided to minimize dissipation under
overcurrent and overtemperature fault conditions. The
devices are available in a space-saving 16-pin (3mm x
3mm) TQFN package with 0.5mm lead spacing.
Benefits and Features
S Reduced Component Count and Board Space
Flyback/Boost with Integrated Internally
Compensated Step-Down Regulator
No Current-Sense Resistor
Space-Saving 16-Pin (3mm x 3mm) TQFN
Package
S Minimal Radio Interference
250kHz Switching in Offline Version
Minimizes Interference with Radio Receivers
in Smart Meter Applications
S Reduced Inrush Current
Programmable Flyback/Boost Soft-Start
Internal Digital Soft-Start for Step-Down
Regulator
S Reduced Power Dissipation Under Fault
Hiccup Mode Overcurrent Protection
Thermal Shutdown with Hysteresis
S Robust Protection Features
Flyback/Boost Programmable Current Limit
Input Overvoltage Protection
S Optimized Loop Performance
Programmable Slope Compensation for
Flyback/Boost Maximizes Obtainable Phase
Margin
S High Efficiency
Low RDSON, 150mI, 65V-Rated Internal
nMOSFET
3.3V Step-Down Regulator Efficiency Greater
Than 90%
S Optional Spread Spectrum
Applications
AC-DC Power Supplies for Smart Meter
Applications
Universal-Input Offline AC-DC Power Supplies
Wide-Range DC Input Flyback/Boost Industrial
Power Supplies
EVALUATION KIT AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
2Maxim Integrated
IN to SGND ............................................................-0.3V to +40V
EN/UVLO to SGND ....................................... -0.3V to VIN + 0.3V
OVI to SGND ...............................................-0.3V to VCC + 0.3V
VCC to SGND ..........................................................-0.3V to +6V
SSF, RLIMF, EAFN, COMPF, SCOMPF
to SGND ............................................... -0.3V to (VCC + 0.3V)
LXF to SGND .........................................................-0.3V to +70V
INB to SGND .........................................................-0.3V to +26V
LXB to SGND .............................................. -0.3V to VINB + 0.3V
OUTB to SGND .......................................................-0.3V to +6V
RESETN to SGND ....................................................-0.3V to +6V
PGNDF, PGNDB to SGND ...................................-0.3V to +0.3V
Continuous Power Dissipation (Single-Layer Board)
TQFN (derate 20.8mW/NC above +70NC)..................1700mW
Operating Temperature Range ........................ -40NC to +125NC
Storage Temperature Range ............................ -65NC to +160NC
Junction Temperature (continuous) ................................+150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY (VIN)
IN Voltage Range (VIN)MAX17497A 4.5 29 V
MAX17497B 4.5 36
IN Supply Startup Current Under
UVLO IINSTARTUP, VIN < UVLO or EN/UVLO = SGND 22 36 FA
IN Supply Current (IIN) Switching, fSW = 250kHz 2.75 4.5 mA
IN Boostrap UVLO Rising
Threshold
MAX17497A 19 20.5 22 V
MAX17497B 3.85 4.15 4.4
IN Bootstrap UVLO Falling 3.65 3.95 4.25 V
EN/UVLO Threshold Rising 1.18 1.23 1.28 V
Falling 1.11 1.17 1.21
EN/UVLO Input Leakage Current 0V < VEN/UVLO < 1.5V, TA = +25NC-100 0 +100 nA
LDO
VCC Output Voltage Range 6V < VIN < 29V, 0mA < IVCC < 50mA 4.8 5 5.2 V
VCC Dropout Voltage VIN = 4.5V, IVCC = 20mA 160 300 mV
VCC Current Limit VCC = 0V, VIN = 6V 50 100 mA
OVERVOLTAGE PROTECTION
OVI Threshold Rising 1.18 1.23 1.28 V
Falling 1.11 1.17 1.21
OVI Masking Delay 2 Fs
OVI Input Leakage Current 0V < VOVI < 1.5V, TA = +25NC-100 0 +100 nA
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
3Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FLYBACK/BOOST CONVERTER
Flyback/Boost Switching
Frequency
MAX17497A 235 250 265 kHz
MAX17497B 470 500 530
Flyback/Boost Maximum Duty
Cycle
fSW = 250kHz (MAX17497A) 92 94.5 97 %
fSW = 500kHz (MAX17497B) 90 92 94
SSF Pullup Current VSSF = 400mV 9 10 11 FA
SSF Set Point Voltage 1.12 1.22 1.24 V
SSF Peak Current-Limit Enable
Threshold 1.11 1.17 1.21 V
EAFN Regulation Point 1.2 1.22 1.24 V
EAFN Input Bias Current 0V < VEAFN < 1.5V, TA = +25NC-100 +100 nA
Error-Amplifier Open-Loop
Voltage Gain 90 dB
Error-Amplifier Transconductance VCOMPF = 2V, VRLIMF = 1V 1.5 1.8 2.1 mS
Error-Amplifier Source Current VCOMPF = 2V, VEAFN = 1V 80 120 210 FA
Error-Amplifier Sink Current VCOMPF = 2V, VEAFN = 1.5V 80 120 210 FA
Current-Sense Transresistance 0.45 0.5 0.55 I
IN Clamp Voltage EN/UVLO = SGND, IIN_ = 1mA (MAX17497A)
(Note 2) 31 33.5 36 V
LXF DMOS Switch On-Resistance
(RDSON_LXF)ILXF = 200mA 175 380 mI
LXF DMOS Peak Current Limit RLIMF = 100K 1.62 1.9 2.23 A
LXF DMOS Runaway Current
Limit RLIMF = 100K 1.9 2.3 2.6 A
LXF Leakage Current VLXF = 65V, TA = +25NC0.1 2 FA
Peak Switch Current Limit with
RLIMF Open 0.35 0.45 0.54 A
Runaway Switch Current Limit
with RLIMF Open 0.39 0.5 0.6 A
RLIMF Reference Current 9 10 11 FA
Number of Flyback/Boost
Runaway Current-Limit Hits
Before Hiccup Timeout
1 #
Flyback/Boost Overcurrent
Hiccup Timeout 32 ms
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum On-Time 110 ns
SCOMPF Pullup Current 9 10 11 FA
Slope-Compensation Resistor
Range MAX17497B 30 150 kI
Slope-Compensation Ramp SCOMPF = 100kI175 200 225 mV/Fs
Default Slope-Compensation
Ramp SCOMPF = open 60 mV/Fs
STEP-DOWN REGULATOR
INB Voltage Range 7 16 V
INB Quiescent Supply Current VINB = 16V, VOUTB > 3.3V 200 300 FA
INB UVLO Threshold Rising 6.2 6.5 6.7 V
Falling 5.9 6.2 6.4
High-Side RDSON ILXB =200mA 425 800 mI
Low-Side RDSON ILXB =200mA 225 425 mI
Switching Frequency 0.94 1 1.06 MHz
LXB Leakage Current VLXB = VINB - 1V, VLXB = VPGNDB + 1V,
TA = +25NC0.1 1 FA
LXB Dead Time (Note 3) 5 ns
VOUTB Output-Voltage Accuracy 7V < VINB <16V, 50mA < IOUT < 600mA 3.245 3.3 3.355 V
VOUTB Input Bias Current VOUTB = 3.3V 7 10 FA
Peak Current-Limit Fault
Threshold VOUTB = 3.1V 0.9 1.1 1.23 A
Runaway Current-Limit Threshold VOUTB < 100mV 1.05 1.25 1.45 A
Soft-Start Duration Count VINB > 7V 2048 Cycles
Number of Runaway Current-Limit
Hits Before Hiccup Timeout 1 Hits
Overcurrent Hiccup Timeout 32,768 Cycles
Minimum On-Time 100 ns
RESETN
RESETN Output Leakage Current
(Off-State) VRESETN = 5V, TA = +25NC-1 +1 FA
RESETN Output Voltage
(On-State) IRESETN = 10mA 0 0.4 V
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
5Maxim Integrated
Note 1: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 2: The MAX17497A is intended for use in universal input power supplies. The internal clamp circuit at IN is used to prevent
the bootstrap capacitor from charging to a voltage beyond the absolute maximum rating of the device when EN/UVLO is
low (shutdown mode). Externally limit the current to IN (hence to clamp) to 2mA (max) when EN/UVLO is low.
Note 3: Guarantees cross conduction is avoided and it is not larger than specified max value to guarantee loop-regulation capability.
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
Typical Operating Characteristics
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESETN Higher Thresholds EAFN rising 93.5 95 96.5 %
OUTB rising 93.5 95 96.5
RESETN Lower Thresholds EAFN falling 90.5 92 93.5 %
OUTB falling 90.5 92 93.5
RESETN Delay After EAFN and
VOUTB Reach 95% Regulation
(MAX17497A/MAX17497B)
4 ms
THERMAL SHUTDOWN
Thermal Shutdown Threshold Temperature rising 160 NC
Thermal Shutdown Hysteresis 20 NC
BOOTSTRAP UVLO WAKE-UP LEVEL
vs. TEMPERATURE (MAX17497A)
MAX17497A/B toc01
TEMPERATURE (°C)
BOOTSTRAP UVLO WAKE-UP LEVEL (V)
100806040200-20
20.16
20.18
20.20
20.22
20.24
20.26
20.14
-40 120
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE (MAX17497B)
MAX17497A/B toc02
TEMPERATURE (°C)
IN UVLO WAKE-UP LEVEL (V)
100806040200-20
4.15
-40 120
3.95
4.00
4.05
4.10
3.90
IN UVLO SHUTDOWN LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc03
TEMPERATURE (°C)
IN UVLO SHUTDOWN LEVEL (V)
100806040200-20
4.015
-40 120
3.975
3.980
3.985
3.990
3.995
4.000
4.005
4.010
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
6Maxim Integrated
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
EN/UVLO RISING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc04
TEMPERATURE (°C)
EN/UVLO RISING LEVEL (V)
100806040200-20
1.235
-40 120
1.215
1.220
1.225
1.230
1.210
OVI RISING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc06
TEMPERATURE (°C)
OVI RISING LEVEL (V)
100806040200-20
1.225
1.210
-40 120
1.215
1.220
IN CURRENT UNDER UVLO vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc08
TEMPERATURE (°C)
IN CURRENT UNDER UVLO (µA)
100806040200-20
30
-40 120
22
24
26
28
20
EN/UVLO FALLING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc05
TEMPERATURE (°C)
EN/UVLO FALLING LEVEL (V)
100806040200-20
1.145
1.150
1.155
1.160
1.165
1.170
1.140
-40 120
OVI FALLING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc07
TEMPERATURE (°C)
OVI FALLING LEVEL (V)
100806040200-20
1.160
-40 120
1.140
1.145
1.150
1.155
1.135
IN CURRENT DURING SWITCHING
vs. TEMPERATURE
MAX17497A/B toc09
TEMPERATURE (°C)
100806040200-20
2.6
2.8
3.0
3.2
3.4
3.6
2.4
-40 120
IN CURRENT DURING SWITCHING (mA)
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
7Maxim Integrated
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
LXF AND PRIMARY
CURRENT WAVEFORM
MAX17497A/B toc10
2µs/div
VDRAIN
100V/div
IPRI
1A/div
MAX17497A/B toc12
4ms/div
ENABLE SHUTDOWN WAVEFORM
(FULL LOAD)
VDC
200V/div
VOUTF
10V/div
VOUTB
2V/div
EN/UVLO
5V/div
PEAK CURRENT LIMIT (ILIMF)
vs. RLIMF AT ROOM TEMPERATURE
MAX17497A/B toc14
RLIMF AT ROOM TEMPERATURE (kI)
PEAK CURRENT LIMIT (ILIMF) (mA)
706040 5020 3010
200
400
600
800
1000
1200
1400
1600
1800
0
08
0
ENABLE STARTUP WAVEFORM
(FULL LOAD)
MAX17497A/B toc11
4ms/div
VDC
200V/div
VOUTF
10V/div
VOUTB
2V/div
EN/UVLO
5V/div
RESETN WAVEFORM
MAX17497A/B toc13
2ms/div
VRESETN
5V/div
VOUTF
5V/div
VOUTB
2V/div
PEAK-CURRENT LIMIT AT RLIMF = 100kI
vs. TEMPERATURE
MAX17497A/B toc15
TEMPERATURE (°C)
100806040200-20
1.95
1.96
1.97
1.98
1.99
2.00
1.94
-40 120
PEAK-CURRENT LIMIT (A)
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
8Maxim Integrated
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
TRANSIENT RESPONSE
(FLYBACK-15V OUTPUT)
MAX17497A/B toc16
1ms/div
VOUTF (AC)
200mV/div
ILOAD
0.5A/div
INB WAKE-UP LEVEL vs. TEMPERATURE
MAX17497A/B toc18
TEMPERATURE (°C)
100806040200-20
6.48
6.41
-40 120
INB WAKE-UP LEVEL (A)
6.42
6.43
6.44
6.45
6.46
6.47
VOUTB vs. INB VOLTAGE
MAX17497A/B toc20
INB VOLTAGE (V)
VOUTB VOLTAGE (V)
8
61
6141210
3.310
3.313
3.316
3.319
3.322
3.325
3.328
BODE PLOT (FLYBACK CONVERTER)
MAX17497A/B toc17
0dBm
67891234567891 234
GAIN
10dB/div
PHASE
36°/div
BW = 6.9kHz
PM = 55°
VOUTB vs. TEMPERATURE
MAX17497A/B toc19
TEMPERATURE (°C)
VOUTB VOLTAGE (V)
0-20-40 80604020
3.26
3.27
3.28
3.29
3.30
3.31
3.32
3.33
3.34
LXB AND INDUCTOR WAVEFORM
MAX17497A/B toc21
400ns/div
ILXB
0.5A/div
VLXB
5V/div
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
9Maxim Integrated
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
VOUTB vs. LOAD CURRENT
MAX17497A/B toc22
LOAD CURRENT, IOUTB (A)
VOUTB VOLTAGE (V)
3.310
3.315
3.320
3.325
3.33
00.1 0.20.3 0.40.5 0.6
BODE PLOT (BUCK REGULATOR)
MAX17497A/B toc24
0dBm
67891234567891 234
GAIN
10dB/div
PHASE
36°/div
BW = 110kHz
PM = 57°
EFFICIENCY vs. LOAD CURRENT
(BUCK REGULATOR)
LOAD CURRENT (A)
EFFICIENCY (%)
0.50.40.30.20.1
10
20
30
40
50
60
70
80
90
100
0
0 0.6
MAX17497A/B toc26
VINB = 15V
LOAD STEP ON BUCK REGULATOR
(3.3V OUTPUT)
MAX17497A/B toc23
1ms/div
VOUTB
50mV/div
ILOAD
0.2A/div
EFFICIENCY GRAPH vs. LOAD CURRENT
(FLYBACK CONVERTER)
MAX17497A/B toc25
LOAD CURRENT (A)
EFFICIENCY (%)
0
10
20
30
40
50
60
70
80
90
100
00.2 0.40.6 0.81.0 1.21.4
VDC = 310V
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
10Maxim Integrated
Pin Description
Pin Configuration
PIN NAME FUNCTION
1 EN/UVLO
Enable/Undervoltage-Lockout Pin. Drive to > 1.23V to start the devices. To externally program the
UVLO threshold of the input supply, connect a resistor-divider between input supply EN/UVLO and
SGND.
2 VCC Linear Regulator Output. Connect input bypass capacitor of at least 1FF from VCC to SGND as close
as possible to the IC.
3 OVI Overvoltage Comparator Input. Connect a resistor-divider between the input supply (OVI) and SGND
to set the input overvoltage threshold.
4 RLIMF Current-Limit Setting Pin. Connect a resistor between RLIMF and SGND to set the peak-current limit
for nonisolated flyback converter. Peak-current limit defaults to 500mA if unconnected.
5 SCOMPF
Slope Compensation Input Pin. Connect a resistor between SCOMPF and SGND to set slope comp
ramp. Connect to VCC for minimum slope comp. See the Programming the Slope Compensation for
the Flyback/Boost Converter (SCOMPF) section.
6 EAFN
Feedback/Inverting Input of the Error Amplifier for Nonisolated Flyback Converter. Connect to
midpoint of resistor-divider from the positive terminal of the output capacitor of the flyback/boost
converter to SGND.
7 COMPF Error-Amplifier Output of Flyback/Boost Converter. Connect the frequency-compensation network
between COMPF and SGND. See Figure 9.
15
16
14
13
6
5
7
VCC
RLIMF
8
EN/UVLO
LXB
OUTB
INB
12
PGNDF
4
12 11 9
LXF
EP
IN
SSF
COMPF
EAFN
SCOMPF
+
OVI PGNDB
3
10
RESETN
TQFN
TOP VIEW
MAX17497A
MAX17497B
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
11Maxim Integrated
Pin Description (continued)
Detailed Description
The MAX17497A is optimized for implementing a noniso-
lated offline flyback converter with output power of up to
30W and a 3.3V, 600mA power rail using the on-board
synchronous step-down regulator. The output voltage of
the flyback converter serves as the input supply voltage
to the on-board 3.3V integrated synchronous step-down
regulator. The outputs of the flyback converter and step-
down regulator are regulated with independent feedback
loops, thus providing two accurately controlled voltages
for the system. If needed, more semi-regulated outputs
can be generated using additional secondary windings
on the flyback converter transformer. The MAX17497B is
optimized for implementing a nonisolated flyback/boost
converter up to 15W and a 3.3V, 600mA synchronous
step-down regulator in low-voltage DC-DC applications
down to 4.5V DC. See the Figure 1 for more information.
Input Voltage Range
The MAX17497A has different rising and falling UVLO
thresholds on the IN pin than those of the MAX17497B.
The thresholds for the MAX17497A are optimized for
implementing power-supply startup schemes typically
used for offline AC-DC power supplies. The MAX17497A
is therefore well suited for operation from the recti-
fied DC bus in AC-DC power-supply applications typi-
cally encountered in electric metering and other low-
power industrial power-supply applications. As such,
the MAX17497A has no limitation on the maximum
input voltage as long as the external components are
rated suitably and the maximum operating voltages of
the MAX17497A are respected. The MAX17497A can
successfully be used in universal input rectified (85V to
265V AC) bus applications, rectified 3-phase DC bus
applications, and telecom (36V to 72V DC) applications.
PIN NAME FUNCTION
8 SSF Soft-Start Pin for Flyback/Boost Converter. Connect a capacitor from SSF to SGND to set the
soft-start time interval.
9 OUTB Feedback for Step-Down Regulator. Connects OUTB to the positive terminal of the step-down
regulator output capacitor.
10 PGNDB Power Ground for Step-Down Regulator
11 LXB External Inductor Connection for Step-Down Regulator. Connect to one end of the output inductor.
Connect the other end of output inductor to output capacitor.
12 INB
Internal Step-Down Regulator Input. Connect INB to either VOUTF, the output of flyback/boost
converter, or directly to the DC input source, as needed in the application. Bypass INB to PGNDB
with a 2.2FF minimum ceramic capacitor.
13 RESETN Open-Drain Output. RESETN goes high when both the outputs are within 5% of their regulation point.
RESETN goes low when either of the outputs falls below 92% of their regulation value.
14 PGNDF Power Ground for Flyback/Boost Converter
15 LXF External Transformer/Inductor Connection for Flyback/Boost Converter
16 IN Internal Linear Regulator Input. Connect IN to the input-voltage source. Bypass IN to PGNDF with
ceramic capacitor of at least 1FF.
— EP Exposed Pad. Internally connected to SGND. Connect EP to a large copper plane at SGND potential
to provide adequate thermal dissipation. Connect EP (SGND) to PGNDF at a single point.
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
12Maxim Integrated
The MAX17497B is intended for implementing a noniso-
lated flyback/boost converter with an on-board 60V rated
n-channel MOSFET. The IN pin of the MAX17497B has
a maximum operating voltage of 36V. The MAX17497B
implements rising and falling thresholds on the IN pin that
assume power-supply startup schemes, typical of lower
voltage DC-DC applications, down to an input voltage of
4.5V DC. Therefore, flyback/boost converters with a 4.5V
to 36V supply voltage range can be implemented with
the MAX17497B. See the Startup Operation section for
more details on power-supply startup schemes for both
devices. The on-board synchronous step-down regulator
is rated for a 16V (max) operating input voltage.
Linear Regulator (VCC)
The devices have an internal linear regulator powered
from the IN pin. The output of the linear regulator is con-
nected to the VCC pin and should be decoupled with a
1FF capacitor to ground for stable operation. The VCC
regulator output supplies the operating current for the
devices. The maximum operating voltage of the IN pin
is 29V for the MAX17497A and 36V for the MAX17497B.
Configuring the Power Stage (LXF)
The devices use an internal nMOSFET to implement
internal current sensing for current-mode control and
overcurrent protection of the flyback/boost converter.
To facilitate this, the drain of the internal nMOSFET is
connected to the source of the external MOSFET in
the MAX17497A application. The gate of the external
MOSFET is connected to the IN pin. Ensure by design
that the IN pin voltage does not exceed the maximum
operating gate-voltage rating of the external MOSFET.
The external MOSFET gate-source voltage is controlled
by the switching action of the internal nMOSFET, while
also sensing the source current of the external MOSFET.
In the MAX17497B application, the LXF pin is directly
connected to either the flyback transformer primary wind-
ing or to the boost-converter inductor.
Maximum Duty Cycle
The MAX17497A/MAX17497B offer a maximum duty cycle
greater than 90%. Both devices can be used to implement both
flyback and boost converters involving large input-to-out-
put voltage ratios in DC-DC applications. The on-board
synchronous step-down regulator has a maximum duty
cycle of 85% and is internally compensated for stable
operation.
RESETN Power-Good Signal
The devices include a RESETN signal that serves as a
power-good signal to the system. RESETN is an open-
drain signal and requires a pullup resistor to the pre-
ferred supply voltage. The RESETN signal monitors both
the flyback/boost output and the synchronous step-down
regulator output, pulling high when both outputs are at
95% (typ) of their regulation values. The RESETN signal
pulls low when either of the outputs fall below 92% (typ)
of their regulation values.
Sequencing
The MAX17497A is typically configured such that the
output of the flyback converter serves as the input source
to the integrated synchronous step-down regulator.
Because the synchronous step-down regulator has a 6.5V
input UVLO threshold, the 3.3V output always comes up
after the output of the flyback converter. Figure 2 shows
the sequencing of the MAX17497A outputs configured
as described above. The sequencing for the devices is
identical when the MAX17497B is configured as either
a flyback or boost output generating the input supply
voltage for the integrated step-down regulator. The step-
down regulator can also operate from an independent 7V
to 16V DC supply. In this case, the step-down regulator
starts up when its INB pin voltage exceeds 7V, provided
that the EN/UVLO pin voltage is greater than 1.23V (typ).
Soft-Start
The devices implement soft-start operation for the flyback/
boost converter, as well as the synchronous step-down
regulator. A capacitor connected to the SSF pin programs
the soft-start period for the flyback/boost converter, while
the step-down regulator has a fixed internal digital soft-
start scheme. The step-down regulator includes soft-start
duration of 2ms. See the Programming the Soft-Start of the
Flyback/Boost Converter (SSF) section for more details
on selection of the SSF capacitor.
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
13Maxim Integrated
Figure 1. MAX17497A/MAX17497B Block Diagram
LDO
POK
5V, 50mA
VCC
EN/UVLO
IN
OVI
RLIMF
SCOMF
EAFN
COMF
CHIPEN
1.23V
1.23V
1.23V
1.23V
1.23V
VOUTB
PGNDB
LXB
INB
RESTEIN
PGNDF
LXF
SSF
1.17V
INB
POK
CHIPEN
EN_BUCK
COMP
250mV
RLIMFINT
CHIPEN
VSS
FIX_SLOPE
VSCOMPF
SLOPE
COMPENSATION
10µA
10µA
33V CLAMP
(MAX17497A ONLY)
OSC
VCS
CLK
CONTROL
LOGIC AND
DRIVER
1 RUNAWAY
CONTROL
LOGIC AND
DRIVER
RUNAWAY HICCUP
VSUM
CHIPEN
HICCUP
VCS
VSCOMPF
PEAK
PWK
RUNAWAY
HICCUP
VCSB
1 RUNAWAY
1.23V
1V
VCSBSUM
VCSBSUM
INBCHIPEN
VOUTB
EAFN
VCSB
SSDONEF
SSDONEF
ISLOPE
SSDONEB
PEAK
PWM
CLK
CLK
VSUM
COMPF
REF 1.23V
MAX17497A
MAX17497B
SSDONEB STEP-DOWN
SOFT-START
10µA
SSDONE
SSDONE
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
14Maxim Integrated
Spread-Spectrum Factory Option
For EMI-sensitive applications, a spread-spectrum-
enabled version of the device can be requested from
the factory. The frequency-dithering feature modulates
the switching frequency by Q10% at a rate of 1/16 the
switching frequency. This spread-spectrum-modulation
technique spreads the energy of switching-frequency
harmonics over a wider band while reducing their peaks,
helping to meet stringent EMI goals.
Applications Information
Startup Voltage and Input Overvoltage-
Protection Setting (EN/UVLO, OVI)
The devices’ EN/UVLO pin serves as an enable/disable
input, as well as an accurate programmable input UVLO
pin. The devices do not commence startup operations
unless the EN/UVLO pin voltage exceeds 1.23V (typ).
The devices turn off if the EN/UVLO pin voltage falls
below 1.17V (typ). A resistor-divider from the input DC
bus to ground can be used to divide down and apply a
fraction of the input DC voltage (VDC) to the EN/UVLO
pin. The values of the resistor-divider can be selected
such that the EN/UVLO pin voltage exceeds the 1.23V
(typ) turn-on threshold at the desired input DC bus volt-
age. The same resistor-divider can be modified with an
additional resistor (ROVI) to implement input overvoltage
protection in addition to the EN/UVLO functionality, as
shown in Figure 3. When voltage at the OVI pin exceeds
1.23V (typ), the devices stop switching and resume
switching operations only if voltage at the OVI pin falls
below 1.17V (typ). For given values of startup DC input
voltage (VSTART), and input overvoltage-protection volt-
age (VOVI), the resistor values for the divider can be cal-
culated as follows, assuming a 24.9kI resistor for ROVI:
OVI
EN OVI START
V
R R 1k
V
= × −Ω
where ROVI is in kI and VSTART and VOVI are in volts.
START
SUM OVI EN
V
R R R 1k
1.23
= + × −Ω
where REN and ROVI are in kI and VSTART is in volts.
RSUM may need to be implemented as equal multiple resistors
in series (RDC1, RDC2, RDC3) such that voltage across each
resistor is limited to its maximum operating voltage.
= = = Ω
SUM
DC1 DC2 DC3
R
RR R k
3
Figure 2. Sequencing of MAX17497A/MAX17497B Output Voltage Rails
EN/UVLO
6.5V
tSSF
tSSB
RESETN
tRESETN
4ms
95% 92%
VOUTB
VOUTF
95%
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
15Maxim Integrated
Figure 3. Programming EN/UVLO and OVI Figure 4. MAX17497A RC-Based Startup Circuit
Startup Operation
The MAX17497A is optimized for implementing offline
flyback converters. A cost-effective RC startup circuit
is used in offline applications. In this startup method,
when the input DC voltage is applied, the startup
resistor (RSTART) charges the startup capacitor (CSTART),
causing the voltage at the IN pin to increase towards the
rising IN UVLO threshold (20V typ). During this time, the
MAX17497A draws a low startup current of 20FA (typ)
through RSTART. When the voltage at IN reaches the
rising IN UVLO threshold, the MAX17497A commences
switching operations and drives the internal nMOSFET
whose drain is connected to the LXF pin. In this con-
dition, the MAX17497A draws 2.5mA current in from
CSTART, in addition to the current required to switch the
gate of the external nMOSFET (Q1). Since this current
cannot be supported by the current through RSTART,
the voltage on CSTART starts to drop. When suitably
configured as show in Figure 4, the external nMOSFET
is switched by the LXF pin and the flyback converter
generates an output voltage (VOUTF) bootstrapped to
the IN pin through the diode (D2). If VOUTF exceeds
the sum of 6V and the drop across D2 before the
voltage on CSTART falls below 5V, then the IN volt-
age is sustained by VOUTF, allowing the MAX17497A
to continue operating with energy from VOUTF. The
large hysteresis (15V typ) of the MAX17497A allows
for a small startup capacitor (CSTART). The low startup
current (20FA typ) allows the use of a large startup resis-
tor (RSTART), thus reducing power dissipation at higher
DC bus voltages. RSTART may need to be implemented
as equal, multiple resistors in series (RIN1, RIN2 and
RIN3) to share the applied high DC voltage in offline
applications, such that the voltage across each resistor
is limited to the maximum continuous operating-voltage
rating. RSTART and CSTART can be calculated as:
GATE sw SSF
START IN 6
Q ft
C I µF
10
10
×
=+×
where IIN is the supply current drawn at the IN pin in mA,
QGATE is the gate charge of the external MOSFET used in
nC, fSW is the switching frequency of the converter in Hz,
and tSSF is the soft-start time programmed for the flyback
converter in ms (see the Programming the Soft-Start of the
Flyback/Boost Converter (SSF) section).
( )
START
START START
V 10 50
Rk
1C
−×
= Ω
+
where CSTART is the startup capacitor in FF.
For designs that cannot accept power dissipation in
the startup resistors at high DC input voltages in offline
applications, the startup circuit can be set up with a
current source instead of a startup resistor, as shown
in Figure 5.
OVI
ROVI
REN
RSUM
RDC3
RDC2
RDC1
VDC
EN/UVLO
MAX17497A
MAX17497B
RSTART
RIN3
VOUTF
D2
VDC
IN LXF
VCC
CVCC
CSTART
RIN2
RIN1
MAX17497A
LDO
VDC VOUTF
D1
COUTF
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
16Maxim Integrated
The startup capacitor (CSTART) can be calculated as
follows:
GATE sw SSF
START IN 6
Q ft
C I µF
10
10
×
=+×
where IIN is the supply current drawn at the IN pin in mA,
QGATE is the gate charge of the external MOSFET used
in nC, fSW is the switching frequency of the converter in
Hz, and tSSF is the soft-start time programmed for the
flyback converter in ms.
Resistors RSTART and RISRC can be calculated as:
START
START
BEQ1
ISRC
V
RM
10
V
RM
70
= Ω
= Ω
The IN UVLO rising threshold of the MAX17497B is
set to 3.9V with hysteresis of 200mV, optimized for
low-voltage DC-DC applications down to 4.5V. For
applications where the input DC voltage is low enough
(e.g., 4.5V to 5.5V DC) so the power loss incurred to
supply the operating current of the MAX17497B can be
tolerated, the IN pin is directly connected to the DC input
(Figure 6). For higher DC input voltages (e.g., 16V to 32V
DC), a startup circuit (Figure 7) can be used to minimize
power dissipation in the startup circuit. In this start-
up scheme, the transistor (Q1) supplies the switching
current until a bias winding NB comes up. The resistor
(RZ) can be calculated as:
Z INMIN
R 9 (V 6.3) k=× −Ω
where VINMIN is the minimum input DC voltage.
Programming the Soft-Start of the
Flyback/Boost Converter (SSF)
The devices’ soft-start period of the flyback/boost con-
verter can be programmed by selecting the value of
the capacitor connected from the SSF pin to GND. The
capacitor (CSSF) can be calculated as:
SSF SSF
C 8.13 t nF= ×
where tSSF is expressed in ms.
Figure 5. MAX17497A Current-Source-Based Startup Circuit
Figure 6. MAX17497B Typical Startup Circuit with IN
Connected Directly to DC Input
RSTART
RIN3
M1IN
Q1
RISRC
VOUTF
VDC
VDC VOUTF
D1
IN LXF
PGNDF
VCC
CVCC
CSTART
D2
RIN2
RIN1
COUTF
MAX17497A
LDO
VDC VOUTF
IN
LXF Np Ns
VCC
D1
IN
CIN COUTF
CVCC
MAX17497B
LDO
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
17Maxim Integrated
Programming the Output Voltage of
the Flyback/Boost Converter (EAFN)
Set the output voltage of the flyback/boost converter by
selecting the correct values for the resistor-divider con-
nected from the flyback/boost output to ground (VOUTF)
with the midpoint of the divider connected to the EAFN
pin (Figure 8). With RB selected in the range of 20kI to
50kI, RU can be calculated as:
OUTF
UB
V
R R 1k
1.22
= × −Ω
where RB is in kI.
Programming the Current Limit of the
Flyback/Boost Converter (RLIMF)
The devices include a robust overcurrent-protection
scheme that protects them during overload and short-
circuit conditions. For the flyback/boost converter, the
devices include a cycle-by-cycle peak current limit that
turns off the driver whenever the current into the LXF pin
exceeds an internal limit programmed by the resistor
connected from the RLIMF pin to ground. The devices
include a runaway current limit that protects them during
short-circuit conditions. One occurrence of the runaway
current limit trigger a hiccup mode, protecting the con-
verter by immediately suspending switching for a period
of time (32ms). This allows the overload current to decay
due to power loss in the converter resistances, load, and
the output diode of the flyback/boost converter before
soft-start is attempted again. The RLIMF resistor for a
desired current limit (IPK) can be calculated as:
LIMF PK
R 50 I k=×Ω
where IPK is expressed in amperes.
For a given peak-current-limit setting, the runaway
current limit is typically 20% higher. The runaway current-
limit-triggered hiccup operation is always enabled, even
during soft-start operation.
Programming the Slope Compensation for
the Flyback/Boost Converter (SCOMPF)
When both devices operate at maximum duty cycle of
49%, in theory they do not require slope compensation
to prevent subharmonic instability that occurs naturally
in continuous peak-current-mode controlled converters
operating at duty cycles greater than 50%. In practice,
the MAX17497A requires a minimum amount of slope
compensation to provide stable, jitter-free operation. The
MAX17497A allows the user to program this default value
of slope compensation simply by connecting the RLIMF
pin to VCC. It is recommended that discontinuous-mode
designs also use this minimum amount of slope compen-
sation to provide noise immunity and jitter-free operation.
Figure 7. MAX17497B Typical Startup Circuit with Bias Winding
to Turn Off Q1 and Reduce Power Dissipation
Figure 8. Programming the Output Voltage of the Flyback/Boost
Converter
VDC
VOUTF
LXF Np Ns
D2
D1
IN
COUTF
MAX17497B
IN
NB
VCC
CVCC
CIN
RZ
ZD1
6.3V
LDO
Q1
RB
RU
EAFN
VOUTF
MAX17497A
MAX17497B
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
18Maxim Integrated
The MAX17497A flyback/boost converter can be
designed to operate in discontinuous mode or to enter
into continuous-conduction mode at a specific heavy-
load condition for a given DC input voltage. In continu-
ous-conduction mode, the flyback/boost converter needs
slope compensation to avoid subharmonic instability that
occurs naturally over all specified load and line condi-
tions in peak-current-mode-controlled converters operat-
ing at duty cycles greater than 50%. A minimum amount
of slope signal is added to the sensed current signal
even for converters operating below 50% duty cycles
to provide stable, jitter-free operation. The SCOMPF pin
allows the user to program the necessary slope com-
pensation by setting the value of the RSCOMPF resistor
connected from the SCOMPF pin to ground:
SCOMPF E
R 0.5 S k= Ω
where the slope (SE) is expressed in millivolts per micro-
second.
Step-Down Overcurrent Protection
The devices’ step-down regulator includes a robust
overcurrent-protection scheme that protects them dur-
ing overload and short-circuit conditions. A runaway
current limit on the high-side switch current at 1A (typ)
protects the device under short-circuit conditions. One
occurrence of the runaway current limit trigger a hiccup
mode to protect the converter by immediately suspend-
ing switching for 32ms. This allows the overload current
to decay, due to power loss in the converter resistances,
and load before soft-start is attempted again.
Error Amplifier, Loop Compensation,
and Power-Stage Design of the
Flyback/Boost Converter
The devices’ flyback/boost converter requires that prop-
er loop compensation be applied to the error-amplifier
output to achieve stable operation. The goal of the com-
pensator design is to achieve the desired closed-loop
bandwidth and sufficient phase margin at the crossover
frequency of the open-loop gain-transfer function of the
converter. The error amplifier included in the devices is a
transconductance amplifier. The compensation network
used to apply the necessary loop compensation is shown
in Figure 9.
The flyback/boost converter can be used to implement
the following converters and operating modes:
• Nonisolated flyback converter in discontinuous-
conduction mode (DCM flyback)
• Nonisolatedflybackconverterincontinuous-conduc-
tion mode (CCM flyback)
• Boost converter in discontinuous-conduction mode
(DCM boost)
• Boost converter in continuous-conduction mode
(CCM boost)
Calculations for loop-compensation values (RZ, CZ, and
CP) for these converter types, and design procedures for
power-stage components, are detailed in the following
sections.
DCM Flyback
Primary Inductance Selection
In a DCM flyback converter, the energy stored in the
primary inductance of the flyback transformer is ideally
delivered entirely to the output. The maximum primary-
inductance value for which the converter remains in
discontinuous mode at all operating conditions can be
calculated as:
( )
( )
2
INMIN MAX
PRIMAX OUTF D OUTF SW
V D 0.4
LV VI f
××
≤+× ×
where DMAX is 0.35 for the MAX17497A and 0.7 for the
MAX17497B, VD is the forward-voltage drop of the out-
put rectifier diode on the secondary side, and fSW is the
switching frequency of the power converter. Choose the
primary inductance value to be less than LPRIMAX.
Figure 9. Programming the Output Voltage of the Flyback/Boost
Converter
RZ
COMPF
CZ
CP
MAX17497A
MAX17497B
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
19Maxim Integrated
Duty-Cycle Calculation
The accurate value of the duty cycle (DNEW) for the
selected primary inductance LPRI can be calculated
using the following equation:
( )
PRI OUTF D OUTF SW
NEW INMIN
2.5 L V V I f
DV
× × +× ×
=
Turns Ratio Calculation (Ns/Np)
Transformer turns ratio (K = Ns/Np) can be calculated as:
( )
+ ×−
=×
OUTF D NEW
INMIN NEW
V V (1 D )
KVD
Peak/RMS Current Calculation
RMS current values in the primary and secondary are
needed by the transformer manufacturer to design the
wire diameter for the different windings. Peak current
calculations are useful in setting the current limit. Use the
following equations to calculate the primary and second-
ary peak and RMS currents:
Maximum primary peak current:
INMIN NEW
PRIPEAK PRI SW
VD
ILf
×
=×
Maximum primary RMS current:
NEW
PRIRMS PRIPEAK
D
II 3
= ×
Maximum secondary RMS current:
PRIPEAK
SECPEAK
I
IK
=
Maximum secondary peak current:
××
=×
OUT PRIPEAK
SECRMS
2I I
I3K
For current-limit setting, the peak current can be calcu-
lated as:
LIMF PRIPEAK
I I 1.2= ×
Primary Snubber Selection
Ideally, the external nMOSFET experiences a drain-
source-voltage stress equal to the sum of the input volt-
age and the reflected voltage across the primary wind-
ing during the off period of the nMOSFET. In practice,
parasitic inductances and capacitors in the circuit, such
as leakage inductance of the flyback transformer, cause
voltage overshoot and ringing. Snubber circuits are used
to limit the voltage overshoots to safe levels within the
voltage rating of the external nMOSFET. The snubber
capacitor can be calculated using the following equation:
22
LK PRIPEAK
SNUB 2
OUTF
2L I K
C
V
×× ×
=
where LLK is the leakage inductance obtained from the
transformer specifications (usually 1% to 2% of the pri-
mary inductance).
The power dissipated in the snubber resistor is calcu-
lated using the following equation:
2
SNUB LK PRIPEAK SW
P 0.833 L I f= ×× ×
The snubber resistor can be calculated based on the
following equation:
2
OUTF
SNUB 2
SNUB
6.25 V
R
PK
×
=×
The voltage rating of the snubber diode is:
OUTF
DSNUB INMAX
V
V V 2.5 K
= +×
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application
so that the output-voltage deviation is contained to 3% of
the output-voltage change. The output capacitance can
be calculated as:
STEP RESPONSE
OUTF OUTF
It
CV
×
=∆
RESPONSE C SW
0.33 1
t ()
ff
≅+
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output volt-
age deviation, and fC is the target closed-loop crossover
frequency. fC is chosen to be 1/10 of the switching fre-
quency (fSW). For the flyback converter, the output
capacitor supplies the load current when the main switch
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
20Maxim Integrated
is on, and the output-voltage ripple is therefore a function
of load current and duty cycle. Use the following equa-
tion to calculate the output-capacitor ripple:
( )
−
××
∆=
× ××
2
OUT PRIPEAK OUTF
COUTF 2
PRIMPEAK SW OUTF
I I KI
V
2I f C
where IOUTF is the load current and DNEW is the duty
cycle at minimum input voltage.
Input-Capacitor Selection
The MAX17497A is optimized for implementing offline
AC-DC converters. In such applications, the input capac-
itor must be selected based either on the ripple due to
the rectified line voltage or on hold-up time requirements.
Hold-up time can be defined as the time period over
which the power supply should regulate its output volt-
age from the instant the AC power fails. The MAX17497B
is useful for implementing low-voltage DC-DC applica-
tions where the switching-frequency ripple must be
used to calculate the input capacitor. In both cases, the
capacitor must be sized to meet RMS current require-
ments for reliable operation.
Capacitor Selection Based on Switching Ripple
(MAX17497B): For DC-DC applications, X7R ceramic
capacitors are recommended due to their stability over
the operating temperature range. The ESR and ESL of a
ceramic capacitor are relatively low, so the ripple voltage
is dominated by the capacitive component. For the fly-
back converter, the input capacitor supplies the current
when the main switch is on. The following equation cal-
culates the input capacitor for a specified peak-to-peak
input switching-ripple voltage (VIN_RIP):
( )
2
NEW PRIPEAK NEW
IN SW IN_RIP
D I 1 0.5 D
C2f V
× −×
=××
Capacitor Selection Based on Rectified Line Voltage
Ripple (MAX17497A): For the flyback converter, the
input capacitor supplies the input current when the diode
rectifier is off:
×
=η×
LOAD
IN 2
INPK
0.45 P
C
V
where PLOAD is the rated output power, VINPK is the
peak voltage at minimum input, and η is the efficiency at
minimum input at maximum load.
Capacitor Selection Based on Hold-Up Time
Requirements (MAX17497A): For a given output power
(PHOLDUP) that needs to be delivered during hold-up
time (tHOLDUP), DC bus voltage at which the AC supply
fails (VINFAIL), and the minimum DC bus voltage at which
the converter can regulate the output voltages (VINMIN),
the input capacitor (CIN) is estimated as:
()
HOLDUP HOLDUP
IN 22
INFAIL INMIN
3P t
C
VV
××
=−
The input capacitor RMS current can be calculated as
follows:
×
=η×
LOAD
INCRMS INPK
2.7 P
IV
External MOSFET Selection
MOSFET selection criteria includes the maximum drain
voltage, peak/RMS current in the primary, and the
maximum allowable power dissipation of the package
without exceeding the junction temperature limits. The
voltage seen by the MOSFET drain is the sum of the input
voltage, the reflected secondary voltage on the trans-
former primary, and the leakage inductance spike. The
MOSFET’s absolute maximum VDS rating must be higher
than the worst-case drain voltage:
OUTF D
DSMAX INMAX
VV
V V 2.5
K
+
=+×
The drain-current rating of the external MOSFET is
selected to be greater than the worst-case peak current-
limit setting.
Secondary Diode Selection
Secondary diode-selection criteria includes the maxi-
mum reverse voltage, average current in the secondary,
reverse recovery time, junction capacitance, and the
maximum allowable power dissipation of the package.
The voltage stress on the diode is the sum of the output
voltage and the reflected primary voltage.
The maximum operating reverse-voltage rating must be
higher than the worst-case reverse voltage:
SECDIODE INMAX OUTF
V 1.25 (K V V )= ×× +
The current rating of the secondary diode should be
selected such that the power loss in the diode (given
as the product of forward-voltage drop and the average
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
21Maxim Integrated
diode current) should be low enough to ensure that the
junction temperature is within limits. This necessitates
the diode-current rating be in the order of 2 x IOUTF to
3x IOUTF. Select fast-recovery diodes with a recovery
time less than 50ns, or Schottky diodes with low junction
capacitance.
Error-Amplifier Compensation Design
The loop-compensation values are calculated as:
2
SW OUTF OUTF
P
ZPRI SW
0 . 1f
1 VI
f
R 450 2L f
+ ××
= × ××
OUTF
POUTF OUTF
I
fVC
=π× ×
ZZP
PZ SW
1
CRf
1
CRf
=π× ×
=π× ×
The devices’ switching frequency (fSW) can be ob-
tained from the Electrical Characteristics section.
In a typical application, the integrated step-down
regulator is fed off the flyback converter’s output. The
step-down regulator poses negative input impedance
or constant input power behavior. Due to this behavior,
the loop bandwidth measured for the flyback converter
would be smaller than the design bandwidth.
CCM Flyback
Transformer Turns Ratio Calculation (K = Ns/Np)
The transformer turns ratio can be calculated using the
following equation:
( )
OUT D MAX
INMIN MAX
V V (1 D )
KVD
+ ×−
=×
where DMAX is the duty cycle assumed at minimum input
(0.35 for the MAX17497A and 0.7 for the MAX17497B).
Primary Inductance Calculation
Calculate the primary inductance based on the ripple:
( )
+ ×−
=× ×β× ×
2
OUTF D NOM
PRI 2
OUTF SW
V V (1 D )
L
2I f K
where DNOM, the nominal duty cycle at nominal operat-
ing DC input voltage (VINNOM), is given as:
( )
( )
+
=
×+ +
OUT D
NOM INNOM OUT D
VV
DV KV V
The output current, down to which the flyback converter
should operate in CCM, is determined by selection of
the fraction A in the above primary inductance formula.
For example, A should be selected as 0.15 so that the
converter operates in CCM down to 15% of the maxi-
mum output-load current. Since the ripple in the primary
current waveform is a function of duty cycle, and is
maximum-at-maximum DC input voltage, the maximum
(worst-case) load current, down to which the converter
operates in CCM, occurs at maximum operating DC input
voltage. VD is the forward drop of the selected output
diode at maximum output current.
Peak and RMS Current Calculation
RMS current values in the primary and secondary are
needed by the transformer manufacturer to design the
wire diameter for the different windings. Peak-current
calculations are useful in setting the current limit. Use the
following equations to calculate the primary and second-
ary peak and RMS currents:
Maximum primary peak current:
OUTF INMIN MAX
PRIPEAK MAX PRI SW
IK
VD
I1D 2L f
××
= +
− ××
Maximum primary RMS current:
( )
2
2PRI
PRIRMS PRIPEAK PRIPEAK PRI
2
MAX
I
II I I
3
D
∆
= + − ×∆
×
where
DIPRI is the ripple current in the primary current
waveform, and is given by:
INMIN MAX
PRI PRI SW
VD
ILf
×
∆=
×
Maximum secondary peak current:
PRIPEAK
SECPEAK
I
IK
=
Maximum secondary RMS current:
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
22Maxim Integrated
( )
2
2SEC
SECRMS SECPEAK SECPEAK SEC
2
MAX
I
II I I
3
1D
∆
= + − ×∆
×−
where DISEC is the ripple current in the secondary current
waveform, and is given by:
INMIN MAX
SEC PRI SW
VD
IL fK
×
∆=
××
Current-limit setting the peak current can be calculated
as follows:
LIMF PRIPEAK
I I 1.2= ×
Primary RCD Snubber Selection
The design procedure for RCD snubber selection is iden-
tical to that outlined in the DCM Flyback section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
STEP RESPONSE
OUTF OUTF
It
CV
×
=∆
RESPONSE C SW
0.33 1
t ()
ff
≅+
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output
voltage deviation, and fC is the target closed-loop cross-
over frequency. fC is chosen to be less than 1/5 of the
worst-case (lowest) RHP zero frequency (fRHP). The right
half-plane zero frequency is calculated as:
2
MAX OUTF
ZRHP 2
MAX PRI OUTF
(1 D ) V
f
2D LI K
−×
=×π× × × ×
For the CCM flyback converter, the output capacitor
supplies the load current when the main switch is on,
and therefore the output-voltage ripple is a function of
load current and duty cycle. Use the following equation
to estimate the output-voltage ripple:
OUTF MAX
COUTF SW OUTF
ID
VfC
×
∆=
×
Input-Capacitor Selection
The design procedure for input capacitor selection is
identical to that outlined in the DCM Flyback section.
External MOSFET Selection
The design procedure for external MOSFET selection is
identical to that outlined in the DCM Flyback section.
Secondary Diode Selection
The design procedure for secondary diode selection is
identical to that outlined in the DCM Flyback section.
Error-Amplifier Compensation Design
In the CCM flyback converter, the primary inductance
and the equivalent load resistance introduces a right
half-plane zero at the following frequency:
2
MAX OUTF
ZRHP 2
MAX PRI OUTF
(1 D ) V
f
2D LI K
−×
=×π× × × ×
The loop-compensation values are calculated as:
( )
×
= × + ×+
−×
2
OUTF RHP
Z MAX
MAX P
200 I f
R K1 1 D
(1 D ) 5 f
where fP, the pole due to output capacitor and load, is
given by:
MAX OUTF
POUTF OUTF
(1 D ) I
f2C V
+×
=×π× ×
The above selection sets the loop-gain crossover fre-
quency (fC, where the loop gain equals 1) equal to 1/5
the right half-plane zero frequency:
ZRHP
C
f
f5
≤
With the control-loop zero placed at the load pole fre-
quency:
ZZP
1
C2R f
=π× ×
With the high-frequency pole placed at 1/2 the switching
frequency:
PZ SW
1
CRf
=π× ×
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
23Maxim Integrated
DCM Boost
In a DCM boost converter, the inductor current returns to
zero in every switching cycle. Energy stored during the
on-time of the main switch is delivered entirely to the load
in each switching cycle.
Inductance Selection
The design procedure starts with calculating the boost
converter’s input inductor, such that it operates in DCM
at all operating line and load conditions. The critical
inductance required to maintain DCM operation is cal-
culated as:
( )
2
OUTF INMIN INMIN
IN 2
OUTF OUTF SW
V V V 0.4
L
IV f
−× ×
≤××
where VINMIN is the minimum input voltage.
Peak/RMS Current Calculation
To set the current limit, the peak current in the inductor
can be calculated as:
LIMF PK
I I 1.2= ×
where IPK is given by:
OUTF INMIN OUTF
PK INMIN SWMIN
2 (V V ) I
ILf
×−×
=
×
LINMIN is the minimum value of the input inductor, taking
into account tolerance and saturation effects. fSWMIN is
the minimum switching frequency for the MAX17497B
from the Electrical Characteristics section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
STEP RESPONSE
OUT OUTF
It
CV
×
=∆
RESPONSE C SW
0.33 1
t ()
ff
≅+
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output-
voltage deviation, and fC is the target closed-loop cross-
over frequency. fC is chosen to be 1/10 the switching
frequency (fSW). For the boost converter, the output
capacitor supplies the load current when the main switch
is on, and therefore the output-voltage ripple is a function
of duty cycle and load current. Use the following equa-
tion to calculate the output-capacitor ripple:
OUTF IN PK
COUTF INMIN OUTF
I LI
VVC
××
∆=
×
Input-Capacitor Selection
The value of the required input capacitor can be calcu-
lated based on the ripple allowed on the input DC bus.
The size of the input capacitor should be based on the
RMS value of the AC current handled by it. The calcula-
tions are as:
OUTF
INF INMIN SWMIN MAX
3.75 I
CV f (1 D )
×
=
× ×−
The capacitor RMS can be calculated as:
PK
CIN_RMS
I
I23
=×
Error-Amplifier Compensation Design
The DC gain of the power stage is given as:
× − ×× ×
=−×
2
OUTF INMIN SW OUTF IN
DC 2
OUTF INMIN OUTF
2 (V V ) f V L
G
(2V V ) I
The loop-compensation values for the error amplifier can
be calculated as:
( )
( )
−
−
××
=π ××
OUTF INMIN OUTF
POUTF INMIN OUTF OUTF
2V V I
f2V V V C
where VINMIN is the minimum operating input voltage
and IOUTF is the maximum load current.
××
= ×+ ×+
2
OUTF SW
ZP
230 V 0.1 f ms
R 11
GDC f mp
where ms = default slope compensation and mp =
VINMIN/L x 0.5.
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
24Maxim Integrated
=π× ×
=π× ×
ZPZ
PSW Z
1
C2fR
1
CfR
Slope Compensation
In theory, the DCM boost converter does not require
slope compensation for stable operation. In practice, the
converter needs a minimum amount of slope for good
noise immunity at very light loads. The minimum slope
is set for the devices by connecting the SCOMPF pin to
the VCC pin.
Output Diode Selection
The voltage rating of the output diode for the boost
converter ideally equals the output voltage of the boost
converter. In practice, parasitic inductances and capaci-
tances in the circuit interact to produce voltage over-
shoot during the turn-off transition of the diode that
occurs when the main switch turns on. The diode rating
should therefore be selected with the necessary margin
to accommodate this extra voltage stress. A voltage rat-
ing of 1.3 x VOUTF provides the necessary design margin
in most cases.
The current rating of the output diode should be selected
such that the power loss in the diode (given as the
product of forward-voltage drop and the average diode
current) should be low enough to ensure that the junction
temperature is within limits. This necessitates the diode
current rating to be in the order of 2 x IOUTF to 3 x IOUTF.
Select fast-recovery diodes with a recovery time less than
50ns, or Schottky diodes with low junction capacitance.
Internal MOSFET RMS Current Calculation
The voltage stress on the internal MOSFET, whose drain
is connected to LXF, ideally equals the sum of the out-
put voltage and the forward drop of the output diode.
In practice, voltage overshoot and ringing occur due
to action of circuit parasitic elements during the turn-off
transition. The maximum rating of the internal nMOSFET
of the devices is 65V, making it possible to design boost
converters with output voltages up to 48V, with sufficient
margin for voltage overshoot and ringing. The RMS
current into LXF is useful in estimating the conduction
loss in the internal nMOSFET and is given as:
3
PK INS SW
LXF_RMS INMIN
I Lf
I3V
××
=×
where IPK is the peak current calculated at the lowest
operating input voltage (VINMIN).
CCM Boost
In a CCM boost converter, the inductor current does
not return to zero during a switching cycle. Since the
MAX17497B implements a nonsynchronous boost con-
verter, the inductor current enters DCM operation at load
currents below a critical value, equal to 1/2 the peak-to-
peak ripple in the inductor current.
Inductor Selection
The design procedure starts with calculating the boost
converter’s input inductor at nominal input voltage for a
ripple in the inductor current, equal to 30% of the maxi-
mum input current:
IN
IN OUTF SW
V D (1 D)
L0.3 I f
××−
=××
where D is the duty cycle calculated as:
OUTF D IN
OUTF D
V VV
DVV
+−
=+
VD is the voltage drop across the output diode of the
boost converter at maximum output current.
Peak/RMS Current Calculation
To set the current limit, the peak current in the inductor
and internal nMOSFET can be calculated as:
× ×−
= +×
×−
<
OUTF MAX MAX OUTF
PK IN SW MAX
MAX
V D (1 D ) I
I 1.2
L f (1 D )
for D 0.5
×
= +× ≥
×−
OUTF OUTF
PK MAX
IN SW MAX
0.25 V I
I 1.2 for D 0.5
L f (1 D )
DMAX, the maximum duty cycle, is obtained by substitut-
ing the minimum input operating voltage (VINMIN) in the
equation above for duty cycle. LINMIN is the minimum
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
25Maxim Integrated
value of the input inductor taking into account tolerance
and saturation effects. fSWMIN is the minimum switch-
ing frequency for the MAX17497B from the Electrical
Characteristics section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
STEP RESPONSE
OUTF OUTF
It
CV
×
=∆
RESPONSE C SW
0.33 1
t ()
ff
≅+
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output-
voltage deviation, and fC is the target closed-loop
crossover frequency. fC is chosen as 1/10 the switch-
ing frequency (fSW). For the boost converter, the output
capacitor supplies the load current when the main switch
is on, and therefore the output-voltage ripple is a function
of duty cycle and load current. Use the following equa-
tion to calculate the output-capacitor ripple:
OUTF MAX
COUTF OUTF SW
ID
VCf
×
∆=×
Input-Capacitor Selection
The input ceramic capacitor value required can be
calculated based on the ripple allowed on the input DC
bus. The input capacitor should be sized based on the
RMS value of the AC current handled by it. The calcula-
tions are as:
OUTF
INF INMIN SW MAX
3.75 I
CV f (1 D )
×
=
× ×−
The input-capacitor RMS current can be calculated as:
LIN
CIN_RMS
I
I23
∆
=×
where:
× ×−
∆= <
×
OUTF MAX MAX
LIN MAX
IN SW
V D (1 D )
I for D 0.5
Lf
×
∆= ≥
×
OUTF
LIN MAX
IN SW
0.25 V
I for D 0.5
Lf
Error-Amplifier Compensation Design
The loop-compensation values for the error amplifier can
now be calculated as:
× × ×−
=×
2
OUTF OUTF MAX
ZOUTF IN
90 V C (1 D )
RIL
where DMAX is the duty cycle at the lowest operating input
voltage and IOUTF_MAX is the maximum load current:
OUTF OUTF
ZOUTF Z
VC
C2I R
×
=××
PSW Z
1
CfR
=π× ×
Slope-Compensation Ramp
The slope required to stabilize the converter at duty
cycles greater than 50% can be calculated as:
×−
=OUTF INMIN
EIN
0.41 (V V )
S V per µs
L
where LIN is in FH.
Output Diode Selection
The design procedure for output diode selection is identi-
cal to that outlined in the DCM Boost section.
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
26Maxim Integrated
Internal MOSFET RMS Current Calculation
The voltage stress on the internal MOSFET, whose drain
is connected to LXF, ideally equals the sum of the output
voltage and the forward drop of the output diode. In prac-
tice, voltage overshoot and ringing occur due to action
of circuit parasitic elements during the turn-off transition.
The devices’ maximum rating of the internal nMOSFET
is 65V, making it possible to design boost converters
with output voltages up to 48V, with sufficient margin for
voltage overshoot and ringing. The RMS current into LXF
is useful in estimating the conduction loss in the internal
nMOSFET and is given as:
OUTF MAX
LXF_RMS MAX
ID
I(1 D )
×
=−
where DMAX is the duty cycle at the lowest operating
input voltage and IOUTF is the maximum load current.
Thermal Considerations
It should be ensured that the junction temperature of the
devices does not exceed +125NC under the operating
conditions specified for the power supply. The power dis-
sipated in the devices to operate can be calculated using
the following equation:
IN IN IN
P VI= ×
where VIN is the voltage applied at the IN pin and IIN is
operating supply current.
The internal nMOSFET experiences conduction loss and
transition loss when switching between on and off states.
These losses are calculated as:
( )
2
CONDUCTION LXF_RMS DSON_LXF
TRANSITION INMAX PK R F SW
P IR
P 0.5 V I t t f
= ×
=× ××+×
where tR and tF are the rise and fall times of the internal
nMOSFET in CCM operation. In DCM operation, because
the switch current starts from zero only, tF exists and the
transition loss equation changes to:
TRANSITION INMAX PK F SW
P 0.5 V I t f= × × ××
Additional loss occurs in the system in every switch-
ing cycle due to energy stored in the drain-source
capacitance of the internal MOSFET being lost when
the MOSFET turns on and discharges the drain-source
capacitance voltage to zero. This loss is estimated as:
2
CAP DS DSMAX SW
P 0.5 C V f=×× ×
The internal step-down regulator also has similar losses
that affect the temperature rise of the part. These losses
are estimated as:
()
2
LOSSBUCK OUTB DC
OUT
1
P P ( 1) I R= × −− ×
η
where E is the efficiency of the internal step-down
regulator at the output current (IOUTB), and RDC is the
DC resistance of the output inductor.
The total power loss in the devices can be calculated
from the following equation:
LOSS IN CONDUCTION TRANSITION CAP
LOSSBUCK
P PP P P
P
=+ ++
+
The maximum power that can be dissipated in the
devices is 1666mW at +70NC temperature. The power-
dissipation capability should be derated as the tem-
perature rises above +70NC at 21mW/NC. For a multilayer
board, the thermal-performance metrics for the package
are given below:
JA 48 C/Wθ=°
JC 10 C/Wθ=°
The junction temperature rise of the devices can be
estimated at any given maximum ambient temperature
(TA_MAX) from the following equation:
( )
J_MAX A_MAX JA LOSS
TT P= +θ ×
If the application has a thermal-management system that
ensures that the devices’ exposed pad is maintained at a
given temperature (TEP_MAX) by using proper heatsinks,
then the junction temperature rise can be estimated at
any given maximum ambient temperature from the fol-
lowing equation:
( )
J_MAX EP_MAX JC LOSS
TT P= +θ ×
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
27Maxim Integrated
Figure 10. MAX17497A Typical Application Example (e.g., Smart Meter)
C13
1µF/25V
INB
R22
10kI
VCC
RESETN
RESETN
C16
10µF/6.3V
PGNDB
LXB
VOUT3
3.3V, 0.6A
L2
15µH
PGNDF
ININ EP
RLIMF
SSF
R11
30kI
C12
47nF
VCC
SCOMPF
VCC
C4
2.2µF
EAFN
VOUT1
R17
49.9kI
R19
4.22kI
R18
442kI
R5
36.5kI
R6
10kI
EN/UVLO
OVI
R4
1.1MI
R3
1.1MI
R2
1.1MI
VIN
R15
3MI
R14
3MI
3MI
R12
3MI
IN
C6
0.47µF
/35V
R23
10kI
N2
FQT1N80TF
C7
2.2µF/50V
VOUT1
Q1
D2
VIN
R10
1.2MI
C3
100µF/
400V
C2
100µF/
400V
L1
1mH
R9
1.2MI
R8
1.2MI
C1
0.1µF/
1kV
D1
LINE
NEUTRAL
85V AC TO
265V AC
R7
1.2MI
R1
10I
OUTB VOUT3
VOUT1
LXF
D4
D3
D5 N1
C8
0.1µF/25V
C14
22µF/
25V
C10
2.2nF/
250V
R16
100kI/0.5W
R20
10I
T1
C15
OPEN
VOUT1
IN
VOUT1
12V, 0.3A
PGND
MAX17497A
COMPF
C11
330pF
C9
0.15µF
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
28Maxim Integrated
Figure 11. MAX17497B Typical Application Example
MAX17497B
IN
VOUT1
R8
49.9kI
VCC
C9
10µF/6.3V
R9
10kI
C8
1µF/25V
VCC
SCOMPF
EAFN
COMPF
OUTB
PGNDB
LXB
INB
RESETN
RESETN
VOUT2
3.3V, 0.6A
L2
15µH
PGNDF
IN
L1
15µH D1
SS26-TP
C7
4.7µF/35V
VOUT1
24V, 0.2A
LXF
IN
VCC
OVI
EP
R7
25kI
R6
481kI
R5
15kI
R2
OPEN
R4
184kI
R3
9.92kI
C5
10nF
C4
2.2µF
C2
0.1µF
C1
10µF
IN
VIN
PGND
10.8V TO
13.2V DC
IN
RLIMF
SSF
R1
75kI
C3
47nF
C6
47pF
EN/UVLO
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
29Maxim Integrated
Layout, Grounding, and Bypassing
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due
to the high di/dt of the currents in high-frequency switch-
ing power converters. This implies that the loop areas for
forward and return pulsed currents in various parts of the
circuit should be minimized. Additionally, small-current
loop areas reduce radiated EMI. Similarly, the heatsink
of the main MOSFET presents a dV/dt source; therefore,
the surface area of the MOSFET heatsink should be mini-
mized as much as possible.
Ground planes must be kept as intact as possible. The
ground plane for the power section of the converter
should be kept separate from the analog ground plane,
except for a connection at the least noisy section of the
power ground plane, typically the return of the input filter
capacitor. The negative terminal of the filter capacitor,
the ground return of the power switch, and the current-
sensing resistor must be close together. PCB layout also
affects the thermal performance of the design. A number
of thermal vias that connect to a large ground plane
should be provided under the exposed pad of the part for
efficient heat dissipation. For a sample layout that ensures
first-pass success, refer to the MAX17497A evaluation kit
layout available at www.maximintegrated.com.
For universal AC input designs, follow all applicable
safety regulations. Offline power supplies can require UL,
VDE, and other similar agency approvals.
Ordering Information
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE DESCRIPTION
MAX17497AATE+ -40NC to +125NC16 TQFN 250kHz, Offline Flyback Converter with 3.3V, 600mA
Synchronous Step-Down Converter
MAX17497BATE+ -40NC to +125NC16 TQFN 500kHz, Flyback/Boost Converter with 3.3V, 600mA
Synchronous Step-Down Converter
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
16 TQFN T1633+5 21-0136 90-0032
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 11/11 Initial release —
1 1/12 Removed future product reference for MAX17497B 29
2 10/12 Modified according to GBD data
1–4, 7–9, 17,
18, 19, 21, 22,
24, 25, 27, 28,
29
3 4/13 Part modification, updated Figure 1, Figure 10, and equations 1, 12, 13, 21,
24, 27
