LM49370RLEVAL - National Semiconductor

February 11, 2008

LM49370

Audio Sub-System with an Ultra Low EMI, Spread

Spectrum, Class D Loudspeaker Amplifier, a Dual-Mode

Stereo Headphone Amplifier, and a Dedicated PCM

Interface for Bluetooth Transceivers

1.0 General Description

The LM49370 is an integrated audio subsystem that supports

both analog and digital audio functions. The LM49370 in-

cludes a high quality stereo DAC, a mono ADC, a stereo

headphone amplifier, which supports output cap-less (OCL)

or AC-coupled (SE) modes of operation, a mono earpiece

amplifier, and an ultra-low EMI spread spectrum Class D

loudspeaker amplifier. It is designed for demanding applica-

tions in mobile phones and other portable devices.

The LM49370 features a bi-directional I2S interface and a bi-

directional PCM interface for full range audio on either inter-

face. The LM49370 utilizes an I2C or SPI compatible interface

for control. The stereo DAC path features an SNR of 85 dB

with an 18-bit 48 kHz input. In SE mode the headphone am-

plifier delivers at least 33 mWRMS to a 32Ω single-ended

stereo load with less than 1% distortion (THD+N) when

A_VDD = 3.3V. The mono earpiece amplifier delivers at least

115mWRMS to a 32Ω bridged-tied load with less than 1% dis-

tortion (THD+N) when A_VDD = 3.3V. The mono speaker

amplifier delivers up to 490mW into an 8Ω load with less than

1% distortion when LS_VDD = 3.3V and up to 1.2W when

LS_VDD = 5.0V.

The LM49370 employs advanced techniques to reduce pow-

er consumption, to reduce controller overhead, to speed de-

velopment time, and to eliminate click and pop. Boomer audio

power amplifiers were designed specifically to provide high

quality output power with a minimal amount of external com-

ponents. It is therefore ideally suited for mobile phone and

other low voltage applications where minimal power con-

sumption, PCB area and cost are primary requirements.

2.0 Applications

■Smart phones

■Mobile Phones and Multimedia Terminals

■PDAs, Internet Appliances and Portable Gaming

■Portable DVD/CD/AAC/MP3 Players

■Digital Cameras/Camcorders

3.0 Key Specifications

■PHP (AC-COUP) (A_VDD = 3.3V, 32Ω, 1% THD) 33 mW

■PHP (OCL) (A_VDD = 3.3V, 32Ω, 1% THD) 31 mW

■PLS ( LS_VDD = 5V, 8Ω, 1% THD) 1.2 W

■PLS (LS_VDD = 4.2V, 8Ω, 1% THD) 900 mW

■PLS (LS_VDD = 3.3V, 8Ω, 1% THD) 490 mW

■Shutdown Current 0.8 µA

■PSRRLS (217 Hz, LS_VDD = 3.3V) 70 dB

■SNRLS (AUX IN to Loudspeaker) 90 dB (typ)

■SNRDAC (Stereo DAC to AUXOUT) 85 dB (typ)

■SNRADC (Mono ADC from Cell Phone In) 90 dB (typ)

■SNRHP (Aux In to Headphones) 98 dB (typ)

4.0 Features

■Spread Spectrum Class D architecture reduces EMI

■Mono Class D 8Ω amplifier, 490 mW at 3.3V

■OCL or AC-coupled headphone operation

■33mW stereo headphone amplifier at 3.3V

■115 mW earpiece amplifier at 3.3V

■18-bit stereo DAC

■16-bit mono ADC

■8 kHz to 192 kHz stereo audio playback

■8 kHz to 48 kHz mono recording

■Bidirectional I2S compatible audio interface

■Bidirectional PCM compatible audio interface for

Bluetooth transceivers

■I2S-PCM Bridge with sample rate conversion

■Sigma-Delta PLL for operation from any clock at any

sample rate

■Digital 3D Stereo Enhancement

■FIR filter programmability for simple tone control

■Low power clock network operation if a 12 MHz or 13 MHz

system clock is available

■Read/write I2C or SPI compatible control interface

■Automatic headphone & microphone detection

■Support for internal and external microphones

■Automatic gain control for microphone input

■Differential audio I/O for external cellphone module

■Mono differential auxiliary output

■Stereo auxiliary inputs

■Differential microphone input for internal microphone

■Flexible audio routing from input to output

■32 Step volume control for mixers in 1.5 dB steps

■16 Step volume control for microphone in 2 dB steps

■Programmable sidetone attenuation in 3 dB steps

■Two configurable GPIO ports

■Multi-function IRQ output

■Micro-power shutdown mode

■Available in the 4 x 4 mm 49 bump micro SMDxt package

Boomer® is a registered trademark of National Semiconductor Corporation.

LM49370 Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker

Amplifier, a Dual-Mode Stereo Headphone Amplifier, and a Dedicated PCM Interface for

Bluetooth Transceivers

5.0 LM49370 Overview

20191724

FIGURE 1. Conceptual Schematic

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LM49370

6.0 Typical Application

20191723

FIGURE 2. Example Application in Multimedia Mobile Phone

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LM49370

Table of Contents

1.0 General Description ......................................................................................................................... 1

2.0 Applications .................................................................................................................................... 1

3.0 Key Specifications ........................................................................................................................... 1

4.0 Features ........................................................................................................................................ 1

5.0 LM49370 Overview .......................................................................................................................... 2

6.0 Typical Application ........................................................................................................................... 3

7.0 Connection Diagrams ....................................................................................................................... 5

7.1 PIN TYPE DEFINITIONS ................................................................................................................ 7

8.0 Absolute Maximum Ratings .............................................................................................................. 8

9.0 Operating Ratings ........................................................................................................................... 8

10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V, BB_VDD = 1.8V,

A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise stated.

Limits apply for 25°C. .............................................................................................................................. 8

11.0 System Control ............................................................................................................................ 14

11.1 I2C SIGNALS ............................................................................................................................ 14

11.2 I2C DATA VALIDITY .................................................................................................................. 14

11.3 I2C START AND STOP CONDITIONS .......................................................................................... 14

11.4 TRANSFERRING DATA ............................................................................................................. 14

11.5 I2C TIMING PARAMETERS ....................................................................................................... 16

12.0 Status & Control Registers ............................................................................................................ 18

12.1 BASIC CONFIGURATION REGISTER ......................................................................................... 19

12.2 CLOCKS CONFIGURATION REGISTER ...................................................................................... 20

12.3 LM49370 CLOCK NETWORK ..................................................................................................... 21

12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC ................................................................... 22

12.5 PLL M DIVIDER CONFIGURATION REGISTER ............................................................................ 23

12.6 PLL N DIVIDER CONFIGURATION REGISTER ............................................................................ 24

12.7 PLL P DIVIDER CONFIGURATION REGISTER ............................................................................ 25

12.8 PLL N MODULUS CONFIGURATION REGISTER ......................................................................... 26

12.9 FURTHER NOTES ON PLL PROGRAMMING ............................................................................... 27

12.10 ADC_1 CONFIGURATION REGISTER ....................................................................................... 30

12.11 ADC_2 CONFIGURATION REGISTER ....................................................................................... 31

12.12 AGC_1 CONFIGURATION REGISTER ...................................................................................... 32

12.13 AGC_2 CONFIGURATION REGISTER ...................................................................................... 33

12.14 AGC_3 CONFIGURATION REGISTER ...................................................................................... 34

12.15 AGC OVERVIEW ..................................................................................................................... 35

12.16 MIC_1 CONFIGURATION REGISTER ........................................................................................ 36

12.17 MIC_2 CONFIGURATION REGISTER ........................................................................................ 37

12.18 SIDETONE ATTENUATION REGISTER ..................................................................................... 38

12.19 CP_INPUT CONFIGURATION REGISTER ................................................................................. 38

12.20 AUX_LEFT CONFIGURATION REGISTER ................................................................................. 39

12.21 AUX_RIGHT CONFIGURATION REGISTER ............................................................................... 39

12.22 DAC CONFIGURATION REGISTER .......................................................................................... 40

12.23 CP_OUTPUT CONFIGURATION REGISTER .............................................................................. 41

12.24 AUX_OUTPUT CONFIGURATION REGISTER ............................................................................ 41

12.25 LS_OUTPUT CONFIGURATION REGISTER .............................................................................. 41

12.26 HP_OUTPUT CONFIGURATION REGISTER .............................................................................. 42

12.27 EP_OUTPUT CONFIGURATION REGISTER .............................................................................. 42

12.28 DETECT CONFIGURATION REGISTER .................................................................................... 43

12.29 HEADSET DETECT OVERVIEW ............................................................................................... 44

12.30 STATUS REGISTER ................................................................................................................ 47

12.31 3D CONFIGURATION REGISTER ............................................................................................. 48

12.32 I2S PORT MODE CONFIGURATION REGISTER ........................................................................ 49

12.33 I2S PORT CLOCK CONFIGURATION REGISTER ....................................................................... 50

12.34 DIGITAL AUDIO DATA FORMATS ............................................................................................. 51

12.35 PCM PORT MODE CONFIGURATION REGISTER ...................................................................... 52

12.36 PCM PORT CLOCK CONFIGURATION REGISTER ..................................................................... 53

12.37 SRC CONFIGURATION REGISTER .......................................................................................... 54

12.38 GPIO CONFIGURATION REGISTER ......................................................................................... 56

12.39 DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS .............................................. 56

13.0 Typical Performance Characteristics .............................................................................................. 58

14.0 LM49370 Demonstration Board Schematic Diagram ......................................................................... 91

15.0 Demoboard PCB Layout ............................................................................................................... 92

16.0 Revision History .......................................................................................................................... 98

17.0 Physical Dimensions .................................................................................................................... 99

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LM49370

7.0 Connection Diagrams

49 Bump micro SMDxt

201917p3

Top View (Bump Side Down)

Order Number LM49370RL

See NS Package Number RLA49UUA

49 Bump micro SMDxt Marking

201917q7

Top View

XY — Date Code

TT — Die Traceability

G — Boomer

I3 — LM49370RL

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LM49370

Pin Descriptions

Pin Pin Name Type Direction Description

A1 EP_NEG Analog Output Earpiece negative output

A2 A_VDD Supply Input Headphone and mixer VDD

A3 INT_MIC_POS Analog Input Internal microphone positive input

A4 PCM_SDO Digital Output PCM Serial Data Output

A5 PCM_CLK Digital Inout PCM clock signal

A6 PCM_SYNC Digital Inout PCM sync signal

A7 PCM_SDI Digital Input PCM Serial Data Input

B1 A_VSS Supply Input Headphone and mixer ground

B2 EP_POS Analog Output Earpiece positive output

B3 INT_MIC_NEG Analog Input Internal microphone negative input

B4 BYPASS Analog Input A_VDD/2 filter point

B5 TEST_MODE/CS Digital Input If SPI_MODE = 1, then this pin becomes CS.

B6 PLL_FILT Analog Input Filter point for PLL VCO input

B7 PLL_VDD Supply Input PLL VDD

C1 HP_R Analog Output Headphone Right Output

C2 EXT_BIAS Analog Output External microphone supply (2.0/2.5/2.8/3.3V)

C3 INT_BIAS Analog Output Internal microphone supply (2.0/2.5/2.8/3.3V)

C4 AUX_R Analog Input Right Analog Input

C5 GPIO_2 Digital Inout General Purpose I/O 2

C6 SDA Digital Inout Control Data, I2C_SDA or SPI_SDA

C7 SCL Digital Input Control Clock, I2C_SCL or SPI_SCL

D1 HP_L Analog Output Headphone Left Output

D2 VREF_FLT Analog Inout Filter point for the microphone power supply

D3 EXT_MIC Analog Input External microphone input

D4 SPI_MODE Digital Input Control mode select 1 = SPI, 0 = I2C

D5 GPIO_1 Digital Inout General Purpose I/O 1

D6 BB_VDD Supply Input Baseband VDD for the digital I/Os

D7 D_VDD Supply Input Digital VDD

E1 HP_VMID Analog Inout Virtual Ground for Headphones in OCL mode, otherwise 1st headset detection input

E2 MIC_DET Analog Input Headset insertion/removal and microphone presence detection input.

E3 AUX_L Analog Input Left Analog Input

E4 CPI_NEG Analog Input Cell Phone analog input negative

E5 IRQ Digital Output Interrupt request signal (NOT open drain)

E6 I2S_SDO Digital Output I2S Serial Data Out

E7 I2S_SDI Digital Input I2S Serial Data Input

F1 HP_VMID_FB Analog Input VMID Feedback in OCL mode, otherwise a 2nd headset detection input

F2 LS_VDD Supply Input Loudspeaker VDD

F3 CPI_POS Analog Input Cell Phone analog input positive

F4 CPO_NEG Analog Output Cell Phone analog output negative

F5 AUX_OUT_NEG Analog Output Auxiliary analog output negative

F6 I2S_WS Digital Inout I2S Word Select Signal (can be master or slave)

F7 I2S_CLK Digital Inout I2S Clock Signal (can be master or slave)

G1 LS_NEG Analog Output Loudspeaker negative output

G2 LS_VSS Supply Input Loudspeaker ground

G3 LS_POS Analog Output Loudspeaker positive output

G4 CPO_POS Analog Output Cell Phone analog output positive

G5 AUX_OUT_POS Analog Output Auxiliary analog output positive

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LM49370

Pin Pin Name Type Direction Description

G6 D_VSS Supply Input Digital ground

G7 MCLK Digital Input Input clock from 0.5 MHz to 30 MHz

7.1 PIN TYPE DEFINITIONS

Analog Input— A pin that is used by the analog and is

never driven by the device. Supplies are

part of this classification.

Analog Output— A pin that is driven by the device and

should not be driven by external sources.

Analog Inout— A pin that is typically used for filtering a

DC signal within the device, Passive com-

ponents can be connected to these pins.

Digital Input— A pin that is used by the digital but is nev-

er driven.

Digital Output— A pin that is driven by the device and

should not be driven by another device to

avoid contention.

Digital Inout— A pin that is either open drain (I2C_SDA)

or a bidirectional CMOS in/out. In the later

case the direction is selected by a control

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LM49370

8.0 Absolute Maximum Ratings (Notes

1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Analog Supply Voltage

(A_VDD & LS_VDD)6.0V

Digital Supply Voltage

(BB_VDD & D_VDD & PLL_VDD)6.0V

Storage Temperature −65°C to +150°C

Power Dissipation (Note 3) Internally Limited

ESD Susceptibility

Human Body Model (Note 4)

Machine Model (Note 5)

2500V

200V

Junction Temperature 150°C

Thermal Resistance

θJA – RLA49 (soldered down to

PCB with 2in2 1oz. copper plane) 60°C/W

Soldering Information

9.0 Operating Ratings

Temperature Range −40°C to +85°C

Supply Voltage

D_VDD/PLL_VDD

BB_VDD

LS_VDD/A_VDD

2.5V to 4.5V

1.8V to 4.5V

2.5V to 5.5V

10.0 Electrical Characteristics (Notes 1, 2) Unless otherwise stated PLL_VDD = 3.3V, D_VDD = 3.3V,

BB_VDD = 1.8V, A_VDD = 3.3V, LS_VDD = 3.3V. The following specifications apply for the circuit shown in Figure 2 unless otherwise

stated. Limits apply for 25°C.

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

POWER

DISD Digital Shutdown Current Chip Mode '00', fMCLK = 13MHz 0.7 2.2 µA (max)

DIST Digital Standby Current Chip Mode '01', fMCLK = 13MHz 0.9 1.8 mA(max)

AISD Analog Shutdown Current Chip Mode '00' 0.1 1.2 µA(max)

AIST Analog Standby Current Chip Mode '01' 0.1 1.2 µA (max)

Digital Playback Mode Digital

Active Current

Chip Mode '10', fMCLK = 12MHz,

fS = 48kHz,

DAC on; PLL off

7.9 mA

Chip Mode '10', fMCLK = 13MHz,

fPLLOUT = 12MHz, fS = 48kHz;

DAC + PLL on

12.5 14.5 mA(max)

Digital Playback Mode Analog

Active Current

Chip Mode '10', HP On, SE mode,

DAC inputs selected 9.0 13.5 mA(max)

Chip Mode '10', HP On, OCL mode,

DAC inputs selected 9.4 13.5 mA(max)

Chip Mode '10', LS On,

DAC inputs selected 11.5 15.5 mA(max)

Analog Playback Mode Digital Active

Current

Chip Mode '10', fMCLK = 13MHz,

DAC +ADC + PLL off 0.9 1.8 mA(max)

Analog Playback Mode Analog Active

Current

Chip Mode '10', HP On, SE mode,

AUX inputs selected 5.9 9.5 mA(max)

Chip Mode '10', HP On, OCL mode,

AUX inputs selected 6.3 9.7 mA(max)

Chip Mode '10', LS On,

AUX inputs selected 8.4 12 mA(max)

CODEC Mode Digital Active Current Chip Mode '10', fMCLK = 13MHz, fS = 8kHz,

DAC +ADC on; PLL Off 2.7 3.5 mA(max)

CODEC Mode Analog Active Current Chip Mode '10', EP On,

DAC inputs selected 11.2 15.5 mA(max)

Voice Module Mode Digital Active

Current

Chip Mode '10', fMCLK = 13MHz,

DAC +ADC + PLL off 0.9 1.8 mA(max)

Voice Module Mode Analog Active

Current

Chip Mode '10', EP + CPOUT on,

CPIN input selected 7.4 11 mA(max)

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LM49370

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

LOUDSPEAKER AMPLIFIER

PLS Max Loudspeaker Power

8Ω load, LS_VDD = 5V 1.2 W

8Ω load, LS_VDD = 4.2V 0.9 W

8Ω load, LS_VDD = 3.3V 0.5 0.43 W (min)

LSTHD+N Loudspeaker Harmonic Distortion 8Ω load, LS_VDD = 3.3V,

PO = 400mW 0.04 %

LSEFF Efficiency 0 dB Input

MCLK = 12.000 MHz 84 %

PSRRLS

Power Supply Rejection Ration

(Loudspeaker)

AUX inputs terminated

CBYPASS = 1.0 µF

VRIPPLE = 200 mVP-P

fRIPPLE = 217 Hz

70 dB

SNRLS Signal to Noise Ratio From 0 dB Analog AUX input, A-weighted 90 80 dB(min)

eNOutput Noise A-weighted 62 µV

VOS Loudspeaker Offset Voltage 12 mV

HEADPHONE AMPLIFIER

PHP Headphone Power

32Ω load, 3.3V, SE 33 25 mW

(min)

16Ω load, 3.3V, SE 52 mW

32Ω load, 3.3V, OCL, VCM = 1.5V 31 mW

32Ω load, 3.3V, OCL, VCM = 1.2V 20 mW

16Ω load, 3.3V, OCL, VCM = 1.5V 50 mW

16Ω load, 3.3V, OCL, VCM = 1.2V 32 mW

PSRRHP

Power Supply Rejection Ratio

(Headphones)

AUX inputs terminated

CBYPASS = 1.0 µF

VRIPPLE = 200 mVP-P

fRIPPLE = 217 Hz

SE Mode 60 dB

OCL Mode

VCM = 1.2V 68 55 dB(min)

OCL Mode

VCM = 1.5V 65 dB

SNRHP Signal to Noise Ratio

From 0dB Analog AUX input

A-weighted

SE Mode 98 dB

OCL Mode

VCM = 1.2V 97 dB

OCL Mode

VCM = 1.5V 96 dB

HPTHD+N Headphone Harmonic Distortion 32Ω load, 3.3V, PO = 7.5mW 0.05 %

eNOutput Noise A-weighted 12 µV

ΔACH-CH

Stereo Channel-to-Channel Gain

Mismatch

0.3 dB

XTALK Stereo Crosstalk SE Mode 61 dB

OCL Mode 71 dB

VOS Offset Voltage 8 mV

EARPIECE AMPLIFIER

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LM49370

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

PEP Earpiece Power 32Ω load, 3.3V 115 100 mW

(min)

16Ω load, 3.3V 150 mW

PSRREP

Power Supply Rejection Ratio

(Earpiece)

CP_IN terminated

CBYPASS = 1.0 µF

VRIPPLE = 200 mVP-P

FRIPPLE = 217 Hz

76 dB

SNREP Signal to Noise Ratio From 0dB Analog AUX input, A-weighted 93 dB

EPTHD+N Earpiece Harmonic Distortion 32Ω load, 3.3V, PO = 50mW 0.04 %

eNOutput Noise A-weighted 41 µV

VOS Offset Voltage 8 mV

AUXOUT AMPLIFIER

THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load 0.02 %

PSRR Power Supply Rejection Ratio

CP_IN terminated

CBYPASS = 1.0μF

VRIPPLE = 200mVPP

fRIPPLE = 217Hz

86 dB

CP_OUT AMPLIFIER

THD+N Total Harmonic Distortion + Noise VO = 1VRMS, 5kΩ load 0.02 %

PSRR Power Supply Rejection Ratio

CBYPASS = 1.0μF

VRIPPLE = 200mVPP

fRIPPLE = 217Hz

86 dB

MONO ADC

RADC ADC Ripple ±0.25 dB

PBADC

ADC Passband Lower (HPF Mode 1), fS = 8 kHz 300 Hz

Upper 3470 Hz

SBAADC ADC Stopband Attenuation Above Passband 60 dB

HPF Notch, 50 Hz/60 Hz (worst case) 58 dB

SNRADC ADC Signal to Noise Ratio From CPI, A-weighted 90 dB

ADCLEVEL ADC Full Scale Input Level 1 VRMS

STEREO DAC

RDAC DAC Ripple 0.1 dB

PBDAC DAC Passband 20 kHz

SBADAC DAC Stopband Attenuation 70 dB

SNRDAC DAC Signal to Noise Ratio A-weighted, AUXOUT 85 dB

DRDAC DAC Dynamic Range 96 dB

DACLEVEL DAC Full Scale Output Level 1 VRMS

PLL

FIN Input Frequency Range Min 0.5 MHz

Max 30 MHz

I2S/PCM

fI2SCLK I2S CLK Frequency

fS = 48kHz; 16 bit mode 1.536 MHz

fS = 48kHz; 25 bit mode 2.4 MHz

fS = 8kHz; 16 bit mode 0.256 MHz

fS = 8kHz; 25 bit mode 0.4 MHz

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LM49370

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

fPCMCLK PCM CLK Frequency

fS = 48kHz; 16 bit mode 0.768 MHz

fS = 48kHz; 25 bit mode 1.2 MHz

fS = 8kHz; 16 bit mode 0.128 MHz

fS = 8kHz; 25 bit mode 0.2 MHz

DCI2S_CLK I2S_CLK Duty Cycle Min 40 % (min)

Max 60 % (max)

DCI2S_WS I2S_WS Duty Cycle 50 %

I2C

TI2CSET I2C Data Setup Time Refer to Pg. 16 for more details 100 ns (min)

TI2CHOLD I2C Data Hold Time Refer to Pg. 16 for more details 300 ns (min)

SPI

TSPISETENB Enable Setup Time 100 ns (min)

TSPIHOLD-ENB Enable Hold Time 100 ns (min)

TSPISETD Data Setup Time 100 ns (min)

TSPIHOLDD Data Hold Time 100 ns (min)

TSPICL Clock Low Time 500 ns (min)

TSPICH Clock High Time 500 ns (min)

VOLUME CONTROL

VCRAUX AUX Volume Control Range

Minimum Gain w/ AUX_BOOST OFF –46.5 dB

Maximum Gain w/ AUX_BOOST OFF 0 dB

Minimum Gain w/ AUX_BOOST ON –34.5 dB

Maximum Gain w/ AUX_BOOST ON 12 dB

VCRDAC DAC Volume Control Range

Minimum Gain w/ DAC_BOOST OFF –46.5 dB

Maximum Gain w/ DAC_BOOST OFF 0 dB

Minimum Gain w/ DAC_BOOST ON –34.5 dB

Maximum Gain w/ DAC_BOOST ON 12 dB

VCRCPIN CPIN Volume Control Range Minimum Gain –34.5 dB

Maximum Gain 12 dB

VCRMIC MIC Volume Control Range Minimum Gain 6 dB

Maximum Gain 36 dB

VCRSIDE SIDETONE Volume Control Range Minimum Gain –30 dB

Maximum Gain 0 dB

SSAUX AUX VCR Stepsize 1.5 dB

SSDAC DAC VCR Stepsize 1.5 dB

SSCPIN CPIN VCR Stepsize 1.5 dB

SSMIC MIC VCR Stepsize 2 dB

SSSIDE SIDETONE VCR Stepsize 3 dB

AUDIO PATH GAIN W/ STEREO (bit 6 of 0x00h) ENABLED (AUX_L & AUX_R signals identical and selected onto mixer)

Loudspeaker Audio Path Gain

Minimum Gain from AUX input,

BOOST OFF

–34.5 dB

Maximum Gain from AUX input,

BOOST OFF

12 dB

Minimum Gain from CPI input –22.5 dB

Maximum Gain from CPI input 24 dB

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LM49370

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

Headphone Audio Path Gain

Minimum Gain from AUX input,

BOOST OFF

–52.5 dB

Maximum Gain from AUX input,

BOOST OFF

–6 dB

Minimum Gain from CPI input –40.5 dB

Maximum Gain from CPI input 6 dB

Minimum Gain from MIC input using

SIDETONE path w/ VCRMIC gain = 6dB –30 dB

Maximum Gain from MIC input using

SIDETONE path w/ VCRMIC gain = 6dB 0 dB

Earpiece Audio Path Gain

Minimum Gain from AUX input,

BOOST OFF

–40.5 dB

Maximum Gain from AUX input,

BOOST OFF

6 dB

Minimum Gain from CPI input –28.5 dB

Maximum Gain from CPI input 18 dB

Minimum Gain from MIC input using

SIDETONE path w/ VCRMIC gain = 6dB –18 dB

Maximum Gain from MIC input using

SIDETONE path w/ VCRMIC gain = 6dB 12 dB

AUXOUT Audio Path Gain

Minimum Gain from AUX input,

BOOST OFF

–46.5 dB

Maximum Gain from AUX input,

BOOST OFF

0 dB

Minimum Gain from CPI input –34.5 dB

Maximum Gain from CPI input 12 dB

CPOUT Audio Path Gain

Minimum Gain from AUX input,

BOOST OFF

–46.5 dB

Maximum Gain from AUX input,

BOOST OFF

0 dB

Minimum Gain from MIC input 6 dB

Maximum Gain from MIC input 36 dB

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LM49370

Symbol Parameter Conditions

LM49370

Units

Typical

(Note 6)

Limit

(Notes 7,

11)

Total DC Power Dissipation

Digital Playback Mode Power

Dissipation

DAC (fS = 48kHz) and HP ON

fMCLK = 12MHz, PLL OFF 56 mW

fMCLK = 13MHz, PLL ON

fPLLOUT = 12MHz 71 mW

Analog Playback Mode Power

Dissipation

AUX Inputs selected and HP ON

fMCLK = 13MHz, PLL OFF 22 mW

VOICE CODEC Mode Power

Dissipation

PCM DAC (fS = 8kHz) + ADC (fS = 8kHz)

and EP ON

fMCLK = 13MHz, PLL OFF 46 mW

VOICE Module Mode Power Dissipation CP IN selected. EP and CPOUT ON

fMCLK = 13MHz, PLL OFF 27 mW

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional but do not guarantee specific performance limits.

Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the

device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication

of device performance.

Note 2: All voltages are measured with respect to the relevant VSS pin unless otherwise specified. All grounds should be coupled as close as possible to the

device.

Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum

allowable power dissipation is PDMAX = (TJMAX – TA)/ θJA or the number given in Absolute Maximum Ratings, whichever is lower.

Note 4: Human body model: 100pF discharged through a 1.5kΩ resistor.

Note 5: Machine model: 220pF – 240pF discharged through all pins.

Note 6: Typical values are measured at 25°C and represent the parametric norm.

Note 7: Limits are guaranteed to Nationals AOQL (Average Outgoing Quality Level).

Note 8: Best operation is achieved by maintaining 3.0V < A_VDD < 5.0 and 3.0V < D_VDD < 3.6V and A_VDD > D_VDD.

Note 9: Digital shutdown current is measured with system clock set for PLL output while the PLL is disabled.

Note 10: Disabling or bypassing the PLL will usually result in an improvement in noise measurements.

Note 11: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

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LM49370

11.0 System Control

Method 1. I2C Compatible Interface

11.1 I2C SIGNALS

In I2C mode the LM49370 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these

signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49370 is 00110102.

11.2 I2C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can

only be changed when SCL is LOW.

201917q1

I2C Signals: Data Validity

11.3 I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning

from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is

HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and

free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and

repeated START conditions are equivalent, function-wise.

201917q2

11.4 TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data

has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse,

signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been re-

ceived.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eight bit which is

a data direction bit (R/W). The LM49370 address is 00110102. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a

READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected

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LM49370

201917q3

I2C Chip Address

201917q5

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by slave)

rs = repeated start

Example I2C Write Cycle

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LM49370

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle

waveform.

201917q6

Example I2C Read Cycle

201917p9

I2C Timing Diagram

11.5 I2C TIMING PARAMETERS

Symbol Parameter Limit Units

Min Max

1 Hold Time (repeated) START Condition 0.6 µs

2 Clock Low Time 1.3 µs

3 Clock High Time 600 ns

4 Setup Time for a Repeated START Condition 600 ns

5 Data Hold Time (Output direction, delay generated by LM49370) 300 900 ns

5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns

6 Data Setup Time 100 ns

7 Rise Time of SDA and SCL 20+0.1Cb300 ns

8 Fall Time of SDA and SCL 15+0.1Cb300 ns

9 Set-up Time for STOP condition 600 ns

10 Bus Free Time between a STOP and a START Condition 1.3 µs

CbCapacitive Load for Each Bus Line 10 200 pF

NOTE: Data guaranteed by design

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LM49370

Method 2. SPI/Microwire Control/3–wire Control

The LM49370 can be controlled via a three wire interface consisting of a clock, data and an active low chip_select. To use this

control method connect SPI_MODE to BB_VDD and use TEST_MODE/CS as the chip_select as follows:

20191706

FIGURE 3. SPI Write Transaction

If the application requires read access to the register set; for example to determine the cause of an interrupt request, the GPIO2

pin can be configured as an SPI format serial data output by setting the GPIO_SEL in the GPIO configuration register (0x1Ah) to

SPI_SDO. To perform a read rather than a write to a particular address the MSB of the register address field is set to a 1, this

effectively mirrors the contents of the register field to read-only locations above 0x80h:

20191707

FIGURE 4. SPI Read Transaction

Three Wire Mode Write Bus Timing

20191709

FIGURE 5. SPI Timing

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LM49370

12.0 Status & Control Registers

TABLE 1. Register Map

(The default value of all I2C registers is 0x00h)

Addre

0x00h BASIC DAC_ MODE CAP_SIZE OSC_ENB PLL_ENB CHP_MODE

0x01h CLOCKS R_DIV DAC_CLK_SEL

0x02h PLL_M FORCERQ PLL_M

0x03h PLL_N PLL_N

0x04h PLL_P VCOFATS Q_DIV PLL_P

0x05h PLL_MOD PLLTEST PLL_CLK_SEL PLL_N_MOD

0x06h ADC_1 HPF_MODE SAMPLE_RATE RIGHT LEFT CPI MIC

0x07h ADC_2 NGZXDD ADC_CLK_SEL PEAKTIME ADCMUTE ADC_MOD

0x08h AGC_1 NOISE_GATE_THRESHOLD NG_ENB AGC_TARGET AGC_ENB

0x09h AGC_2 AGC_TIGH

AGC_DECAY AGC_MAX_GAIN

0x0Ah AGC_3 AGC_ATTACK AGC_HOLD_TIME

0x0Bh MIC_1 INT_EXT SE_DIFF MUTE PREAMP_GAIN

0x0Ch MIC_2 BTN_DEBOUNCE_TIME BTNTYPE MIC_BIAS_VOLTAGE VCMVOLT

0x0Dh SIDETONE SIDETONE_ATTEN

0x0Eh CP_INPUT MUTE CPI_LEVEL

0x0Fh AUX_LEFT AUX_DAC MUTE BOOST AUX_LEFT_LEVEL

0x10h AUX_RIGHT AUX_DAC MUTE BOOST AUX_RIGHT_LEVEL

0x11h DAC USAXLVL DACMUTE BOOST DAC_LEVEL

0x12h CP_OUTPUT MICGATE MUTE LEFT RIGHT MIC

0x13h AUX

OUTPUT

MUTE LEFT RIGHT CPI

0x14h LS_OUTPUT MUTE LEFT RIGHT CPI

0x15h HP_OUTPUT OCL STEREO MUTE LEFT RIGHT CPI SIDE

0x16h EP_OUTPUT MUTE LEFT RIGHT CPI SIDE

0x17h DETECT HS_DBNC_TIME TEMP_INT BTN_INT DET_INT

0x18h STATUS GPIN1 GPIN2 TEMP BTN MIC STEREO HEADSET

0x19h 3D CUST_COM

ATTENUATE FREQ LEVEL MODE 3DENB

0x1Ah I2SMODE WORD_

ORDER

I2S_WS_GEN_MODE WS_MS STEREO

REVERSE

I2S_MODE INENB OUTENB

0x1Bh I2SCLOCK PCM_SYNC__WIDTH I2S_CLOCK_GEN_MODE CLKSCE CLK_MS

0x1Ch PCMMODE ALAW/

μLAW

COMPAND SDO_

LSB_HZ

SYNC_MS CLKSRCE CLK_MS INENB OUTENB

0x1Dh PCMCLOCK PCM_SYNC_GEN_MODE PCM_CLOCKGEN MODE

0x1Eh BRIDGE MONO_SUM_MODE MONO_

SUM_SEL

DAC_TX_SEL I2S_TX_SEL PCM_

TX_SEL

0x1Fh GPIO DAC_SRC_

MODE

ADC_SRC_

MODE

GPIO_2_SEL GPIO_1_SEL

0x20h CMP_0_LSB CMP_0_LSB

0x21h CMP_0_0SB CMP_0_MSB

0x22h CMP_1_LSB CMP_1_LSB

0x23h CMP_1_MSB CMP_1_MSB

0x24h CMP_2_LSB CMP_2_LSB

0x25h CMP_2_MSB CMP_2_MSB

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LM49370

12.1 BASIC CONFIGURATION REGISTER

This register is used to control the basic function of the chip.

TABLE 2. BASIC (0x00h)

Bits Field Description

1:0 CHIP_MODE The LM49370 can be placed in one of four modes which dictate its basic operation. When a new mode

is selected the LM49370 will change operation silently and will re-configure the power management

profile automatically. The modes are described as follows:

CHIP MODE Audio System Typical Application

002Off Power-down Mode

012Off Stand-by mode with headset event detection

102On Active without headset event detection

112On Active with headset event detection

2 PLL_ENABLE This enables the PLL.

3 USE_OSC If set the power management and control circuits will assume that no external clock is available and

will resort to using an on-chip oscillator for headset detection and analog power management functions

such as click and pop. The PLL, ADC, and DAC are not wired to use this low quality clock. This bit

must be cleared for the part to be fully turned off power-down mode.

5:4 CAP_SIZE This programs the extra delays required to stabilize once charge/discharge is complete, based on the

size of the bypass capacitor.

CAP_SIZE Bypass Capacitor

Size

Turn-off/on time

0020.1 µF 45 ms/75 ms

0121 µF 45 ms/140 ms

1022.2 µF 45 ms/260 ms

1124.7 µF 45 ms/500 ms

7:6 DAC_MODE The DAC can operate in one of four modes. If an “fs*2∧N” audio clock is available, then the DAC can

be run in a slightly lower power mode. If such a clock is not available, the PLL can be used to generate

a suitable clock.

DAC MODE DAC OSR Typical Application

002125 48kHz Playback from

12.000MHz

012128 48kHz Playback from

12.288MHz

10264 96kHz Playback from 12.288MHz

11232 192kHz Playback from 24.576MHz

For reliable headset / push button detection the following bits should be defined before enabling the headset detection system by

setting bit 0 of CHIP_MODE:

The OCL-bit (Cap / Capless headphone interface; bit 6 of HP_OUTPUT (0x15h))

The headset insert/removal debounce settings (bits 6:3 of DETECT (0x17h))

The BTN_TYPE-bit (Parallel / Series push button type; bit 3 MIC_2 register (0x0Ch))

The parallel push button debounce settings (bits 5:4 of MIC_2 register (0x0Ch))

All register fields controlling the audio system should be defined before setting bit 1 of CHIP_MODE and should not be altered

while the audio sub-system is active.

If the analog or digital levels are below −12dB then it is not necessary to set the stereo bit allowing greater output levels to be

obtained for such signals.

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LM49370

12.2 CLOCKS CONFIGURATION REGISTER

This register is used to control the clocks throughout the chip.

TABLE 3. CLOCKS (0x01h)

Bits Field Description

1:0 DAC_CLK This selects the clock to be used by the audio DAC system.

DAC_CLK DAC Input Source

002MCLK

012PLL_OUTPUT

102I2S_CLK_IN

112PCM_CLK_IN

7:2 R_DIV This programs the R divider.

R_DIV Divide Value

0 Bypass

1 Bypass

2 1.5

3 2

4 2.5

5 3

6 3.5

7 4

8 4.5

9 5

10 5.5

11 6

12 6.5

13 to 61 7 to 31

62 31.5

63 32

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LM49370

12.3 LM49370 CLOCK NETWORK

The audio ADC operates at 125*fs ( or 128*fs), so it requires a 1.000 MHz (or 1.024MHz) clock to sample at 8 kHz (at point C as

marked on the following diagram). If the stereo DAC is running at 125*fs (or128*fs), it requires a 12.000MHz (or 12.288MHz) clock

(at point B) for 48 kHz data. It is expected that the PLL is used to drive the audio system operating at 125*fs unless a 12.000 MHz

master clock is supplied or the sample rate is always a multiple of 8 kHz. In this case the PLL can be bypassed to reduce power,

with clock division being performed by the Q and R dividers instead. The PLL can also be bypassed if the system is running at

128*fs and a 12.288MHz master clock is supplied and the sample rate is a multiple of 8kHz. The PLL can also use the I2S clock

input as a source. In this case, the audio DAC uses the clock from the output of the PLL and the audio ADC either uses the PLL

output divided by 2*FS(DAC)/FS(ADC) or a system clock divided by Q, this allows n*8 kHz recording and 44.1 kHz playback.

MCLK must be less than or equal to 30 MHz. I2S_CLK and PCM_CLK should be below 6.144MHz.

When operating at 125*fs, the LM49370 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. When operating

at 128*fs, the LM49370 is designed to work from a 12.288MHz or 11.2896 MHz clock at point A. This is used to drive the power

management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates

significantly beyond this range.

20191710

FIGURE 6. LM49370 Clock Network

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LM49370

12.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC

When DAC_MODE = '00' (bits 7:6 of (0x00h)), the DAC has an over sampling ratio of 125 but requires a 250*fs clock at point B.

This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz

exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes:

TABLE 4. Common DAC Clock Frequencies

DAC Sample Rate (kHz) Clock Required at B (OSR = 125) Clock Required at B (OSR = 128)

8 2 MHz 2.048 MHz

11.025 2.75625 MHz 2.8224 MHz

12 3 MHz 3.072 MHz

16 4 MHz 4.096 MHz

22.05 5.5125 MHz 5.6448 MHz

24 6 MHz 6.144 MHz

32 8 MHz 8.192 MHz

44.1 11.025 MHz 11.2896 MHz

48 12 MHz 12.288 MHz

Note: When DAC_MODE = '01' with the I2S or PCM interface operating as master, the stereo DAC operates at half the frequency

of the clock at point B. This divided by two DAC clock is used as the source clock for the audio port.

The over sampling ratio of the ADC is set by ADC MODE (bit 0 of 0x07h)). The table below shows the required clock frequency at

point C for the different ADC modes.

TABLE 5. Common ADC Clock Frequencies

ADC Sample Rate (kHz) Clock Required at C (OSR = 125) Clock Required at C (OSR = 128)

8 1 MHz 1.024 MHz

11.025 1.378125 MHz 1.4112 MHz

12 1.5 MHz 1.536 MHz

16 2 MHz 2.048 MHz

22.05 2.75625 MHz 2.8224 MHz

24 3 MHz 3.072 MHz

Methods for producing these clock frequencies are described in the PLL Section.

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LM49370

12.5 PLL M DIVIDER CONFIGURATION REGISTER

This register is used to control the input section of the PLL. (Note 12)

TABLE 6. PLL_M (0x02h)

Bits Field Description

0 RSVD RESERVED

6:0 PLL_M PLL_M Input Divider Value

0 No Divided Clock

1 1

2 1.5

3 2

4 2.5

... 3 to 63

126 63.5

127 64

7 FORCERQ If set, the R and Q divider are enabled and the DAC and ADC clocks are propagated. This allows operation

of the I2S and PCM interfaces without the ADC or DAC being enabled, for example to act as a bridge or

a clock master.

The M divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz.

The division of the M divider is derived from PLL_M such that:

M = (PLL_M + 1) / 2

Note 12: See Further Notes on PLL Programming for more detail.

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LM49370

12.6 PLL N DIVIDER CONFIGURATION REGISTER

This register is used to control the feedback divider of the PLL. (Note 13)

TABLE 7. PLL_N (0x03h)

Bits Field Description

7:0 PLL_N This programs the PLL feedback divider as follows:

PLL_N Feedback Divider Value

0 to 10 10

11 11

12 12

13 13

14 14

… …

249 249

250 to 255 250

The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting

VCO frequency, FVCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as Fcomp

(comparison frequency) or Fref (reference frequency), in this document Fcomp is used.

The integer division of the N divider is derived from PLL_N such that:

For 9 < PLL_N < 251: N = PLL_N

Note 13: See Further Notes on PLL Programming for further details.

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LM49370

12.7 PLL P DIVIDER CONFIGURATION REGISTER

This register is used to control the output divider of the PLL. (Note 14)

TABLE 8. PLL_P (0x04h)

Bits Field Description

3:0 PLL_P This programs the PLL output divider as follows:

PLL_P Output Divider Value

0 No Divided Clock

1 1

2 1.5

3 2

4 2.5

... 3 to 7

14 7.5

15 8

6:4 Q_DIV This programs the Q Divider

Q_DIV Divide Value

00022

00123

01024

01126

10028

101210

110212

111213

7 FAST_VCO This programs the PLL VCO range:

FAST_VCO PLL VCO Range

0 40 to 60MHz

1 60 to 80MHz

The division of the P divider is derived from PLL_P such that:

P = (PLL_P + 1) / 2

Note 14: See Further Notes on PLL Programming for more details.

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LM49370

12.8 PLL N MODULUS CONFIGURATION REGISTER

This register is used to control the modulation applied to the feedback divider of the PLL. (Note 15)

TABLE 9. PLL_N_MOD (0x05h)

Bits Field Description

4:0 PLL_N_MOD This programs the PLL N divider's fractional component:

PLL_N_MOD Fractional Addition

0 0/32

1 1/32

2 to 30 2/32 to 30/32

31 31/32

6:5 PLL_CLK_SEL This selects the clock to be used as input for the audio PLL.

PLL_INPUT_CLK

002MCLK

012I2S_CLK_IN

102PCM_CLK_IN

112—

7 RSVD Reserved.

The complete N divider is a fractional divider as such:

N = PLL_N + PLL_N_MOD/32

If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following

formula:

Fout = (Fin*N)/(M*P)

Note 15: See Further Notes on PLL Programming for more details.

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LM49370

12.9 FURTHER NOTES ON PLL PROGRAMMING

The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies of up to 30MHz with frequency errors

noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample

rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC a clock

synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available,

then the PLL can be used to obtain a clock that is accurate to within 1Hz of the correct sample rate although this is highly unlikely

to be a problem.

201917r0

FIGURE 7. PLL Overview

TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 00

Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P Fout (MHz)

11 48 11 60 5 21 60 0 9 12

12.288 48 4 19.53125 5 7 19 17 9 12

13 48 13 60 5 25 60 0 9 12

14.4 48 9 37.5 5 17 37 16 9 12

16.2 48 27 100 5 53 100 0 9 12

16.8 48 14 50 5 27 50 0 9 12

19.2 48 13 40.625 5 25 40 20 9 12

19.44 48 27 100 6 53 100 0 11 12

19.68 48 20.5 62.5 5 40 62 16 9 12

19.8 48 16.5 50 5 32 50 0 9 12

11 44.1 11 55.125 5 21 55 4 9 11.025

11.2896 44.1 8 39.0625 5 15 39 2 9 11.025

12 44.1 5 22.96875 5 9 22 31 9 11.025

13 44.1 13 55.125 5 25 55 4 9 11.025

14.4 44.1 12 45.9375 5 23 45 30 9 11.025

16.2 44.1 9 30.625 5 17 9 20 9 11.025

16.8 44.1 17 55.78125 5 33 30 25 9 11.025

19.2 44.1 16 45.9375 5 31 45 30 9 11.025

19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025

19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025

19.8 44.1 11 30.625 5 21 30 20 9 11.025

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LM49370

TABLE 11. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 01

Fin (MHz) Fs (kHz) M N P PLL_M PLL_N PLL_N_MOD PLL_P Fout (MHz)

12 48 12.5 64 5 24 64 0 9 12.288

13 48 26.5 112.71875 4.5 52 112 23 8 12.288

14.4 48 37.5 128 4 74 128 0 7 12.288

16.2 48 37.5 128 4.5 74 128 0 8 12.288

16.8 48 12.53 32 3.5 24 32 0 6 12.288

19.2 48 12.5 32 4 24 32 0 7 12.288

19.44 48 40.5 128 58 80 128 0 9 12.288

19.68 48 20.5 64 5 40 64 0 9 12.288

19.8 48 37.5 128 5.5 74 128 0 10 12.288

12 44.1 35.5 133.59375 4 70 133 19 7 11.2896

13 44.1 37 144.59375 4.5 73 144 19 8 11.2896

14.4 44.1 37.5 147 5 74 147 0 9 11.2896

16.2 44.1 47.5 182.0625 5.5 94 182 2 10 11.2896

16.8 44.1 12.5 42 5 24 42 0 9 11.2896

19.2 44.1 12.5 36.75 5 24 36 24 9 11.2896

19.44 44.1 37.5 98 4.5 74 98 0 9 11.2896

19.68 44.1 44.5 114.875 4.5 88 114 28 8 11.2896

19.8 44.1 48 136.84375 5 95 136 27 9 11.2896

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LM49370

These tables cover the most common applications, obtaining clocks for derivative sample rates such as 22.05 kHz should be done

by increasing the P divider value or using the R/Q dividers.

An example of obtaining 12.000 MHz from 1.536 MHz is shown below (this is typical for deriving DAC clocks from I2S

datastreams).

Choose a small range of P so that the VCO frequency is swept between 40 MHz and 60 MHz (or 60–80 MHz if VCOFAST is used).

Remembering that the P divider can divide by half integers, for a 12 MHz output, this gives possible P values of 3, 3.5, 4, 4.5, or

5. The M divider should be set such that the comparison frequency (Fcomp) is between 0.5 and 5 MHz. This gives possible M

values of 1, 1.5, 2, 2.5, or 3. The most accurate N and N_MOD can be calculated by sweeping the P and M inputs of the following

formulas:

N = FLOOR(((Fout/Fin)*(P*M)),1)

N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0)

This shows that setting M = 1, N = 39+1/16, P = 5 (i.e. PLL_M = 0, PLL_N = 39, PLL_N_MOD = 2, & PLL_P = 4) gives a comparison

frequency of 1.536MHz, a VCO frequency of 60 MHz and an output frequency of 12.000 MHz. The same settings can be used to

get 11.025 from 1.4112 MHz for 44.1 kHz sample rates.

Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used but an exact

frequency match cannot be found. The I2S should be master on the LM49370 so that the data source can support appropriate

SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems.

Where a system clock exists at an integer multiple of the required ADC or DAC clock rate it is preferable to use this rather than

the PLL. The LM49370 is designed to work in 8, 12, 16, 24, 48 kHz modes from a 12 MHz clock and 8 kHz modes from a 13 MHz

clock without the use of the PLL. This saves power and reduces clock jitter which can affect SNR.

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LM49370

12.10 ADC_1 CONFIGURATION REGISTER

This register is used to control the LM49370's audio ADC.

TABLE 12. ADC_1 (0x06h)

Bits Field Description

0 MIC_SELECT If set the microphone preamp output is added to the ADC input signal.

1 CPI_SELECT If set the cell phone input is added to the ADC input signal.

2 LEFT_SELECT If set the left stereo bus is added to the ADC input signal.

3 RIGHT_SELECT If set the right stereo bus is added to the ADC input signal.

5:4 ADC_SAMPLE_

RATE

This programs the closest expected sample rate of the mono ADC, which is a variable required by the

AGC algorithm whenever the AGC is in use. This does not set the sample rate of the mono ADC.

ADC_SAMPLE_RATE Sample Rate

0028 kHz

01212 kHz

10216 kHz

11224 kHz

7:6 HPF_MODE This sets the HPF of the ADC

HPF-MODE HPF Response

002No HPF

012FS = 8 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz

FS = 12 kHz, −0.5 dB @ 450 Hz, Notch @ 82 Hz

FS = 16 kHz, −0.5 dB @ 600 Hz, Notch @ 110 Hz

102FS = 8 kHz, −0.5 dB @ 150 Hz, Notch @ 27 Hz

FS = 12 kHz, −0.5 dB @ 225 Hz, Notch @ 41 Hz

FS = 16 kHz, −0.5 dB @ 300 Hz, Notch @ 55 Hz

112No HPF

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LM49370

12.11 ADC_2 CONFIGURATION REGISTER

This register is used to control the LM49370's audio ADC.

TABLE 13. ADC_2 (0x07h)

Bit

Field Description

0 ADC_MODE This sets the oversampling ratio of the ADC

MODE ADC OSR

0 125fs

1 128fs

1 ADC_MUTE If set, the analog inputs to the ADC are muted.

4:2 AGC_FRAME_TIME This sets the frame time to be used by the AGC algorithm. In a given frame, the AGC's peak detector

determines the peak value of the incoming microphone audio signal and compares this value to the target

value of the AGC defined by AGC_TARGET (bits [3:1] of register (0x08h)) in order to adjust the microphone

preamplifier's gain accordingly. AGC_FRAME_TIME basically sets the sample rate of the AGC to adjust for

a wide variety of speech patterns. (Note 16)

AGC_FRAME_TIME Time (ms)

000296

0012128

0102192

0112256

1002384

1012512

1102768

11121000

6:5 ADC_CLK This selects the clock to be used by the audio ADC system.

ADC_CLK Source

002MCLK

012PLL_OUTPUT

102I2S_CLK_IN

112PCM_CLK_IN

7 NGZXDD If set, the noise gate will not wait for a zero crossing before mute/unmuting. This bit should be set if the

ADC's HPF is disabled and if there is a large DC or low frequency component at the ADC input.

NGZXDD Result

0 Noise Gate operates on ZXD events

1 Noise Gate operates on frame boundaries

Note 16: Refer to the AGC overview for further detail.

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LM49370

12.12 AGC_1 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control. (Note 17)

TABLE 14. AGC_1 (0x08h)

Bit

Field Description

0 AGC_ENABLE If set, the AGC controls the analog microphone preamplifier gain into the system. This feature is useful for

microphone signals that are routed to the ADC.

3:1 AGC_TARGET This programs the target level of the AGC. This will depend on the expected transients and desired headroom.

Refer to AGC_TIGHT (bit 7 of 0x09h) for more detail.

AGC_TARGET Target Level

0002−6 dB

0012−8 dB

0102−10 dB

0112−12 dB

1002−14 dB

1012−16 dB

1102−18 dB

1112−20 dB

4 NOISE_GATE_ON If set, signals below the noise gate threshold are muted.The noise gate is only activated after a set period of

signal absence.

7:5 NOISE_

GATE_

THRES

This field sets the expected background noise level relative to the peak signal level. The sole presence of

signals below this level will not result in an AGC gain change of the input and will be gated from the ADC

output if the NOISE_GATE_ON is set. This level must be set even if the noise gate is not in use as it is required

by the AGC algorithm.

NOISE_GATE_THRES Level

0002−72 dB

0012−66 dB

0102−60 dB

0112−54 dB

1002−48 dB

1012−42 dB

1102−36 dB

1112−30 dB

Note 17: See the AGC overview.

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LM49370

12.13 AGC_2 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control.

TABLE 15. AGC_2 (0x09h)

Bits Field Description

3:0 AGC_MAX_GAIN This programs the maximum gain that the AGC algorithm can apply to the microphone preamplifier.

AGC_MAX_GAIN Max Preamplifier Gain

000026 dB

000128 dB

0010210 dB

0011212 dB

01002 to 1100214 dB to 30 dB

1101232 dB

1110234 dB

1111236 dB

6:4 AGC_DECAY This programs the speed at which the AGC will increase gains if it detects the input level is a quiet signal.

AGC_DECAY Step Time (ms)

000232

001264

0102128

0112256

1002512

10121024

11022048

11124096

7 AGC_TIGHT If set, the AGC algorithm controls the microphone preamplifier more exactly. (Note 18)

AGC_TIGHT = 0 AGC_TARGET Min Level Max Level

0002−6 dB −3 dB

0012−8 dB −4 dB

0102−10 dB −5 dB

0112−12 dB −6 dB

1002−14 dB −7 dB

1012−16 dB −8 dB

1102−18 dB −9 dB

1112−20 dB −10 dB

AGC_TIGHT = 1 0002−6 dB −3 dB

0012−8 dB −5 dB

0102−10 dB −7 dB

0112−12 dB −9 dB

1002−14 dB −11 dB

1012−16 dB −13 dB

1102−18 dB −15 dB

1112−20 dB −17 dB

Note 18: The AGC can be used to control the analog path of the microphone to the output stages or to optimize the microphone path for recording on the ADC.

When the analog path is used this bit should be set to ensure the target is tightly adhered to. If the ADC is the only destination of the microphone or the desired

analog mixer level is line level then AGC_TIGHT should be cleared, allowing greater dynamic rage of the recorded signal. For further details see the AGC

overview.

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LM49370

12.14 AGC_3 CONFIGURATION REGISTER

This register is used to control the LM49370's Automatic Gain Control. (Note 19)

TABLE 16. AGC_3 (0x0Ah)

Bits Field Description

4:0 AGC_HOLDTIME This programs the amount of delay before the AGC algorithm begins to adjust the gain of the microphone

preamplifier.

AGC_HOLDTIME No. of speech segments

0000020

0000121

0001022

0001123

001002 to 1110024 to 28

11101229

11110230

11111231

7:5 AGC_ATTACK This programs the speed at which the AGC will reduce gains if it detects the input level is too large.

AGC_ATTACK Step Time (ms)

000232

001264

0102128

0112256

1002512

10121024

11022048

11124096

Note 19: See the AGC overview.

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LM49370

12.15 AGC OVERVIEW

The Automatic Gain Control (AGC) system can be used to optimize the dynamic range of the ADC for voice data when the level

of the source is unknown. A target level for the output is set so that any transients on the input won’t clip during normal operation.

The AGC circuit then compares the output of the ADC to this level and increases or decreases the gain of the microphone pream-

plifier to compensate. If the audio from the microphone is to be output digitally through the ADC then the full dynamic range of the

ADC can be used automatically. If the output is through the analog mixer then the ADC is used to monitor the microphone level.

In this case, the analog dynamic range is less important than the absolute level, so AGC_TIGHT should be set to tie transients

closely to the target level.

To ensure that the system doesn’t reduce the quality of the speech by constantly modulating the microphone preamplifier gain,

the ADC output is passed through an envelope detector. This frames the output of the ADC into time segments roughly equal to

the phonemes found in speech (AGC_FRAME_TIME). To calculate this, the circuit must also know the sample rate of the data

from the ADC (ADC_SAMPLERATE). If after a programmable number of these segments (AGC_HOLDTIME), the level is consis-

tently below target, the gain will be increased at a programmable rate (AGC_DECAY). If the signal ever exceeds the target level

(AGC_TARGET) then the gain of the microphone is reduced immediately at a programmable rate (AGC_ATTACK). This is demon-

strated below:

20191712

AGC Operation Example

The signal in the above example starts with a small analog input which, after the hold time has timed out, triggers a rise in the gain

((1) → (2)). After some time the real analog input increases and it reaches the threshold for a gain reduction which decreases the

gain at a faster rate ((2) → (3)) to allow the elimination of typical popping noises.

Only ADC outputs that are considered signal (rather than noise) are used to adjust the microphone preamplifier gain. The signal

to noise ratio of the expected input signal is set by NOISE_GATE_THRESHOLD. In some situations it is preferable to remove

audio considered to be consisting solely of background noise from the audio output; for example conference calls. This can be

done by setting NOISE_GATE_ON. This does not affect the performance of the AGC algorithm.

The AGC algorithm should not be used where very large background noise is present. If the type of input data, application and

microphone is known then the AGC will typically not be required for good performance, it is intended for use with inputs with a

large dynamic range or unknown nominal level. When setting NOISE_GATE_THRESHOLD be aware that in some mobile phone

scenarios the ADC SNR will be dictated by the microphone performance rather than the ADC or the signal. Gain changes to the

microphone are performed on zero crossings. To eliminate DC offsets, wind noise, and pop sounds from the output of the ADC,

the ADC's HPF should always be enabled.

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LM49370

12.16 MIC_1 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

TABLE 17. MIC_1 (0x0Bh)

Bits Field Description

3:0 PREAMP_GAIN This programs the gain applied to the microphone preamplifier if the AGC is not in use.

PREAMP_GAIN Gain

000026 dB

000128 dB

0010210 dB

0011212 dB

01002 to 1100214 dB to 30 dB

1101232 dB

1110234 dB

1111236 dB

4 MIC_MUTE If set, the microphone preamplifier is muted.

5 INT_SE_DIFF If set, the internal microphone is assumed to be single ended and the negative connection is connected

to the ADC common mode point internally. This allows a single-ended internal microphone to be used.

6 INT_EXT If set, the single ended external microphone is used and the negative microphone input is grounded

internally, otherwise internal microphone operation is assumed. (Note 20)

Note 20: On changing INT_EXT from internal to external note that the dc blocking cap will not be charged so some time should be taken (300 ms for a 1 µF cap)

between the detection of an external headset and the switching of the output stages and ADC to that input to allow the DC points on either side of this cap to

stabilize. This can be accomplished by deselecting the microphone input from the audio outputs and ADC until the DC points stabilize.

An active MIC path to CPOUT or the ADC may result in the microphone DC blocking caps causing audio pops under the following situations:

1) Switching between internal and external microphone operation while in chip modes '10' or '11'.

2) Toggling in and out of powerdown/standby modes.

3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected.

4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected.

To avoid these potential pop issues, it is recommended to deselect the microphone input from CPOUT and ADC until the DC points stabilize.

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LM49370

12.17 MIC_2 CONFIGURATION REGISTER

This register is used to control the microphone configuration.

TABLE 18. MIC_2 (0x0Ch)

Bits Field Description

0 OCL_

VCM_

VOLTAGE

This selects the voltage used as virtual ground (HP_VMID pin) in OCL mode. This will depend on the

available supply and the power output requirements of the headphone amplifiers.

OCL_VCM_VOLTAGE Voltage

0 1.2V

1 1.5V

2:1 MIC_

BIAS_

VOLTAGE

This selects the voltage as a reference to the internal and external microphones. Only one bias pin is driven

at once depending on the INT_EXT bit setting found in the MIC_1 (0x0Bh) register. MIC_BIAS_VOLTAGE

should be set to '11' only if A_VDD > 3.4V. In OCL mode, MIC_BIAS_VOLTAGE = '00' (EXT_BIAS = 2.0V)

should not be used to generate the EXT_BIAS supply for a cellular headset external microphone. Please

refer to Table 19 for more detail.

MIC_BIAS_VOLTAGE EXT_BIAS/INT_BIAS

0022.0V

0122.5V

1022.8V

1123.3V

3 BUTTON_TYPE If set, the LM49370 assumes that the button (if used) in the headset is in series (series push button) with

the microphone, opening the circuit when pressed. The default is for the button to be in parallel (parallel

push button), shorting out the microphone when pressed.

5:4 BUTTON_

DEBOUNCE_

TIME

This sets the time used for debouncing the pushing of the button on a headset with a parallel push button.

BUTTON_DEBOUNCE_TIME Time (ms)

0020

0128

10216

11232

In OCL mode there is a trade-off between the external microphone supply voltage (EXT_MIC_BIAS - OCL_VCM_ VOLTAGE) and

the maximum output power possible from the headphones. A lower OCL_VCM_VOLTAGE gives a higher microphone supply

voltage but a lower maximum output power from the headphone amplifiers due to the lower OCL_VCM_VOLTAGE - A_VSS.

TABLE 19. External MIC Supply Voltages in OCL Mode

Available

A_VDD

Recommended

EXT_MIC_BIAS

Supply to Microphone

OCL_VCM_VOLT = 1.5V OCL_VCM_VOLT = 1.2V

> 3.4V 3.3V 1.8V 2.1V

2.9V to 3.4V 2.8V 1.3V 1.6V

2.8V to 2.9V 2.5V 1.0V 1.3V

2.7V to 2.8V 2.5V - 1.3V

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LM49370

12.18 SIDETONE ATTENUATION REGISTER

This register is used to control the analog sidetone attenuation. (Note 21)

TABLE 20. SIDETONE (0x0Dh)

Bits Field Description

3:0 SIDETONE_

ATTEN

This programs the attenuation applied to the microphone preamp output to produce a sidetone signal.

SIDETONE_ATTEN Attenuation

00002-Inf

00012−30 dB

00102−27 dB

00112−24 dB

01002−21 dB

01012 to 10102−18 dB to −3 dB

10112 to 111120 dB

Note 21: An active SIDETONE path to an audio output may result in the microphone DC blocking caps causing audio pops under the following situations:

1) Switching between internal and external microphone operation while in chip modes '10' or '11'.

2) Toggling in and out of powerdown/standby modes.

3) Toggling between chip modes '10' and '11' whenever external microphone operation is selected.

4) The insertion/removal of a headset while in chip modes '10' or '11' whenever external microphone operation is selected.

To avoid potential pop noises, it is recommended to set SIDETONE_ATTEN to '0000' until DC points have stabilized whenever the SIDETONE path is used.

12.19 CP_INPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone input.

TABLE 21. CP_INPUT (0x0Eh)

Bits Field Description

4:0 CPI_LEVEL This programs the gain/attenuation applied to the cell phone input.

CPI_LEVEL Level

000002−34.5 dB

000012−33 dB

000102−31.5 dB

000112−30 dB

00100 to 111002−28.5 dB to +7.5 dB

111012+9 dB

111102+10.5 dB

111112+12 dB

5 CPI_MUTE If set, the CPI input is muted at source.

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LM49370

12.20 AUX_LEFT CONFIGURATION REGISTER

This register is used to control the left aux analog input.

TABLE 22. AUX_LEFT (0x0Fh)

Bits Field Description

4:0 AUX_

LEFT_

LEVEL

This programs the gain/attenuation applied to the AUX LEFT analog input to the mixer. (Note 22)

AUX_LEFT_LEVEL Level (With Boost) Level (Without Boost)

000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 AUX_

LEFT_

BOOST

If set, the gain of the AUX_LEFT input to the mixer is increased by 12 dB (see above).

6 AUX_L_MUTE If set, the AUX LEFT input is muted.

7 AUX_OR_DAC_L If set, the AUX LEFT input is passed to the mixer, the default is for the DAC LEFT output to be passed to

the mixer.

Note 22: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur

if the analog power supply is insufficient to cater for the required gain.

12.21 AUX_RIGHT CONFIGURATION REGISTER

This register is used to control the right aux analog input.

TABLE 23. AUX_RIGHT (0x10h)

Bits Field Description

4:0 AUX_

RIGHT_

LEVEL

This programs the gain/attenuation applied to the AUX RIGHT analog input to the mixer. (Note 23)

AUX_RIGHT_LEVEL Level (With Boost) Level (Without Boost)

000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 AUX_

RIGHT_BOOST

If set, the gain of the AUX_RIGHT input to the mixer is increased by 12 dB (see above).

6 AUX_R_MUTE If set, the AUX RIGHT input is muted.

7 AUX_OR_DAC_R If set, the AUX RIGHT input is passed to the mixer, the default is for the DAC RIGHT output to be passed

to the mixer.

Note 23: The recommended mixer level is 1V RMS. The auxiliary analog inputs can be boosted by 12 dB if enough headroom is available. Clipping may occur

if the analog power supply is insufficient to cater for the required gain.

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LM49370

12.22 DAC CONFIGURATION REGISTER

This register is used to control the DAC levels to the mixer.

TABLE 24. DAC (0x11h)

Bits Field Description

4:0 DAC_LEVEL This programs the gain/attenuation applied to the DAC input to the mixer. (Note 24)

DAC_LEVEL Level (With Boost) Level (Without Boost)

000002−34.5 dB −46.5 dB

000012−33 dB −45 dB

000102−31.5 dB −43.5 dB

000112−30 dB −42 dB

00100 to 111002−28.5 dB to +7.5 dB −40.5 dB to −4.5 dB

111012+9 dB −3 dB

111102+10.5 dB −1.5 dB

111112+12 dB 0 dB

5 DAC_BOOST If set, the gain of the DAC inputs to the mixer is increased by 12dB (see above).

6 DAC_MUTE If set, the stereo DAC input is muted on the next zero crossing.

7 USE_AUX_

LEVELS

If set, the gain of the DAC inputs is controlled by the AUX_LEFT and AUX_RIGHT registers, allowing a

stereo balance to be applied.

Note 24: The output from the DAC is 1V RMS for a full scale digital input. This can be boosted by 12 dB if enough headroom is available. Clipping may occur if

the analog power supply is insufficient to cater for the required gain.

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LM49370

12.23 CP_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential cell phone output. (Note 25)

TABLE 25. CP_OUTPUT (0x12h)

Bit

Field Description

0 MIC_SELECT If set, the microphone channel of the mixer is added to the CP_OUT output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the CP_OUT output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the CP_OUT output signal.

3 CPO_MUTE If set, the CPOUT output is muted.

4 MIC_NOISE_GAT

If this is set and NOISE_GATE_ON (register 0x08h) is enabled, the MIC to CPO path will be gated if the

signal is determined to be noise by the AGC (that is, if the signal is below the set noise threshold).

Note 25: The gain of cell phone output amplifier is 0 dB.

12.24 AUX_OUTPUT CONFIGURATION REGISTER

This register is used to control the differential auxiliary output. (Note 26)

TABLE 26. AUX_OUTPUT (0x13h)

Bits Field Description

0 CPI_SELECT If set, the cell phone input channel of the mixer is added to the AUX_OUT output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the AUX_OUT output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the AUX_OUT output signal.

3 AUX_MUTE If set, the AUX_OUT output is muted.

Note 26: The gain of the auxiliary output amplifier is 0 dB. If a second (external) loudspeaker amplifier is to be used its gain should be set to 12 dB to match the

onboard loudspeaker amplifier gain.

12.25 LS_OUTPUT CONFIGURATION REGISTER

This register is used to control the loudspeaker output. (Note 27)

TABLE 27. LS_OUTPUT (0x14h)

Bits Field Description

0 CPI_SELECT If set, the cell phone input channel of the mixer is added to the loudspeaker output signal.

1 RIGHT_SELECT If set, the right channel of the mixer is added to the loudspeaker output signal.

2 LEFT_SELECT If set, the left channel of the mixer is added to the loudspeaker output signal.

3 LS_MUTE If set, the loudspeaker output is muted.

4 RSVD Reserved.

Note 27: The gain of the loudspeaker output amplifier is 12 dB.

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LM49370

12.26 HP_OUTPUT CONFIGURATION REGISTER

This register is used to control the stereo headphone output. (Note 28)

TABLE 28. HP_OUTPUT (0x15h)

Bits Field Description

0 SIDETONE_SELECT If set, the sidetone channel of the mixer is added to both of the headphone output signals.

1 CPI_SELECT If set, the cell phone input channel of the mixer is added to both of the headphone output signals.

2 RIGHT_SELECT If set, the right channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is

set, the right channel is added to the right headphone output signal only. If the STEREO bit (0x00h)

is cleared, it is added to both the right and left headphone output signals.

3 LEFT_SELECT If set, the left channel of the mixer is added to the headphone output. If the STEREO bit (0x00h) is

set, the left channel is added to the left headphone output signal only. If the STEREO bit (0x00h) is

cleared, it is added to both the right and left headphone output signals.

4 HP_MUTE If set, the headphone output is muted.

5 STEREO If set, the mixers assume that the signals on the left and right internal busses are highly correlated and

when these signals are combined their levels are reduced by 6dB to allow enough headroom for them

to be summed.

6 OCL If set, the part is placed in OCL (Output Capacitor Less) mode.

Note 28: The gain of the headphone output amplifier is –6 dB for the cell phone input channel and sidetone channel of the mixer. When the STEREO bit (0x00h)

is set, headphone output amplifier gain is –6 dB for the left and right channel. When the STEREO bit (0x00h) is cleared, the headphone output amplifier gain is

–12 dB for the left and right channel (to allow enough headroom for adding them and routing them to both headphone amplifiers).

12.27 EP_OUTPUT CONFIGURATION REGISTER

This register is used to control the mono earpiece output. (Note 29)

TABLE 29. EP_OUTPUT (0x16h)

Bits Field Description

0 SIDETONE_SELECT If set, the sidetone channel of the mixer is added to the earpiece output signal.

1 CPI_SELECT If set, the cell phone input channel of the mixer is added to the earpiece output signal.

2 RIGHT_SELECT If set, the right channel of the mixer is added to the earpiece output signal.

3 LEFT_SELECT If set, the left channel of the mixer is added to the earpiece output signal.

4 EP_MUTE If set, the earpiece output is muted.

Note 29: The gain of the earpiece output amplifier is 6 dB.

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LM49370

12.28 DETECT CONFIGURATION REGISTER

This register is used to control the headset detection system.

TABLE 30. DETECT (0x17h)

Bits Field Description

0 DET_INT If set, an IRQ is raised when a change is detected in the headset status. Clearing this bit will clear an IRQ

that has been triggered by the headset detect.

1 BTN_INT If set, an IRQ is raised when the headset button is pressed. Clearing this bit will clear an IRQ that has been

triggered by a button event.

2 TEMP_INT If set, an IRQ is raised during a temperature event. The LM49370 will still automatically cycle the class AB

power amplifiers off if the internal temperature is too high. This bit should not be set whenever the class

D amplifier is turned on. Clearing this bit will clear an IRQ that has been triggered by a temperature event.

6:3 HS_

DBNC_TIME

This sets the time used for debouncing the analog signals from the detection inputs used to sense the

insertion/removal of a headset.

HS_DBNC_TIME Time (ms)

000020

000128

0010216

0011232

0100248

0101264

0110296

01112128

10002192

10012256

10102384

10112512

11002768

110121024

111021536

111122048

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LM49370

12.29 HEADSET DETECT OVERVIEW

The LM49370 has built in monitors to automatically detect headset insertion or removal. The detection scheme can differentiate

between mono, stereo, mono-cellular and stereo-cellular headsets. Upon detection of headset insertion or removal, the LM49370

updates read-only bit 0 - headset absence/presence, bit 1- mono/stereo headset and bit 2 - headset without mic / with mic, of the

STATUS register (0x18h). Headset insertion/removal and headset type can also be detected in standby mode; this consumes no

analog supply current when the headset is absent.

The LM49370 can be programmed to raise an interrupt (set the IRQ pin high) when headset insert/removal is sensed by setting

bit 0 of DETECT (0x17h). When headset detection is enabled in active mode and a headset is not detected, the HPL_OUT and

HPR_OUT amplifiers will be disabled (switched off for capless mode and muted for AC-coupled mode) and the EXT_BIAS pin will

be disconnected from the MIC_BIAS amplifier, irrespective of control register settings.

The LM49370 also has the capability to detect button press, when a button is present on the headset microphone. Both parallel

button-type (in parallel with the headset microphone, default value) and series button-type (in series with the headset microphone)

can be detected; the button type used needs to be defined in bit 3 of MIC_2 (0x0Ch). Button press can also be detected in stand-

by mode; this consumes 10 µA of analog supply current for a series type push button and 100 µA for a parallel type push button.

Upon button press, the LM49370 updates bit 3 of STATUS (0x18h). In active OCL mode, with internal microphone selected

(INT_EXT = 0; (reg 0x0Bh)), if a parallel pushbutton headset is inserted into the system, INT_EXT must be set high before BTN

(bit 3 of STATUS (0x18h)) can be read. The LM49370 can also be programmed to raise an interrupt on the IRQ pin when button

press is sensed by setting bit 1 of DETECT (0x17h).

The LM49370 provides debounce programmability for headset and button detect. Debounce programmability can be used to reject

glitches generated, and hence avoid false detection, while inserting/removing a headset or pressing a button.

Headset insert/removal debounce time is defined by HS_DBNC_TIME; bits 6:3 of DETECT (0x17h). Parallel button press debounce

time is defined by BTN_DBNC_TIME; bits 5:4 of MIC_2 (0x0Ch).

Note that since the first effect of a series button press (microphone disconnected) is indistinguishable from headset removal, the

debounce time for series button press in defined by HS_DBNC_TIME.

Headset and push button detection can be enabled by setting CHIP_MODE 0; bit 0 of BASIC (0x00h). For reliable headset / push

button detection all following bits should be defined before enabling the headset detection system:

1) the OCL-bit (AC-Coupled / Capless headphone interface (bit 6 of HP_OUTPUT (0x15h))

2) the headset insert/removal debounce settings (bit 6:3 of DETECT (0x17h))

3) the BTN_TYPE-bit (Parallel / Series push button type (bit 3 of MIC_2 (0x0Ch))

4) the parallel push button debounce settings (bit 5:4 of MIC_2 (0x0Ch))

Figure 8 shows terminal connections and jack configuration for various headsets. Care should be taken to avoid any DC path from

the MIC_DET pin to ground when a headset is not inserted.

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LM49370

20191713

FIGURE 8. Headset Configurations Supported by the LM49370

The wiring of the headset jack to the LM49370 will depend on the intended mode of the headphone amplifier:

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LM49370

20191714

FIGURE 9. Connection of Headset Jack to LM49370 Depends on the Mode of the Headphone Amplifier.

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LM49370

12.30 STATUS REGISTER

This register is used to report the status of the device.

TABLE 31. STATUS (0x18h)

Bits Field Description

0 HEADSET This field is high when headset presence is detected (only valid if the detection system is enabled). (Note

30)

1 STEREO_

HEADSET

This field is high when a headset with stereo speakers is detected (only valid if the detection system is

enabled). (Note 30)

2 MIC This field is high when a headset with a microphone is detected (only valid if the detection system is

enabled). (Note 30)

3 BTN This field is high when the button on the headset is pressed (only valid if the detection system is enabled).

IRQ is cleared when the button has been released and this register has been written to. (Note 31)

4 TEMP If this field is high then a temperature event has occurred (write to this register to clear IRQ). This field will

stay high even when the IRQ is cleared so long as the event occurs. This bit is only valid whenever the

loudspeaker amplifier is turned off. (Note 31)

5 GPIN1 When GPIO_SEL is set to a readable configuration a digital input on GPIO1 can be read back here.

6 GPIN2 When GPIO_SEL is set to a readable configuration, a digital input on the relevant GPIO can be read back

here.

Note 30: The detection IRQ is cleared when this register has been written to.

Note 31: This field is cleared whenever the STATUS (0x18h) register has been written to.

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LM49370

12.31 3D CONFIGURATION REGISTER

This register is used to control the configuration of the 3D circuit.

TABLE 32. 3D (0x19h)

Bits Field Description

0 3D_ENB Setting this bit enables the 3D effect. When cleared to zero, the 3D effect is disabled and the 3D module

then passes the I2S left and right channel inputs to the DAC unchanged. The stereo AUX inputs are

unaffected by the 3D module.

1 3D_TYPE This bit selects between type 1 and type 2 3D sound effect. Clearing this bit to zero selects type 1 effect

and setting it to one selects type 2.

Type1: Rout = Ri-G*Lout3d, Lout = Li-G*Rout3d

Type2: Rout = -Ri-G*Lout3d, Lout = Li+G*Rout3d

where,

Ri = Right I2S channel input

Li = Left I2S channel input

G = 3D gain level (Mix ratio)

Rout3d = Ri filtered through a high-pass filter with a corner frequency controlled by FREQ

Lout3d = Li filtered through a high-pass filter with a corner frequency controlled by FREQ

3:2 LEVEL This programs the level of 3D effect that is applied.

LEVEL

00225%

01237.5%

10250%

11275%

5:4 FREQ This programs the HPF rolloff (-3dB) frequency of the 3D effect.

FREQ

0020Hz

012300Hz

102600Hz

112900Hz

6 ATTENUATE Clearing this bit to zero maintains the level of the left and right input channels at the output. Setting this

bit to one attenuates the output level by 50%.

This may be appropriate for high level audio inputs when type 2 3D effect is used. Type 2 effect involves

adding the same polarity of left and right inputs to give the final outputs. Type 2 effect has the potential

for creating a clipping condition, however this bit offers an alternative to clipping.

7 CUST_COMP If set, the DAC compensation filter may be programmed by the user through registers (0x20h) to( 0x25h).

Otherwise, the defaults are used.

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LM49370

12.32 I2S PORT MODE CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

TABLE 33. I2S Mode (0x1Ah)

Bits Field Description

0 I2S_OUT_ENB If set, the I2S output bus is enabled. If cleared, the I2S output will be tristate and all RX clocks will be

gated.

1 I2S_IN_ENB If set, the I2S input is enabled. If this bit cleared, the I2S input is ignored and all TX clocks gated.

2 I2S_MODE This programs the format of the I2S interface.

Definition

0 Normal

1 Left Justified

3 I2S_STEREO_REVERSE If set, the left and right channels are reversed.

Operation

0 Normal

1 Reversed

4 I2S_WS_MS If set, I2S_WS generation is enabled and is Master. If cleared, I2S_WS acts as slave.

6:5 I2S_WS_GEN_MODE This programs the I2S word length.

Bits/Word

00216

01225

10232

112—

7 I2S_WORD_ORDER This bit alters the RX phasing of left and right channels. If this bit is cleared: right then left. If this bit

is set: left then right.

201917r4

I2S Audio Port CLOCK/SYNC Options

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LM49370

12.33 I2S PORT CLOCK CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

TABLE 34. I2S Clock (0x1Bh)

Bit

Field Description

0 I2S_CLOCK_MS If set, then I2S clock generation is enabled and is Master. If this bit is cleared, then the I2S clock is

driven by the device slave.

1 I2S_CLOCK_SOURCE This selects the source of the clock to be used by the I2S clock generator.

I2S_CLOCK_SOURCE Clock is source from

0 DAC (from R divider)

1 ADC (from Q divider)

5:2 I2S_CLOCK_GEN_MODE This programs a clock divider that divides the clock defined by I2S_CLOCK_SOURCE. This divided

clock is used to generate I2S_CLK in Master mode. (Note 32)

Value Divide By Ratio

000021

000122

001024

001126

010028

0101210

0110216

0111220 —

100022.5 2/5

100123 1/3

101023.90625 32/125

101125 25/125

110027.8125 16/125

11012— —

11102— —

11112— —

7:6 PCM_SYNC_WIDTH This programs the width of the PCM sync signal.

Generated SYNC Looks like:

0021 bit (Used for Short PCM Modes)

0124 bits (Used for Long PCM Modes)

1028 bits (Used for Long PCM Modes)

11215 bits (Used for Long PCM Modes)

Should not be set if the bits/word is less than 16.

Note 32: For DAC_MODE = '00', '10', '11', DAC_CLOCK is the clock at the output of the R divider. For DAC_MODE = '01', DAC_CLOCK is a divided by two

version of the clock at the output of the R divider.

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LM49370

12.34 DIGITAL AUDIO DATA FORMATS

I2S master mode can only be used when the DAC is enabled unless the FORCE_RQ bit is set. PCM Master mode can only be

used when the ADC is enabled, unless the FORCE_RQ bit is set. If the PCM receiver interface is operated in slave mode the clock

and sync should be enabled at the same time because the PCM receiver uses the first PCM frame to calculate the PCM interface

format. This format can not be changed unless a soft reset is issued. Operating the LM49370 in master mode eliminates the risk

of sample rate mismatch between the data converters and the audio interfaces.

In slave mode, the PCM and I2S receivers only record the 1st 16 and 18 bits of the serial words respectively. The I2S and PCM

formats are as followed:

20191715

FIGURE 10. I2S Serial Data Format (Default Mode)

201917q8

FIGURE 11. I2S Serial Data Format (Left Justified)

20191716

FIGURE 12. PCM Serial Data Format (16 bit Slave Example)

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LM49370

12.35 PCM PORT MODE CONFIGURATION REGISTER

This register is used to control the audio data interfaces.

TABLE 35. PCM MODE (0x1Ch)

Bits Field Description

0 PCM_OUT_ENB If set, the PCM output bus is enabled. If this bit is cleared, thr PCM output will be tristate and all

RX clocks will be gated.

1 PCM_IN_ENB If set, the PCM input is enabled. If this bit is cleared, the PCM input is ignored and TX clocks are

generated.

3 PCM_CLOCK_SOURCE DAC or ADC Clock 0 = DAC, 1 = ADC (Note 32)

4 PCM_SYNC_MS If set, PCM_SYNC generation is enabled and is driven by the device (Master).

5 PCM_SDO_LSB_HZ If set, when the PCM port has run out of bits to transmit, it will tristate the SDO output.

6 PCM_COMPAND If set, the data sent to the PCM port is companded and the PCM data received by the PCM receiver

is treated as companded data.

7PCM_ALAW_μLAW If PCM_ COMPAND is set, then the data across the PCM interface to the DAC and from the ADC

is companded as follows:

PCM_ALAW_μLAW Commanding Type

0μ-LAW

1 A-Law

201917r1

FIGURE 13. PCM Audio Port CLOCK/SYNC Options

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LM49370

12.36 PCM PORT CLOCK CONFIGURATION REGISTER

This register is used to control the configuration of audio data interfaces.

TABLE 36. PCM Clock (0x1Dh)

Bits Field Description

3:0 PCM_CLOCK_

GEN_MODE

This programs a clock divider that divides the clock defined by PCM_CLOCK_SOURCE reg

(0x1Ch). The divided clock is used to generate PCM_CLK in Master mode. (Note 32)

Value Divide By Ratio

000021

000122

001024

001126

010028

0101210

0110216

0111220 —

100022.5 2/5

100123 1/3

101023.90625 32/125

101125 25/125

110027.8125 16/125

11012— —

11102— —

11112— —

6:4 PCM_SYNC_MODE This programs a clock divider that divides PCM_CLK. The divided clock is used to generate

PCM_SYNC.

Valve Divide By

00028

001216

010225

011232

100264

1012128

1102—

1112—

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LM49370

12.37 SRC CONFIGURATION REGISTER

This register is used to control the configuration of the Digital Routing interfaces. (Note 33)

TABLE 37. Bridges (0x1Eh)

Bits Field Description

0 PCM_TX_SEL This controls the data sent to the PCM transmitter.

PCM_TX_SEL Source

0 ADC

1 MONO SUM Circuit

2:1 I2S_TX_SEL This controls the data sent to the I2S transmitter.

I2S_TX_SEL Source

002ADC

012PCM Receiver

102DAC Interpolator (oversampled)

112Disabled

4:3 DAC_INPUT_SEL This controls the data sent to the DAC.

DAC_INPUT_SEL Source

002I2S Receiver (In stereo)

012PCM Receiver (Dual Mono)

102ADC

112Disabled

5 MONO_SUM_SEL This controls the data sent to the Stereo to Mono Converter

MONO_SUM_SEL Source

0 DAC Interpolated Output

1 I2S Receiver Output

7:6 MONO_SUM_MODE This controls the operation of the Stereo to Mono Converter.

MONO_SUM_ MODE Operation

002(Left + Right)/2

012Left

102Right

112(Left + Right)/2

Note 33: Please refer to the Application Note AN-1591 for the detailed discussion on how to use the I2S to PCM Bridge.

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LM49370

201917r2

FIGURE 14. I2S to PCM Bridge

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LM49370

12.38 GPIO CONFIGURATION REGISTER

This register is used to control the GPIOs and to control the digital signal routing when using the ADC and DAC to perform sample

rate conversion.

TABLE 38. GPIO Control (0x1Fh)

Bits Field Description

2:0 GPIO_1_SEL This configures the GPIO_1 pin.

GPIO_1_SEL Does What? Direction

0002Disable HiZ

0012SPI_SDO Output

0102Output 0 Output

0112Output 1 Output

1002Read Input

1012Class D Enable Output

1102AUX Enable Output

1112Dig_Mic_Data Input

5:3 GPIO_2_SEL This configures the GPIO_2 pin.

GPIO_2_SEL Does What? Direction

0002Disable HiZ

0012SPI_SDO Output

0102Output 0 Output

0112Output 1 Output

1002Read Input

1012Class D Enable Output

1102Dig_Mic L Clock Output

1112Dig_Mic R Clock Output

6 ADC_SRC_MODE If set, the ADC analog is disabled and the digital is enabled, using the resampler input.

7 DAC_SRC_MODE This does not have to be set to use DAC in SRC mode, but should be set if the user wishes to disable the

DAC analog to save power.

12.39 DAC PATH COMPENSATION FIR CONFIGURATION REGISTERS

To allow for compensation of roll off in the DAC and analog filter sections an FIR compensation filter is applied to the DAC input

data at the original sample rate. Since the DAC can operate at different over sampling ratios the FIR compensation filter is pro-

grammable. By default the filter applies approx 2dB of compensation at 20kHz. 5 taps is sufficient to allow passband equalization

and ripple cancellation to around +/0.01dB.

The filter can also be used for precise digital gain and simple tone controls although a DSP or CPU should be used for more

powerful tone control if required. As the FIR filter must always be phase linear, the coefficients are symmetrical. Coefficients C0,

C1, and C2 are programmable, C3 is equal to C1 and C4 is equal to C0. The maximum power of this filter must not exceed that

of the examples given below:

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LM49370

201917r3

FIGURE 15. FIR Consumption Filter Taps

Sample Rate DAC_MODE C0 C1 C2 C3 C4

48kHz 00 334 –2291 26984 –2291 343

48kHz 01 61 –371 25699 –371 61

For DAC_MODE = '00 and '01', the defaults should be sufficient; but for DAC_MODE = '10' and '11', care should be taken to ensure

the widest bandwidth is available without requiring such a large attenuation at DC that inband noise becomes audible.

TABLE 39. Compensation Filter C0 LSBs (0x20h)

Bits Field Description

7:0 C0_LSB Bits 7:0 of C0[15:0]

TABLE 40. Compensation Filter C0 MSBs (0x21h)

Bits Field Description

7:0 C0_MSB Bits 15:8 of C0[15:0]

TABLE 41. Compensation Filter C1 LSBs (0x22h)

Bits Field Description

7:0 C1_LSB Bits 7:0 of C1[15:0]

TABLE 42. Compensation Filter C1 MSBs (0x23h)

Bits Field Description

7:0 C1_MSB Bits 15:8 of C1[15:0]

TABLE 43. Compensation Filter C2 LSBs (0x24h)

Bits Field Description

7:0 C2_LSB Bits 7:0 of C2[15:0]

TABLE 44. Compensation Filter C2 MSBs (0x25h)

Bits Field Description

7:0 C2_MSB Bits 15:8 of C2[15:0]

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LM49370

13.0 Typical Performance Characteristics

(For all performance curves AVDD refers to the voltage applied to the A_VDD and LS_VDD pins. DVDD refers to the voltage applied

to the D_VDD and PLL_VDD pins; AVDD = 3.3V and DVDD = 3.3V unless otherwise specified.

Stereo DAC Frequency Response

fS = 8kHz

20191701

Stereo DAC Frequency Response Zoom

fS = 8kHz

20191702

Stereo DAC Frequency Response

fS = 16kHz

20191703

Stereo DAC Frequency Response Zoom

fS = 16kHz

20191704

Stereo DAC Frequency Response

fS = 24kHz

20191705

Stereo DAC Frequency Response Zoom

fS = 24kHz

20191708

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LM49370

Stereo DAC Frequency Response

fS = 32kHz

20191711

Stereo DAC Frequency Response Zoom

fS = 32kHz

20191717

Stereo DAC Frequency Response

fS = 48kHz

20191718

Stereo DAC Frequency Response Zoom

fS = 48kHz

20191719

THD+N vs

Stereo DAC Input Voltage

(0dB DAC, AUXOUT)

20191720

Stereo DAC Crosstalk

(0dB DAC, HP SE)

20191721

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LM49370

MONO ADC Frequency Response

fS = 8kHz, 6dB MIC

20191722

MONO ADC Frequency Response Zoom

fS = 8kHz, 6dB MIC

20191725

MONO ADC Frequency Response

fS = 8kHz, 36dB MIC

20191726

MONO ADC Frequency Response Zoom

fS = 8kHz, 36dB MIC

20191727

MONO ADC Frequency Response

fS = 16kHz, 6dB MIC

20191728

MONO ADC Frequency Response Zoom

fS = 16kHz, 6dB MIC

20191729

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LM49370

MONO ADC Frequency Response

fS = 16kHz, 36dB MIC

20191747

MONO ADC Frequency Response Zoom

fS = 16kHz, 36dB MIC

20191748

MONO ADC Frequency Response

fS = 24kHz, 6dB MIC

20191749

MONO ADC Frequency Response Zoom

fS = 24kHz, 6dB MIC

20191750

MONO ADC Frequency Response

fS = 24kHz, 36dB MIC

20191751

MONO ADC Frequency Response Zoom

fS = 24kHz, 36dB MIC

20191752

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LM49370

MONO ADC Frequency Response

fS = 32kHz, 6dB MIC

20191753

MONO ADC Frequency Response Zoom

fS = 32kHz, 6dB MIC

20191754

MONO ADC Frequency Response

fS = 32kHz, 36dB MIC

20191755

MONO ADC Frequency Response Zoom

fS = 32kHz, 36dB MIC

20191756

MONO ADC HPF Frequency Response

fS = 8kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01')

20191757

MONO ADC HPF Frequency Response

fS = 16kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01')

20191758

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LM49370

MONO ADC HPF Frequency Response

fS = 24kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01')

20191759

MONO ADC HPF Frequency Response

fS = 32kHz, 36dB MIC

(from left to right: HPF_MODE '00', '10', '01')

20191760

MONO ADC THD+N

vs MIC Input Voltage

(fS = 8kHz, 6dB MIC)

20191761

MONO ADC THD+N

vs MIC Input Voltage

(fS = 8kHz, 36dB MIC)

20191762

MONO ADC PSRR vs Frequency

AVDD = 3.3V, 6dB MIC

20191763

MONO ADC PSRR vs Frequency

AVDD = 5V, 6dB MIC

20191764

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LM49370

MONO ADC PSRR vs Frequency

AVDD = 3.3V, 36dB MIC

20191765

MONO ADC PSRR vs Frequency

AVDD = 5V, 36dB MIC

20191766

AUXOUT PSRR vs Frequency

AVDD = 3.3V, 0dB AUX

(AUX inputs terminated)

20191767

AUXOUT PSRR vs Frequency

AVDD = 5V, 0dB AUX

(AUX inputs terminated)

20191768

AUXOUT PSRR vs Frequency

AVDD = 3.3V, 0dB CPI

(CPI inputs terminated)

20191769

AUXOUT PSRR vs Frequency

AVDD = 5V, 0dB CPI

(CPI inputs terminated)

20191770

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LM49370

AUXOUT PSRR vs Frequency

AVDD = 3.3V, 0dB DAC

(DAC inputs selected)

20191771

AUXOUT PSRR vs Frequency

AVDD = 5V, 0dB DAC

(DAC inputs selected)

20191772

CPOUT PSRR vs Frequency

AVDD = 3.3V, 0dB AUX

(AUX inputs terminated)

20191773

CPOUT PSRR vs Frequency

AVDD = 5V, 0dB AUX

(AUX inputs terminated)

20191774

CPOUT PSRR vs Frequency

AVDD = 3.3V, 0dB DAC

(DAC inputs selected)

20191775

CPOUT PSRR vs Frequency

AVDD = 5V, 0dB DAC

(DAC inputs selected)

20191776

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LM49370

Earpiece PSRR vs Frequency

AVDD = 3.3V, 0dB AUX

(AUX inputs terminated)

20191777

Earpiece PSRR vs Frequency

AVDD = 5V, 0dB AUX

(AUX inputs terminated)

20191778

Earpiece PSRR vs Frequency

AVDD = 3.3V, 0dB CPI

(CPI input terminated)

20191779

Earpiece PSRR vs Frequency

AVDD = 5V, 0dB CPI

(CPI input terminated)

20191780

Earpiece PSRR vs Frequency

AVDD = 3.3V, 0dB DAC

(DAC input selected)

20191781

Earpiece PSRR vs Frequency

AVDD = 5V, 0dB DAC

(DAC input selected)

20191782

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LM49370

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB AUX, OCL 1.2V

(AUX inputs terminated)

20191783

Headphone PSRR vs Frequency

AVDD = 5V, 0dB AUX, OCL 1.2V

(AUX inputs terminated)

20191784

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB CPI, OCL 1.2V

(CPI input terminated)

20191785

Headphone PSRR vs Frequency

AVDD = 5V, 0dB CPI, OCL 1.2V

(CPI input terminated)

20191786

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB ADC, OCL 1.2V

(DAC input selected)

20191787

Headphone PSRR vs Frequency

AVDD = 5V, 0dB ADC, OCL 1.2V

(DAC input selected)

20191788

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LM49370

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB AUX, OCL 1.5V

(AUX inputs terminated)

20191789

Headphone PSRR vs Frequency

AVDD = 5V, 0dB AUX, OCL 1.5V

(AUX inputs terminated)

20191790

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB CPI, OCL 1.5V

(CPI input terminated)

20191791

Headphone PSRR vs Frequency

AVDD = 5V, 0dB CPI, OCL 1.5V

(CPI input terminated)

20191792

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB DAC, OCL 1.5V

(DAC input selected)

20191793

Headphone PSRR vs Frequency

AVDD = 5V, 0dB DAC, OCL 1.5V

(DAC input selected)

20191794

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LM49370

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB AUX, SE

(AUX inputs terminated)

20191795

Headphone PSRR vs Frequency

AVDD = 5V, 0dB AUX, SE

(AUX inputs terminated)

20191796

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB CPI, SE

(CPI input terminated)

20191797

Headphone PSRR vs Frequency

AVDD = 5V, 0dB CPI, SE

(CPI input terminated)

20191798

Headphone PSRR vs Frequency

AVDD = 3.3V, 0dB DAC, SE

(DAC input selected)

20191799

Headphone PSRR vs Frequency

AVDD = 5V, 0dB DAC, SE

(DAC input selected)

201917a0

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LM49370

Loudspeaker PSRR vs Frequency

AVDD = 3.3V, 0dB AUX

(AUX inputs terminated)

20191730

Loudspeaker PSRR vs Frequency

AVDD = 5V, 0dB AUX

(AUX inputs terminated)

20191731

Loudspeaker PSRR vs Frequency

AVDD = 3.3V, 0dB CPI

(CPI input terminated)

20191732

Loudspeaker PSRR vs Frequency

AVDD = 5V, 0dB CPI

(CPI input terminated)

20191733

Loudspeaker PSRR vs Frequency

AVDD = 3.3V, 0dB DAC

(DAC input selected)

20191734

Loudspeaker PSRR vs Frequency

AVDD = 5V, 0dB DAC

(DAC input selected)

20191735

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LM49370

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 3.3V, MICBIAS = 2.0V

201917a1

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 5V, MICBIAS = 2.0V

201917a2

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 3.3V, MICBIAS = 2.5V

201917a3

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 5V, MICBIAS = 2.5V

201917a4

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 3.3V, MICBIAS = 2.8V

201917a5

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 5V, MICBIAS = 2.8V

201917a6

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LM49370

INT/EXT MICBIAS PSRR vs Frequency

AVDD = 5V, MICBIAS = 3.3V

201917a7

AUXOUT THD+N vs Frequency

AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ

201917a8

AUXOUT THD+N vs Frequency

AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ

201917a9

CPOUT THD+N vs Frequency

AVDD = 3.3V, 0dB, VOUT = 1VRMS, 5kΩ

201917b0

CPOUT THD+N vs Frequency

AVDD = 5V, 0dB, VOUT = 1VRMS, 5kΩ

201917b1

Earpiece THD+N vs Frequency

AVDD = 3.3V, 0dB, POUT = 500mW, 32Ω

201917b2

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LM49370

Earpiece THD+N vs Frequency

AVDD = 5V, 0dB, POUT = 50mW, 32Ω

201917b3

Headphone THD+N vs Frequency

AVDD = 3.3V, OCL 1.5V, 0dB

POUT = 7.5mW, 32Ω

201917b4

Headphone THD+N vs Frequency

AVDD = 5V, OCL 1.5V, 0dB

POUT = 10mW, 32Ω

201917b5

Headphone THD+N vs Frequency

AVDD = 3.3V, OCL 1.2V, 0dB

POUT = 7.5mW, 32Ω

201917b6

Headphone THD+N vs Frequency

AVDD = 5V, OCL 1.2V, 0dB

POUT = 10mW, 32Ω

201917b7

Headphone THD+N vs Frequency

AVDD = 3.3V, SE, 0dB

POUT = 7.5mW, 32Ω

201917b8

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LM49370

Headphone THD+N vs Frequency

AVDD = 5V, SE, 0dB

POUT = 10mW, 32Ω

201917b9

Loudspeaker THD+N vs Frequency

AVDD = 3.3V, POUT = 400mW

15μH+8Ω+15μH

20191736

Loudspeaker THD+N vs Frequency

AVDD = 5V, POUT = 400mW

15μH+8Ω+15μH

20191737

Earpiece THD+N vs Output Power

AVDD = 3.3V, 0dB AUX

fOUT = 1kHz, 16Ω

201917c0

Earpiece THD+N vs Output Power

AVDD = 5V, 0dB AUX

fOUT = 1kHz, 16Ω

201917c1

Earpiece THD+N vs Output Power

AVDD = 3.3V, 0dB AUX

fOUT = 1kHz, 32Ω

201917c2

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LM49370

Earpiece THD+N vs Output Power

AVDD = 5V, 0dB AUX

fOUT = 1kHz, 32Ω

201917c3

Earpiece THD+N vs Output Power

AVDD = 3.3V, 0dB CPI

fOUT = 1kHz, 16Ω

201917c4

Earpiece THD+N vs Output Power

AVDD = 5V, 0dB CPI

fOUT = 1kHz, 16Ω

201917c5

Earpiece THD+N vs Output Power

AVDD = 3.3V, 0dB CPI

fOUT = 1kHz, 32Ω

201917c6

Earpiece THD+N vs Output Power

AVDD = 5V, 0dB CPI

fOUT = 1kHz, 32Ω

201917c7