This is information on a product in full production.
August 2012 Doc ID 018946 Rev 2 1/23
23
STGIPL20K60
SLLIMM™ (small low-loss intelligent molded module)
IPM, 3-phase inverter - 20 A, 600 V short-circuit rugged IGBT
Datasheet − production data
Features
■IPM 20 A, 600 V 3-phase IGBT inverter bridge
including control ICs for gate driving and free-
wheeling diodes
■Short-circuit rugged IGBTs
■VCE(sat) negative temperature coefficient
■3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull down/pull
up resistors
■Undervoltage lockout
■Internal bootstrap diode
■Interlocking function
■Smart shutdown function
■Comparators for fault protection against
overtemperature and overcurrent
■Op amps for advanced current sensing
■DBC substrate leading to low thermal
resistance
■Isolation rating of 2500 Vrms/min
■5 kΩ NTC for temperature control
■UL Recognized : UL1557 file E81734
Applications
■3-phase inverters for motor drives
■Home appliances, such as washing machines,
refrigerators, air conditioners and sewing
machines
Description
This intelligent power module provides a compact,
high performance AC motor drive in a simple,
rugged design. Combining ST proprietary control
ICs with the most advanced short-circuit-rugged
IGBT system technology, this device is ideal for 3-
phase inverters in applications such as home
appliances and air conditioners. SLLIMM™ is a
trademark of STMicroelectronics.
AM01193v1
SDIP-38L
Table 1. Device summary
Order code Marking Package Packaging
STGIPL20K60 GIPL20K60 SDIP-38L Tube
www.st.com
Contents STGIPL20K60
2/23 Doc ID 018946 Rev 2
Contents
1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STGIPL20K60 Internal schematic diagram and pin configuration
Doc ID 018946 Rev 2 3/23
1 Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
Internal schematic diagram and pin configuration STGIPL20K60
4/23 Doc ID 018946 Rev 2
Table 2. Pin description
Pin Symbol Description
1OUT
UHigh side reference output for U phase
2V
boot U Bootstrap voltage for U phase
3LIN
ULow side logic input for U phase
4HIN
UHigh side logic input for U phase
5OP-
UOp amp inverting input for U phase
6OP
OUT UOp amp output for U phase
7OP+
UOp amp non inverting input for U phase
8CIN
UComparator input for U phase
9OUT
VHigh side reference output for V phase
10 Vboot V Bootstrap voltage for V phase
11 LINVLow side logic input for V phase
12 HINVHigh side logic input for V phase
13 OP-VOp amp inverting input for V phase
14 OPOUT VOp amp output for V phase
15 OP+VOp amp non inverting input for V phase
16 CINVComparator input for V phase
17 OUTWHigh side reference output for W phase
18 Vboot W Bootstrap voltage for W phase
19 LINWLow side logic input for W phase
20 HINWHigh side logic input for W phase
21 OP-WOp amp inverting input for W phase
22 OPOUT W Op amp output for W phase
23 OP+WOp amp non inverting input for W phase
24 CINWComparator input for W phase
25 VCC Low voltage power supply
26 SD / OD Shutdown logic input (active low) / open drain (comparator output)
27 GND Ground
28 T2NTC thermistor terminal 2
29 T1NTC thermistor terminal 1
30 NWNegative DC input for W phase
31 W W phase output
32 P Positive DC input
33 NVNegative DC input for V phase
34 V V phase output
STGIPL20K60 Internal schematic diagram and pin configuration
Doc ID 018946 Rev 2 5/23
Figure 2. Pin layout (bottom view)
35 P Positive DC input
36 NUNegative DC input for U phase
37 U U phase output
38 P Positive DC input
Table 2. Pin description (continued)
Pin Symbol Description
Marking area
Electrical ratings STGIPL20K60
6/23 Doc ID 018946 Rev 2
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3. Inverter part
Symbol Parameter Value Unit
VPN Supply voltage applied between P-NU, NV
, NW450 V
VPN(surge)
Supply voltage (surge) applied between P-NU, NV
,
NW
500 V
VCES Each IGBT collector emitter voltage (VIN(1) = 0)
1. Applied between HINi, LINi and GND for i = U, V, W
600 V
± IC(2)
2. Calculated according to the iterative formula:
Each IGBT continuous collector current
at TC = 25 °C 20 A
± ICP (3)
3. Pulse width limited by max junction temperature
Each IGBT pulsed collector current 40 A
PTOT Each IGBT total dissipation at TC = 25 °C 56 W
tscw
Short circuit withstand time, VCE = 0.5 V(BR)CES
Tj = 125 °C, VCC = Vboot = 15 V, VIN (1)= 0 - 5 V 5µs
Table 4. Control part
Symbol Parameter Min. Max. Unit
VOUT
Output voltage applied between
OUTU, OUTV
, OUTW - GND Vboot - 21 Vboot + 0.3 V
VCC Low voltage power supply - 0.3 21 V
VCIN Comparator input voltage - 0.3 VCC + 0.3 V
Vop+ OPAMP non-inverting input - 0.3 VCC + 0.3 V
Vop- OPAMP inverting input - 0.3 VCC + 0.3 V
Vboot Bootstrap voltage - 0.3 620 V
VIN
Logic input voltage applied between HIN, LIN and
GND - 0.3 15 V
VSD/OD Open drain voltage - 0.3 15 V
dVOUT/dt Allowed output slew rate 50 V/ns
ICTC
() Tjmax()
TC
–
Rthj c–VCE sat()max()
Tjmax()
ICTC
(),()×
----- ---- ----------- ---- --------------- ---- ----------- ---- ----------- ---- ----------- ---- ---------------=
STGIPL20K60 Electrical ratings
Doc ID 018946 Rev 2 7/23
2.2 Thermal data
Table 5. Total system
Symbol Parameter Value Unit
VISO
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.) 2500 V
TjPower chips operating junction temperature -40 to 150 °C
TCModule case operation temperature -40 to 125 °C
Table 6. Thermal data
Symbol Parameter Value Unit
RthJC
Thermal resistance junction-case single IGBT 2.2 °C/W
Thermal resistance junction-case single diode 4.5 °C/W
Electrical characteristics STGIPL20K60
8/23 Doc ID 018946 Rev 2
3 Electrical characteristics
Tj = 25 °C unless otherwise specified.
Note: ton and toff include the propagation delay time of the internal drive. tC(ON) and tC(OFF) are the
switching time of IGBT itself under the internally given gate driving condition.
Table 7. Inverter part
Symbol Parameter Test condition
Value
Unit
Min. Typ. Max.
VCE(sat)
Collector-emitter
saturation voltage
VCC = VBoot = 15 V, VIN(1)= 0 - 5 V,
IC = 12 A -2.22.75
V
VCC = VBoot = 15 V, VIN(1)= 0 - 5 V,
IC = 12 A, Tj = 125 °C -1.8
ICES
Collector-cut off current
(VIN(1) = 0 “logic state”)
VCE = 550 V
VCC = Vboot = 15 V - 150 µA
VFDiode forward voltage VIN(1) = 0 “logic state”, IC = 12 A - 2.5 V
Inductive load switching time and energy
ton Tur n - on t i m e
VDD = 300 V,
VCC = Vboot = 15 V,
VIN(1) = 0 - 5 V,
IC = 12 A
(see
Figure 3
)
-915
ns
tc(on) Crossover time (on) - 155
toff Turn-off time - 375
tc(off) Crossover time (off) - 120
trr Reverse recovery time - 75
Eon Turn-on switching losses - 300 µJ
Eoff Turn-off switching losses - 170
1. Applied between HINi LINi and GND for i = U, V, W (LIN inputs are active-low).
STGIPL20K60 Electrical characteristics
Doc ID 018946 Rev 2 9/23
Figure 3. Switching time test circuit
Figure 4 "Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), VIN polarity
must be inverted for turn-on and turn-off.
Figure 4. Switching time definition
VCE ICIC
VIN
tON
tC(ON)
VIN(ON) 10% IC 90% IC 10% VCE
(a) turn-on (b) turn-off
trr
100% IC 100% IC
VIN
VCE
tOFF tC(OFF)
VIN(OFF) 10% VCE 10% IC
AM09223V1
Electrical characteristics STGIPL20K60
10/23 Doc ID 018946 Rev 2
3.1 Control part
Table 8. Low voltage power supply (VCC = 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Vcc_hys Vcc UV hysteresis 1.2 1.5 1.8 V
Vcc_thON Vcc UV turn ON threshold 11.5 12 12.5 V
Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
VCC = 10 V
SD/OD = 5 V; LIN = 5 V;
HIN = 0, CIN = 0
450 µA
I
qcc
Quiescent current
V
cc
= 15 V
SD/OD = 5 V; LIN = 5 V
HIN = 0, CIN = 0
3.5 mA
V
ref
Internal comparator (CIN)
reference voltage 0.5 0.54 0.58 V
Table 9. Bootstrapped voltage (VCC = 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VBS_hys VBS UV hysteresis 1.2 1.5 1.8 V
VBS_thON VBS UV turn ON threshold 10.6 11.5 12.4 V
VBS_thOFF VBS UV turn OFF threshold 9.1 10 10.9 V
I
QBSU
Undervoltage VBS quiescent
current
V
BS
< 9 V
SD/OD = 5 V; LIN and
HIN = 5 V; CIN = 0
70 110 µA
I
QBS
VBS quiescent current
V
BS
= 15 V
SD/OD = 5 V; LIN and
HIN = 5 V; CIN = 0
150 210 µA
R
DS(on)
Bootstrap driver on resistance LVG ON 120 Ω
Table 10. Logic inputs (VCC = 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
il
Low logic level voltage 0.8 V
V
ih
High logic level voltage 2.25 V
I
HINh
HIN logic “1” input bias current HIN = 15 V 110 175 260 µA
I
HINl
HIN logic “0” input bias current HIN = 0 V 1 µA
ILINl LIN logic “1” input bias current LIN = 0 V 3 6 20 µA
ILINh LIN logic “0” input bias current LIN = 15 V 1 µA
I
SDh
SD logic “0” input bias current SD = 15 V 30 120 300 µA
I
SDl
SD logic “1” input bias current SD = 0 V 3 µA
Dt Dead time see
Figure 8
600 ns
STGIPL20K60 Electrical characteristics
Doc ID 018946 Rev 2 11/23
Table 11. Op amp characteristics (VCC = 15 V unless otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
Vio Input offset voltage Vic = 0 V, Vo = 7.5 V 6 mV
Iio Input offset current Vic = 0 V, Vo = 7.5 V 440nA
Iib Input bias current (1) 100 200 nA
V
icm
Input common mode voltage
range 0V
V
OL
Low level output voltage RL = 10 kΩ to VCC 75 150 mV
V
OH
High level output voltage RL = 10 kΩ to GND 14 14.7 V
I
o
Output short circuit current
Source,
Vid = +1; Vo = 0 V 16 30 mA
Sink,
Vid = -1; Vo = VCC
50 80 mA
SR Slew rate Vi = 1 - 4 V; CL = 100 pF;
unity gain 2.5 3.8 V/μs
GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz
Avd Large signal voltage gain RL = 2 kΩ70 85 dB
SVR Supply voltage rejection ratio vs. VCC 60 75 dB
CMRR Common mode rejection ratio 55 70 dB
1. The direction of input current is out of the IC.
Table 12. Sense comparator characteristics (VCC = 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Iib Input bias current VCP+ = 1 V - 3 µA
V
ol
Open-drain low-level output
voltage Iod = 3 mA - 0.5 V
t
d_comp
Comparator delay SD/OD pulled to 5 V through
100 kΩ resistor - 90 130 ns
SR Slew rate CL = 180 pF; Rpu = 5 kΩ-60 V/µsec
tsd Shutdown to high / low side
driver propagation delay
VOUT = 0, Vboot = VCC,
VIN = 0 to 3.3 V 50 125 200
ns
tisd
Comparator triggering to high /
low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CINi
50 200 250
Electrical characteristics STGIPL20K60
12/23 Doc ID 018946 Rev 2
Note: X: don’t care.
Table 13. Truth table
Condition
Logic input (VI) Output
SD/OD LIN HIN LVG HVG
Shutdown enable
half-bridge 3-state LXXLL
Interlocking
half-bridge 3-state HLHLL
0 ‘’logic state”
half-bridge 3-state HHL L L
1 “logic state”
low side direct driving HLLHL
1 “logic state”
high side direct driving HHHLH
Figure 5. Maximum IC(RMS) current vs.
switching frequency (1)
Figure 6. Maximum IC(RMS) current vs. fsine(1)
1. Simulated curves refer to typical IGBT parameters and maximum Rthj-c.
AM09907v1
0
2
4
6
8
10
12
14
16
18
20
22
24
26
0 4 8 12 16 20
Ic(RMS) [A]
fsw[kHz]
VPN = 300 V, Modulaon index = 0.8,
PF = 0.6, Tj = 150 °C, fSINE = 60 Hz
TC = 80 °C
TC = 100 °C
AM09908v1
8
9
10
11
12
13
14
15
16
17
18
1 10 100
Ic(RMS) [A]
fSINE [Hz]
fsw = 12 kHz
fsw = 20 kHz
fsw = 16 kHz
V
PN
= 300 V, Modulaon index = 0.8,
PF = 0.6, T
j
= 150 °C, T
c
= 100°C
STGIPL20K60 Electrical characteristics
Doc ID 018946 Rev 2 13/23
3.1.1 NTC thermistor
Equation 1: resistance variation vs. temperature
Where T are temperatures in Kelvin
Table 14. NTC thermistor
Symbol Parameter Test conditions Min. Typ. Max. Unit.
R25 Resistance TNTC = 25°C to 85°C 5 kΩ
R125 Resistance TNTC = 125°C 300 Ω
B B-constant TC = 25°C to 85°C 3340 K
T Operating temperature -40 125 °C
Figure 7. NTC resistance vs. temperature
RT() R25 e
B1
T
--- 1
298
----------–
⎝⎠
⎛⎞
⋅=
Electrical characteristics STGIPL20K60
14/23 Doc ID 018946 Rev 2
3.2 Waveform definitions
Figure 8. Dead time and interlocking waveforms definitions
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DTLH DTHL
DTLH DTHL
DTLH DTHL
DTLH DTHL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
(*) HIN and LIN can be connected together and driven by just one control signal
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
STGIPL20K60 Smart shutdown function
Doc ID 018946 Rev 2 15/23
4 Smart shutdown function
The STGIPL20K60 integrates a comparator for fault sensing purposes. The comparator
non-inverting input (CIN) can be connected to an external shunt resistor in order to
implement a simple overcurrent protection function. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low-level leading the half-
bridge in 3-state. In the common overcurrent protection architectures the comparator output
is usually connected to the shutdown input through a RC network, in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
internal logic turns on the open-drain output and holds it on until the shutdown voltage goes
below the logic input lower threshold. Finally the smart shutdown function provides the
possibility to increase the real disable time without increasing the constant time of the
external RC network.
Figure 9. Smart shutdown timing waveforms
Pls refer to
Table 12
for internal propagation delay time details.
HIN/LIN
HVG/LVG
SD/OD
open drain gate
(internal)
upper
threshold lower
threshold
comp
Vref
CP+
PROTECTION
Fast shut down:
the driver outputs are set in SD state
immediately after the comparator
triggering even if the SD signal
has not yet reach
the lower input threshold
real disable time
2
1
1
2
= (RON_OD // RSD)CSD
= RSD CSD
SD/OD
FROM/TO
CONTROLLER
VBIAS
SMART
SD
LOGIC
CSD
RSD
RON_OD
SHUT DOWN CIRCUIT
TIME CONSTANTS
Application information STGIPL20K60
16/23 Doc ID 018946 Rev 2
5 Application information
Figure 10. Typical application circuit
STGIPL20K60 Application information
Doc ID 018946 Rev 2 17/23
5.1 Recommendations
●Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each
high side input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.
●Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an
internal 5 V regulator through a diode, is built-in for each low side input.
●To prevent the input signals oscillation, the wiring of each input should be as short as
possible.
●By integrating an application specific type HVIC inside the module, direct coupling to
MCU terminals without any opto-coupler is possible.
●Each capacitor should be located as nearby the pins of IPM as possible.
●Low inductance shunt resistors should be used for phase leg current sensing.
●Electrolytic bus capacitors should be mounted as close to the module bus terminals as
possible. Additional high frequency ceramic capacitor mounted close to the module
pins will further improve performance.
●The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: Smart shutdown function
for detailed info).
For further details refer to AN3338.
Table 15. Recommended operating conditions
Symbol Parameter Conditions
Value
Unit
Min. Typ. Max.
VPN Supply voltage Applied between P-Nu, Nv, Nw 300 400 V
VCC Control supply voltage Applied between VCC-GND 13.5 15 18 V
VBS High side bias voltage Applied between VBOOTi-OUTi for
i = U, V, W 13 18 V
tdead
Blanking time to
prevent Arm-short For each input signal 1 µs
fPWM PWM input signal -40°C < Tc < 100°C
-40°C < Tj < 125°C 20 kHz
TC
Case operation
temperature 100 °C
Package mechanical data STGIPL20K60
18/23 Doc ID 018946 Rev 2
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Please refer to dedicated technical note TN0107 for mounting instructions.
Table 16. SDIP-38L mechanical data
Dimensions
mm.
Min. Typ. Max.
A 49.10 49.60 50.10
A1 1.10 1.30 1.50
A2 1.40 1.60 1.80
A3 44.10 44.60 45.10
B 24.00 24.50 25.00
B1 11.25 11.85 12.45
B2 27.10 27.60 28.10
B3 28.60 29.10 29.60
C 5.00 5.40 6.00
C1 6.50 7.00 7.50
C2 10.35 10.85 11.35
e 1.10 1.30 1.50
e1 3.20 3.40 3.60
e2 5.80 6.00 6.20
e3 4.60 4.80 5.00
e4 5.60 5.80 6.00
e5 6.30 6.50 6.70
e6 4.50 4.70 4.90
D 38.10
D1 5.75
E 11.80
E1 2.15
F 0.85 1.00 1.15
F1 0.35 0.50 0.65
R 1.55 1.75 1.95
T 0.45 0.55 0.65
V0° 6°
STGIPL20K60 Package mechanical data
Doc ID 018946 Rev 2 19/23
Figure 11. SDIP-38L package dimensions
8142868_G
Package mechanical data STGIPL20K60
20/23 Doc ID 018946 Rev 2
Figure 12. SDIP-38L shipping tube type A (dimensions are in mm.)
8147106_E
STGIPL20K60 Package mechanical data
Doc ID 018946 Rev 2 21/23
Figure 13. SDIP-38L shipping tube type B (dimensions are in mm.)
8147106_E
Revision history STGIPL20K60
22/23 Doc ID 018946 Rev 2
7 Revision history
Table 17. Document revision history
Date Revision Changes
16-Jun-2011 1Initial release
28-Aug-2012 2
Modified: Min. and Max. value
Table 4 on page 6
.
Updated:
Figure 12 on page 20
.
Added:
Figure 13 on page 21
.
STGIPL20K60
Doc ID 018946 Rev 2 23/23
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