MC14050BDR2G - ON Semiconductor - Datasheet.Directory

June, 2011 − Rev. 7

1Publication Order Number:

MC14049B/D

MC14049B, MC14050B

Hex Buffer

The MC14049B Hex Inverter/Buffer and MC14050B Noninverting

Hex Buffer are constructed with MOS P−Channel and N−Channel

enhancement mode devices in a single monolithic structure. These

complementary MOS devices find primary use where low power

dissipation and/or high noise immunity is desired. These devices

provide logic level conversion using only one supply voltage, VDD.

The input−signal high level (VIH) can exceed the VDD supply

voltage for logic level conversions. Two TTL/DTL loads can be driven

when the devices are used as a CMOS−to−TTL/DTL converter

(VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).

Note that pins 13 and 16 are not connected internally on these

devices; consequently connections to these terminals will not affect

circuit operation.

Features

•High Source and Sink Currents

•High−to−Low Level Converter

•Supply Voltage Range = 3.0 V to 18 V

•VIN can exceed VDD

•Meets JEDEC B Specifications

•Improved ESD Protection On All Inputs

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin Input Voltage Range (DC or Transient) −0.5 to +18.0 V

Vout Output Voltage Range (DC or Transient) −0.5 to VDD +

0.5

V

Iin Input Current (DC or Transient) per Pin ±10 mA

Iout Output Current (DC or Transient) per Pin ±45 mA

PDPower Dissipation, per Package (Note 1)

(Plastic)

(SOIC)

825

740

mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature (8−Second Soldering) 260 °C

1. Temperature Derating: See Figure 3.

This device contains protection circuitry to protect the inputs against damage

due to high static voltages or electric fields referenced to the VSS pin only. Extra

precautions must be taken to avoid applications of any voltage higher than the

maximum rated voltages to this high−impedance circuit. For proper operation, the

ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

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MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC140xxBCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

140xxBG

AWLYWW

14

050B

ALYWG

G

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Indicator

SOEIAJ−16

F SUFFIX

CASE 966

MC140xxB

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

16

1

16

1

16

1

16

(Note: Microdot may be in either location)

MC14049B, MC14050B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

OUTE

NC

INF

OUTF

NC

IND

OUTD

INE

OUTB

INA

OUTA

VDD

VSS

INC

OUTC

INB

LOGIC DIAGRAM

MC14049B

14 15

11

9

7

5

3

12

10

6

4

2

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

MC14050B

14 15

11

9

7

5

3

12

10

6

4

2

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

ORDERING INFORMATION

Device Package Shipping†

MC14049BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14049BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14049BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14049BFELG SOEIAJ−16

(Pb−Free)

2000 Units / Tape & Reel

MC14050BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14050BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14050BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC14050BDTG TSSOP−16*

(Pb−Free)

96 Units / Rail

MC14050BDTR2G TSSOP−16*

(Pb−Free)

2500 Units / Tape & Reel

MC14050BFELG SOEIAJ−16

(Pb−Free)

2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC14049B, MC14050B

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

– 55_C

ÎÎÎÎÎÎÎÎÎ

+ 25_C

ÎÎÎÎÎ

+ 125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD

“1” Level

Vin = 0

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

“1” Level

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 1.6

– 4.7

ÎÎÎ

−

ÎÎÎÎ

– 1.25

– 1.30

– 3.75

ÎÎÎ

– 2.5

– 2.6

– 10

ÎÎÎÎ

−

ÎÎÎ

– 1.0

– 3.0

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

3.75

10

30

ÎÎÎ

−

ÎÎÎÎ

3.2

8.0

24

ÎÎÎ

6.0

16

40

ÎÎÎÎ

−

ÎÎÎ

2.6

6.6

19

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

±0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

±0.1

ÎÎÎ

−

ÎÎÎ

±1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance (Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

10

ÎÎÎÎ

20

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current (Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.0

2.0

4.0

ÎÎÎÎ

−

ÎÎÎ

0.002

0.004

0.006

ÎÎÎÎ

1.0

2.0

4.0

ÎÎÎ

−

ÎÎÎ

30

60

120

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent,

per package)

(CL = 50 pF on all outputs, all

buffers switching

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (1.8 mA/kHz) f + IDD

IT = (3.5 mA/kHz) f + IDD

IT = (5.3 mA/kHz) f + IDD

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at + 25_C

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

Where: IT is in mA (per Package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency and k = 0.002.

MC14049B, MC14050B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = + 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (0.7 ns/pF) CL + 65 ns

tTLH = (0.25 ns/pF) CL + 37.5 ns

tTLH = (0.2 ns/pF) CL + 30 ns

ÎÎÎÎÎ

tTLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

160

80

60

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (0.2 ns/pF) CL + 30 ns

tTHL = (0.06 ns/pF) CL + 17 ns

tTHL = (0.04 ns/pF) CL + 13 ns

ÎÎÎÎÎ

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

40

20

15

ÎÎÎÎ

60

40

30

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

tPLH = (0.33 ns/pF) CL + 63.5 ns

tPLH = (0.19 ns/pF) CL + 30.5 ns

tPLH = (0.06 ns/pF) CL + 27 ns

ÎÎÎÎÎ

tPLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

80

40

30

ÎÎÎÎ

140

80

60

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

tPHL = (0.2 ns/pF) CL + 30 ns

tPHL = (0.1 ns/pF) CL + 15 ns

tPHL = (0.05 ns/pF) CL + 12.5 ns

ÎÎÎÎÎ

tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

40

20

15

ÎÎÎÎ

80

40

30

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Typical Output Source Characteristics Figure 2. Typical Output Sink Characteristics

MC14049B MC14050B MC14049B MC14050B

VDD

VSS

VDD

VSS

1

8

1

8

IOL

IOH VOH VOL

VDS = VOH - VDD

VDD

VSS

1

8

IOL VOL

VDD

VSS

1

8

IOH VOH

VDD = VOL

IOH, OUTPUT SOURCE CURRNT (mAdc)

IOL, OUTPUT SINK CURRENT (mAdc)

-50

-40

-30

-20

-10

0

-10 -8.0 -6.0 -4.0 -2.0 0

VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

VGS = 5.0 Vdc

VGS = 10 Vdc

MAXIMUM CURRENT LEVEL

VGS = 15 Vdc

160

120

80

40

00 2.0 4.0 6.0 8.0 10

VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

VGS = 15 Vdc

VGS = 10 Vdc

MAXIMUM CURRENT LEVEL

VGS = 5.0 Vdc

MC14049B, MC14050B

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5

Figure 3. Ambient Temperature Power Derating

PD, MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE

1200

1100

1000

900

825

800

740

700

600

500

400

300

200

100

0175150125100755025

TA, AMBIENT TEMPERATURE (°C)

175 mW (P)

120 mW (D)

(P) PDIP

(D) SOIC

tPHL

Figure 4. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR

VDD

VSS

8

1

CL

Vout

Vin

#

#Invert on MC14049B only

20 ns 20 ns

VDD

VSS

VOH

VOL

VOH

VOL

90%

50%

10%

90%

50%

10%

90%

50%

10%

tPLH

tTLH

tPHL

tTHL

tPHL

tPLH

tTLH tTHL

OUTPUT

MC14049B

OUTPUT

MC14050B

INPUT

MC14049B, MC14050B

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6

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC14049B, MC14050B

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7

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

16

89

8X

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC14049B, MC14050B

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8

PACKAGE DIMENSIONS

TSSOP−16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F−01

ISSUE B

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC14049B, MC14050B

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9

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14049B/D

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