IntegratorSeriesFPGAs: 40M X and 42M X Families Preliminary Datla Sheet (Revision 1.4) Features High Capacity * 2,000 to 52,000 Available Logic Gates * Up to3Kbits Configurable Dual-Port SRAM * Fast Wide-Decode Circuitry * Up to 250 User-Programmabie! Pins High Performance * .6ns Clock-to-Out * 250 MHz Performance * SnsDual-Port SRAM Access * 100MHzFIFOs * 7.5 ns 35-Bit Address Decode Ease of Integration * Mixed Voltage Operation (5.0V or 3.3V 1,0). * Synthesis-Friendly Architecture to Support ASIC Design Methodologies. * 95--100% Resource Utilization, Using Automatic Place and Route Tools with up to 100% Pin Fixing. Integrator Series Product Profile * Deterministic, User-Controllable Timing Via DirectTime Software Tools. * MX Diagnostics and Debug Supported by Silicon Explorer. Supported by Actel Designer Series D evelopment System with Interfaces to Popular Design Environments Including Cadence, Exemplar, |ST, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. * Low Power Consumption (less than 100 A in Stand-By Mode). * IEEE Standard 1149.4 (JTAG) Boundary Scan Testing * 5.0V and 3.3V Programmable PCI-Compliant 1). General Description The newest additions to Actals Integrator Series of programmable logic devices, the 40MX and 42MX families, provide system logic designers with a high performance, cost-effective ASIC alternative in a single FPGA. The MX device architecture is based on Actel's patented antifuse technology implemented in a 0.45 triple-metal Device Ad0MX82 AGOMX04 =Ag2MX09 AS2MX16 AS2MX24 Aa2MX36 AS2MX52 Capacity Gates 2,000 4,000 9,000 16,000 24,000 36,000 52,000 ASIC-Equivalent Gates 1,200 2,000 4,000 8,000 14,000 20,000 30,000 SRAM Bits N/A N/A N/A N/A N/A 2,560 3,072 Logic Modules Sequential 348 624 954 1,230 1,888 Combinatorial 295 547 336 608 912 1,184 1,833 Decode _ _ N/A N/A 24 24 28 Clock-to-Out 9.5ns 9.5 ns 5.6 ns 6.1 ns 6.1 ns 6.3 ns 7.28 SRAM Modules (64x4 or 32x8) N/A N/A N/A N/A N/A 10 12 Dedicated Flip-Flops _ _ 348 624 954 1,230 1,888 Maximum Flip-Flops 147 273 516 928 1,410 1,822 2,804. Clocks 1 1 2 2 2 6 6 User 1/0 (Maximum) 57 69 104 140 176 202 250 JTAG No No No No Yes Yes Yes Packages PL44 PL44 PL84 PL84 PL84 PQ208 RQ208 PL68 PL68 PQ100 PQ100 PQ160 RQ240 RQ240 PQ100 PL84 PQi60 PQ160 PQ208 BG304 VQ80 PQ100 TQ176 PQ208 TQ176 Q80 VQ100 TQ176 VQ100 February 1998 1 1998 Actel CorporationICLS/ CMOS process. With capacities ranging from 2,000 to 52,000 gales, the syn thesis-friendly MX devices provide datapaths up to 250 MHz, are live on power-up, and deliver up to five times lower stand-by power consumption than any other FPGA device. Actels MX FPGAs provide up to 250 | /Os, and are available in a wide variety of packages and speed grades. Actels 42MX family of FPGAs also feature MultiPlex | 0, an advanced architectural feature that Supports mixed voltage systems, enables programmable PCI, delivers high-performance operation at both 5.0V and 3.3V, and provides a low-power mode. MulliPlex 1/0 supports the most common voltage standards today. pure 5.0V operation, pure 3.3V operation, and mixed 3.3V operation with 5.0V opertaion input tolerance for maximum performance. Internal array performance is retained in 3.3V systems by using complimentary pass gates that operate as fast at 3.3V as they do at 5.0V. Ordering Information A42MX16 + PQ 100 Package PL PQ RQ TQ VQ BG Speed Grade Blank = 1= 2 = 3 = F = Part Number A40MX02 = 2,000 Gates A40MX04 = 4,000 Gates A42MX09 = 9,000 Gates A42MX16 = 16,000 Gates A42MX24 = 24,000 Gates A42MX36 = 36,000 Gates A42MX52 = 52,000 Gates MultiPlax | /O includes selectable PCI output drives in certain 42MX devices, enabling 100% PCI compliance for both 5.0V and 3.3V systems. For low-power systems, MultiPlex 1/0 is used to turn off all inputs and outputs to cut current consumption ta below 100 A. The 42MX FPGA devices also include system-level features such as JTAG, dual-port SRAM, and fast wide-decode modules. The 42MX family offers the industry's fastest dual-port SRAM for implementing fast FIFQs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation, and can perform transformation functions such as telecommunications, networking, and DSP. The 42M X FPGAs were designed to intagrate system logic that is typically implemented in multiple CPLDs, PAL\s and FPGAs. Application (Temperature Range) Blank Commercial (0 to +70C) | Industrial (~40 to +85C) ll ou Package Lead Count Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Plastic Power Quad Flat Pack Thin (1.4 mm) Quad Flat Pack Very Thin (1.0 mm) Quad Flat Pack Ball Grid Array von Ww ob om a Standard Speed Approximately 15% Faster than Standard Approximately 25% Faster than Standard Approximately 35% Faster than Standard Approximately 40% Slower than StandardProduct Plan Integrator Series FPGAs: 40MX and 42MX Families Speed Grade Application Std -1 -2 -3* -F* c ! M A40MX02 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) VV YI VV ~ 68-Pin Plastic Leaded Chip Carrier (PLCC) VWVVV4V Vv 100-Pin Plastic Quad Flat Pack (PQFP) VV Vv _ 80-Pin Very Thin Plastic Quad Flat Pack (VQFP) VV VV vv A40MX04 Device 44-Pin Plastic Leaded Chip Carrier (PLCC) VIN Vv 68-Pin Plastic Leaded Chip Carrier (PLCC) VVVYV Vv 84-Pin Plastic Leaded Chip Carrier (PLCC) VV Vv 100-Pin Plastic Quad Flat Pack (PQFP) Asam ad ~ 80-Pin Very Thin Plastic Quad Flat Pack (VQFP} VV vV Vv A42MX09 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) vv vvv 100-Pin Plastic Quad Flat Pack (PQFP) VV a ~~ 160-Pin Plastic Quad Flat Pack (PQFP) Vv vv 176-Pin Thin Plastic Quad Flat Pack (TQFP) el _ VWvv 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) P P P = P P P _ A42MX16 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) vvv os vv _ 100-Pin Plastic Quad Flat Pack (PQFP) VV v vv 160-Pin Plastic Quad Flat Pack (PQFP) vvY Vvv _ 208-Pin Plastic Quad Flat Pack (PQFP) vv _ vv 176-Pin Thin Plastic Quad Fiat Pack (TQFP) VV Vv 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) P P P _ P P P A42MX24 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) vVv Vvv 160-Pin Plastic Quad Flat Pack (PQFP) Vvv _ vd 208-Pin Plastic Quad Flat Pack (PQFP) Vvvv Vvv 176-Pin Thin Plastic Quad Flat Pack (TQFP) VVv vv A42MX36 Device 208-Pin Plastic Quad Flat Pack (PQFP) Vvv vv 240-Pin Plastic Power Quad Flat Pack (RQFP) Vv _ vv _ 304-Pin Ball Grid Array (BGA) P P P P P P _ A42MX52 Device 208-Pin Plastic Power Quad Flat Pack (RQFP) P P P P P P 240-Pin Plastic Power Quad Flat Pack (RQFP) P P _ P P P Applications: C = Commercial Availability. W = Available Speed Grade: -1 = Approx. 15%Faster than Standard I = Industrial P = Planned 2 = Approx. 25%Faster than Standard M = Military = Not Planned ~3 = Approx. 35%Faster than Standard B = MLSTD 883 F = Approx. 40%Slower than StandardICTS) Integrator Series devices ara supported by Actels Designer Series development software, which provides a seamless integration into many ASIC design flows. The Designer Series development tools offer automatic place and route (even with pre-assigned pins), static timing analysis, user programming, and debug and diagnostic probe capabilities. The DirectTime tool provides deterministic and controllable timing, allowing the designer to specify the performance requirements of individual paths and system clocks. Using these specifications, the software will automatically optimize the placement and routing of the logic to meet the constraints. Also included with the Designer Series tools is Actels ACTgen Macro Builder. ACTgen allows the designer quickly to build fast, efficient logic functions such as counters, adders, FIFOs, and RAM. The Designer Series tools provide designers with the Capability to move up to high-level description languages, Plastic Device Resources such as VHDL and Vaerilog-HDL, or to use schematic design entry with interfaces to most EDA tools. Designer Series is supported on 486 and Pentium PCs and on Sun and HP workstations. The software provides CAE interfaces to Cadence, Mentor Graphics, Escalade, OrCAD, and Viewlogic design environments. Additional development tools are supported through Actels Industry Alliance Program, including Datal /O (ABEL FPGA) and MING. Actels MX FPGAs provide a high-performance, single-chip solution for shortening the system design and development cycle, and they offer a cost-effective alternative to ASICs. The 40MX and 42MX devices are an excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP, and co-processor functions. User I/Os PLCC PLCC PLCC | VQFP VQFP | PQFP PQFP PQFP ROFP RQFP | TQFP | BGA Device |44-Pin 68-Pin 84-Pin | 80-Pin 100-Pin|100-Pin 160-Pin 208-Pin 208-Pin 240-Pin |176-Pin |304-Pin A40MX02 34 57 _ 57 _ 57 A40MX04 34 57 69 69 69 _ _ _ _ A42MX09 _ 72 83 83 100 _ _ 103 A42MX16 72 83 83 125 140 140 A42MX24 _ _ 72 _ 125 176 _ 150 A42MX36 _ _ _ 176 202 202 A42MX52 _ = _ _ _ _ _ 176 202 _ Packa ge Definitions (Consult your local Actel sales Tepresentative for product availability.) PLOC= Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VOFP = Very Thin Quad Flat Pack, ROP = Plastic Power Quad Flat Pack, BGA= Enhanced Ball Grid ArrayPin Description CLK, CLKA, CLKB Clock Clock A and Clock B (Input) TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an | /0. DCLK Diagnostic Clock (input) TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an | /0 when the MODE pin is LOW. GND Ground (Input) Input LOW supply voltage. VO Input/Output (Input, Output) Input, output, tri-state, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused | /O pins are automatically driven LOW by the Designer Series software. MODE Mode (Input) Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). To provide ActionP robe capability, the MODE pin should be held HIGH. To facilitate this the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled HIGH when required. NG No Connection Not connected to circuitry within the device. PRB, I/O Probe A (Output) Used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined 1/0 when debugging has been completed. The pins probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an | /O when the MODE pin is LOW. PRB, I/O Probe B (Output) Used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined | /O when debugging has been completed. The pins probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an |/O when the MODE pin is LOW. Integrator Series FPGAs: 40MX and 42MX Families QCLKA/B,C,D Quadrant Clock (Input/Output) Quadrant clock inputs. When not used as a register control signal, these pins can function as general-purpose | /0. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin isHIGH. This pin functions as an IO when the MODE pin is LOW. TCK Test Clock Clock signal to shift the JTAG data into the device. This pin functions as an I /O when the JTAG fuse is not programmed. TDI Test Data In Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an | 0 when the JTAG fuse is not programmed. TDO Test Data Out Serial data output for JTAG instructions and test data. This pin functions as an 1/0 when the JTAG fuse is not programmed. TMS Test Mode Select Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an 1/0 when the JTAG fuse is not programmed. Voc Supply Voltage (Input) Input HIGH supply voltage. Voca Supply Voltage (Input) Input HIGH supply voltage, supplies array core only. Voc Supply Voltage (Input) Input HIGH supply voltage, supplies! /O cells only. LP Low Power Mode Controls the low power mode of all 42MX devices. This pin must be set HIGH to switch the device to low power mode. In low power mode, all | /Os are tri-stated, all input buffers are turned OFF, and the core of the devicesis turned OFF. To exit the LOW power mode, the LP pin must be set LOW. This mode is enabled 800 nsec after LP pin is set HIGH. TCX, TDI, TDO, TMS are available only on devices containing JTAG circuitry. Note:Scts/ ey Connecting V 40MX cc on MX Devices The 40MX FPGAs will operate in 5.0V only systems or 3.3V only systems. Vor Input Output 3.3V 3.3V 3.3V 5.0V 5.0V 5.0V 42MX The 42M X FPGAs will operate in 5.0V only systems, 3.3V only systems, or mixed 5.0V/8.3V systems. Voca Vee Input Output 3.3V 3.3V 3.3V 3.3V 5.0V 3.3V 3.3V, 5.0V 3.3V 5.0V 5.0V 5.0V 5.0V MX Architectural Overview The 40MX and 42MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within the Integrator Series are composed of logic modules, routing resources, clock networks, and | /O modules, which are the building blocks for designing fast logic designs. In addition, a subset of devices contain embedded dual-port SRAM and wide decode modules. The dual-port SRAM modules are optimized for high-speed datapath functions such as FIFOs, LIFOs, and scratchpad memory, The "Integrator Series Product Profile on page 1 lists the specific logic resources contained within each device. Logic Modules The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1). The logic module can impiement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions with different combinations of active LOW inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in tha array, since latches and flip-flops can be constructed from logic modules wherever needed in the application. Figure 1 40MX Logic ModuleThe 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules), and decode (D-modules). The C-module is shown in Figure 2 and implements the following function: Y=181*!50*D 00+ !S1*S0*D 01+ $1*1S0*D10+$1*S0"D11 where S0= A0*BO S1=A1+B1 The $-module shown in Figure 3 is designed to implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D flip-flop or a transparent latch. To increase flexibility, the S-module register can be bypassed so that it implements purely combinatorial logic. Integrator Series FPGAs: 40MX and 42MX Families Ao _ Bo Al Bi Figure 2* C-Module Implementation -H OUT Up to 7-Input Function Plus D-Type Flip-Flop with Clear DO r OUT D1 GATE CLR Up to 4-Input Function Plus Latch with Clear - OUT GATE Up to 7-Input Function Plus Latch OUT Up to 8-Input Function Ssame as C-Module) Figure 3* = S-Module ImplementationSome of the 42MX devices contain a third type of logic module, D-modules, which are arranged around the peripheries of the devices. D-modules contain wide-decode circuitry, which provides a fast, wide-input AND function similar to that found in product term architectures (Figure 4). The D-module allows 42MX devices to perform wide-decode functions at speeds comparable to CPLDs and PAL devices. The output of the D-module has a programmable invertar for active HIGH or LOW assertion. The D-module output is hard-wired to an output pin, or it can be fed back into the array to be incorporated into other logic. Dual-Port SRAM Modules Several 42MX devices contain dual-port SRAM modules that have been optimized for synchronous or asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as 32x8 or 64x4. (Refer to the "Integrator Series Product Profile" table, on page 1, for the number of SRAM blocks within a particular device.) SRAM 7 Inputs Hard-Wire to I/O Programmable Inverter Feedback to Array Figure 4* D-Module Implementation modules can be cascaded together to form memory spaces of user -definable width and depth. A block diagram of the 42MX dual-port SRAM block is shown in Figure 5. WD[7:0] D- Latches [7:0] [5:0] RDADI5:0] Write SRAM Module Read Latches Port 32 x 8 or 64 x 4 Port WRADIS:0] (5:0) | Logic (256 Bits) Logic ea tes oe Logic REN MODE jam] ADI t_ RCLK BLKEN Bm Write 70) ogic WEN A Routing Tracks WCLK Figure 5* 42MX Dnal-Port SRAMBlock The 42MX SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRADS5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]}, and eight outputs (RD[7:0]) which are connected to segmented vertical routing tracks. The 42MX dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring fast FIFO and LIFO queues. Actels ACTgen Macro Builder provides the capability to quickly design memory functions, such as FIFOs,Integrator Series FPGAs: 40MX and 42MX Families LIFOs, and RAM arrays. In addition, unused SRAM blocks can be used to implement registers for other logic within the design. MultiPlex 1/O Modules The MultiPlex | /O modules provide the interface between the device pins and the logic array. The top of Figure 6 is a block diagram of the 42MX I/O module. A variety of user functions, determined bya library macro selection, can be implemented in the module. (Refer to the Macro Library Guide for more information.) All 42M X | 0 moduies contain a tri-state buffer, with input and output latches that can be configured for input, output, or bi-directional operation. EN Q oO From Array PAD | G/CLK* * Can be Configured as a Latch or D Flip-Flop (Using C-Module) ~ jo D To Array GiCLK*- Schematic STD NK Vv Signal x] |) | Output PCI Drive PCI Enable JL Fuse Figure 6 I/O Module The Integrator Series devices contain flexible | /O structures, where each output pin has a dedicated output-enable control. The | module can be used to latch input or output data, or both, providing a fast set-up time. In addition, the Actel Designer Series software tools can build a D-type flip-flop using a C-module to register input and output signals. To achieve 5.0V or 3.3V PCl-compliant output drives on A42M X24, A42MX36, and A42MX52 devices, a chip-wide PC| fuse is programmed. When the PCI fuse is not programmed, output drive is standard. (See the bottom portion of Figure 6.) Actels Designer Series development tools provide a design library of | /O macrofunctions that can implement alt 1/0 configurations supported by the MX FPGAs. Routing Structure The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and 1/0 modules. These routing tracks are metat interconnects that may be either of continuous length or broken into pieces cailed segments Var ying segment lengths allows the interconnect of aver 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifusas to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 7. Non-dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Vertical Routing Another set of routing tracks run vertically through the module. Vertical tracks are of thraa types: input, output, and long, and are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module, each segment in an output track is dedicated to the output of a particular module. Long segments ar uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the alray, where edge effects occur. Long vertical tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 7. Antifuse Structures An antifuse is a "normally open structure as opposed to the normally closed fuse structure used in PROMS or PALS. The use of antifuses to implement a programmable logic device results in highly-testable structures as wall as efficientSegmented Logi gic Horizontal | | f | fT ff Modules Routing Tracks Antifuses Vertical Routing Tracker Routing Structure Figure 7* Programming algorithms. The structure is highly-testable because there are no pre-existing connections; therefore, temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed and individual circuit structures to be tested, which can be done before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Clock Networks The 40MX devices have one global CLK distribution network. Two low-skew, high-fanout clock distribution networks are provided in each 42M X device. These networks are referred to as CLKO and CLKL Each network has a clock module (CLKMOD) that selects the source of the clock signal and May be driven as follows: , * Externaily from the CLKA pad * Externally from the CLKB pad * Internally from the CLKINA input * Internally from the CLKINB input The clock modules are located in the top row of | 0 modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The user controls the clock module by selecting one of two clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally-generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLKQ or CLK1 is being used. The clock input pads can also be used as normal |/Os, bypassing the clock networks. (See Figure 8.) The 42MX devices that contain SRAM modules have four additional register control resources, called quadrant clock networks (Figure 9}. Each quadrant clock provides a focal, LKB IX} CLKIN LKA [_ CLKIN Pa So ads Internal CLKMOD |__ $1 Signal PD GLKO(17} Clock Drivers t CLKO(16) P CLKO(15} 1 td Pt i tt ciKey) CLKO(1) Clock Tracks Figure 8 Clock Networks high-fanout resource to the contiguous logic modules within its quadrant of the device. Quadrant clock signals can originate from specific | /O pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Test Circuitry Both 40MX and 42M X devices provide the means to test and debug a design once it is programmed into a device. The 40MX and 42MX devices contain Actals test circuitry. Once a device has been programmed, the ActionProbe test circuitry allows the designer to probe any internal node during device operation to aid in debugging a design. In addition, 42Mx devices contain IEEE Standard 1149.1 (JTAG) Boundary Scan Test. JTAG Boundary Scan Testing (BST) Device pin spacingis decreasing with the advent of fine-pitch packages such as TQFP and BGA, and manufacturers are routinely implementing surface-mount technology with multilayer PC boards. The Joint Test Action Group (JTAG) developed !EEE Standard 1149.1 Boundary Scan Test to facilitate boar d-level testing during manufacturing. IEEE Standard 1149.1 defines a four-pin Test Access Port (TAP) interface for testing integrated circuits in a system. The 42MX family provides four JTAG BST pins: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCLK), and Test Mode Select (TMS). Devices are configured in a JTAG "chain" where BST data can be transmitted serially between devices via TDO-to-TD! interconnections. The TMS and TCLK signalsIntegrator Series FPGAs: 40MX and 42MX Families are shared among ail devices in the JTAG chain so that ali components operate in the same state. The 42M X family implements a subset of the IEEE Standard 1149.1 BST instruction in addition to a private instruction, which allows the use of Actels ActionProbe facility with JTAG BST. Refer to the IEEE Standard 1149.1 specification for detailed in formation ragar ding JTAG testing. JTAG Architecture The 42MX JTAG BST circuitry consist of a Test Access Port (TAP) controller, JTAG instruction register, a JPROBE register, a bypass register, and a boundary scan register. Figure 10 is a block diagram of the 42MX JTAG circuitry. QCLKA ar Quad Clock #- QCLKB BF Module *QCLK1IN | So $1 QCLK1 Quad Clock Module QCLK2 *QCLK2IN SO Si pre QCLKC Quad Clock Module can: QCLKD *QCLK3IN QCLK3 Si SO Quad Clock Module QCLK4 *QCLK4IN Si SO *QCLKIIN, QCLE2IN, QCLK3IN, and QCKLAINare internally-generated signals. Figure 9* Quadrant Clock Net work | JPROBE Register Boundary S Regist < oundary Scan Register SZ] TDO P| Bypass Register Control Logic } TMS ; pe TAP Controller -Y'"sttuction TCLK FQ Instruction TDI K Register Figure 10 JTAGBST Crcuitry 11(By When a device is operating in JTAG BST mode, four 1/0 pins are used for the TDI, TOO, TMS, and TCLK signals. An active reset (nTRST) pin is not supported; however, the 42MX contains power-on circuitry that resets the JTAG BST circuitry upon power-up. During normal device operation, the JTAG pins should be heid LOW to disable the JTAG circuitry. The following table summarizes the functions of the JTAG BST signals. JTAG Signal Name Function TDI Test DataIn Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. TDO Test Data Serial data output for JTAG Out instructions and test data. TMS Test Mode Serial data input for JTAG test Select mode. Data is shifted in on the rising edge of TCLK. TCLK Test Clock Clock signal to shift the JTAG data into the device. Test Mode Code Description JTAG BST Instructions JTAG BST testing within the 42MX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the thres-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signat to control the JTAG testing of the device. The JTAG test mode is determined by the bitstream entered on the TMS pin. The table in the next column describes the JTAG instructions supported by the 42M X, ActionProbe If a device has been successfully programmed and the security fuse has not been programmed, any internal logic or |/O module output can be observed in real time using the ActionProbe circuitry, PRA and/or PRB pins and Actel's Silicon Explorer diagnostic and debug tool kit. Refer to "Using the ActionProbe for System-Level Debug" application note for further information. EXTEST SAMPLE/ PRELOAD INTEST JPROBE USER INSTRUCTION HIGH Z CLAMP BYPASS 000 001 0710 o11 100 101 110 an Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Allows a snapshot of the signals at the device pins to be captured and examined during device operation. . Refer to the IEEE Standard 1149.1 specification. A private instruction allowing the user to connect Actels Micro Probe registers to the JTAG chain. Allows the user to build application-specific instructions such as RAM READ and RAM WRITE. Refer to the IEEE Standard 1149.1 specification. Refer to the IEEE Standard 1149.1 specification. Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the JTAG chain. t2Integrator Series FPGAs: 40MX and 42MX Families 5.0V Operating Conditions Mixed 5.0V/3.3V Operating Conditions Recommended Operating Conditions Param eter Commercial . Industrial Units Absoaluie Maximum Ratings 1 Temperature Oto 40 to C Range! +70 +85 Free Air Temperature Range Power Supply Symbol Parameter Limits Units Tolerance +5 +10 % Voc Voc DC Supply Voltage 0.5 to +7.0 V Veo! 4.75 to 5.25 4.5 to 5.5 V Vv; Input Voltage 0.510 Vo5 40.5 V Voca 4.75 to 5.25 4.5 to 5.5 V Vo Output Voltage 0.6 tO Vo5+0.5 V Voc 4.75 to 5.25 4.5 to 5.5 V lo VO Source/Sink +20 mA Voor* 3.14103.47 3.0t03.6 Vv Current Note: Tst Storage Temperature -65 to +150 S 1. Ambient temperature (T's) is used for commercial and Noles: industrial. 1, Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage tothe device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than Voc + 0.5Vor less than GND 0,5V, the internal protection diode will be forward-biased and can draw excessive current. Electrical Specifications 2 Operating condition for I/Oin mixed voltage mode. Com mercial Commercial -F Industrial Symbol Parameter Units Min. Max. Min. Max. Min. Max. Von! (loy = -10 mA) * 2.4 2.4 Vv (logy = 6 mA) 3.84 3.84 Vv (lon = 4 mA) 3.7 Vv Vo! (Ig, = 10 mA) * 0.5 0.5 v (lop = 6 MA) 0.33 0.33 0.40 Vv Vi 0.3 0.8 ~0.3 0.8 ~0.3 0.8 Vv Vin 2.0 Voc + 0.3 2.0 Voc + 0.3 20 Veco+0.3 V Input Transition Time ta, te 500 500 500 ns Cig VO Capacitance? 4 10 10 10 pF Standby Current, loc* (typical = 1 mA) 2.0 20.0 5.0 mA lec(p) Dynamic Veg Supply Current See Power Dissipation on page 15. Low Power Mode Standby Current, log 0.5 10.0 2.0 mA Notes: 1. Only one output tested at a time. Vop = min. Not tested, for information only. 2. 3. Includes worst-case 84-Pin CPGA package capacitance. Vggp=0V,f= 1 MHz. 4. All outputs unloaded. All inputs = V qcoor GND, typical | (= 0.5mA loc limit includes I pp and I gyduring normal operation. 13for 3.3V Operating Conditions Recommended Operating Conditions Absolufe Maximum Ratings 1 Parameter Commercial Industrial Units Free Air Temperature Range . Temperature 40 to a Range! 0 to +70 485 Cc Symbol Parameter Limits Units Power Supply Veco DC Supply Voltage -0.5 to +7.0 V Tolerance + +10 %V Vy input Voltage -0.510Voo 40.5 V Veci 3.0 to 3.6 3.0 to 3.6 Vv Vo Output Voltage -O0.51t0 Voge 40.5 Vv Voca 3.0 to 3.6 3.0 to 3.6 Vv VO Source Sink Note: lo 2 +20 mA 1. Ambient temperature (T,) is used for commercial. Current Tste Storage Temperature -65 to +150 C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage tothe device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than Voc+ 0.5Vor less than GND 0.5V, the internal protection diodes will forward-bias and can draw excessive current. Electrical Specifications Com mercial Industrial Parameter Units Min. Max. Min. Max. 1 (loy = 4 mA) 2.15 3.7 Vv Vou (Igy = ~3.2 mA) 2.4 Vv Vor (lo. =6 mA) 0.4 0.48 Vv Vit -0.3 0.8 0.3 0.8 Vv Vin 2.0 Veo +0.3 2.0 Veco + 0.3 Vv Input Transition Time tp, if 500 500 ns Cig VO Capacitance 7 10 10 pF Standby Current, loc (typical = 0.3 mA) 2.0 5.0 mA loc(p) Dynamic Vgg Supply Current See Power Dissipation on page 15. Low Power Mode Standby Current, log 0.5 2.0 mA Notes: 1. Onlyone output tested at a time. Vgo = min. Not tested, for information only. Fwy Includes worst-case 84-Pin PLOC package capacitance. V gyp= 0 V, f= 1 MHz. Typical standby current = 0.5 mA All outputs unloaded, All inputs = V_ gcor GND.Integrator Series FPGAs: 40MX and 42MX Families Package Thermal Characteristics The device junction-to-case thermal characteristic is Bj. and the junction-to-ambient air characteristic is 6. The thermal characteristics for |, are shown with two different air flow rates. Maximum junction temperature is 150 C. A sample calculation of.the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: Max. junction temp. (C) Max. commercial temp. _ 150C ~70C _ 8, (C/W) - Soecw = 2OW Bja Maximum Power Dissipation Package Type Pin Count Still Air 300 ft/min Seill Air 300 ft/min Plastic Quad Flat Pack 100 42C/W 33C/W 1.9W 2.4W Plastic Quad Flat Pack 160 34C/W 27CW 2.4W 3.0 W Plastic Quad Flat Pack 208 25CW 16.2C/W 3.2 W 4.9W Plastic Leaded Chip Carrier 44 45C/W 35C/W 1.8W 2.3 W Plastic Leaded Chip Carrier 68 38CW 29CW 2.1W 2.8 W Plastic Leaded Chip Carrier 84 37C/W 28CAW 2.2 W 2.9W Thin Plastic Quad Flat Pack 176 32C/W 25C/W 2.5W 3.2 W Very Thin Plastic Quad Flat Pack 80 43C/W 35C/W 1.9W 2.3W Very Thin Plastic Quad Flat Pack 100 438C/IW 35C/W 1.9W 2.3 W Power Quad Flat Pack 208 16.8C/W 11.4C/W 48W 7.0W Power Quad Flat Pack 240 16.1C/W 10.6CAV 5.0 W 7.5W Power Dissipation General Power Equation P = [I gcstandby + | gcactive] * Veg + Ig. * Vo_* N + lon * (Yoo ~ Vou) *M where: Icstandby is the current flowing when no inputs or outputs are changing. lcactive is the current flowing due to CMOS switching. lou loy are TTL sink /source currents. Vou. You are TTL level output voltages. N equals the number of outputs driving TTL loads to Vo). M equals the number of outputs driving TTL loads to Voy. An accurate determination of N and M is problematic because their values depend on the family type, on design details, and an the system | /0. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have smali static power components that resultin power dissipation lower than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated for commercial, worst-case conditions: lec Vec Power 2mA 9.25 V 10.5 mW The static power dissipation by TTL loads depends on the number of outputs driving HIGH or LOW, and on the DC load current. Again, this number is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving LOW, and 140 mW with all outputs driving HIGH. The actual dissipation will average somewhere in between, as | /Os switch states with time. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external |/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem pola current in the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation.Sy Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by Equation t. Power ( W) = Ceg* Voc? * F (1) where: CgQ is the equivalent capacitance expressed in picofarads (pF). Vec is power supply in volts (V). F is the switching frequency in megahertz (MHz). Equivalent capacitance is calculated by measuring| ccactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of Vee. Equivalent capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. Ceq Values for Actel FPGAs Modules (Cegy) 3.5 Input Buffers (Ceq;) 11.6 Output Buffers (Ce go} 22.0 Routed Array Clock Buffer Loads (Cegca) 3.5 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = Voc? *[(m x Ceqy * fn) woduiest (n *Ceq * fh) inputs t (Pp *(Cego + G,) * 1) outputs + 0.5*(d1* Croce * ftbroutea cca + (11 * fytdroutea crus + 0.5*(G2* Ceacr * fg2)routed cika * (To * fg2) routed _cik2 (2) where: m = Number of logic modules switching al frequency f,, n = Number of input buffers switching at frequency f, p = Number of output buffers switching at frequency f, ay = Number of clock loads on the first routed array clock G2 = ~Number of clock loads on the second routed array clock Ty = Fixed capacitance due to first routed array clock Tp = Fixed capacitance due to second routed array clock Ceom = Equivalent capacitance of logic modules in pF Cegi = Equivalent capacitance of input buffers in pF Cego = Equivalent capacitance of output buffers in pF Ceacr = Equivalent capacitance of routed array clock in pF C. = Output load capacitance in pF tm = Average logic module switching rate in MHz fa = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fg) = ~Average first routed array clock rate in MHz q2 Average second routed array clock rate in MHz Fixed Capacitance Values for Actel FPGAs (pF) "4 rg Device Type routed _Clk1 routed_Clk2 A40M X02 41.4 N/A A40MX04 68.6 N/A A40MX09 134 134 A42MX16 168 168 A42MX24 190 190 A42M X36 230 230 A42M X52 285 285 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidetines represent worst-case scenarios, these can be used to generally predict the upper limits of power dissipation. Logic Modules (m) = 80% of Combinatorial Modules Inputs Switching (n)} = #oflnputs4 Outputs Switching (p) = #Outputs/4 First Routed Array Clock Loads (44) 40% of Sequential Modules Second Routed Array Clock Loads 40% of Sequential (2) Modules It Load Capacitance (C,) = 35 pF Average Logic Module Switching = FAO Rate ( tr} Average Input SwitchingRate(f,) = Ff Average Output Switching Rate ({f)) = FAO Average First Routed Array Clock = F Rate ( fa1) Average Second Routed Array Clock = F /2 Rate ( fa) - 16Integrator Series FPGAs: 40MX and 42MX Families 40MX Timing Madel* input Delay Internal Delays Predicted Output Delay Routing _ Delays oo 1/0 Module 7 [70 Module ~] ' tinyt = 0.62 ns) tinD2 = 2.59 ns _ | MN, | a Logic Module a | ! ! L_ __ Tou osens | xX L- hor = 2.09 ns _ tap = 1.28 ns ting = 3.64 ns Po = Von he taD2= 1.80 ns tennz = 7.92 ns linpg = 5.73ns CO trp4 = 2.33 ns traps = 4.93 ns Arra Cloc toxy=455ns FO = 128 Fraax = 180 MHz * Values are shown for 40MX-3 speed devices at 5.0V worst-case commercial conditions. x 17ChE 42MX Timing Modal Input Delays Internal Delays Predicted Output Delays outing - Delays _ [ vO Module 1 tpt = [1/0 Module 47 nye 1.16 ns 2.24 nst Ko | | Xt+ [> Combinatorial ? |= ix Logic Module ' = | | ' [_ toLH = 2.70 "| D tant = 0.80 ns CCU r-sos | Q | tep = 1.55 ns trope = 1.00 ns tapa = 1.50 ns 1 = 2.50 ns _- _ G | ADS ire Module toiy =2.70 ns Sequential | | | iH = one ns | Logic Module INSU = J.0% NS - TT [tiner=140ns | | | | Combin- 3) Q D Q | atorial Logic tap. = 0.80 ns tennz = 5.40 ns | included G in tgup I [__ _ _ __ _| | ' toutH = oO ns | = = ouTsu = U.0U NS Array tsup = 0.36 ns tco = 1.37 ns tory = 4.60 ns Clocks typ = 0.00 ns LL _| x r toy = 4.51 ns FO = 256 Fraax = 245 MHz ILco = 5.67 ns (64 loads, pad-to-pad) *Values are shown for A42MXD9-2 at 5.0V worst-case commercial conditions f Input module predicted routing delay 18Integrator Series FPGAs: 40MX and 42MX Families 42MX Timing Model (Logic Functions using Quadrant Clocks)" Input Delays Internal Delays Predicted Output Delays outing __ Delays a [1/0 Module [VO Module 7] eyes 114 MS tippy 2.18 ng NK xX T L_ t Combinatorial ? T L x Module L ton = 2.84 ns D Q tro1 = 1.04 ns _->- | | a) = 1.46 ns tape = 1.42 ns tapa =2.18ns G | Decode | tiny = 0.00 ns e_ Module tinsu =0.53 ns {pop = 0.38 ns |. tinco = 1.55 ns _| i 1.78 ns 7-7 PDD = |. [vO Module loty = 2.84 ns Sequential | | Logic Module Combin- | atorial Db @ | Logic t _ | _|incuded | ENHZ = 9.80 ns in tsup > r 7G [ _| tty = 0.00 ns | lgup = 0.30ns | tgg= 1.43 ns isu = 0.53 ns tup = 0.00 ns Quadrant Clocks <> FMaAx = 163 MHz toKH = 4.35 ns** * Preliminary values are shown for A42MX36-2 at 5.0V worst-case commercial conditions ** Load-dependent | tcu= 5.50 ns 1942MX Timing Model (SRAM Function: } Seer Input Delays [vo Module _ inpy = 1.14 NS fhapy = 2.18 ns Leal | G | tinsu = 0.53 ns tinH = 0.00 ns tinco = 1.55 ns _| WD [7:0] WRAD [5:0] BLKEN WEN WCLK tapsu = 1.80 ns tapH = 0.00 ns Array twensu = 2-90 ns Clocks tBENS = 2.90 ns Predicted Routing VO Module Delays totH = 2.84 ns RD [7:0] > tao = 1.04 ns * a Xl RDAD [5:0] . REN . DQ RCLK G tapsu = 1.80 ns toui= 5.50 ns tapH = 0.00 ns itgy = 0.30 ns treNsu = 0.80 ns tity = 0.00 ns taco = 3.80 ns Fax = 151 MHz *Values are shown for Ad2MX36-2 at 5.0V worst-case commercial conditions.Integrator Series FPGAs: 40MX and 42MX Families Parameter Measurement Output Buffer Delays tot toHL em To AC test loads (shown below) 50% 50% AC Test Loads Load 1 (Used to measure propagation delay) To the output under test Load 2 (Used to measure rising/falling edges) Voc GND e e ai 35 pF Rto Veco for tprzipz, | R to GND for tpyz/tpzy = To the output under test R=1kQO tl Input Buffer Delays Module Delays PAD INvH tinyL S, A or BA50% 502) 50% 50% Y 50% 50% tet te 50% 50% tPHL tei 21IchS)/ Sequential Module Timing Characteristics Flip-Flops and Latches d D4 PRE -yY E CLK -P CLR (Positive Edge- Triggered) | to k= p! < Ss : tsup > twoxa k#>] je 1, -| Hisuente be two ki >| tena E : le iGo] Q x x }+| tas PRE, CLR ] { | twasyn Note: Drepresents all data functions involving A, B, and Sfor multiplexed flip-flops.integrator Series FPGAs: 40MX and 42MX Families Sequential Timing Characteristics (continued) Input Buffer Latches DATA IBDL CLK CLKBUF DATA x xX. G + tinsu > Ht text | CLK ~ tsuext >) Output Buffer Latches D - ie OBDLHS ~ toutsu-_a>4 <t tour omSy Decode Module Timing A-G,H OnnVOGy SRAM Timing Characteristics Write Port Read Port WRAD [5:0] RDAD [5:0] BLKEN RAM Array LEW 32x8 or 64x4 WEN (256 Bits) REN WCLK RCLK WD [7:0] AD [7:0] 24Integrator Series FPGAs: 40MX and 42MX Families Dual-Port SRAM Timing Waveforms 42MX SRAM Write Operation. tRCKHL tRCKHL WCLK j tapH WD{7:0] WRADI5.0} WENH WEN BENH BLKEN Note: Identical timing for falling edge clock. 42MX SRAM Synchronous Read Operation RCLK / \ / tRENsU tRENH REN tapsu tabH RDAD[S:0} Valid taco box RD[7:0] Old Data New Data Note: Identical timing for falling edge clock.42MX SRAM Asynchronous Read OperationType 1 (Read Address Controlled) RDAD[5:0} RD{7:0] 42MX SRAM Asynchronous Read OperationType 2 (Write Address Controlled) WEN WD7:0} WRADI5:0} BLKEN ADSU taDH WCLK RDI7:0] Old DataIntegrator Series FPGAs: 40MX and 42MX Families Precictable Perlormance: Tigh! Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The MX FPGAs deliver a tight fanout delay distribution. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect slements per path. Actals patented PLICE antifuse offers an very low resistive capacitive interconnect. The antifuses, fabricated in 0.45 micron lithography, offer nominal levels of 100 ohms resistance and 7.0 femtofarad (fF) capacitance per antifuse. The Integrator Series fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. Timing Characteristics Timing characteristics for devices fall into threa categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all Integrator Series members. Internal routing delays are device-dependent. Design dependency means actuai delays are not determined until after place and route of the user's design is complete. Delay values may then be determined by using the Designer Series utility or by per forming simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays in this data sheet apply to typical nets. The abundant routing resources in the MX architecture allows for deterministic timing using Actels Designer Series development tools which include DirectTime, a timing-driven place-and-route tool. Using DirectTime, the designer can spacify timing-critical nats and system clock frequency. Using these timing specifications, the place-and-route software optimizes the layout of the design to meet the users specifications. Long Tracks Some nats in the design use jong tracks which are spacial routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections, which increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks add approximately 3 ns to 6 ns delay, which is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating A timing derating factor of 0.45 is used to reflect best-case processing. Note that this factor is relative to the standard speed timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. Timing Derating Factor (Temperature and Voltage} Industrial Min. Max. (Commercial Specification) x 0.69 1.11 Timing Derating Factor for Designs al Typical Temperature (T .= and Voltage (5.0V} ne un 0 (Maximum Specification, Worst-Case Condition) x 0.85 Note: This derating factor applies to all routing and propagation delays. 27Sy Temperaiure and Voltage Derating Factors (Normalized ic Werst-Case Commercial, F g = 4.75V, 70C} -55 -40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 .25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 Note: 06 Junction Temperature and Voltage Derating Curves (Normalized to Worst-Case Commercial, Ty= 4.75V, 70C) 4.50 4.75 500 5.25 5.50 Yoltage () This derating factor applies to all routing and propagation delays.Integrator Series FPGAs: 40MX and 42MX Families A40MXO02 Timing Characieristics (Nomina! 5.0V Operation} (Worst-Case Commercial Conditions, V cc = 4.75V, Ty = 70C) Logic Module Propagation Delays -3 Speed 2 Speed -1' Speed Std Speed -F' Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Unite tpp; Single Module 1.24 1.43 1.63 1.90 2.66 | ns tpp2 Dual-Module Macros 2.65 3.06 3.47 4.08 5.71 ns tco Sequential Glock-to-Q 1.24 1.43 1.62 1.90 2.66 | ns leo Latch G-to-Q 1.24 1.43 1.62 1.90 2.66 | ns trs Flip-Flop (Latch) Reset-to-Q 1.24 1.43 1.62 1.90 2.66 | ns Predicted Routing Delays tro+ FO=1 Routing Delay 1.28 1.48 1.67 1.97 2.76 | ns trp2 FO=2 Routing Delay 1.80 2.08 2.35 2.77 3.88 | ns tro3 FO=3 Routing Delay 2.33 2.69 3.04 3.58 5.01 | ns taba FO=4 Routing Delay 2.85 3.29 3.72 4.38 6.13 | ns taps FO=8 Routing Delay 4.93 5.69 6.45 7.59 10.63 | ns Sequential Timing Characteristics tsup? Flip-Flop (Latch) Data Input Set-Up 3.06 3.53 4.00 4.70 6.58 ns typ? Flip-Flop (Latch) Data Input Hold 0.00 6.00 0.00 0.00 0.00 ns tsuUENA Flip-Flop (Latch) Enable Set-Up 3.06 3.53 4.00 4.70 6.58 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.25 3.75 4.25 5.00 7.00 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 3.25 3.75 4.25 5.00 7.00 ns ta Flip-Flop Clock Input Period 4.84 5.59 6.33 7.45 10.43 ns {max Flip-Flop (Latch) Clock Frequency (FO = 128) 180.90 ]* 167.50 154.10 134.00 80.40 | MHz Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2 Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. The hald time for the DFME1A macro may be greater than Ons. Lse the Designer 3.0 of later DirectTime Analyzer to check the hold time for this macro. jeiy) A4O0MXO2 Timing Characteristics (Nominal 5.0V Operation} (continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays -3 Speed 2 Speed -1' Speed Sid Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units tinyy Pad-to-Y HIGH 0.70 0.80 0.91 1.07 1.50 | ns tnye Pad-to-Y LOW 0.62 0.71 0.81 0.95 1.33 | ns Input Module Predicted Routing Delays tippy FO=1 Routing Delay 2.07 2.39 2.17 3.19 447 | ns tinp2 FO=2 Routing Delay 2.59 2.99 3.39 3.99 5.59 | ns tiro3 FO=3 Routing Delay 3.12 3.60 4.08 4.80 6.72 | os tirpa FO=4 Routing Delay 3.64 4.20 4.76 5.60 7.84 | ns tirps FO=8 Routing Delay 5.73 6.62 7.50 8.82 12.35 | ns Global Clock Network icky Input Low to HIGH FO = 16 4.55 5.25 5.95 7.00 3.80 FO = 128 4.55 5.25 .95 7.00 9.80 | ns ton Input High to LOW FO = 16 4.381 5.55 6.29 7.40 10.36 FO = 128 431 6.55 6.29 7.40 10.36 ] ns tpwu Minimum Pulse Width HIGH FO=16 | 2.24 2.58 2.92 3.44 4.82 FO = 128] 2.35 271 3.07 3.61 5.05 ns tpwL Minimum Pulse Width LOW FO=16 | 2.24 2.58 2.92 3.44 482 FO = 128] 2.35 2.71 3.07 3.61 5.05 ns texsw Maximum Skew FO = 16 0.39 0.45 0.51 0.60 0.84 FO = 128 0.53 0.62 0.70 0.82 1.15 | ns Ip Minimum Period FO=16 | 4.67 5.39 6.10 7.18 10.05 FO = 128] 4.84 5.59 6.33 7.45 10.43 ns Max Maximum Frequency FO = 16 187.60 174.79 159.85 139.00 83.40 FO = 128 180.90 167.50 154.10 134.00 80.40 | MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simmilation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 30Integrator Series FPGAs: 40MX and 42MX Families A40MX62 Timing Characieristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing - Speed -2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units TTL Output Module Timing toy Data-to-Pad HIGH 3.32 3.83 4.34 5.11 7.15 | ns toHL Data-to-Pad LOW 3.98 4.60 5.21 6.13 8.58 | ns tenzH Enable Pad Z to HIGH 3.74 4.31 4.89 5.75 8.05 | ns teNZL Enable Pad Z to LOW 4.69 5.41 6.13 7.21 10.09] ns tenHz Enable Pad HIGH to 7 7.92 9.14 10.35 12.18 17.05] ns tentz Enable Pad LOW to Z 5.86 6.77 767 9.02 12.63] ns qty Delta LOW to HIGH 0.02 0.02 0,03 0.03 0.04 | ns/pF ata Delta HIGH to LOW 0.03 0.03 0.03 0.04 0.06 |ns/pF CMOS Output Module Timing toLy . Data-to-Pad HIGH 3.93 4.54 5.14 6.05 8.47 | ns tou Data-to-Pad LOW 3.39 3.92 4.44 5.22 7.31 ns lENZH Enable Pad Z to HIGH 3.37 3.89 441 5.19 7.27 | ns tenze Enable Pad Z to LOW 4.88 5.63 6.38 7.51 10.51} ns tenyz Enable Pad HIGH to 2 7.92 9.14 10.35 12.18 17.05 | ns tENLZ Enable Pad LOW to Z 5.86 6.77 7.67 9.02 12.63] ns atu Delta LOW to HIGH 0.03 0.04 0.04 0.05 0.07 |ns/pF He Delta HIGH to LOW 0.02 6.02 0.03 0.03 0.04 |ns/pF Notes: 1. Delays based on 35 pF loading. 31ey A40MXO2 Timing Characieristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V cc = 3.0V, Ty = 70C) Logic Module Propagation Delays 3 Speed -2 Speed -1' Speed Std Speed '-F Speed [Parameter Deacription Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units tpp, Single Module 1.73 2.00 2.26 2.66 3.72 | ns tpp2 Dual-Module Macros 3.71 4.28 4.86 5.71 8.00 | ns ico Sequential Clock-to-Q 1.73 2.00 2.26 2.66 3.72 | ns loo Latch G-to-Q 1.73 2.00 2.26 2.66 3.72 | ns trs Flip-Flop (Latch) Reset-to-Q 1.73 2.00 2.26 2.66 3.72 | ns Predicted Routing Delays tro1 FO=1 Routing Delay 1.93 2.23 2.52 2.97 4.16 | ns tro2 FO=2 Routing Delay 2.66 3.07 3.47 4.09 5.72 | ns tros FO=3 Routing Delay 3.39 3.92 4.44 5.22 7.31 | ns trpa FO=4 Routing Delay 4.12 4.76 5.39 6.34 8.88 | ns taps FO=8 Routing Delay 7.05 8.14 9.22 10.85 15.19] ns Sequential Timing Characteristics tsup Flip-Flop (Latch) Data Input Set-Up 4.28 4.94 5.59 6.58 9.21 ns tip? Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 0.00 ns tgueNa Flip-Flop (Latch) Enable Set-Up 4.28 4.94 5.59 6.58 9.21 ns tHENA Flip-Flop (Latch) Enable Hald 0.00 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 4.55 5.25 5.95 7.00 9.80 ns twasyn Flip-Flop (Latch) Asynchronous Pulse Width 4.55 5.25 5.95 7.00 9.80 ns ta Flip-Flop Clock Input Period 6.78 7.82 8.87 10.43 14.60 ns fraax Flip-Flop (Latch) Clock Frequency (FO = 128) 108.54 100.50 92.46 80.40 48.24 | MHz Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Posi-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2 Setarp Limes assume fanout of 3. Further testing information can be obiained from the DirectTime Analyzer utility. 3. The hold time for the DFMELA macro may be greater than Ons. Use the Designer 3.009 later DirectTime Analyzer tocheck the hold yime for this macro, 32A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions) Integrator Series FPGAs: 40MX and 42MX Families (continued) Input Module Propagation Delays -3 Speed 2 Speed -1' Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units tnyH Pad-to-Y HIGH 0.97 1.12 1.27 1.50 2.10 | ns tnye Pad-to- Y LOW 0.86 1.00 1.13 1.33 1.86 | ns Input Module Predicted Routing Delays tro: FO=1 Routing Delay 2.90 3.35 3.80 4.47 6.25 | ns bape FO=2 Routing Delay 3.63 4.19 4.75 5.59 7.82 | ns trp FO=3 Routing Delay 4.37 5.04 5.71 6.72 9.41 | ns traps FO=4 Routing Delay 5.10 5.88 6.66 7.84 10.98] ns tinps FO=8 Routing Delay 8.03 9.26 10.50 12.35 17.29] ns Global Clock Network toKH Input LOW to HIGH FO =16 6.37 7.35 8.33 9.80 13.72 FO = 128 6.37 7.35 8.33 9.80 13.72] ns ton Input HIGH to LOW FO = 16 6.73 7.77 8.81 10.36 14.50 FO = 128 6.73 177 8.81 10.36 14.50] ns tpwH Minimum Pulse Width FO = 16 3.13 3.61 4.09 4.82 6.74 HIGH FO=128 | 3.29 3.79 4.30 5.05 7.08 ns tpw Minimum Pulse Width FO= 16 3.13 3.61 4.09 482 6.74 LOW FO= 128 | 3.29 3.79 4.30 5.05 7.08 ns toxsw Maximum Skew FO = 16 0.55 0.63 0.71 0.84 FO = 128 0.75 0.86 0.398 1.15 ns tp Minimum Period FO = 16 6.53 7.54 8.54 10.05 14.07 FO=128 | 6.78 7.82 8.87 10.43 14.60 ns {Max Maximum Frequency FO=16 112.60 104.88 95.91 83.40 50.04 FO = 128 108.54 100.50 92.46 80.40 48.24 | MHz Note 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required {o determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device pricy toshipment. 33fone A40MX02 Timing Characteristics (Nominal 3.38V Operatian) (Worst-Case Commercial Conditions) (continued) Output Module Timing -3 Speed -2 Speed ~1 Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Unite TTL Output Module Timing tory Data-to-Pad HIGH 4.65 5.36 6.08 7.15 10.02 | ns ton Data-to- Pad LOW 5.58 6.44 7.29 8.58 12.01] ns tenzH Enable Pad Z to HIGH 5.23 6.04 6.84 8.05 11.27} ns teNZL Enable Pad Z to LOW 6.56 7.57 8.58 10.09 14.13] ns tenHz Enable Pad HIGH to 7 11.08 12.79 14.49 17.05 23.87 | ns teniz Enable Pad LOW to Z 8.21 9.47 10.73 12.63 17.68] ns dtu Delta LOW to HIGH 0.03 0.03 0.04 0.04 0.06 | ns/pF GTHL Delta HIGH to LOW 0.04 0.04 0.05 0.06 0.08 | ns/pF CMOS Output Module Timing 'oLH Data-to- Pad HIGH 5.51 6.35 7.20 8.47 11.86] ns tone Data-to- Pad LOW 4.75 5.48 6.21 7.31 10.23 | ns tenzH Enable Pad Z to HIGH 4.72 5.45 6.18 7.27 10.17] ns tewzi Enable Pad Z to LOW 6.83 7.89 8.94 10.51 14.72] as lENHZ Enable Pad HIGH to 2 11.08 12.79 14.49 17.05 23.87 | ns tencz Enable Pad LOW to Z 8.21 9.47 10.73 12.63 1768] as day Delta LOW to HIGH 0.05 0.05 0.06 0.07 0.10 |ns/pF CTH Delta HIGH to LOW 0.03 0.03 0.04 0.04 0.06 | ns/pF Notes: 1. Delays based on 35 pF loading.Integrator Series FPGAs: 40MX and 42MX Families A40MX04 Timing Characteristics (Nomina! 5.0V Operation) (Worst-Case Commercial Conditions, V co = 4.75V, Ty = 70%) Logic Module Propagation Delays ~3 Speed -2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units ppt Single Module 1.24 1.43 1.62 1,90 2.66 | ns tep2 Dual-Modute Macros 2.25 3.06 3.47 4.08 5.71 | ns tco Sequential Clock-to-Q 1.24 1.43 1.62 1.90 2.66 | ns tco Latch G-to-Q 1.24 1.43 1.62 1.90 2.66 | ns trs Flip-Flop (Latch) Reset-to-Q 1.24 1.43 1.62 1.90 2.66 | ns Predicted Routing Delays trot FO=1 Routing Delay 1.17 1.59 1.80 2.12 2.97 | ns tape FO=2 Routing Delay 1.90 2.19 2.48 2.92 4.09 | ns trp3 FO=3 Routing Delay 2.42 2.80 3.17 3.73 5.22 | ns traps FO=4 Routing Delay 2.94 3.40 3.85 4.53 6.34 | ns traps FO=8 Routing Delay 5.04 5.81 6.59 7.75 10.85] ns Sequential Timing Characteristics tsup* Flip-Flop (Latch) Data Input Set-Up 3.06 3.53 4.00 4.70 6.58 ns tp? Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 0.00 ns tsuENA Flip-Flop (Latch) Enable Set-Up 3.06 3.53 4.00 4.70 6.58 ns tuENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.25 3.75 4.25 5.00 7.00 ns twasyn Flip-Flop (Latch) Asynchronous Pulse Width 3.25 3.75 4.25 5.00 7.00 ns ta Flip-Flop Clock Input Period 4.84 5.59 6.33 745 10.43 ns fMax Flip-Flop (Latch) Clock Frequency {FO = 128) . 180.90 167.00 154.10 134.00 80.40 | MHz Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-+oute timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2 Set-up times assume fanont of 3. Further testing information can be obtained from the DirectTime Analyzer utility. The hold time for the DFME1A macro may be greater than Ons. Use the Designer 30 of Jater Direct'Time Analyzer to check the hold time for this macro. 35(Sy A40MXO04 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions} (continued) Input Module Propagation Delays -3' Speed -2' Speed -1' Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units tNYH Pad-to-Y HIGH 0.70 0.80 0.91 1.07 1.50 | as tiny Pad-to-Y LOW 0.62 0.71 0.81 0.95 1.33 ns Input Module Predicted Routing Delays traps FO=1 Routing Delay 2.07 2.39 2.17 3.19 447 | ns urbe FO=2 Routing Delay 2.59 2.99 3.39 3.99 5.59 | as traps FO=3 Routing Delay 3.12 3.60 4.08 4.80 6.72 | ns haps FO=4 Routing Delay 3.64 4.20 4.76 5.60 784 | ns traps FO=8 Routing Delay 5.73 6.62 7.50 8.82 12.35 | ns Global Clock Network toxy Input LOW to HIGH FO = 16 4.58 5.29 5.99 7.05 9.87 FO = 128 4.58 5.29 5.99 7.05 9.87 | ns teoKL Input HIGH to LOW FO = 16 4.84 5.59 6.33 7.45 10.43 FO = 128 4.84 5.59 6.33 745 10.43 | ns tpwH Minimum Pulse Width HIGH FO = 16 | 2.24 2.58 2.92 3.44 4.82 FO = 128] 2.35 2.71 3.07 3.61 5.05 ns tpwL Minimum Pulse Width LOW FO=16 | 2.24 2.58 2.92 3.44 4.82 FO = 128| 2.95 2.71 3.07 3.61 5.05 ns texsw Maximum Skew FO = 16 0.39 0.45 0.51 0.60 0.84 FO = 128 0.53 0.62 0.70 0.82 1.15 | ns tp Minimum Period FO=16 | 4.69 5.39 6.10 7.18 10.05 FO=128] 4.84 5.59 6.33 7.45 10.43 ns Max Maximum Frequency FO =16 187.68 174.79 159.85 139.00 83.40 FO = 128 180.90 167.50 154.10 134.00 80.40 | MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 36Integrator Series FPGAs: 40MX and 42MX Families A40MX64 Timing Characteristics (Nominal 5.0V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing 3 Speed -2 Speed -1' Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units TTL Output Module Timing tous Data-to-Pad HIGH 3.32 3.83 4.34 5.11 7.15.7 ns toot Data-to-Pad LOW 3.98 4.60 5.21 6.13 8.58 | ns tenzH Enable Pad Z to HIGH 3.74 4.31 4.89 5.75 8.05 | ns tewze Enable Pad Z to LOW 4.69 5.41 6.13 7.21 10.09] ns tenHz Enable Pad HIGH to Z 7.92 9.14 10.35 12.18 17.05] ns teNEZ Enable Pad LOW to Z 5.86 6.77 767 9.02 12.63] ns atu Delta LOW to HIGH 0.02 0.02 0.03 0.03 0.04 [ns/pF CTH Delta HIGH to LOW 0.02 0.03 0.03 0.04 0.06 [ns/pF CMOS Output Module Timing toLH Data-to-Pad HIGH 3.93 4.54 5.14 6.05 847 | ns tou Data-to-Pad LOW 3.39 3.92 4.44 5.22 731 ns tenzH Enable Pad Z to HIGH 3.37 | 3.89 4.41 5.19 7.27 | 0s tena, Enable Pad 2 to LOW 4.88 5.63 6.38 751 10.51] ns tennz Enable Pad HIGH to Z 7.92 9.14 10.35 12.18 17.05] ns teNLz Enable Pad LOW to Z 4.98 6.77 7.67 9.02 12.63 | ns Gy Delta LOW to HIGH 0.03 0.04 0.04 0.05 0.07 |ns/pF HL Delta HIGH to LOW 0.02 0.02 0.03 0.03 0.04 |ns/pF Notes: 1. Delays based on 35 pF loading. 37Sy A40MX04 Timing Characteristics (Nominal 3.3V Operatian) cco = 3-0V, Ty = 70C) (Worst-Case Commercial Conditions, Vv Logic Module Propagation Delays -3 Speed '-2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Units tep: Single Module 1.73 2.00 2.26 2.66 3.72 | ns tppe Dual-Module Macros 3.71 4.28 4.86 5.71 8.00 | ns tco Sequential Clock-to-Q 1.73 2.00 2.26 2.66 3.72 | ns tco Latch G-to-Q 1.73 2.00 2.26 2.66 3.72 | ns tas Flip-Flop (Latch) Reset-to-Q 1.73 2.00 2.26 2.66 3.72 | ns Predicted Routing Delays taps FO=1 Routing Delay 1.93 2.23 2.52 2.97 4.16 | ns tape FO=2 Routing Delay 2.66 3.07 3.47 4.09 5.72 | ns tap3 FO=3 Routing Delay 3.39 3.92 4.44 5.22 7.31 ns tapa FO=4 Routing Delay 4.12 4.76 5.39 6.34 8.88 | ns taps FO=8 Routing Delay 7.05 8.14 9.22 10.85 15.19 | ns Sequential Timing Characteristics? tsup Flip-Flop (Latch) Data Input Set-Up 4.28 4.94 5.59 6.58 9.21 ns tup? Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 0.00 ns tsuENA Flip-Flop (Latch) Enable Set-Up 4.28 4.94 5.59 6.58 9.21 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 0.00 ns tWOLKA Flip-Flop (Latch) Clock Active Pulse Width 4.55 5.25 5.95 7.00 9.80 ns twasyn Flip-Flop (Latch) Asynchronous Pulse Width 4.55 5.25 5.95 7.00 9.80 ns ty Flip-Flop Clock Input Period 6.78 7.82 8.87 10.43 14.60 ns fax Flip-Flop (Latch) Clock Frequency ; (FO = 128) 108.54 100.50 92.46 80.40 48.24 | MHz Notes: 2, Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Postroute timing analysis or simulation is required to determine actual worst-case performance. Post+oute timing is based on actual touting delay Measurements performed on the device prior to shipment. 3. Set-up Limes assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. The hdd time for the DFME1A macro may be greater than Ons. Lse the Designer 3.0 or later DirectTime Analyzer tocheck the hold time for this macra 38A40MX04 Timing Characleristics (Nomina! 3.3V Operation) (Worst-Case Commercial Conditions). Integrator Series FPGAs: 40MX and 42MX Families (continued) Input Module Propagation Delays -3 Speed -2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. [Unite tnyH Pad-to-Y HiGH 0.97 1.12 1.27 1.50 210 | ns tnyL Pad-to-Y LOW 0.86 1.00 1.13 1.33 1.86 | ns Input Module Predicted Routing Detays taps FO=1 Routing Delay 2.90 3.35 3.80 447 6.25 | ns trp2 FO=2 Routing Delay 3.63 4.19 4.75 5.59 7.82 | ns hap FO=3 Routing Delay 4.37 5.04 5.71 6.72 9.41 | ns bapa FO=4 Routing Delay 5.10 5.88 6.66 7.84 10.98} ns tinps FO=8 Routing Delay 8.03 9.26 10.50 12.35 17.29] ns Global Clock Network toKy Input LOW to HIGH FO = 16 6.42 7.40 8.39 9.87 13.82 FO = 128 6.42 7.40 8.39 9.87 13.82 ] ns toKL Input HIGH to LOW FO = 16 6.78 7.82 8.87 10.43 14.60 FO = 128 6.78 7.82 8.87 10.43 14.60] nas tpwu Minimum Pulse Width FO = 16 3.13 3.61 4.09 4.82 6.74 HIGH FO = 128 | 3.29 3.79 4.30 5.05 7.08 ns tpw Minimum Pulse Width FO = 16 3.13 3.61 4.09 4.82 6.74 LOW FO = 128 | 3.29 3.79 4.30 5.05 7.08 ns loksw Maximum Skew FO = 16 0.55 0.63 0.71 0.84 1.18 FO = 128 0.75 0.86 0.98 1.15 1.61 ns tp Minimum Period FO = 16 6.53 7.54 8.54 10.05 14.07 FO=128 | 6.78 7.82 8.87 10.43 14.60 ns fax Maximum Frequency FO =16 112.50 104.88 95.31 83.40 50.04 FO = 128 108.54 100.50 92.46 80.40 48.24 | MHz Note 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by Oto 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or sirmlation is Tequired to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior toshipment. 39Sy A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions) (continued) Output Module Timing '-3 Speed ~2' Speed -1" Speed Std Speed -F Speed [Parameter Description Min. Max. | Min. Max. | Min. Max. | Min. Max. | Min. Max. |Unite TTL Output Module Timing tou Data-to Pad HIGH 4.65 5.37 6.08 7.15 10.02] ns ton Data-to-Pad LOW 5.58 6.44 7.29 8.58 12.01] ns tenzH Enable Pad Z to HIGH 5.23 6.04 6.84 8.05 11.27] ns tenze Enable Pad Z to LOW 6.56 7.57 8.58 10.09 14.13] ns tenHz Enable Pad HIGH to Z 11.08 12.79 14.49 17.05 23,87 | ns tenLz Enable Pad LOW to Z 8.21 9.47 10.73 12.63 17.68] ns GTi Delta LOW to HIGH 0.03 0.03 0.04 0.04 0.06 | ns/pF dqHe Delta HIGH to LOW 0.04 0.04 0.05 0.06 0.08 | ns/pF CMOS Output Module Timing tor Data-to-Pad HIGH 5.51 6.35 7.20 8.47 11.86] ns lone Data-to Pad LOW 4.75 5.48 6.21 731 10.23] ns tenzH Enable Pad Z to HIGH 4.72 5.45 6.18 7.27 10.17] ns tenze Enable Pad Z to LOW 6.83 7.89 8.94 10.51 14.72] ns tennz Enable Pad HIGH to Z 11.08 12.79 14.49 17.05 23.87 | ns lentz Enable Pad LOW to Z 8.21 9.47 10.73 12.63 17.68] ns aH Delta LOW to HIGH 0.05 0.05 0.06 0.07 0.10 |ns/pF dtu Delta HIGH to LOW 0.03 0.03 0.04 0.04 0.06 | ns/pF Notes: 1. Delays based on 35 pF loading,Integrator Series FPGAs: 40MX and 42MX Families A42MX09 Timing Characieristics (Nomina! 5.0V Operation) (Worst-Case Commercial Conditions, V co = 4.75V, Ty = 70C) : Logic Module Propagation Delays -2' Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max, Min. Max. Min. Max, Min. Max. | Units tpp; Single Module 1.33 1.50 1.77 2.48 ns too Sequential Clock-to-Q 1.43 1.62 1.91 2.67 ns tco Latch G-to-Q 1.37 1.55 1.82 2.55 ns tas Flip-Flop (Latch) Reset-to-Q 1.58 1.79 2.10 2.94 ns Predicted Routing Delays tro1 FO=1 Routing Delay 0.77 0.87 1.02 1.43 ns tap2 FO=2 Routing Delay 1.02 1.16 1.36 1.90 ns trog FO=3 Routing Delay 1.28 1.45 1.70 2.38 ns tap FO=4 Routing Delay 1.53 1.73 2.04 2.86 ns taps FO=8 Routing Delay 2.60 2.30 3.41 4.77 ns Sequential Timing Characteristica:* tsup Flip-Flop (Latch) Data Input Set-Up 0.36 0.41 0.48 0.67 ns tub Flip-Flop (Latch) Data input Hold 0.00 0.00 0.00 0.00 ns tsuUENA Flip-Flop (Latch) Enable Set-Up 0.45 0.51 0.60 0.84 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns 'WCLKA Flip-Flop (Latch) Clock Active Pulse Width |, 427 5.02 703 ns IWaSYN Flip-Flop (Latch) Asynchronous Pulse Width 4.94 5.59 6.58 94 ns ta Flip-Flop Clock Input Peried 3.89 434 5.10 7.14 ns tinH Input Buffer Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Buffer Latch Set-Up 0.30 0.40 0.40 0.60 ns touTH Output Buffer Latch Hold 0.00 0.00 0.00 0.00 ns toutsu Output Buffer Latch Set-Up 0.30 0.40 0.40 0.60 ns fax Flip-Flop (Latch) Clock Frequency 243.75 224,25 195.00 117.00 | MHz Notes: 1. For dual-module macros, use t pp: + tapi + tpn toot trot + tpn OF tpp: + tpi + typ, Whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the Smodule. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect tothe PAD and the Dinput. External setup/hold timing parameters must account for delay from an external PAD signal to the G (adds) to the internal setup (hold) time. inputs. Delay from an external PADsignal to the G input subtracts 41ofS) A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions) (continued) Input Module Propagation Delays 2 Speed 1 Speed Std Speed -F Speed [Parameter Description Min. Max. Min. Max. Min. Max. Nin. Max. | Units tinvH Pad-to-Y HIGH 1.16 1.32 1.55 2.17 ns tinYL Pad-to-Y LOW 0.90 1.02 1.20 1.68 as tNGH G to Y HIGH 1.43 1.62 1.90 2.66 ns tiNneL G to Y LOW 1.43 1.62 1.90 2.66 ns Input Module Predicted Routing Delays' tippy FO=1 Routing Delay 2.24 2.54 2.99 4.19 ns iro FO=2 Routing Delay 2.51 2.85 3.35 4.69 os tirnps FO=3 Routing Delay 2.78 3.15 3.71 5.19 ns tinpa FO=4 Routing Delay 3.05 3.46 4.07 5.70 ns tiaps FO=8 Routing Delay 4.13 4.68 5.50 7.70 ns Global Clock Network toKH Input LOW to HIGH FO =32 4.10 4.65 5.47 7.66 ns FO = 256 451 5.11 6.01 8.41 ns tok Input HIGH to LOW FO =32 3.92 444 5.22 7.31 ns FO = 256 4.30 4.87 5.73 8.02 ns tpwu Minimum Pulse Width HIGH FO =32 1.35 1.53 1.80 2.52 ns FO = 256 1.46 1.66 1.95 2.73 ns tpwe Minimum Pulse Width LOW FO = 32 1.35 1.53 1.80 2.52 ns FO = 256 1.46 1.66 1.95 2.73 ns tcKsw Maximum Skew FO =32 0.34 0.38 0.45 0.63 ns FO = 256 0.34 0.38 0.45 0.63 ns tgsuexT Input Latch External Set'Up FO =32 0.00 0.00 0.00 0.00 ns FO = 256 9.00 0.00 0.00 0.00 ns tuext Input Latch External Hold FO = 32 2.60 - 3.00 3.50 4.90 as FO = 256 2.43 3.30 3.90 5.46 ns tp Minimum Period FO =32 3.72 4.04 4.65 7.75 ns FO = 256 4.10 4.46 5.13 8.55 ns fMax Maximum Frequency FO = 32 268.75 247,25 215.00 129.00 | MHz FO = 256 243.75 224.25 195.00 117.00 | MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by Oto 3 ns. Routing delays are for typical designs across worst-case operating conditions. Post-oute timing analysis or simulation is required to determine actual worst case performance 42Integrator Series FPGAs: 40MX and 42MX Families A42MX609 Timing Characteristics (Nomina! 5.0V Operation) (Worst-Case Commercial Conditions} (continued) Output Module Timing -2 Speed -1' Speed Std Speed ~F Speed Parameter Description Min. Max. Min, Max. Min. Max. Min. Max. | Units TTL Output Module Timing toLH Datla-to-Pad HIGH 271 3.07 3.61 5.05 ns tou Data-to-Pad LOW 3.19 3.61 4.25 5.95 ns tENZH Enable Pad Z to HIGH 2.93 3.32 3.90 5.46 ns tenz- Enable Pad Z to LOW 3.24 3.67 4.32 6.05 ns teNHZ Enable Pad HIGH to Z 5.44 6.16 7.25 10.15 ns teNLZ Enable Pad LOW to Z 5.93 6.72 7.30 11.06 ns tetH G-to-Pad HIGH 4.61 5.22 6.14 8.60 ns lGHL G-to-Pad LOW 4.61 5.22 6.14 8.60 ns ksu V/O Latch Set-Up 0.54 0.61 0.72 1.01 ns tty VO Latch Hold 0.00 0.00 0.00 0.00 ns lico Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 5.78 6.55 7.70 10.78 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 8.18 9.27 10.90 15.26 ns QTtH Capacity Loading, LOW to HIGH 0.03 0.03 0.04 0.06 | ns/pF GTHL Capacity Loading, HIGH to LOW 0.04 0.04 0.05 0.07 | ns/pF CMOS Output Module Timing : toLH Data-to-Pad HIGH 2.71 3.07 3.61 5.05 as toHL Data-to-Pad LOW 3.19 3.61 4.25 5.95 ns tenzH Enable Pad Z to HIGH 2.93 3.32 3.90 5.46 ns tenz Enable Pad Z to LOW 3.24 3.67 4.32 6.05 ns teNHZ Enable Pad HIGH to Z 5.44 6.16 7.25 10.15] ns tenLz Enable Pad LOW to 2 5.93 6.72 7.30 11.06 ns totH G-to-Pad HIGH 4.61 5.22 6.14 8.60 ns toHL G+to-Pad LOW 4.61 5.22 6.14 8.60 ns tLsu /O Latch Set-Up 0.54 0.61 0.72 1.01 ns tH VO Latch Hold 0.00 0.00 0.00 0.00 ns tico VO Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 5.78 6.55 7.70 10.78 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 8.18 9.27 10.90 15.26 ns Gt1y Capacity Loading, LOW to HIGH 0.03 0.03 0.04 0.06 | ns/pF OTe Capacity Loading, HIGH to LOW 0.04 0.04 0.05 0.07 | ns/pF Notes: 1. Delays based on 35 pF leading. 43Acts A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions, V cc = 3.0V, Ty = 70C) Logic Module Propagation Delays -2' Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units lept Single Module 1.80 2.13 2.50 3.47 ns tco Sequential Clock-to-Q 2.00 2.30 2.70 3.76 ns tco Latch G-to-Q 1.88 2.13 2.50 3.50 ns tras Flip-Flop (Latch) Reset-to-Q 2.18 247 2.90 . 4.06 ns Predicted Routing Delays tapi FO=1 Routing Delay 1.10 1.20 1.40 2.00 ns tape FO=2 Routing Delay 1.40 1.60 1.90 2.67 ns tap3 FO=3 Routing Delay 1.80 2.00 2.40 3.33 ns taps FO=4 Routing Delay 2.10 2.40 2.90 4.00 ns taps FO=8 Routing Delay 3.60 4.10 4.80 6.68 ns Sequential Timing Characteristics * tsup Flip-Flop (Latch) Data input Set-Up 0.50 0.57 0.67 0.94 ns tub Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tsuENA Flip-Flop (Latch) Enable Set-Up 0.63 0.71 0.84 1.18 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 as 'WCLKA Flip-Flop (Latch) Clock Active Pulse Width | , 5.97 7.03 9.84 as 'wasyn Flip-Flop (Latch) Asynchronous Pulse Width 691 7.383 921 12.90 ns ta Flip-Flop Clock Input Period 5.60 6.20 7.10 9.94 ns tiny Input Buffer Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Buffer Latch Set-Up 0.30 0.34 0.40 0.56 ns touTH Output Buffer Latch Hold 0.00 0.00 0.00 0.00 ns touTsu Output Buffer Latch Set-Up 0.30 0.34 0.40 0.56 ns feaax Flip-Flop (Latch) Clock Frequency 146.30 134.60 117.00 70.20 | MHz Notes: 1. For dual-module macros, use t pp; + trot+ tppn- fgo+ tro + pon OF tppy+ trpy + tgup. whichever is appropriate. 2 Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post+oute timing analysis or simulation is required to determine actual worst-case performance. Post-oute timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the Smodule. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PADand the Dinput. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the Ginput subtracts (adds) tothe internal setup (hold) time.Integrator Series FPGAs: 40MX and 42MX Families A42MX089 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commercial Conditions) (continued) Input Module Propagation Delays -2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min, Max. Min. Max. | Units tay Pad-to-Y HIGH 1.63 1.84 2.17 3.04 ns tiNYL Pad-to-Y LOW 1.30 1.40 1.70 2.40 ns tINGH G to Y HIGH 2.00 2.30 2.70 3.72 | ns tiNGL Gto Y LOW 2.00 2.30 2.70 3.72 ns Input Module Predicted Routing Delays tinp1 FO=1 Routing Delay 3.15 3.57 4.20 5.86 ns tinp2 FO=2 Routing Delay 3.50 4.00 4.70 6.57 ns tino FO=3 Routing Delay 3.90 4.40 5.20 7.27 ns tira FO=4 Routing Delay 4.30 4.85 5.70 7.98 ns tinps FO=8 Routing Delay 5.80 6.55 7.70 10.78 | ns Global Clock Network toKH Input LOW to HIGH FO =32 6.80 6.55 7.70 10.78 | ns FO = 256 6.30 7.14 8.40 11.78 | ns tox Input HIGH to LOW FO =32 5.50 6.20 7.30 10.23 | os FO = 256 6.00 6.80 8.00 11.23 ns tpwu Minimum Pulse Width HIGH FO =32 1.89 2.14 2.52 3.53 ns FO = 256 2.05 2.32 2.73 3.82 ns tow. Minimum Pulse Width LOW FO =32 1.89 2.14 2.52 3.53 ns FO = 256 2.05 2.32 2.73 3.82 ns toxsw Maximum Skew FO =32 0.47 0.54 0.63 0.88 ns FO = 256 0.47 0.54 0.63 0.88 ns tsuEXT Input Latch Extemal Set-Up FO = 32 0.00 0.00 0.00 0.00 ns FO = 256 0.00 0.00 0.00 0.00 ns tyexT Input Latch Extemal Hold FO =32 3.70 4.20 4.90 6.86 ns - FO = 256 4.10 4.60 5.50 7.64 ns tp Minimum Period FO =32 6.20 6.74 7.75 12.90 ns FO = 256 6.80 7.43 8.54 14.20 ns imax Maximum Frequency FO = 32 161.30 148.40 129.00 77.40 | MHz FO = 256 146.30 134.60 117.00 70.20 | MHz Note: 1, These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 3 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst case performance 45By A42MX09 Timing Characteristics (Nominal 3.3V Operation) (continued) (Worst-Case Commercial Conditions) Output Module Timing -2 Speed -1' Speed Std Speed -F Speed [Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. [Units TTL Output Module Timing toty Data-to-Pad HIGH 3.79 4.30 5.05 7.08 ns tout Data-to-Pad LOW 4.46 5.06 5.95 8.33 ns tENZH Enable Pad 2 to HIGH 4.10 4.64 5.46 7.64 ns tena Enable Pad 7 to LOW 454 5.14 6.05 8.47 ns tENHZ Enable Pad HIGH to Z 7.61 8.63 10.15 14.21 | ns tentz Enable Pad LOW to Z 8.30 9.40 11.06 15.48 ns tery G-to-Pad HIGH 6.45 7.31 8.60 12.03 | ns tout G-to-Pad LOW 6.45 7.31 8.60 12.03 | ns tisu V/O Latch Set-Up 0.76 0.86 1.01 1.41 ns tun VO Latch Hold 0.00 0.00 0.00 0.00 ns tico /O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 9.70 10.90 42.90 18.03 ns taco Array Clock-to-Out (Pad-to- Pad), 64 Clock Loading 13.50 15.40 18.10 25.30 ns dtu Capacity Loading, LOW to HIGH 0.00 0.00 0.10 0.008 | ns/pF OTH Capacity Loading, HIGH to LOW 0.10 0.10 0.10 0.100 | ns/pF CMOS Output Module Timing! toy Data-to-Pad HIGH 3.80 5.45 644 8.98 | ns ton Data-to-Pad LOW 4.50 4.22 4.97 6.96 ns tenzH Enable Pad 2 to HIGH 4.10 4.64 5.46 7.64 ns teNazL Enable Pad Z to LOW 4.54 5.14 6.05 8.47 ns tenHz Enable Pad HIGH to Z 7.61 8.63 10.15 14.21 | ns tentz Enable Pad LOW to Z 8.36 9.40 11.06 15.48 | ns tory G-to-Pad HIGH 6.45 7.31 8.60 12.03 | ns lent G-to-Pad LOW 6.45 7.34 8.60 12.03 ns tLsu V/O Latch Set-Up 0.76 0.86 1.01 1.41 ns tly VO Latch Hold 0.00 0.00 0.00 0.00 ns tico VO Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 9.70 10.90 12.90 18.03 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 13.50 15.40 18.10 25.30 ns 71H Capacity Loading, LOW to HIGH 0.00 0.00 0.10 0.08 | ns/pF OTH Capacity Loading, HiGH to LOW 0.10 0.10 0.10 0.10 | ns/pF Notes: 1. Delays based on 35 pF loading.A42MX16 Timing Characieristics (Nominal 5.0V Operation) Integrator Series FPGAs : 40MX and 42MX Families (Worst-Case Cammercial Conditions, V co = 4-75V, Ty = 70C) Logic Module Propagation Delays -2 Speed -1' Speed Std Speed -F' Speed Parameter Description Nin. Max. Min. Max. Min. Max. Min. Max. | Unite tps Single Module 4.52 1.73 2.03 2.84 ns tco Sequential Clock-lo-Q 1.60 1.81 2.13 2.98 ns tao Latch G-to-Q 1.52 1.73 2.03 2.84 ns tas Flip-Flop (Latch) Reset-to-Q 1.74 1.97 2.32 3.26 ns Predicted Routing Delays trp1 FO=1 Routing Delay 0.86 0.98 V.15 1.61 ns tape FO=2 Routing Delay 1.15 1.30 1.53 2.14 ns taps FO=3 Routing Delay 1.43 1.62 1.91 2.67 ns taba FO=4 Routing Delay 1.72 1.95 2.29 3.21 ns traps FO=8 Routing Delay 2.86 3.24 3.84 5.33 ns Sequential Timing Ch aracteristica* fsup Flip-Flop (Latch) Data Input Set-Up 0.36 0.41 0.48 0.67 ns tub Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns ISuUENA Flip-Flop (Latch) Enable Set-Up 0.75 0.85 1.00 1.40 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns 'WCLKA Flip-Flop (Latch) Clock Active Pulse Width | 7. 428 5.04 706 ns 'WaSYN Flip-Flop (Latch) Asynchronous Pulse Width 4.95 5.61 6.60 924 ns ta Flip-Flop Clock Input Period 7.56 8.57 10.08 14.11 os tiny Input Buffer Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Buffer Latch Set-Up 0.54 0.61 0.72 1.01 ns touTH Output Buffer Latch Hold 0.00 0.00 0.00 0.00 ns touTsu Output Buffer Latch Set-Up 0.54 0.61 0.72 1.01 ns {MAX Flip-Flop (Latch) Clock Frequency 195.00 179.40 156.00 93.60 | MHz Notes: 1. For dual-module macros, use t pp + trp + tppp toot tapi + tpn OF tppy + troy + tsup; point and position whichever is appropriate. ? 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect tothe PADand the Dinput. External setup/hold timing parameters must account for delay from an external PAD signal to the Ginputs. Delay from an external PAD signal tothe Ginput subtracts (adds) to the internal setup (hold) time. 47(Sy A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions) (continued) Input Module Propagation Delays -2 Speed -1" Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units tinyy Pad-to-Y HIGH 1.17 1.33 1.56 2.18 ns tnyL Pad-to-Y LOW ~ 0.90 1.02 1.20 1.68 ns TINGL G to YLOW 1.56 1.77 2.08 2.91 ns Input Module Predicted Routing Delays ties FO=1 Routing Delay 2.03 2.30 2.71 3.79 ns tigpe FO=2 Routing Delay 2.32 2.63 3.09 4.33 ns tiaps FO=3 Routing Delay 2.60 2.95 3.47 4.86 ns tirnpa FO=4 Routing Delay 2.89 3.27 3.85 5.39 ns tiRDs FO=8 Routing Delay 4.03 4.56 5.37 7.52 ns Global Clock Network toKH Input LOW to HIGH FO = 32 4.50 5.10 6,00 8.40 ns FO = 384 5.25 5.95 7.00 9.80 ns teKL Input HIGH to LOW FO = 32 4.20 4.76 5.60 7.84 ns FO = 384 4.95 5.61 6.60 9.24 ns tpwH Minimum Pulse Width HIGH FO = 32 3.53 4.00 4.70 6.58 ns FO = 384 4.05 4.59 5.40 7.56 ns tpwL Minimum Pulse Width LOW FO = 32 3.53 4.00 4.70 6.58 ns FO = 384 4.05 4.59 5.40 7.56 ns tcxsw Maximum Skew FO = 32 0.38 0.43 0.50 0.70 ns FO = 384 1.73 1.96 2.30 3.22 ns lguexT Input Latch External Set-Up FO =32 0.00 0.00 0.00 0.00 ns FO = 384 0.00 0.00 0.00 0.00 ns tuext Input Latch External Hold FO = 32 * 3.08 5.49 4.10 5.74 ns FO = 384 3.53 4.00 4.70 6.58 ns tp Minimum Period FO = 32 4.65 5.06 5.81 9.69 ns FO = 384 5.12 5.57 6.41 10.68 ns fax Maximum Frequency FO = 32 215.00 197.80 172.00 103.20 | MHz FO = 384 195.00 179.40 156.00 93.60 | MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0to4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.Integrator Series FPGAs: 40MX and 42MX Families A42MX16 Timing Characieristics (Nomina! 5.0V Operation) (Worst-Case Commercial Conditions) (continued) Output Module Timing -2' Speed ~1' Speed Std Speed '-F Speed Parameter Description Min. Max. Min. Max. Min. Max. | Min. Max. | Units TTL Output Module Timing tory Data-to-Pad HIGH 2.79 3.16 3.72 5.21 ns toHL Data-to-Pad LOW 3.27 3.719 4.36 6.10 ns teNzH Enable Pad Z to HIGH 3.00 3.40 4.00 5.60 ns tenzL Enable Pad Z to LOW 3.32 3.76 4.42 6.19 ns tENHZ Enable Pad HIGH to Z 6.02 6.82 8.02 11.23 ns tenLz Enable Pad LOW to Z 5.57 6.31 7.42 10.39 ns toy G-to- Pad HIGH 5.63 6.38 7.51 10.51 ns tcHL G-to Pad LOW 5.63 6.38 751 10.51 ns ico VO Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 6.28 7.12 8.38 11.90 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 8.93 10.12 11.90 16.66 ns Gty Capacilive Loading, LOW to HIGH 0.03 0.03 0.04 0.06 | ns/pF GH Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.07 | ns/pF CMOS Output Module Timing toLH Data-to-Pad HIGH 3.56 4.03 4.74 6.64 ns tpHL Data-to-Pad LOW 2.73 3.09 3.64 5.10 ns teNZH Enable Pad Z to HIGH 3.00 3.40 4.00 5.60 ns tenzi Enable Pad 7 to LOW 3.32 3.76 442 6.19 ns tenyz Enable Pad HIGH to Z 6.02 6.82 8.02 11.23 ns teNLZ Enable Pad LOW to Z 5.57 6.31 742 10.39 ns totH G-to Pad HIGH 5.63 6.38 7.51 10.51 ns toHL G-to Pad LOW 5.63 6.38 7.51 10.51 ns tico VO Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 6.28 712 8.38 11.90 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 8.93 10.12 41.90 16.66 ns dtuy Capacitive Loading, LOW to HIGH 0.03 0.03 0.04 0.06 | ns/pF qty Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.07 | ns/pF Notes: 1. Delays based on 35 pF loading. 49(Sy) A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Worst-Case Commetcial Conditions, V co = 3-0V, Ty = 70C) Logic Module Propagation Delays 2 Speed -1' Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max, Min. Max. | Units tpp: Single Module 2.13 2.42 2.84 3.98 as tco Sequential Clock-to-Q 2.24 2.53 2.98 417 ns tco Latch G-lo-Q 2.13 2.42 2.84 3.98 ns tas Flip-Flop (Latch) Reset-to-Q 2.44 2.76 3.25 4.55 ns Predicted Routing Delays troy FO=1 Routing Delay 1.21 1.37 1.61 2.25 ns tape FO=2 Routing Delay 1.61 1.82 2.44 3.00 ns tans FO=3 Routing Delay 2.01 2.27 2.67 3.74 ns taps FO=4 Routing Delay 2.40 2.73 3.21 4.49 ns taps FO=8 Routing Delay 4.00 4.53 5.33 747 ns Sequential Timing Characteristica * tsup Flip-Flop (Latch) Data Input Set-Up 0.50 0.57 0.67 0.94 ns typ Flip-Flop (Latch) Data Input Hold 0.00 0.00 0.00 0.00 ns tsueENA Flip-Flop (Latch) Enable Set-Up 1.05 1.19 1.40 1.96 ns tHENA Flip- Hop (Latch) Enable Hold 0.00 9,00 0.00 0.00 ns 'wouKa Flip-Flop (Latch) Glock Active Pulse Width | 54 6.00 706 oss ne 'wasyn Flip-Flop (Latch) Asynchronous Pulse Width], 94 7.85 9.24 12.94 ns ta Flip-Flop Clock Input Period 10.58 12.00 14.11 19.76 ns tiny Input Buffer Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Buffer Latch Set-Up 0.76 0.86 1.01 1.41 ns touTH Output Buffer Latch Hold 0.00 0.00 0.00 0.00 ns toutsu Output Buffer Latch Set-Up 0.76 0.86 1.01 1.44 ns fax Flip-Flop (Latch) Clock . Frequency 117.00 107.64 93.60 56.16 | MHz Notes: 1, For dual-module macros use t pp) + tgp, + tppn toot tro + tpn OT tppr + tapi + tsup, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the Smodule. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4, Set-up and hold timing parameters for the input buffer latch are defined with respect to the PADand the Dinput. External setup/hold timing parameters must account for delay from an external PADsignal to the G inputs. Delay from an external PAD signal to the Ginput subtracts (adds) tothe internal setup (hold) time.A42MX16 Timing Characieristics (Nomina (Worst-Case Commercial Conditions) Integrator Series FPGAs: 40MX and 42MX Families 14 i 3.3V Operation) (continued) input Module Propagation Delays ~2' Speed ~1 Speed Std' Speed -F Speed Parameter Description Min. Max, Min. Max. Min. Max. Min. Max. | Units tinyH Pad-to-Y HIGH 1.64 1.86 2.18 3.06 ns tinye Pad-to-Y LOW 1.26 1.43 1.68 2.35 as tineH Gto Y HIGH 2.18 2.48 2.91 4.08 ns tiNGL Gto Y LOW 2.18 2.48 2.91 4.08 ns Input Module Predicted Routing Delays tieps FO=1 Routing Delay 2.85 3.22 3.79 5.31 ns tinpe FO=2 Routing Delay 3.24 3.68 4.33 6.06 ns taps FO=3 Routing Delay 3.64 4.13 4.86 6.80 ns traps FO=4 Routing Delay 4.04 4.58 5.39 7.55 ns tiros FO=8 Routing Delay 5.64 6.39 7.52 10.53 ns Global Clock Network tcKH Input LOW to HIGH FO = 32 6.30 7.14 8.40 11.76] ns FO = 384 7.35 8.33 9.80 13.72 ns teKL Input HIGH to LOW FO = 32 5.88 6.66 7.84 10.98 ns FO = 384 6.93 7.85 9.24 12.94 ns tpwH Minimum Pulse Width HIGH = FO = 32 6.30 7.14 8.40 11.76 ns FO = 384 7.35 8.33 9.80 13.72 ns tow Minimum Pulse Width LOW FO=32 5.88 6.66 7.84 10.98 ns FO = 384 6.93 7.85 9.24 12.94 ns tcxsw Maximum Skew FO =32 0.53 0.60 0.70 0.98 ns FO = 984 2.42 2.74 3.22 4.51 ns tguext Input Latch External Set-Up FO = 32 0.00 0.00 0.00 0.00 ns FO = 384 0.00 0.00 0.00 0.00 ns tuexT Input Latch External Hold FO =32 4.31 4.88 5.74 8.04 ns FO = 384 4.94 5.59 6.58 9.21 ns tp Minimum Period FO =32 7.75 8.43 9.71 16.15 ns FO = 384 8.55 9.29 10.68 17.81 ns fax Maximum Frequency FO = 32 129.00 118.68 103.20 61.92 | MHz FO = 384 117.00 107.64 93.60 56.16 | MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by Oto 4. ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simnlation is Tequired to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 51(Sy A42MX16 Timing Characteristics (Nominal 3.3V Operation) - (Worst-Case Commercial Conditions) (continued) Output Module Timing -2' Speed -1' Speed Std Speed ~F' Speed Parameter Description Min. Max. Min. Max. Min, Max. Min. Max. | Units TTL Output Module Timing! torr Data-to-Pad HIGH 3.91 4.43 5.21 7.29 ns tou Data-to-Pad LOW 4.58 5.19 6.10 8.55 ns tenzH Enable Pad Z to HIGH 4.20 4.76 5.60 7.84 ns tenzy Enable Pad 2 toLOW 4.64 5.26 6.19 8.66 ns feNHZ Enable Pad HIGH to Z 8.42 - 9.54 11.23 15.72] > os tentz Enable Pad LOW to Z 7.79 8.83 10.39 14.54 ns tony G-to-Pad HIGH 7.89 8.94 10.51 14.72 ns tout G-to-Pad LOW 7.89 8.94 10.51 14.72] ns tico VO Latch Clock-to-Out (Pad-to-Pad), 8.93 64 Clock Loading 10.12 11.90 16.66 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 12.50 14.16 16.66 23.32 | ns Oty Capacitive Loading, LOW to HIGH 0.04 0.05 0.06 0.08 | ns/pF GTHL Capacitive Loading, HIGH to LOW 0.05 0.06 0.07 0.10 | ns/pF CMOS Output Module Timing loa Data-to-Pad HIGH 4.98 5.64 6.64 9.29 ns tou Data-to-Pad LOW 3.82 4.33 5.10 7.13 ns tenzH Enable Pad 2 to HIGH 4.20 4.76 5.60 7.84 ns tenze Enable Pad 7 to LOW 4.64 5.26 6.19 8.66 ns tennz Enable Pad HIGH to Z 8.42 9.54 11.23 15.72 ns tenLz Enable Pad LOW to Z 7.79 8.83 10.39 14.54 ns tory G-to-Pad HIGH 7.89 8.94 - 10.51 14.72 ns teHL G-to-Pad LOW 7.89 8.94 10.51 14.72] ns tico /O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading 8.93 10.12 11.90 16.66 ns taco Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading 12.50 14.16 16.66 23.32 | ns din Capacitive Loading, LOW to HIGH 0.04 0.05 0.06 0.08 | ns/pF OTH Capacitive Loading, HIGH to LOW 0.05 0.06 0.07 0.10 | ns/pF Notes: 1. Delays based on 35 pF loading.Integrator Series FPGAs: 40MX and 42MX Families A42MX24 Timing Characieristics (Nomina! 5.0V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays -2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. Min, Max. Min. Max. Min. Max. | Units Combinatorial Functions tpp Intemal Array Module Delay 1.31 1.49 1.75 2.45 ns tppp Intemat Decode Module Delay 1.59 1.80 2.12 2.97 ns Predicted Routing Delays trp. FO=1 Routing Delay 0.89 1.01 1.19 1.67 | os tap2 FO=2 Routing Delay 1.15 1.30 1.53 2.14 ns tos FO=3 Routing Delay 1.40 1.59 1.87 2.62 | ns trp4 FO=4 Routing Delay 1.66 1.88 2.21 3.03 ns traps FO=8 Routing Delay 2.67 3.03 3.56 4.98 ns Sequential Timing Characteristics * tco Flip-Flop Clock-to-Output 1.43 1.62 1.90 2.66 ns tao Latch Gate-to-Output 1.31 1.49 1.75 2.45 ns tsu Flip-Flop (Latch) Set-Up Time 0.35 0.40 0.47 0.66 ns ty Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tro Flip-Flop (Latch) Reset-to-Output 1.55 1.76 2.07 2.90 ns TguENA Flip-Flop (Latch) Enable Set-Up 0.45 0.51 0.60 0.84 ns THENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns LWOLKA Flip-Flop (Latch) Clock Active Pulse Width 3.68 4.17 4.91 6.87 ns WasYN Flip-Flop (Latch) Asynchronous Pulse Width 4.89 547 6.44 9.02 ns Notes: 1. For dualmodule macros, use t pp + tao + tppa> toot tapi + tppp > Of tppy + tap; + typ, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-upand hold timing parameters for the Input Buffer Latch are defined with respect tothe PADand the Dinput. External setup/hold timing parameters must account for delay from an external PADsignal to the Ginputs. Delay from an external PAD signal tothe G input subtracts (adds) to the internal setup (hold) time.ICTS A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case Commercial Conditions) (continued) Preliminary Information Input Module Propagation Delays -2? Speed -1' Speed Std Speed ~F Speed Parameter Description Nin. Max. Min. Max. Min. Max. Min. Max. | Units tinpy Input Data Pad-to-Y 1.14 1.29 1.52 2.13 ns tinco Input Latch Gate-to-Output 1.39 1.57 1.85 2.59 ns tw Input Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Latch Set-Up 0.53 0.60 0.70 0.98 ns tiLa Latch Active Pulse Width 5.18 5.87 6.90 9.66 ns Input Module Predicted Routing Delays tino FO=1 Routing Delay 2.03 2.30 271 3.79 ns tinpe FO=2 Routing Delay 2.29 2.59 3.05 4.27 ns bRps FO=3 Routing Delay 2.54 2.88 3.39 4.75 ns tinpa FO=4 Routing Delay 2.80 3.17 3.73 5.22 ns tirnps FO=8 Routing Delay 3.81 4.32 5.08 7.01 ns Global Clack Network toKH Input LOW to HIGH FO=32 4.35 4.93 5.80 8.12 ns FO=486 5.03 5.70 6.70 9.38 ns toKL Input HIGH to LOW FO=32 4.05 4.59 5.40 7.56 ns FO=486 4.73 5.36 6.30 8.82 ns tpwH Minimum Pulse Width HIGH FO=32 2.40 2.72 3.20 4.48 ns FO=486 2.63 2.98 3.50 4.90 ns tpwL Minimum Pulse Width LOW FO=32 2.40 2.72 3.20 4.48 ns FO=486 2.63 2.98 3.50 4.90 ns tcxsw Maximum Skew FO=32 0.60 0.68 0.80 1.12 ns FO=486 0.60 0.68 0.80 12 ns tsuext Input Latch External Set-Up FO=32 0.00 0.00 0.00 0.00 ns FO=486 0.00 0.00 0.00 0.00 ns tHexT Input Latch External Hold FO=32 3.08 3.49 4.10 5.74 ns FO=486 3.68 4.17 4.90 6.86 ns fp Minimum Period (1/hyax) FO=32 5.23 5.68 6.50 10.89 ns FO=486 5.71 6.21 7.14 11.90 ns fax Maximum Datapath Frequency FO=32 191.25 175.95 153.00 91.80 | MHz FO=486 175.00 161.00 140.00 84.00 | MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.Integrator Series FPGAs: 40MX and 42MX Families A42MX24 Timing Characteristics (Worst-Case Commercial Conditions) (Nomina! 5.0V Operation) (continued) Preliminary Information Output Module Timing -2 Speed -1' Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units TTL Output Module Timing foLH Data-to-Pad HIGH 2.70 3.06 3.60 5.04 ns toHL Data-to-Pad LOW 3.15 3.57 4.20 5.88 ns teNZH Enable Pad Z to HIGH 2.82 3.20 3.76 5.26 ns tenzL Enable Pad Z to LOW 3.13 3.54 417 5.84 ns tenyz Enable Pad HIGH to Z 5.72 6.48 7.62 10.67 ns tenLz Enable Pad LOW to Z 5.33 6.04 7.10 9.94 ns t6LH G-to- Pad HIGH 5.42 6.15 7.23 10.12 ns tcGHL G-to- Pad LOW 5.42 6.15 7.23 10.12 | ns tLsu VO Latch Output Set-Up 0.53 0.60 0.70 0.98 ns ty VO Latch Output Hold 0.00 0.00 0.00 0.00 ns ico VO Latch Clock-to-Out (Pad-to-Pad) 32 I/O 6.08 6.89 8.10 11.34 ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32 VO 11.78 13.35 15.70 21.98 ns Oty Capacitive Loading, LOW to HIGH 0.04 0.04 0.05 0.07 | ns/pF atu. Capacitive Loading, HIGH to LOW 0.03 0.03 0.04 0.06 | ns/pF CMOS Output Module Timing loLH Data-to Pad HIGH 3.45 3.91 4.60 6.44 ns loHL Data-to-Pad LOW 2.61 2.96 3.48 4.87 ns tenzH Enable Pad 2 to HIGH 2.82 3.20 3.76 5.26 ns tenzL Enable Pad 2 to LOW 3.13 3.54 4.17 5.84 ns tenHz Enable Pad HIGH to Z 5.72 6.48 7.62 10.67 ns teNLZ Enable Pad LOW to Z 5.33 6.04 7.10 9.94 ns teLH G-to Pad HIGH 5.42 6.15 7.23 10.12 ns tou G-to Pad LOW 5.42 6.15 7.23 10.12 | ns isu VO Latch Set-Up 0.53 0.60 0.70 0.98 ns thy VO Latch Hold 0.00 0.00 0.00 0.00 ns ttco VO Latch Clock-to-Out (Pad-to- Pad) 32 /O 6.08 6.89 8.10 11.34 ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32/0 11.78 13.35 15.70 21.98 ns qty Capacitive Loading, LOW to HIGH 0.04 0.04 0.05 0.07 | ns/pF qty Capacitive Loading, HIGH to LOW 0.03 0.03 0.04 0.06 | ns/pF Notes: 1. Delays based on 35 pF loading.(ey A42MX24 Timing Characteristics (Nominal 3.3V Operation} (Worst-Case Commercial Conditions) Preliminary Inform ation Logie Module Propagation Delays -2 Speed -1" Speed Std Speed -F Speed Parameter Description Min. Max. Min, Max. Min. Max. Min. Max. [Units Combinatorial Functions tpp Internal Array Module Delay 1.84 2.08 2.45 3.43 ns tepp Internal Decode Module Delay 2.23 2.52 297 4.16 ns |Predicted Routing Delays tro+ FO=1 Routing Delay 1.25 1.42 1.67 2.33 ns trp2 FO=2 Routing Delay 1.61 1.82 2.14 3.00 ns taps FO=3 Routing Delay 1.96 2.23 2.62 3.67 ns trp FO=4 Routing Delay 2.32 263 3.09 4.33 ns irps FO=8 Routing Delay 3.74 4.24 4.98 6.98 ns Sequential Timing Characteristics * tco Flip-Flop Clock-to- Output 2.00 2.26 2.66 3.72 ns tco Latch Gate-to-Output 1.84 2.08 2.45 3.43 ns tsu Flip-Flop (Latch) Set-Up Time 0.49 0.56 0.66 0.92 ns ty Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tro Flip-Flop (Latch) Reset-to-Output 2.17 2.46 ; 2.90 4.06 ns tgUENA Flip-Flop (Latch) Enable Set-Up 0.63 0.71 0.84 1.18 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCoLKA Flip-Flop (Latch) Clock Active Pulse Width 5.16 5.84 6.87 9.62 ns 'wasyn Flip-Flop (Latch) Asynchronous Pulse Width 676 766 9.02 12.62 ns Notes: 1. For dual-module macros, use t pp; + tap + tpon too + tro + tpn OF tppy + tap, + tgyyp, Whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timin gis based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PADand the Dinput. External setup/hold timing parameters must account for delay from an external PAD signal tothe Gin (adds) tothe internal setup (hold) time. puts. Delay from an external PAD signal to the Ginput subtractsIntegrator Series FPGAs: 40MX and 42MX Families A42MX24 Timing Characteristics (Nomina! 3.3V Operation) (Worst-Case Commercial Conditions) (continued) Preliminary Information Input Module Propagation Delays -2 Speed ~1' Speed Std Speed -F Speed Parameter Description Nin. Max. Min. Max. Min. Max. Min. Max. | Units tNPY Input Data Pad-to-Y 1.60 1.81 2.13 2.98 As tinco Input Latch Gate-to-Output 1.94 2.20 2.59 3.63 ns tiny Input Latch Hold 0.00 0.00 0.00 0.00 ns tinsu input Latch Set-Up 0.74 0.83 0.38 1.37 ns tiLA Latch Active Pulse Width 7.25 8.21 9.66 13.52 ns Input Module Predicted Routing Delays trD1 FO=1 Routing Delay 2.85 3.22 3.79 5.31 ns tape FO=2 Routing Delay 3.20 3.63 4.27 5.98 ns tirnps FO=3 Routing Delay 3.56 4.03 475 6.64 ns tirnpa FO=4 Routing Delay 3.92 4.44 5.22 7.31 ns tinos FO=8 Routing Delay 5.33 6.05 711 9.96 ns Global Clock Network toKH Input LOW to HIGH FO=32 6.09 6.90 8.12 11.37 | ns FO=486 7.04 7.97 9.38 13.13 As teKL Input HIGH to LOW FO=32 5.67 6.43 7.56 10.58 | ns FO=486 6.62 7.50 8.82 12.35 ns tpwH Minimum Pulse Width HIGH FO=32 3.36 3.81 448 6.27 ns FO=486 | 3.68 417 4.30 6.86 ns tpwe Minimum Pulse Width LOW FO=32 3.96 3.81 448 6.27 os FO=486 | 3.68 4.17 4.90 6.86 ns toxsw Maximum Skew FO=32 0.84 0.95 1.12 1.57 ns FO=486 0.84 0.95 4.12 1.57 ns tsuEXT Input Latch Extemal Set-Up FO=32 9.00 0.00 0.00 0.00 ns FO=486 | 0.00 0.00 0.00 0.00 ns text Input Latch Extemal Hold FO=32 4.31 4.88 5.74 8.04 ns FO=486 | 5.15 5.83 6.86 9.60 ns tp Minimum Period (1/fyax) FO=32 8.71 9.47 10.80 18.15 ns FO=486 | 9.52 10.35 11.90 19.84 ns fax Maximum Datapath Frequency FO=32 114.75 105.57 91.80 55.08 | MHz FO=486 105.00 96.60 84.00 50.40 | MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 57Sy A42MX24 Timing Characteristics (Nominal 3.3V Operation) . (Worst-Case Commercial Conditions) (continued) Preliminary Inform ation Output Module Timing -2 Speed -~1 Speed Std Speed ~F Speed Parameter Description Min, Max. Min. Max. Min. Max. Min. Max. | Units TTL Output Module Timing toLH Data-to-Pad HIGH 3.78 4.28 5.04 7.06 ns {pH Data-to-Pad LOW 441 5.00 5.88 8.23 ns tenzH Enable Pad Z to HIGH 3.95 4.47 5.26 7.37 ns tenze Enable Pad 7 to LOW 4.38 4.96 5.84 8.17 ns tennz Enable Pad HIGH to Z 8.00 9.07 10.67 14.94 ns tentz Enable Pad LOW to Z 7.46 8.45 9.94 13.92 | ns tony G-to-Pad HIGH 7.59 8.60 10.12 14.17 | ns tout G-to-Pad LOW 7.59 8.60 10.12 14.17 | ns tLsu VO Latch Output Set-Up 0.74 0.83 0.98 1.37 ns ty VO Latch Output Hold 0.00 0.00 0.00 0.00 ns tico VO Latch Clock-to-Oul (Pad-to-Pad) 32 VO 8.51 9.64 11.34 15.88 | ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32 V0 16.49 18.68 21.98 30.77 ns any Capacitive Loading, LOW to HIGH 0.05 0.06 0.07 0.10 | ns/pF OTH Capacitive Loading, HIGH to LOW 0.04 0.05 0.06 0.08 | ns/pF CMOS Output Module Timing tpLH Data-to-Pad HIGH 5.32 5.47 6.44 9.02 ns fou Data-to-Pad LOW 3.90 4.14 4.387 6.82 ns tenzH Enable Pad Z to HIGH 3.95 447 5.26 7.37 as tenzi " Enable Pad Z to LOW 3.75 4.96 5.84 8.17 | ns tennyz Enable Pad HIGH to Z 8.00 9.07 10.67 14.94 ns teNLz Enable Pad LOW to 2 746 8.45 9.94 13.92 ns tou G-to-Pad HIGH 7.59 8.60 10.12 14.17 ns tou G-to-Pad LOW 7.59 8.60 10.12 14.17 | ns tisu VO Latch SetUp 0.74 0.83 0.98 1.37 ns ty VO Latch Hold 0.00 0.00 0.00 0.00 ns tico VO Latch Clock-to-Out (Pad-to-Pad) 32/0 8.51 9.64 11.34 15.88 | ons taco Array Latch Clock-to-Out (Pad-to-Pad} 32 VO 16.49 18.68 21.98 30.77 | ns Onn Capacilive Loading, LOW to HIGH 0.05 0.06 0.07 0.10 | ns/pF qty Capacitive Loading, HIGH to LOW 0.04 0.05 0.06 0.08 | ns/pF Notes: 1. Delays based on 35 pF loading,Integrator Series FPGAs: 40MX and 42MX Families A42MX36 Timing Characieristics (Norminai 5.0V Operation) (Worst-Case Commercial Conditions) Preliminary information Logic Module Propagation Delays -2 Speed ~1 Speed Std Speed '-F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units Combinatorial Functions tpp Intemal Array Module Delay 1.46 1.66 1.95 2.73 ns tepp Intemal Decode Module Delay 1.78 2.01 2.37 3.32 ns Predicted Module Routing Delays tro1 FO=1 Routing Delay 1.04 1.18 1.39 1.95 | ns tape FO=2 Routing Delay 1.42 1.61 1.89 2.65 ns taps FO=3 Routing Delay 1.79 2.03 2.39 3.35 ns taba FO=4 Routing Delay 2.18 247 2.90 4.06 ns taps FO=8 Routing Delay 3.68 4.17 491 6.87 ns trop Decode to-Output Routing Delay 0.38 0.43 0.50 0.70 ns Sequential Timing Characteristics tco Flip-Flop Ciock-to-Output 1.43 1.62 1.90 2.66 ns teo Latch Gate-to-Output 1.43 1.62 1.90 2.66 ns tsu Flip-Flop (Latch) Set-Up Time 0.35 0.40 0.47 0.66 ns ty Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tro Flip-Flop (Latch) Reset-to-Output 1.73 1.96 2.31 3.23 ns tsUENA Flip-Flop (Latch) Enable Set-Up 0.75 0.85 1.00 1.40 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 3.68 4.17 4.91 6.87 ns 'WASYN Flip-Flop (Latch) Asynchronous Pulse Width} 4 4, 5.47 644 9.02 as 59Sy/ A42MX36 Timing Characteristics (Nominal 5.0V Operalion) (Worst-Case Commercial Conditions) (continued) Preliminary information jLogic Module Timing -2 Speed -1' Speed Std Speed -F Speed IP arameter Description Nin. Max. Min. Max. Min. Max. Min. Max. | Unite Synchronous SRAM Operations tre Read Cycle Time 7.50 8.50 10.00 14.00 ns two Write Cycle Time 7.50 8.50 10.00 14.00 ns tROKHL Clock HIGH/LOW Time 3.75 4.25 5.00 7.00 ns tgco Data Valid After Clock HIGH/LOW 3.75 4.25 5.00 7.00 ns tapsu Address/Data Set-Up Time 1.80 2.04 2.40 3.36 ns taDH Address/Data Hold Time 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Set-Up 0.68 0.77 0.90 1.26 ns tRENH Read Enable Hold 3.75 4.25 5.00 7.00 ns tWENSU Write Enable Set-Up 3.00 3.40 4.00 5.60 ns tWeNH Write Enable Hold 0.00 0.00 0.00 0.00 ns tgeNns Block Enable Set-Up 3.08 3.49 4.10 5.74 ns tgENH Block Enable Hold 0.00 0.00 0.00 0.00 ns Asynchronous SRAM Operations tRpp Asynchronous Access Time 9.00 10.20 12.00 16.80 ns troapv Read Address Valid 9.75 11.10 13.00 18.20 ns lapsu Address/Data Set-Up Time 1.80 2.04 2.40 3.36 ns tabH Address/Data Hold Time 0.00 0.00 0.00 0.00 ns tRENSUA Read Enable Set-Up to Address Valid 0.68 0.77 0.90 1.26 ns TRENHA Read Enable Hold 3.75 4.25 5.00 7.00 ns tWENsU Write Enable Set-Up 3.00 3.40 4.00 5.60 hs tWeENH Write Enable Hold 0.00 0.00 0.00 0.00 ns Ipou Data Out Hold Time 1.35 1.53 1.80 2.52 nsIntegrator Series FPGAs: 40MX and 42MX Families A42MX36 Timing Characieristics (Nomina! 5.0V Operation) (Worst-Gase Commercial Conditions) (continued) Advanced Information Input Module Propagation Delays -2 Speed =1 Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min, Max. Min. Max. | Unite tiney Input Data Pad-to-Y 1.14 1.29 1.52 2.13 ns tneo Input Latch Gate-to-Output' 1.55 1.76 2.07 290 | ns tinea Input Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Latch Set-Up" 0.53 0.60 0.70 0.98 ns tA Latch Active Pulse Width 5.18 5.87 6.90 9.66 ns Input Module Predicted Routing Delays tirps FO=1 Routing Delay 2.18 247 2.91 4.07 ns tape FO=2 Routing Delay 2.56 2.90 3.41 4.77 ns bros FO=3 Routing Delay 2.93 3.32 3.91 5.47 ns tinpa FO=4 Routing Delay 3.32 3.76 4.42 6.19 ns trps FO=8 Routing Delay 4.82 5.47 6.43 9.00 ns Global Clock Network toKy Input LOW to HIGH FO=32 4.35 4.93 5.80 8.12 ns FO=635 5.63 6.38 7.50 10.50 ns teKL Input HIGH to LOW FO=32 4.20 4.76 5.60 7.81 ns FO=635 5.40 6.12 7.20 10.08 | ns tewH Minimum Pulse Width HIGH FO=32 1.95 2.21 2.60 3.64 ns FO=635 2.18 2.47 2.90 4.06 ns tewL Minimum Pulse Width LOW FO=32 1.95 2.21 2.60 3.64 ns FO=635 2.18 2.47 2.90 4.06 ns icxsw Maximum Skew FO=32 0.83 0.94 1.00 1.40 as FO=635 0.83 0.94 1.00 1.40 ns tsuExT Input Latch Extemal Set-Up FO=32 0.00 0.00 0.00 0.00 ns FO=635 0.00 0.00 0.00 0.00 ns tHext Input Latch Extemal Hold FO=32 3.15 3.57 4.20 5.88 ns FO=635 3.68 417 4.90 6.86 ns tp Minimum Period (1/fyax) FO=32 6.10 6.64 7.63 12.72 ns FO=635 6.61 7.19 8.26 13.77 ns fHMAX Maximum Datapath Frequency FO=32 163.75 150.65 131.00 78.60 | MHz FO=635 151.25 139.15 121.00 72.60 | MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. 61By A42MX36 Timing Characteristics (Nominal 5.0V Operation) (Worst-Case,Commercial Conditions) (continued) Advanced Information Output Module Timing -2' Speed 1 Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. [Units TTL Output Module Timing toy Data-to-Pad HIGH 2.84 3.21 3.78 5.29 ns foHL Data-to-Pad LOW 3.29 3.73 4.39 6.15 ns fenzH Enable Pad Z to HIGH 2.95 3.34 3.93 5.50 ns fenzL Enable Pad Z to LOW 3.26 3.69 4.34 6.08 ns tennz Enable Pad HIGH to Z 5.84 6.62 7.79 10.91 ns teniz Enable Pad LOW to Z 5.45 6.18 7.27 10.18 | ns tein G-to-Pad HIGH 5.59 6.33 7.45 10.43 ns tou G-to-Pad LOW 5.59 6.33 7.45 10.43 ns tusu VO Latch Output Set-Up 0.53 0.60 0.70 0.98 ns tty VO Latch Output Hold 0.00 0.00 0.00 0.00 ns tico VO Latch Clock-to-Out (Pad-to-Pad} 32 V0 6.30 7.14 8.40 11.76 | ons taco Array Latch Clock-to-Out (Pad-to-Pad) 32 V0 8.63 9.78 11.50 16.10 ns dtu Capacitive Loading, LOW to HIGH 0.08 0.09 0.10 0.14 | ns/pF OTH Capacitive Loading, HIGH to LOW 0.08 0.09 0.10 0.14 | as/pF CMOS Output Module Timing! toy Data-to-Pad HIGH 3.92 4.45 5.23 7.32 ns toHL Data-to-Pad LOW 2.73 3.09 3.64 5.10 ns tenzH Enable Pad Z to HIGH 2.95 3.34 3.93 5.50 ns tena Enable Pad 7 to LOW 3.26 3.69 4.34 6.08 ns tenyz Enable Pad HIGH to Z 5.84 6.62 7.79, 10.91 ns tenLz Enable Pad LOW to Z 5.45 6.18 7.27 10.19 ns tery G-to-Pad HIGH 5.59 6.33 7.45 10.43 | ns igut G-to-Pad LOW 5.59 6.33 7.45 10.43 ns tisu VO Latch Set-Up 0.53 0.60 0.70 0.98 ns tty VO Latch Hold 0.00 0.00 0.00 0.00 ns tico /O Latch Clock-to-Out (Pad-to-Pad) 32 VO ; 6.30 7.14 8.40 11.76 ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32 VO 8.63 9.78 11.50 16.10 ns 4TH Capacitive Loading, LOW to HIGH 0.08 0.09 0.10 0.14 | ns/pF Gru Capacitive Loading, HIGH to LOW 0.08 0.03 0.10 0.14 | ns/pF Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.Integrator Series FPGAs: 40MX and 42MX Families A42MX36 Timing Characteristics (Nomina 3.3V Operation) (Worst-Case Commercial Conditions) Preliminary Information Logic Module Propagation Delays -2 Speed '-1 Speed Std Speed '-F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units Combinatorial Functions tpp Intemal Array Module Delay 2.05 2.32 2.73 3.82 ns tppp intemal Decode Module Delay 2.49 2.82 3.32 4.65 ns Predicted Module Routing Delays trp: FO=1 Routing Delay 1.46 1.65 4.95 2.72 ns trp2 FO=2 Routing Delay 1.98 2.25 2.65 3.70 ns tro FO=3 Routing Delay 2.51 2.84 3.35 4.68 ns trpa FO=4 Routing Delay 3.05 3.45 4.06 5.68 ns taps FO=8 Routing Delay 5.16 5.84 6.87 9.62 ns trop Decode-to-Output Routing Delay 0.53 0.60 0.70 0.98 ns Sequential Timing Characteristics tco Flip-Flop Clock-to-Output 2.06 2.26 2.66 3.72 ns teo Latch Gate-to-Output 2.00 2.26 2.66 3.72 ns tsu Flip-Flop (Latch) Set-Up Time 0.49 0.56 0.66 0.92 ns ty Flip-Flop (Latch) Hold Time 0.00 0.00 0.00 0.00 ns tro Flip-Flop (Latch) Reset-to- Output 2.43 2.75 3.23 4.53 ns tsuENA Flip-Flop (Latch) Enable Set-Up 1.05 1.19 1.40 1.96 ns tHENA Flip-Flop (Latch) Enable Hold 0.00 0.00 0.00 0.00 ns twoLKA Flip-Flop (Latch) Clock Active Pulse Width 5.16 5.84 6.87 9.62 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width] 6.76 7.66 9.02 12.62 nsonen . A42MX36 Timing Characteristics (Nominal 3.3V Operatian} (Worst-Case Commercial Conditions) (continued) Preliminary Inform ation Logic Module Timing '-2 Speed -1' Speed Std Speed -F Speed Parameter Description Nin. Max. Min. Max. Min. Max. Min. Max. | Unite Synchronous SRAM Operations tac Read Cycle Time 10.50 11.90 14.00 19.60 ns two Write Cycle Time 10.50 11.90 14.00 19.60 ns trom =" Clock HIGH/LOW Time 5.30 6.00 7.00 9.80 ns taco Data Valid After Clock HIGH/LOW 5.30 6.00 7.00 9.80 ns tapsu Address/Data Set-Up Time 2.50 2.80 3.40 4.80 ns taDH Address/Data Hold Time 0.00 0.00 0.00 0.00 ns tRENSU Read Enable Set-Up 12.00 1.10 1.30 1.80 ns tRENH Read Enable Hold 5.30 6.00 7.00 3.80 ns tweENnsu Write Enable Set-Up 4.20 4.80 5.60 7.80 ns tWENH Write Enable Hold 0.00 0.00 0.00 0.00 ns IBENS Block Enable Set-Up 4.30 4.90 5.70 8.00 ns tBENH Block Enable Hold 0.00 0.00 0.00 0.00 ns Asynchronous SRAM Operations tepp Asynchronous Access Time 12.60 14.30 16.80 23.50 ns troapv Read Address Valid 13.70 15.50 18.20 25.50 ns tapsu Address/Data Set-Up Time 2.50 2.80 3.40 4.76 ns taDH Address/Data Hold Time 0.00 0.00 0.00 0.00 ns tRENSUA Read Enable Set-Up to Address Valid 1.00 1.10 1.30 1.80 ns tRENHA Read Enable Hold 5.30 6.00 7.00 9.80 ns twensu Write Enable Set-Up 4.20 4.80 5.60 7.80 ns tWeENH Write Enable Hold 0.00 9.00 0.00 0.00 ns pou Data Out Hold Time 2.00 2.10 2.50 3.50 nsIntegrator Series FPGAs: 40MX and 42MX Families A42MX36 Timing Characteristics (Nomina! 3.3V Operation) (Warst-Case Commercial Conditions) (continued) Preliminary Information Input Module Propagation Delays -2 Speed -1" Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units tinpy Input Data Pad-to-Y 1.60 1.81 2.13 2.98 ns tinco Input Latch Gate-to-Output" 2.17 2.46 2.90 4.06 ns tin Input Latch Hold 0.00 0.00 0.00 0.00 ns tinsu Input Latch Set-Up! 0.74 0.83 0.98 1.37 ns tia Latch Active Pulse Width! 7.25 8.21 9.66 13.52 ns Input Module Predicted Routing Delays tiro1 FO=1 Routing Delay 3.06 3.46 4.07 5.70 ns tirpe FO=2 Routing Delay 3.58 4.06 4.77 6.68 ns urps FO=3 Routing Delay 4.11 4.65 5.47 7.66 ns trapa FO=4 Routing Delay 4.64 5.26 6.19 8.66 ns taps FO=8 Routing Delay 6.75 7.65 9.00 12.60 ns Global Clock Network toKH Input LOW to HIGH FO=32 6.09 6.90 8.12 11.37 | as FO=635 7.88 8.93 10.50 14.70 ns teKL Input HIGH to LOW FO=32 5.88 6.66 7.84 10.98 | ns FO=635 7.56 8.57 10.08 14.11 ns tpwH Minimum Pulse Width HIGH FO=32 2.73 3.09 3.64 5.10 ns FO=635 3.05 3.45 4.06 5.68 ns tpwe Minimum Pulse Width LOW FO=32 2.73 3.09 3.64 5.10 ns FO=635 3.05 3.45 4.06 5.68 ns tcxsw Maximum Skew FO=32 1.16 1.31 1.54 2.16 ns FO=635 16 1.31 1.54 2.16 ns tSUEXT Input Latch Extemal Set-Up FO=32 0.00 0.00 0.00 0.00 ns FO=635 0.00 0.00 0.00 0.00 ns tHExT Input Latch External Hold FO=32 441 5.00 5.88 8.23 ns FO=635 5.15 5.83 6.86 9.60 ns tp Minimum Period (1/fmax) FO=32 10.18 11.06 12.70 21.20 ns FO=635 11.02 11.98 13.77 22.96 ns fumax Maximum Datapath Frequency FO=32 98.25 90.39 78.60 47.16 | MHz FO=635 90.75 83.49 72.60 43.56 | MHz Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.Sy A42MX36 Timing Characteristics (Nominal 3.3V Operalion) (Worst-Case Commercial Gonditions) (continued) Preliminary Inform ation Output Module Timing '-2 Speed -1 Speed Std Speed -F Speed Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. | Units TTL Output Module Timing toLH Data-to-Pad HIGH 3.97 4.50 5.29 741 ns fpHL Data-to-Pad LOW 461 5.22 6.15 8.60 ns teNZH Enable Pad 2 to HIGH 4.13 4.68 5.50 7.70 ns tenzL Enable Pad Z to LOW 4.56 5.16 6.08 8.51 ns tenyz Enable Pad HIGH to Z 8.18 9.27 10.91 15.27 | ns tenLz Enable Pad LOW to Z 1.63 8.65 10.18 14.25 | ns tetH G-to-Pad HIGH 7.82 8.87 10.43 14.60 ns tent G-to-Pad LOW 7.82 8.87 10.43 14.60 ns tisu VO Latch Output Set-Up 0.74 0.83 0.98 1.37 ns tly VO Latch Output Hold 0.00 0.00 0.00 0.00 ns tLlco VO Latch Clock-to-Out (Pad-to-Pad) 32 VO 8.82 10.00 11.76 16.46 ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32 /O 12.08 13.69 16.10 22.54 ns yi Capacitive Loading, LOW to HIGH 0.11 0.12 0.14 0.20 | ns/pF GTHL Capacitive Loading, HIGH to LOW 0.11 0.12 0.14 0.20 | ns/pF CMOS Output Module Timing! toto Data-to-Pad HIGH 5.49 6.22 1.32 10.25 ns tou Data-to-Pad LOW 3.82 4.33 5.10 7.13 ns tenzH Enable Pad Z to HIGH 4.13 468 5.50 7.70 ns tenze Enable Pad 7 to LOW 4.56 5.16 6.08 8.51 ns tenyz Enable Pad HIGH to Z 8.18 9.27 10.91 15.27 ns tentz Enable Pad LOW to Z 7.63 8.65 10.18 14.25 | ns teu G-to-Pad HIGH 7.82 8.87 10.43 14.60 ns tout Gto-Pad LOW 7.82 8.87 10.43 14.60 ns ttsu VO Latch Set-Up 0.74 0.83 0.98 1.37 ns tua VO Latch Hold 0.00 0.00 0.00 0.00 ns fico Latch Glock-to-Out (Pad-to-Pad) 32 VO 8.82 10.00 11.76 16.46 | ns taco Array Latch Clock-to-Out (Pad-to-Pad) 32 VO 12.08 13.69 16.10 22.54 ns dt Capacitive Loading, LOW to HIGH 0.11 0.12 0.14 0.20 | ns/pF qT Capacitive Loading, HIGH to LOW 0.11 0.12 0.14 0.20 | ns/pF Notes: 1, Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.Integrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments 44-Pin PLCC 68-Pin PLGG 5 i+ A 5 5 = = 5 mm Pn = DB PLOL = =) - ma) =] ) : : oI = rs om) A40M X02 A40OMX04 A40MX02 A40OMX04 Signal Function Function Signal Function Function 3 Voc Voc 4 Voc Voc 10 GND GND 14 GND GND 14 Voc Voc 15 GND GND 21 GND GND 25 Voc Voc 25 Voc Voc 32 GND GND 32 GND GND 38 Voc Voc 33 CLK, lO CLK, /O 49 GND GND 34 MODE MODE 52 CLK, VO CLK, VO 35 Veo Voc 54 MODE MODE 36 SDI, VO SDI, /O 55 Voc Veco 37 DCLK, I/O DCLK, VO 56 SDI, VO SDI, VO 38 PRA, VO PRA, VO 57 DCLK, O DGLK, /O 39 PRB, VO PRB, O 58 PRA, VO PRA, lO 43 GND GND 59 PRB, VO PRB, VO 66 GND GND 67Package Pin Assignments (continued) 84-Pin PLCC DQUUU UU CUUU UU OU UULUUUUU A4OM X04 Signal Function 4 Veo 12 NC 18 GND 19 GND 25 Voc 26. Voc 33 Voc 40 GND 46 Voc 60 GND 61 GND 64 CLK, I/O 66 MODE 67 Voc 68 Veco 72 SDI, /O 73 DCLK, VO 74 PRA, /O 75 PRB, /O 82 GND Notes: 1. NC Denotes No Connection. 2. Allunlisted pin numbers are user I/Os. 3. | MODE should be terminated to GND through a 10K resistor toenable ActionProbe usage; otherwise, it can be terminated directly to GND.Integrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 100-Pin PQFP A40MX02 A40MX04 A40MX02 A40MX04 Pin Function Function Pin Function Function 1 NC NG 53 NC NG 2 NC NC 54 NC NC 3 NC NC 55 NC NC 4 NC NC 56 Voc Voc 5 NG NC 63 GND GND 6 PRB, VO PRB, I/O 69 Voc Voc 13 GND GND 77 NG NC 19 Voc Voc 78 NG NC 27 NG NG 79 NG NG 28 NG NC 80 NG VO 29 NC NC 81 NG vO 30 NC NC 82 NG vO 31 NC vO 86 GND GND 32 NC vO 87 GND GND 33 NG vO 90 CLK, VO CLK, VO 36 GND GND 92 MODE MODE 37 GND GND 93 Voc Voc 43 Voc Voc 94 Voc Voc 44 Voc Veco 95 NC vO 48 NC vO 96 NC vO 49 NG vO 97 NC ie) 50 NC vO 98 SDI, VO SDI, VO 51 NC NC 99 DCLK, /O DCLK, VO 52 NG NC 100 PRA, I/O PRA, I/O Notes: 1. NC Denctes No Connection. 2. All unlisted pin numbers are user 1/Qs. 3. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 69sy Package Pin Assignments (continued) 80-Pin VQFP A4OMX02 AGOMX04 A4OMX02 A4OMX08 Pin Function Function Pin Function Function NC vO 47 GND GND NC vO 50 CLK, I/O CLK, /O NG vO 52 MODE MODE GND GND 53 Veo Voc 13 Vec Voc 54 NG vO 17 NC vO 55 NG vO 18 NC vO 56 NG Ze) 19 NG Te) 57 SDI, VO SDI, VO 20 Voc Voc 58 DCLK, VO DCLK, VO 27 GND GND 59 PRA, VO PRA, VO 33 Vec Voc 60 NG NC 41 NC vO 61 PRB, VO PRB, VO 42 NG vO 68 GND GND 43 NG vO 74 Veco Voc Notes: 1. NC Denotes No Connection. 2. All unlisted pin numbers are user I/Qs. 3. | MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 70Integrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 84-Pin PLCC Package (Top View) a DOOODODOOOUD OOO DOO OO UU UUUUUUUUUUUUUUUUU Uo a84-Pin PLCC Package Pin A42MX0s A42M X16 Ad2MX24 Number Function Function Function 2 CLKB, VO CLKB, I/O CLKB, VO 4 PRB, VO PRB, VO PRB, VO 5 VO vO VO (WD) 6 GND GND GND 8 VO vO VO (WD) 9 vO VO VO (WD) 10 DCLK, VO DCLK, VO DCLK, VO 12 MODE MODE MODE 22 Veci Voc! Veco! 23 Voca Voca Veca 28 GND GND GND 34 vO fe) TMS, VO 35 vO @) TDI, VO 36 vO @) VO (WD) 38 vO vO VO (WD) 39 vO vO VO (WD) 43 Voca Voca Voca 44 VO VO VO (WD) 45 vO vO VO (WD) 46 VO vO VO (WD) 47 vO vO VO (WD) 49 GND GND GND 50 vO vO VO (WD) 51 vO vO VO (WD) 52 vO vO TDO (WD) 62 VO VO TCK, VO 63 GND (LP) GND (LP) GND (LP) 64 Voca Voca Voca 65 Voc Voci Veco! 70 GND GND GND 76 SDI, VO SDI, /O SDI, /O 78 vO VO VO (WD) 79 vO vO VO (WD) 80 vO vO VO (WD) 81 PRA, /O PRA, I/O PRA, VO 83 CLKA, I/O CLKA, V/O CLKA, I/O 84 Voca Voca Voca Notes: 1. YOCWD): Denotes l/Opin with an associated wide-decode module. 2. Wide-decode 1/O( WE) can also be general-purpose user YO. 3. NC Denotes No Connection. 4. All unlisted pin numbers are user I/Os. 5. MOLE should be terminated to GND through a 10Kresistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 72Integrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 100-Pin PQFP Package (Top View) O100-Pin PQFP Package A42MX09 A42MX16 A42MX09 A42MX16 PQ100 PQ100 PQ100 PQ100 Pin Number Function Function Pin Number Function Function 2 DCLK, VO DCLK, VO 64 GND (LP) GND (LP) 4 MODE MODE 65 Voca Voca 7 @) vO 66 Veci Voci 9 GND GND 67 Voca Voca 14 vO vO 70 vO vO 15 vO Ke) 72 GND GND 16 Voca Voca 77 vO vO 17 Voor Voca 79 SDI, /O SDI, vO 20 vO vO 82 vO fe) 22 GND GND 84 GND GND 32 vO vO 85 vo vO 34 GND GND 87 PRA, V/O PRA, I/O 38 vO vO 88 VO vO 40 Voca Voca 89 CLKA, VO GLKA, VO 44 vO vO 90 Voca Voca 46 GND GND 92 CLKB, I/O CLKB, VO 55 vO vO 94 PRB, I/O PRB, I/O 57 GND GND 96 GND GND 62 vO @) 100 vO vO 63 vO ie) Notes: 1. NC Denotes No Connection. 2. All unlisted pin numbers are user 1/Qs. 3. | MODE should be terminated to GND through a 10Kresistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 74Integrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 160-Pin PQFP Package (Top View) Notes: 1. YO CW: Denctes Opin with an associated wide-decade module. 2. Wide-decode 1/O( WY can also be general-purpose user 1/O. 3. NC Denotes No Connection. 4, All unlisted pin numbers are user I/Os. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 75160-Pin PQFP Package Pin A42MX09 A42MX16 A42MX24 Pin A42M X09 A42MX16 A42MX24 Number Function Function Function Number Function Function Function 2 DCLK, I/O DCLK, VO DCLK, 6 83 VO vO VO (WD) 4 vO VO VO (WD) 84 VO vO VO (WD) 5 VO vO VO (WD) 86 NG Voc Voc 6 NC Voci Voc 87 vO VO ie) 7 VO Ze) vO 88 VO i) VO (WD) 10 NC vO vO 89 GND GND GND 11 GND GND GND 92 VO 1) vO 12 NG vO vO 93 vO vO vO 13 vO vO VO (WD) 96 vO vO VO (WD) 14 vO vO VO (WD) 97 VO ie) vO 16 PRB, VO PRB, /O PRB, VO 98 Voca Vocoa Voca 18 CLKB, I/O CLKB, VO CLKB, VO 99 GND GND GND 20 Voca Voca Voca 100 NC vo VO 21 CLKA, I/O CLKA, VO CLKA, I/O 103 NC vO vO 23 PRA, V/O PRA, I/O PRA, VO 106 vO vo VO (WD) 24 NG vO VO (WD) 107 vO VO VO (WD) 25 vO vO VO (WD) 109 GND GND GND 26 VO vO VO 110 NG 0) vO 28 NG ie) vO 414 NG vO VO (WD) 29 VO vO VO (WD) 112 vO vO VO (WD) 30 GND GND GND 114 NG Voc Voc 31 NG vO VO (WD) 115 vO vO VO (WD) 34 vO vO vO 116 NC vO VO (WD) 35 NC Voc Voc 118 vO vO TDI, VO 36 vO vO VO (WD) 119 vO vO TMS, vO 37 vO VO VO (WD) 120 GND GND GND 38 SDI, VO SDI, /O SDI, VO 124 NC vO vO 40 GND GND GND 125 NC GND GND 44 GND GND GND 129 NC vO ie) 49 GND GND GND 130 GND GND GND 52 @) vO vo 131 NC VO VO 57 Voca Voca Voca 138 NC Voca Voca 58 Voc! Voct Voci 139 Veci Veo Voc! 59 GND GND GND 140 GND GND GND 60 Voca Voca Voca 141 NC vO ie) 61 GND (LP) GND (LP) GND (LP) 145 GND GND GND 62 vO vO TCK, VO 146 NC vO vO 64 GND GND GND 150 NG Voca Voca 69 GND GND GND 151 NG VO vO 70 NG vO vO 152 NC vO vO 75 NC vO vO 153 NG vO vO 77 NC vO vO 154 NG vO vO 79 NC vO vO 155 GND GND GND 80 GND GND GND 159 MODE MODE MODE 82 vO vO TDO, VO 160 GND GND GNDIntegrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 208-Pin PQFP Package (Top View) Notes: 1. OC WD): Denotes I/Opin with an associated wide-decode module. 2. Wide-decode 1/O WD) can also be general-purpose user YO. 3. NC Denotes No Connection. 4. Alluntisted pin numbers are user I/Os. 5. | MODE should be terminated to GNDthrough a 10K resistor toenable ActionProbe usage; otherwise, it can be terminated directlyto GND. 6. RQFPhas an exposed circular metal heat sink on the top surface.ey 208-Pin PQFP Package Ad2MX16 A42MX24a A42M X36 A42M X16 A42M X24 AG2M X36 Pin Mumber Function Function PQ208 Function Pin Number Function Function PQ208 Functlon 7 GND GND GND TOF VO VO TO 2 NG Voua VGCA 105 GND CND CND a MODE MODE MODE 106 NC Voca Voca 5 VO VO vO 107 VO vO VO 6 oO Vo VO 108 VO vO VO 7 VO VO VO 410 VO vO vO 9 NC Vo vO 112 NC vO vo 10 NC VO vo 113 NG vO vO "1 NG vo vO 414 NC vO VO 13 lO Vo vO 115 NG vO vO 15 VO Vo vO 117 vO vO ie) 16 NC VO VO 121 vO vO ie) 17 Voca Voca Veca 122 vO vo vO 13 VO vO 126 GND GND GND 20 vO VO vO 128 VO TCK, VO TCK, VO 22 GND GND GND 129 GND (LP) GND (LP} GND (LP) 24 vO vO vO 130 Voca Voca Voca 26 vO VO VO 131 GND GND GND 27 GND GND GND 132 Veo Voor Voc! 28 Veci Veci Veci 133 Voca Voca Vaca 29 Voca Voca Voca 136 Voca Veca Veca 30 vO vo vO 137 vO vo VO 32 Voca Voca Veca 138 vO vO ie) 33 vO vO vO 141 NC vo VO 38 VO vO vO 142 vO ie] vO 40 0 vO vO 144 vO vO vO 41 NC vO VO 146 NG vo VO 42 NG vO vO 147 NC vo vo . 43 NC VO vO 148 NC vO vO 45 vO VO VO 149 NG vo vO 47 vO VO vO 150 GND GND GND 48 vO 0 vO 151 vO vo vO 50 NC VO vO 152 vO vo ie} 51 NC vO VO 154 vO vo vo 52 GND GND GND 155 vO VG vO 53 GND GND GND 156 vO vo vO 54 ie) TMS, VO TMS, VO 157 GND GND GND 55 vO TDI, VO TDI, O 159 SDI, O SDI, VO SDI, VO 57 vO VO (WD) VO (WD) 161 VO VO (WD) VO (WD) 58 vO 170 (WD) VO (WD) 162 vo VO (WD) VO (WD) 59 vO vo vO 164 Veo Voor Voc 60 Voct Veci Voc 165 NG vo vo 61 NC vo ie] 166 NG vo VO 62 NC vo ie] 168 vO VO (WD) VO (WD) 65 ie) vO QCLKA, I/O 169 VO VO (WD) VO (WD) 66 VO VO (WD) VO (WD) 171 NG vO QCLKD, I/O 67 NC VO (WD) VO (WD) 176 vO VO (WD) VO (WD) 68 NG vO VO 177 vO VO (WD) VO (WD) 70 vO VO (WD) VO (WD) 178 PRA, VO PRA, YO PRA, /O 71 vO VO (WD) VO (WD) 180 CLKA, //O CLKA, VO CLKA, VO 74 vO VO VO 181 Nc vO VO 77 vo vo vo 182 NC Vee Veci 78 GND GND GND 183 Voca Voca Veca 79 Voca Voc Voca 184 GND GND GND 80 NC Veo Voc 186 CLKB, /O CLKB, VO CLKB, YO Bt ie) vO ie) 187 vO vO vO 83 VO vO VO 188 PRB, VO PRB, VO PRB, YO 85 vO vO (WD) VO (WD) 190 vO VO (WD) vO (WD) 86 VO VO (WD) 70 (WD) 191 vO VO (WD) VO (WD) 89 NC vO vO 193 NC vO vO 90 NC vO VO 194 NC VO (WD) vO (WD) 31 VO vO - QCLKB, V/O 195 Nc VO (WD) VO (WD) 33 vO VO (WD) VO (WD) 196 vO vO QCLKC, VO 94 VO VO (WD) /O (WD) 197 Nc VO vO 95 Nc vo He) 201 NC VO vO 96 NC vO vO 202 Veo! Vecl Veci 97 NC VO vO 203 VO VO (WD) VO (WD) 98 Vcc Voci Voc! 204 VO vO (WD) VO (WD) 100 VO VO (WD) VO (WD) 206 VO VO vo 101 VO VO (WD) 1/0 (WD) 207 DCLK, O DCLK, /O DCLK, /O 103 VO TDO, VO TBO, VO 208 vO VO VOIntegrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 240-Pin RQFP Package (Top View) Notes: 1/O( WI): Denotes [/Opin with an associated wide-decode module. Wide-decode 1/O( WD) can also be general-purpose user I/O. NC Denotes No Connection. All unlisted pin numbers are user VOs. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; other wise, it can be terminated directly to GND. ROQFP has an exposed circular metal heat sink on the top surface. RDwP-WN Eeey 240-Pin RQFP Package Pin Number A42MX36 Function 2 DCLK, VO 6 VO (WD) 7 vO (WD) 8 Voci 15 QCLKG, I/O 17 VO (WD) 18 VO (WD) 21 VO (WD) 22 VO (WD) 24 PRB, I/O 26 CLKB, VO 28 GND 29 Voca 30 Veci 32 CLKA, I/O 34 PRA, I/O 37 vO (WD) 38 vO (WD) 45 QCLKD, I/O 47 VO (WD) 48 VO (WD) 52 Veo 54 VO (WD) 55 VO (WD) 57 SDI, /O 59 Voca 60 GND 61 GND ra Voci 85 Voca 88 Voca 89 Voct 90 Voca 91 GND (LP) 92 TCK, VO 94 GND 108 Vea 118 Voca . Pin Number A&2MX36 Function 119 120 121 123 125 126 128 132 133 135 142 143 150 151 152 159 160 163 164 166 172 174 175 178 179 180 181 182 192 206 209 210 219 227 237 238 239 240 GND GND GND TDO, VO VO (WD) VO (WD) Veci VO (WD) VO (WD) QCLKB, VO 0 (WD) VO (WD) Voc Voca GND vO (WD) VO (WD) VO (WD) vO (WD) QCLKA, V/O Voc vO (WD) vO (WD) FDI, VO TMS, I/O GND Voca GND Voc Voca Voca Voc Voca Voc GND MODE Voca GNDIntegrator Series FPGAs: 40MX and 42MX Families Package Pin Assignments (continued) 176-Pin TQFP Package (Top View) Notes: 1. 1/OCWD): Denotes [/Opin with an associated wide-decode module. 2. Wide-decode 1//O( WD) can also be general-purpose user I/O. 3. NC Denotes No Connection. 4. Allunksted pin numbers are user /Qs. 5. MODE should be terminated to GND through a 10K resistor to enable ActionProbe usage; otherwise, it can be terminated directly to GND. 81Sy 176-Pin TQFP Package Aa&2M X09 A42MX16 AGd2MX24 Ad2Mxog9 A42MX16 Ad2MX24 Pin Number Function Funeticn Funetion Pin Number Function Function Function 1 GND GND GND 97 NC VO vO 2 MODE MODE MODE 101 NC NC Ke) 8 NC NG vO 103 NC vO vO 10 NC VO vO 106 GND GND GND 1 NC vo vO 107 NC VO ie) 13 NG Voca Voca 108 NG VO TCK, VO 18 GND GND GND 109 GND (LP) GND (LP} GND (LP) 19 NC vO vo 110 Voca Voca Voca 20 NC vo vO 111 GND GND GND 22 NC vO vO 112 Veci Vecl Vecr 23 GND GND GND 113 Voca Voca Voca 24 NC Voc Veci 114 Nc VO VO 25 Voca Voca Voca 115 NC 0 vO 26 NC vO vO 116 NG Veca VocaA 27 NC vo VO 17 1/0 VO vO 28 Voc Veca Voca 121 NG NC vO 29 NC vO vo 124 NG ie) VO 33 NG NC VO 125 NG vO vO 37 NC vO vO 126 NC NC VO 38 NC NC vO 133 GND GND GND 45 GND GND GND 195 SDI, VO SDI, lO SDI, VO 46 vO vO TMS, VO 136 NC WO vO 47 vo vo TDI, VO 137 vo 10 l/O (WD) 48 vo vo vO 138 vO ie) lO (WD) 49 vO vO VO (WD) 139 vO VO VO 50 VO vO VO (WD) 140 NC Vec Vect 52 NC Voc Voc 144 he) 0 VO 54 NC vo vo 143 NC vO VO 55 NC vO VO (WD) 144 NC vO /O (WD) 56 VO vO VO (WD) 145 NC NC I/O (WD) 57 Nc NG vO 146 vO vO vO 59 vO vO VO (WD) 147 NC vO VO 60 vo vO VO (WD) 149 vO vO VO 61 NG vO vo 150 VO vO VO (WD) 64 NC vO VO 151 NC vO VO (WD) 66 NC vO vO 152 PRA, V/O PRA, VO PRA, I/O 67 GND GND GND 154 CLKA, /O CLKA, I/O CLKA, VO 68 Voca Veca Voca 155 Voca Voca Voca 69 vO vo VO (WD) 156 GND GND GND 70 vo vO V/O (WD) 158 CLKB, I/O CLKB, VO CLKB, VO 73 vO vO VO 160 PRB, VO PRB, VO PRB, I/O 74 NC vO Vo 161 NC VO VO (WD) 75 vo vO vO 162 VO vO VO (WD) 77 NC NG VO (WD) 163 vO vO V0 78 NG vo VO (WD) 165 NC NC HO (WD) 80 NG vo vO 166 NG He) (/O (WD) 81 vO vO vO 168 NG VO VO 82 NC Vecr Veci 169 vO vo vO 84 vo vO VO (WD) 170 NC Veci Vect 85 vO vO 70 (WD) 171 VO vO VO (WD) 86 NC vO vo 172 vO vO /O (WD) 87 vO vo TDO, /O 173 NC vO 1/0 89 GND GND GND 175 DCLK, I/O DCLK, I/O DCLK, lO 96 NC vo vOIntegrator Series FPGAs: 40MX and 42MX Families Package Mechanical Drawings Plastic Leaded Chip Carrier (PLCC) | UUDVUUUUUUUUUUUUUU B Q G + QUUU UU UU UU UU UU ooo 3 ei - Ee i me o* f- 032 70.84 005 80.4275 Atter Lead Finn 0 10.508) OH on Bale ayy1Chsy/ Plastic Leaded.Chip Carrier Packages (PLCC) PLCC 44 PLCC 68 PLCC 84 JEDEC Equivalent MS007 AE VAR MS007 AE VAR MS007 AE VAR Dimension Min. Max. Min. Max. Min. Max. A 0.155 0.175 0.155 0.175 0.155 0.175 Al 0.090 0.130 0.090 0.130 0.090 0.130 B 0.013 0.027 0.013 0.027 0.013 0.027 B2 0.026 0.032 0.026 0.032 0.026 0.032 CG 0.007 0.013 0.005 0.011 0.005 0.011 D/E 0.670 0.710 0.970 1.010 1.170 1.210 Di/E1 0.640 0.660 0.940 0.960 1.140 1.160 D2/E2 0.590 0.630 0.890 0.930 1.090 1.130 D3/E3 50 nominal .80 nominal 1.00 nominal e1 0.050 BSC 0.050 BSC 0.050 BSC Notes: 1. All dimensions are in inches. 2 BSCBasic Spacing between Centers.Integrator Series FPGAs: 40MX and 42MX Families Package Mechanical Drawings (continued) Plastic Quad Flat Pack (RQFP, RQFP, TQFP, VQFP) Bt Soo Deobil A >| he = . - 1 | se i ale Detail AICS) Package Mechanical Drawings (continued) Plastic Quad Flat Pack Rectangular Package (PQ100) B > Seo Dobil A Aq oh L le Dobeil A 10 Typ Q20FA4 D Theta c o O20RAD BpIntegrator Series FPGAs: 40MX and 42MX Families Plastic Quad Flat Packages (PQFP) PQFP 100 PQFP 160 PQFP 208 JEDEC Equivalent MO-108 MO-112 MO-143 Dimension Min. Max. Min. Max. Min. Max. A 3.40 4.07 4.10 Al 0.25 0.25 0.25 A2 2.55 3.05 3.17 3.67 3.20 3.60 b 0.22 0.38 0.22 0.38 0.17 0.27 c 0.13 0.23 0.13 0.23 0.09 0.20 23.20 BSC 31.90 BSC 30.60 BSC D1 20.00 BSG 28.00 BSC 28.00 BSC E 17.20 BSC 31.90 BSC 30.60 BSC E1 14.00 BSG 28.00 BSC 28.00 BSC e 0.65 BSC 0.65 BSG 0.50 BSC L 0.73 1.03 0.65 0.95 0.50 0.75 ccc 0.10 0.10 0.08 Theta 0 7 deg 0 7 deg 0 7 deg Notes: 1. All dimensions are in millimeters. 2. BSCBasic Spacing between Centers. Plastic Quad Flat Packages (RQFP) RQFP 240 JEDEC Equivalent MO-143 Dimension : Min. Max. A 4.10 Al 0.25 A2 3.20 3.60 b 0.17 0.27 c 0.09 0.20 D/E 34.60 BSC DiV/Et 32.00 BSG e 0.50 BSC L 0.50 0.75 ccc 0.08 Theta 0 7 deg Notes: 1. Alldimensions are in millimeters. . 2. BSCBasic Spacing between Centers. 87Thin Quad Flat Packs (TQFP and VQFP)} TQFP 176 VQFP 80 JEDEC Equivalent MO-136 MO-136 Dimension Min. Max. Min. Max. A 1.60 1.20 Al 0.05 0.15 0.05 0.15 A2 1.35 1.45 0.95 1.05 b 0.17 0.27 0,22 0.38 0.09 0.20 0.09 0.20 D/E 26.00 BSC 16.00 BSC Di/E1 24.00 BSG 14.00 BSC e 0.50 BSC 0.65 BSC L 0.45 0.75 0.45 0.75 ccc 0.08 0.10 Theta 0 7 deg 0 7 deg Notes: 1. All dimensions are in millimeters. 2. BSCBasic Spacing between Centers.Integrator Series FPGAs: 40MX and 42MX FamiliesActel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Talos It te 2 higher Level. http://www.actel.com Actel Europe Lid. Actel Corporation Actel Japan Daneshill House, Lutyens Close 955 East Arques Avenue EXOS Ebisu Bldg. 4F Basingstoke, Hampshire RG24 8AG Sunnyvale, California 94086 1-24-14 Ebisu Shibuya-ku United Kingdom USA Tokyo 150 Japan Tel: +44.(0)1256.305600 Tel: 408.739.1010 Tel: +81.(0)3.3445.7671 Fax: +44.(0)1256.355420 Fax: 408.739.1540 Fax: +81.(0)3.3445.7668 5172136-0