PIC12F675-I/SN - Microchip Technology

PIC12F629/675

The PIC12F629/675 family of devices that you have

received conform functionally to the current Device Data

Sheet (DS41190F), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata describ ed in this document will be addressed

in future revisions of the PIC12F629/67 5 silic on.

Data Sheet clarifications and corrections start on page 4,

following the discu ssion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB® IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger>Connect). Depending on the

development tool used, the part number and

Device Revision ID value appear in the Output

window.

The DEVREV values for the various PIC12F629/675

silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the curre nt silicon revision

(B0).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID(1) Revision ID for Silicon Revision(2)

A9 B0

PIC12F629 1111110 xxxxx 0F90h 0F8Bh

PIC12F675 1111100 xxxxx 0FD0h 0FCBh

Note 1: The Devic e IDs (DEVID an d DEVREV) are locate d at the las t two implemen ted addres ses of config uration

memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC12F629/675 Flash Programming Specificati on” (DS41191) for detailed information on

Device and Revision IDs fo r your specific device.

PIC12F629/675 Family

Silicon Errata and Data Sheet Clarification

PIC12F629/675

TABLE 2: SILICON ISSUE SUMMARY

Module Feature Item

Number Issue Summary Affected Revis ions (1)

A9 B0

Data EEPROM

Memory Interrupt Flag 1. Inadvertently clears. X X

Power-on Reset — 2. Low VDD Level may fail to release

the Reset. X

Note 1: Only those issues indicated in the last column apply to the current silicon revision.

PIC12F629/675

Silicon Errata Issues

1. Module: Data EEPROM Memory

The EEIF flag may be cleared inadvertently when

performing operations on the PIR1 register,

simultaneously with the completion of an EEPROM

write. This condition occurs when the EEPROM

write timer completes at the same moment that the

PIR1 register operation is executed. Register

operations are those that have the PIR1 register as

the destination and include, but are not limited to,

BSF, BCF, ANDWF, IORWF and XORWF.

Work around

1. Avoid operations on the PIR1 register when

writing to the EEPROM memory.

2. Poll the WR bit (EECON1<1>) to determine

when the write is complete.

3. Use a timer interrupt to catch any instances

when the EEIF flag is inadvertently cleared.

The timer interrupt should be set longer than

8 ms. If EEIF fails, then the timer interrupt

occurs as a default time out. The WR and

WRERR flags are c he ck ed as p a rt of the tim er

Interrupt Service Routine to verify the

EEPROM write success.

4. If pe riodic interrupt s are oc curring in a ddition to

the EEIF interrupts, then use a secondary flag

to sense write completion. The secondary flag

is set wh enever EEPROM writes a re active. An

EEPROM write completion is indicated when

the secondary flag is set and the WR flag is

clear.

Affected Silicon Revisions

2. Module: Power-on Reset (Rising VDD

Detect)

The PIC12F629/675 Power-on Reset (POR)

circuitry is sensitive to a low VDD level and may fail

to release the Reset if VDD returns to an operational

voltage after dropping to a very low level.

The sensitive VDD condition occurs when VDD

drops into an out-of-specification voltage region

below the Brown-out Detect threshold and then

recovers to a normal operating condition. The

voltage region that can cause the problem is

dependant upon temperature with the region

growing as the temper ature drops. A typical region

is between 0.5 and 0.7V at -25°C. Below the region,

the POR operates corr ectly. Above the region, the

POR is inactive per the data sheet. Inside the

region, the POR will assert Reset and will not

release Reset until power is removed and VDD

reaches VSS. Be cause the POR is independent of

other Reset circuits (see Figure 9-4 of the data

sheet), activating BOR or using the MCLR input will

not eliminate the problem.

Work around

To resolve this problem, the application must be

designed to assure that VDD reaches VSS. This is

described as D003 VPOR in Section 12.0

“Electrical Specifications” of the Device Data

Sheet (DS41190F).

Affected Silicon Revisions

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated by the shaded column in

the following tables apply to the current

silicon revision (B0).

A9 B0

PIC12F629/675

Data Sheet Clarificatio n

None.

PIC12F629/675

APPENDIX A: DOCUMENT

REVISION HISTORY

Rev. A Document (3/2002)

First revision of this document. Revised Table 12.3

Rev. B Document (9/2002)

Added Module 1: “In-Circuit Serial Programming™”,

changes made to the Typical In-Circuit Serial Program-

ming Connection, Figure 9-18.

Rev. C Document (04/02/04)

Removed Table 12.3 and Figure 9-18 due to Data

Sheet revisions.

Added Module 1: “GPIO Port”, changes made to the

TRISIO – GPIO Tri-state Register.

Rev. D Document (11/2004)

Added Module 1: “Data EEPROM Memory” for

PIC12F629/675 silicon.

Rev. E Document (07/2005)

Data Sheet Clarifications/Corrections Section: Added

Module 2: New 4x4 DFN Package added.

Rev. F Document (10/2005)

Data Sheet Clarifications/Corrections Section:

Replaced 8-Lead Plastic Dual Flat No Lead Package

4x4 (DFN).

Rev. G Document (8/2006)

Added Module 2: “Power-on Reset (Rising VDD

Detect)” for PIC12F629/675 silicon.

Rev. H Document (6/2009)

Updated the document with new format. Deleted

Module 1 and 2 from the Data Sheet Clarification

section. Updated Table 1 and 2. Other minor edits.

PIC12F629/675

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce

and may be supers eded by updates . I t is you r r es ponsibil it y to

ensure that your application meets with your specifications.

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OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

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conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,

rfPIC and UNI/O are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI-TIDE , In-Circuit Seria l

Prog ra m ming , IC SP, IC EPIC , Mi n d i , M iW i , MPASM, MP L AB

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Omniscient Code Generation, PICC, PICC-18, PICkit,

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ZENA are trademarks of Microchip Technology Incorporated

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SQTP is a service mark of Microchip T echnology Incorporated

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All other trademarks mentioned herein are property of their

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and ds PIC® DSCs, KEELOQ® code ho pping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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