ACD300xx Family Advanced Communication Devices 8-/12-/16-/24-Port Dual-Speed "Super Class" Ethernet Hub Controllers The ACD300xx is a family of single chip Dual-Speed "Super Class" Ethernet Hub controllers. It consists of four members: the 8-port ACD30008, the 12-port ACD30012, the 16-port ACD30016 and the 24-port ACD30024. All controllers are in compliance with the IEEE 802.3 and 802.3u standard. Each controller includes 8/12/16/24 independent 10/100 MACs, which interface with external PMD/PHYs through standard MII interfaces. Each port can operate at either 10Mbps or 100Mbps, which can be either automatically configured or manually set. The ACD300xx segregates each port into independent collision domains, which allows multi-level cascading and effectively removes the 205 meter network-diameter limitation imposed on a traditional Dual-Speed hub based networks. The non-blocking Dual-Speed "Super Class" hub manager can simultaneously bridge up to 24 asynchronous 10/100Mbps ports, with an aggregated throughput of up to 2.4 Gbps, or effectively 50 times faster than a traditional Dual-Speed hub. A complete 10/100 Dual-Speed "Super Class" Hub can be built with the use of the ACD300xx, 10/100 PHYs and SRAM. Dual-Speed "Super Class" Hubs with advanced features can also be implemented with the use of interfaces for optional external ARL (Address Resolution Logic), external MIB (Management Information Base), control CPU and management CPU. MAJOR FEATURES * * * * * * * * * * * * * * 8/12/16/24 ports, 10/100 auto-sensing with a MII interface Half-duplex operation on each port Non-blocking bridging with up to 2.4 Gbps (24 ports) aggregated throughput Built-in storage of 2,048 MAC address Automatic address management Back-pressure flow control Store-and-forward operation mode Wire speed forwarding rate Port based V-LAN support Interfaces for optional external ARL, MIB & CPU Status LEDs: Link, Speed, Transmit, Receive, Collision and Frame Error 388-pin PBGA for 8/12-port, 576-pin PBGA for 16/24-port Single 3.3V power supply 3.3V I/O with 5V tolerance ACD300xx Functional Block Diagram MAC Lookup Engine (2K MAC Addr.) LED Controller To LED Driver MAC MX Dual Speed "Super Class" Hub Manager To 10/100 PHYs DMX MAC SRAM Interface Other Other Other Interfaces Interfaces Interfaces MAC To Frame Buffer SRAM Brochure - ACD300xx, 3/99 To Optional ARL, MIB & CPU 1 INTRODUCTORY GENERAL DESCRIPTION 352-pin PBGA Package for ACD30008/ACD30012 Top View 35 30 Advanced Comm. Devices FLLLLL SMAYYWW INTRODUCTORY ACD30008/12 Side View 2.33 0.56 0.6 Bottom View 31.75 1.27 0.635 0.75 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 Brochure - ACD300xx, 3/99 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 576-pin PBGA Package for ACD30016/ACD30024 Top View Advanced Comm. Devices FLLLLLSMAYYWW INTRODUCTORY ACD30016/24 34.50 40.00+/-0.20 Side View o.56 0.60+/-0.05 2.33+/-0.13 Bottom View AA A B C D E F G H J K L M N P R T U V W Y AC AE AG AJ AB AD AF AH AK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1.27 0.75+/-0.15 36.83 Brochure - ACD300xx, 3/99 3