©2003 Silicon Storage T echnology, Inc.
S71150-07-000 11/03
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
512 Kbit / 1 Mbi t / 2 Mbi t / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
FEATURES:
Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8
Single Voltage Read and Write Operations
3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption
(typical values at 14 MHz)
Active Current: 5 mA (typical)
Standby Current: 1 µA (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
45 ns for SST39LF5 12/0 10/ 020/ 040
55 ns for SST39LF0 20/0 40
70 and 90 ns for SST39VF512/010/020/040
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical )
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
CMOS I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm )
48-ball TFBGA (6mm x 8mm) for 1M and 2M
34-ball WFBGA (4mm x 6mm) for 1M and 2M
PRODUCT DESCRIPTION
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are 64K x8, 128K x8, 256K x8 and 5124K x8
CMOS Multi-Purpose Flash (MPF) manufactured with
SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/ 040 devices wr ite (Program or Erase) with a 3.0-
3.6V power supply. The SST39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts f or x8 memories.
Featuring high performance Byte-Program, the
SST39LF512/010/020/040 and SST39VF512/010/020/
040 d evices provide a ma ximum Byte -Program time of 2 0
µsec. These devices use Toggle Bit or Data# P olling to indi-
cate the completion of Program operation. To protect
agains t inad ver tent wr ite, t hey have on-c hip har dware an d
Software Data Protection schemes. Designed, manufac-
tured, a nd tes ted for a wide spe ctr um of a pplic atio ns, they
are offered with a guaranteed typical endurance of 10,000
cycles . Data retention is rated at greater than 100 years.
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices are suited for applications that require
convenient and economical updating of program, configu-
ration, or data memory. For all system applications, they
significantly impro ves perf ormance and reliability, while low-
ering power consumption. The y inherently use less energy
dur ing Eras e and P rogram tha n alternative flash techn olo-
gies. The total energy consumed is a function of the
applied volt age, current, a nd time of app lication. S ince for
any given voltage range, the SuperFla sh techno logy uses
less c urrent to program and has a shor ter erase tim e, the
total energy consumed during any Erase or Progr am oper-
ation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications .
The S upe r Flas h te ch no logy pr ovid es fi xed Erase an d P r o-
gram times, in depen dent o f the num ber of Erase/ Pro gram
cycles that have occurred. Therefore the system software
or hardware does not ha v e to be modified or de-rated as is
nec essary with al tern ativ e flas h techno logies , whose E rase
and Pr ogram tim es inc rease with accumul ated Erase/Pr o-
gr am cycles .
To meet surface mount requirements, the SST39LF512/
010/020/040 and SST39VF512/010/020/040 devices are
off ered in 32-lead PLCC and 32-lead TSOP packages . The
SST39LF/VF010 and SST39LF/VF020 are also offered in
a 48-ball TFBGA package. See Figures 1, 2, 3, and 4 for
pin assignments.
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
2
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
Device Operatio n
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asse rtin g WE# low while keepi ng CE#
low. The address b us is latched on the f alling edge of WE#
or CE#, whichever oc curs l ast. T he data bus is latc hed o n
the rising edge of WE# or CE#, whichev er occurs first.
Read
The Rea d op era tio n o f the S ST3 9LF 5 12/ 01 0/0 20/ 040 an d
SST39VF512/010/020/040 device is controlled by CE#
and OE#, both hav e to be low for the system to obtain data
from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. Refer to the
Read cycl e timing diagra m f or furth er details (Fig ure 5).
Byte-P rogram Opera ti on
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 are programmed on a byte-by-byte basis. Before
programming, the sector where the byte exists must be
fully erased. The Program operation is accomplished in
three s teps. The first step is the thr ee-byte load s equenc e
for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichev er
occurs first. The third step is the internal Progr am operation
which is i niti ate d a fte r t he rising edge of the fourth WE# or
CE#, whic hever occur s firs t. The Pr ogram operat ion, on ce
initiated, will be completed, within 20 µs. See Figures 6 and
7 for WE# and CE# controlled Program operation timing
diagrams and Figure 16 f or flowcharts. During the Program
operatio n, the only valid reads ar e Data# Poll ing and Tog-
gle Bit. During the inter nal Program operation, the host is
free to perform additional tasks. Any commands written
during the internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector ba sis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The sector
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H) is latched on the rising
edge o f the si xt h WE # pulse. The inte r n al Era se op erat io n
begins after the sixth WE# pulse . The End-of-Erase can be
deter mined using either Data# Polling or Toggle Bit meth-
ods. See Figur e 10 for timing wavefor ms. Any commands
written during the Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the ‘1’s
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the risi ng ed ge of th e si xth WE # o r CE# , which eve r oc cu rs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# P olling. See Table 4 f or the command
sequenc e, Figur e 11 for ti ming diagram, an d Fi gure 19 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Write Opera ti on Status De te ct ion
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 devices provide two software means to detect the
completion of a Write (Program or Erase) cycle, in order to
optimize the system write cycle time. The software detec-
tion in cl ud es two s ta tus b it s: Dat a# Poll in g (D Q 7) and Tog-
gle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Pro-
gr am or E rase op er ation.
The act ual co mple tion of the nonvolatile wr ite is as ynchr o-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
3
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
Data# Polling (DQ7)
When the SST39LF512/010/020/040 and SST39VF512/
010/020/040 are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once th e Pr ogram operation is c omplete d, D Q7
will produce true data. Note that even though DQ7 may
have valid data immediately following completion of an
internal Write operation, the remaining data outputs may
still be invalid: valid dat a on the entir e d ata bus wi ll a ppe ar
in subsequent successive Read cycles after an interval of 1
µs. During internal Erase operation, any attempt to read
DQ7 will produce a “0”. Once the internal Erase operation is
completed, DQ7 will produce a “1”. The Data# Polling is
valid aft er the rising edge of four th WE # (or CE#) pul se for
Program operation. For Sector- or Chip-Erase, the Data#
Po lling is valid a fter the risi ng edge o f sixth W E# (or CE #)
pulse. See Figure 8 for Data# Polling timing diagram and
Figure 17 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to rea d DQ6 will produce alternating ‘0’s
and ‘1’s, i.e., toggli ng between 0 and 1. Whe n the inte r nal
Program or E rase ope ration is com plete d, the toggl ing wi ll
stop. The device is t hen ready for the n ext operation. Th e
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 9 f or Toggle Bit timing dia-
gr am an d Figu re 17 f or a flo wcha rt.
Data Protection
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide both hardware and software features to
pro tect no nv ol atile d ata fr om inad ve rte nt writes .
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pu lse of less t han 5
ns will not ini tiate a Wri te cycle .
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will in hi bit t he Write operation . T hi s prevents inadvert-
ent w rites durin g pow er-u p or po wer- dow n.
Software Data Protection (SDP)
The SST39LF512/010/020/040 and SST39VF512/010/
020/040 provide the JEDEC approved Software Data Pro-
tection scheme for all data alteration operation, i.e., Pro-
gram and Erase. Any Program operation requires the
inclusion of a series of three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadver tent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase op erat io n requires the i nc lus io n of six-byte load
sequence. These devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequ ence, invalid com mands w ill abor t the device to read
mode, within TRC.
Product Identifica tion
The Product Identification mode identifies the devices as
the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020
and SST39LF/VF040 and manufacturer as SST. This
mode may be accessed by software operations. Users
may use the Software Product Identification operation to
identify the part (i.e ., using the device ID) when using m ulti-
ple manufacturers in the same socket. For details, see
Table 4 for software operation, Figure 12 for the Software
ID Entr y and Read timing diagram, and Figure 18 for the
Software ID entry command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Produc t Ident ificati on mode must be exited. Exit is acco m-
plished by issuing the Software ID Exit command
sequence , which returns the device to the Read operation.
Please note that the Soft ware ID E xit command is ig nor e d
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 13 for timing wave-
f orm, and Figure 18 for a flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST39LF/VF512 0001H D4H
SST39LF/VF010 0001H D5H
SST39LF/VF020 0001H D6H
SST39LF/VF040 0001H D7H
T1.1 1150
4
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD PLCC
Y-Decoder
I/O Buffers and Data Latches
1150 B1.1
Address Buffers & Latches
X-Decoder
DQ7 - DQ0
Memory Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
FUNCTIONAL BLOCK DIAGRAM
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
4 3 2 1 32 31 30
A12
A15
NC
NC
VDD
WE#
NC
A12
A15
A16
NC
VDD
WE#
NC
A12
A15
A16
NC
VDD
WE#
A17
A12
A15
A16
A18
VDD
WE#
A17
32-lead PLCC
Top View
1150 32-plcc NH P4.3
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512
SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
5
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
FIGURE 3: PIN ASSIGNMENT FOR 48-BALL TFBGA (6MM X 8MM) FOR 1 MBIT AND 2 MBIT
FIGURE 4: PIN ASSIGNMENT FOR 34-BALL WFBGA (4MM X 6MM) FOR 1 MBIT AND 2 MBIT
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
NC
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
SST39LF/VF512SST39LF/VF010SST39LF/VF020SST39LF/VF040 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040SST39LF/VF512
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1150 32-tsop WH P1.0
Standard Pinout
Top View
Die Up
1150 48-tfbga B3K P2.0
A B C D E F G H
SST39LF/VF010
6
5
4
3
2
1
TOP VIEW (balls facing down)
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
NC
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
NC
NC
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
VDD
VDD
NC
OE#
VSS
DQ7
DQ4
NC
DQ1
VSS
1150 48-tfbga B3K P3.0
A B C D E F G H
SST39LF/VF020
6
5
4
3
2
1
TOP VIEW (balls facing down)
A14
A9
WE#
NC
A7
A3
A13
A8
NC
NC
NC
A4
A15
A11
NC
NC
A6
A2
A16
A12
NC
NC
A5
A1
A17
NC
DQ5
DQ2
DQ0
A0
NC
A10
NC
DQ3
NC
CE#
NC
DQ6
VDD
VDD
NC
OE#
VSS
DQ7
DQ4
NC
DQ1
VSS
A2
A1
A0
CE#
VSS
A17
VDD
A16
A12
A8
A14
WE#
A18
A15
A6
A9
A13
A7
A5
A11
A4
NC1
NC2
OE#
A3
A10
DQ7
A0
A2
CE#
DQ5
DQ3
DQ2
DQ0
A1
DQ6
DQ4
VSS
DQ1
TOP VIEW (balls facing down)
Note: For SST39LF020, ball B3 is "No Connect"
For SST39LF010, balls B3 and A5 are "No Connect"
A B C D E F G H J
6
5
4
3
2
1
1150 34-wfbga MM P5.0
6
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
TABLE 2: PIN DESCRIPTION
Symbol Pin Name Functions
AMS1-A0Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 addre ss l ine s w ill s ele ct the
sector. During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040
2.7-3.6V for SST39VF512/010/020/040
VSS Ground
NC No Connection Unconnected pins.
T2.1 1150
1. AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
TABLE 3: OPERATION MODES SELECTION
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector address,
XXH for Chip-Erase
Standby VIH XXHigh Z X
Write Inhibit X VIL XHigh Z/ D
OUT X
XXV
IH High Z/ DOUT X
Product Identification
Softw are Mode VIL VIL VIH See Table 4
T3.4 1150
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
7
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence 1st Bus
Write Cycle 2nd Bus
Write Cycle 3rd Bus
Write Cycle 4th Bus
Write Cycle 5th Bus
Write Cycle 6th Bus
Write Cycle
Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data
Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2Data
Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX330H
Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Softw are ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H
Softw are ID Exit6XXH F0H
Softw are ID Exit65555H AAH 2AAAH 55H 5555H F0H
T4.2 1150
1. Address format A14-A0 (Hex),
Address A15 can be V IL or VIH, but no other value, for the Command sequence for SST39LF/VF512.
Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
2. BA = Program By te address
3. SAX for Sector-Erase; uses AMS-A12 address lines
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST39LF/VF512 Device ID = D4H, is read with A0 = 1,
SST39LF/VF010 Device ID = D5H, is read with A0 = 1,
SST39LF/VF020 Device ID = D6H, is read with A0 = 1,
SST39LF/VF040 Device ID = D7H, is read with A0 = 1.
6. Both Software ID Exit operations are equivalent
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operatio n
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on An y Pin to G round Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Pac kage Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Output Short Circuit Cur rent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shor ted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE FOR SST39LF 512/010 /020/040
Range Ambient Temp VDD
Commercial 0°C to +70°C 3.0-3.6V
OPERATING RANGE FOR SST39V F512/010/020 /040
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load
CL = 30 pF for SST39LF512/010/020/040
CL = 100 pF for SST39VF512/010/020/040
See Figures 14 and 15
8
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
TABLE 5: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/0401
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
Read220 mA CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase330 mA CE#=WE#=VIL, OE #=VIH
ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T5.7 1150
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 3V for VF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the
Multi-Purpose Flash P ower Rating
application note fo r further information.
3. 30 mA max for Erase operations in the industrial temperature range.
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T6.1 1150
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T7.0 1150
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1,2
1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD m A JED EC Standard 78
T8.3 1150
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
9
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
AC CHARACTERISTICS
TABLE 9: READ CYCLE TIMING PARAMETERS
VDD = 3.0-3.6V FOR SST39LF512/010/020/040 AND 2.7-3.6V FOR SST39VF512/010/020/040
Symbol Parameter
SST39LF512-45
SST39LF010-45
SST39LF020-45
SST39LF040-45 SST39LF020-55
SST39LF040-55
SST39VF512-70
SST39VF010-70
SST39VF020-70
SST39VF040-70
SST39VF512-90
SST39VF010-90
SST39VF020-90
SST39VF040-90
UnitsMin Max Min Max Min Max Min Max
TRC Read Cycle Time 45 55 70 90 ns
TCE Chip Enable Access Time 45 55 70 90 ns
TAA Address Access Time 45 55 70 90 ns
TOE Output Enable Access Time 30 30 35 45 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.
CE# Low to Active Output 0 0 0 0 ns
TOLZ1OE# Low to Active Output 0 0 0 0 ns
TCHZ1CE# High to High-Z Output 15 15 25 30 ns
TOHZ1OE# High to High-Z Output 15 15 25 30 ns
TOH1Output Hold from Address Change 0000ns
T9.2 1150
TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol Parameter Min Max Units
TBP Byte-Program Time 20 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# Hi gh Setup Ti me 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 40 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TSCE Chip-Erase 100 ms
T10.1 1150
10
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 5: READ CYCLE TIMING DIAGRAM
FIGURE 6: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
1150 F03.0
ADDRESS AMS-0
DQ7-0
WE#
OE#
CE# TCE
TRC TAA
TOE
TOLZVIH
HIGH-Z TCLZ TOH
TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
Note: AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A
17 for SST39LF/VF020 and A18 for SST39LF/VF040
1150 F04.0
ADDRESS AMS-0
DQ7-0
TDH
TWPH
TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
WE#
TBP
Note: AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A
17 for SST39LF/VF020 and A18 for SST39LF/VF040
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
11
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 7: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
FIGURE 8: DATA# POLLING TIMING DIAGRAM
1150 F05.0
ADDRESS AMS-0
DQ7-0
TDH
TCPH
TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
5555 2AAA 5555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
TBP
Note: AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A
17 for SST39LF/VF020 and A18 for SST39LF/VF040
1150 F06.0
ADDRESS AMS-0
DQ7DD# D# D
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
Note: AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A
17 for SST39LF/VF020 and A18 for SST39LF/VF040
12
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 9: TOGGLE BIT TIMING DIAGRAM
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1150 F07.0
ADDRESS AMS-0
DQ6
WE#
OE#
CE#
TOETOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010,
A
17 for SST39LF/VF020 and A18 for SST39LF/VF040
1150 F08.0
ADDRESS AMS-0
DQ7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 3055AA 80 AA
SAX
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
TWP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
SAX = Sector Address
AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
13
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 11: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
FIGURE 12: SOFTWARE ID ENTRY AND READ
1150 F17.0
ADDRESS AMS-0
DQ7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
AMS = Most significant address
A
MS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040
1150 F09.2
Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
ADDRESS A14-0
TIDA
DQ7-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-byte Sequence for
Software ID Entry
TWP
TWPH TAA
BF
Device ID
55AA 90
14
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 13: SOFTWARE ID EXIT AND RESET
1150 F10.0
ADDRESS A14-0
DQ7-0
TIDA
TWP
TWHP
WE#
SW0 SW1 SW2
5555 2AAA 5555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
AA 55 F0
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
15
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 15: A TEST LOAD EXAMPLE
1150 F12.1
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
A C test inputs are driven at VIHT (0.9 VDD) for a l ogic “1” and VILT (0.1 VDD) f or a logi c “0”. Measu rement reference points
f or inputs and outputs are VIT (0.5 VDD) and V OT (0.5 VDD). Input rise and f all times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1150 F11.1
TO TESTER
TO DUT
CL
16
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 16: BYTE-PROGRAM ALGORITHM
1150 F13.1
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
17
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 17: WAIT OPTIONS
1150 F14.0
Wait TBP,
TSCE, or TSE
Byte-Program/
Erase
Initiated
Internal Timer Toggle Bit
Ye s
Ye s
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
byte
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read byte
Is DQ7 =
true data?
Read DQ7
Byte-Program/
Erase
Initiated
Byte-Program/
Erase
Initiated
18
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 18: SOFTWARE ID COMMAND FLOWCHARTS
1150 F15.2
Load data: AAH
Address: 5555H
Software ID Entry
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 90H
Address: 5555H
Wait TIDA
Read Software ID
Load data: AAH
Address: 5555H
Software ID Exit &
Reset Command Sequence
Load data: 55H
Address: 2AAAH
Load data: F0H
Address: 5555H
Load data: F0H
Address: XXH
Return to normal
operation
Wait TIDA
Wait TIDA
Return to normal
operation
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
19
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
FIGURE 19: ERASE COMMAND SEQUENCE
1150 F16.1
Load data: AAH
Address: 5555H
Chip-Erase
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: AAH
Address: 5555H
Wait TSCE
Chip erased
to FFH
Load data: AAH
Address: 5555H
Sector-Erase
Command Sequence
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 30H
Address: SAX
Load data: AAH
Address: 5555H
Wait TSE
Sector erased
to FFH
20
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
PRODUCT ORDERING INFORMATION
Environmental Attribute
E = non-Pb
Package Modifier
H = 32 leads
K = 48 balls
M = 34 balls (54 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
N = PLCC
M = WFBGA (0.5mm pitch, 4mm x 6mm)
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
512 = 512 Kbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Product Serie s
39 = Multi-Purpose Flash
SST39LF 040 -45-4C- NH E
XX XXXXXX-XXX -XX-XXX X
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
21
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
Valid combinations for SST39LF512
SST39LF512-45-4C-NH SST39LF512-45-4C-WH
SST39LF512-45-4C-NHE SST39LF512-45-4C-WHE
Valid combinations for SST39VF512
SST39VF512-70-4C-NH SST39VF512-70-4C-WH
SST39VF512-70-4C-NHE SST39VF512-70-4C-WHE
SST39VF512-90-4C-NHSST39VF512-90-4C-WH
SST39VF512-90-4C-NHESST39VF512-90-4C-WHE
SST39VF512-70-4I-NH SST39VF512-70-4I-WH
SST39VF512-70-4I-NHE SST39VF512-70-4I-WHE
SST39VF512-90-4I-NHSST39VF512-90-4I-WH
SST39VF512-90-4I-NHESST39VF512-90-4I-WHE
Valid combinations for SST39LF010
SST39LF010-45-4C-NH SST39LF010-45-4C-WH SST39LF010-45-4C-B3K SST39LF010-45-4C-MM
SST39LF010-45-4C-NHE SST39LF010-45-4C-WHE SST39LF010-45-4C-B3KE SST39LF010-45-4C-MME
Valid combinations for SST39VF010
SST39VF010-70-4C-NH SST39VF010-70-4C-WH SST39VF010-70-4C-B3K
SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE SST39VF010-70-4C-B3KE
SST39VF010-90-4C-NHSST39VF010-90-4C-WHSST39VF010-90-4C-B3K
SST39VF010-90-4C-NHESST39VF010-90-4C-WHESST39VF010-90-4C-B3KE
SST39VF010-70-4I-NH SST39VF010-70-4I-WH SST39VF010-70-4I-B3K
SST39VF010-70-4I-NHE SST39VF010-70-4I-WHE SST39VF010-70-4I-B3KE
SST39VF010-90-4I-NHSST39VF010-90-4I-WHSST39VF010-90-4I-B3K
SST39VF010-90-4I-NHESST39VF010-90-4I-WHESST39VF010-90-4I-B3KE
Valid combinations for SST39LF020
SST39LF020-45-4C-NH SST39LF020-45-4C-WH SST39LF020-45-4C-B3K SST39LF020-45-4C-MM
SST39LF020-45-4C-NHE SST39LF020-45-4C-WHE SST39LF020-45-4C-B3KE SST39LF020-45-4C-MME
SST39LF020-55-4C-NH SST39LF020-55-4C-WH
SST39LF020-55-4C-NHE SST39LF020-55-4C-WHE
Valid combinations for SST39VF020
SST39VF020-70-4C-NH SST39VF020-70-4C-WH SST39VF020-70-4C-B3K
SST39VF020-70-4C-NHE SST39VF020-70-4C-WHE SST39VF020-70-4C-B3KE
SST39VF020-90-4C-NHSST39VF020-90-4C-WHSST39VF020-90-4C-B3K
SST39VF020-90-4C-NHESST39VF020-90-4C-WHESST39VF020-90-4C-B3KE
SST39VF020-70-4I-NH SST39VF020-70-4I-WH SST39VF020-70-4I-B3K
SST39VF020-70-4I-NHE SST39VF020-70-4I-WHE SST39VF020-70-4I-B3KE
SST39VF020-90-4I-NHSST39VF020-90-4I-WHSST39VF020-90-4I-B3K
SST39VF020-90-4I-NHESST39VF020-90-4I-WHESST39VF020-90-4I-B3KE
Valid combinations for SST39LF040
SST39LF040-45-4C-NH SST39LF040-45-4C-WH
SST39LF040-45-4C-NHE SST39LF040-45-4C-WHE
SST39LF040-55-4C-NH SST39LF040-55-4C-WH
SST39LF040-55-4C-NHE SST39LF040-55-4C-WHE
22
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
Valid combinations for SST39VF040
SST39VF040-70-4C-NH SST39VF040-70-4C-WH
SST39VF040-70-4C-NHE SST39VF040-70-4C-WHE
SST39VF040-90-4C-NHSST39VF040-90-4C-WH
SST39VF040-90-4C-NHESST39VF040-90-4C-WHE
SST39VF040-70-4I-NH SST39VF040-70-4I-WH
SST39VF040-70-4I-NHE SST39VF040-70-4I-WHE
SST39VF040-90-4I-NHSST39VF040-90-4I-WH
SST39VF040-90-4I-NHESST39VF040-90-4I-WHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
These 90 ns parts will be phased out and replaced by 70 ns parts in 2004.
Customers should use 70 ns parts for new designs and qualifications.
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
23
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
PACKAGING DIAGRAMS
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)
SST PACKAGE CODE: NH
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
.040
.030
.021
.013 .530
.490
.095
.075
.140
.125
.032
.026
.032
.026
.029
.023
.453
.447
.553
.547
.595
.585
.495
.485 .112
.106
.042
.048
.048
.042
.015 Min.
T OP VIEW SIDE VIEW BO TT OM VIEW
1232
.400
BSC
32-plcc-NH-3
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
.050
BSC
.050
BSC
Optional
Pin #1
Identifier .020 R.
MAX. R.
x 30˚
A1 CORNER
H G F E D C B A
A B C D E F G H
BOTTOM VIEWTOP VIEW
SIDE VIEW
6
5
4
3
2
1
6
5
4
3
2
1
SEATING PLANE
0.35 ± 0.05
1.10 ± 0.10
0.12
6.00 ± 0.20
0.45 ± 0.05
(48X)
A1 CORNER
8.00 ± 0.20
0.80
4.00
0.80
5.60
48-tfbga-B3K-6x8-450mic-4
Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
1mm
24
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
32-tsop-WH-7
Note: 1.Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2.All linear dimensions are in millimeters (max/min).
3.Coplanarity: 0.1 mm
4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
1.20
max.
1mm
Pin # 1 Identifier
12.50
12.30
14.20
13.80
0.70
0.50
8.10
7.90 0.27
0.17
0.50
BSC
1.05
0.95
0.15
0.05
0.70
0.50
0˚- 5˚
DETAIL
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
25
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
34-BALL VERY-VERY-THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (WFBGA) 4MM X 6MM
SST PACKAGE CODE: MM
J H G F E D C B A
ABCDEFGHJ
6
5
4
3
2
1
6
5
4
3
2
1
0.50
0.50
BOTTOM VIEW
4.00 ± 0.08
0.32 ± 0.05
(34X)
A1 INDICATOR4
6.00 ± 0.08
2.50
4.00
A1 CORNER
TOP VIEW
34-wfbga-MM-4x6-32mic-1
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No ball is present in position A1; a gold-colored indicator is present.
5. Ball opening size is 0.29 mm (± 0.05 mm)
1mm
DETAIL SIDE VIEW
SEATING PLANE
0.20 ± 0.06
0.63 ± 0.10
0.08
26
Data Sheet
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
©2003 Silicon Storage Technology, Inc. S71150-07-000 11/03
TABLE 11: REVISION HISTORY
Number Description Date
01 2000 Data Book Feb 2000
02 Changed speed from 45 ns to 55 ns for the SST39LF020 and SST39LF040 Aug 2000
03 2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040 Feb 2002
04 Added the B3K package for the 2 Mbit devices
Added footnote in Table 5 to indicate IDD Write is 30 mA max for Erase operations in
the Industrial temperature range.
Oct 2002
05 Changes to Table 5 on page 8
Added footnote for MPF power usage and Typical conditions
Clarified the Test Conditions for Pow er Supply Current and Read parameters
–Clarified I
DD Write to be Program and Erase
Corrected IDD Program and Erase from 20 mA to 30 mA
Part number changes - see page 21 for additional information
Mar 2003
06 Added new “MM Micro-Package MPNs for 1M and 2M LF parts- see page 21 Oct 200 3
07 2004 Data Book
Added non-Pb MPNs and removed footnote (See page 21)
Updated B3K and MM package diagrams
Nov 2003
Silicon Stor age Technol ogy, In c. • 117 1 Sonor a C ourt • Sunnyvale , CA 940 86 • Telephone 408-73 5-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com