TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET Check for Samples: TPS54386-Q1 FEATURES APPLICATIONS * * * * 1 23 * * * * * * * * * * * * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 2: -40C to +105C Ambient Operating Temperature - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C3B 4.5-V to 28-V Input Range Output Voltage Range 0.8 V to 90% of Input Voltage Output Current Up to 3 A Fixed Switching Frequency: 600 kHz Three Selectable Levels of Overcurrent Protection (Output 2) 0.8-V 1.5% Voltage Reference 2.1-ms Internal Soft Start Dual PWM Outputs 180 Out-of-Phase Ratiometric or Sequential Startup Modes Selectable by a Single Pin 85-m Internal High-Side MOSFETs Current Mode Control Internal Compensation Pulse-by-Pulse Overcurrent Protection Thermal Shutdown Protection at 148C 14-Pin PowerPADTM HTSSOP Package Power for DSP Consumer Electronics CONTENTS Device Ratings 2 Electrical Characteristics 3 Device Information 9 Application Information 12 Design Examples 32 Additional References 44 DESCRIPTION The TPS54386-Q1 are dual-output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4.5-V to 28-V input supply voltage, and require output voltages between 0.8 V and 90% of the input voltage. With an internally-determined operating frequency, soft-start time, and control-loop compensation, these converters provide many features with a minimum of external components. Channel-1 overcurrent protection is set at 4.5 A, whereas the channel-2 overcurrent protection level is selected by connecting a pin to ground, to BP, or left floating. The setting levels are used to allow for scaling of external components for applications that do not need the full load capability of both outputs. The outputs may be enabled independently, or may be configured to allow either ratiometric or sequential start-up sequencing. Additionally, the two outputs may be powered from different sources. VIN TPS54386 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 3 SW1 SW2 12 4 GND BP 11 5 EN1 6 EN2 7 FB1 OUTPUT1 SEQ 10 ILIM2 9 FB2 8 GND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012, Texas Instruments Incorporated TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. ORDERING INFORMATION (1) PART NUMBER OPERATING FREQUENCY (kHz) PACKAGE MEDIA UNITS TOP-SIDE MARKING TPS54386TPWPRQ1 600 14-HTSSOP package Tape and reel 2000 54386T (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS (1) VALUE PVDD1, PVDD2, EN1, EN2 Input voltage range UNIT 30 BOOT1, BOOT2 VSW+ 7 SW1, SW2 -2 to 30 SW1, SW2 transient (< 50 ns) -3 to 31 BP V 6.5 SEQ, ILIM2 -0.3 to 6.5 FB1, FB2 -0.3 to 3 SW1, SW2 output current 7 A BP load current 35 mA Tstg Storage temperature -55 to 165 C TA Operating temperature -40 to 105 C 2 kv 750 V Human Body Model (HBM) AEC-Q100 Classification Level H2 ESD ratings (1) Charged Device Model (CDM) AEC-Q100 Classification Level C3B Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VPVDD2 Input voltage 4.5 28 V TA Operating junction temperature -40 125 C PACKAGE DISSIPATION RATINGS (1) (1) (2) (3) (4) 2 (2) (3) PACKAGE THERMAL IMPEDANCE JUNTION-TO-THERMAL PAD (C/W) TA = 25C POWER RATING (W) TA = 105C POWER RATING (W) Plastic 14-Pin HTSSOP (PWP) 2.07 (4) 1.6 0.8 For more information on the PWP package, see TI Technical Brief (SLMA002A). TI device packages are modeled and tested for thermal performance using printed circuit board designs outlined in JEDEC standards JESD 51-3 and JESD 51-7. For application information, see the Power Derating section. TJ-A = 40C/W. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS -40C TA 105C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY (PVDD) VPVDD1 VPVDD2 Input voltage range 4.5 28 4.5 28 V A IDDSDN Shutdown V EN1 = V EN2 = VPVDD2 70 150 IDDQ Quiescent, non-switching VFB = 0.9 V, outputs off 1.8 3 IDDSW Quiescent, while-switching SW node unloaded; Measured as BP sink current VUVLO Minimum turnon voltage PVDD2 only VUVLO(hys) Hysteresis tSTART (1) (2) CBP = 10 F, EN1 and EN2 go low simultaneously Time from start-up to soft-start begin mA 5 3.8 4.1 V 4.4 V 400 mV 2 ms ENABLE (EN) VEN1 Enable threshold VEN2 0.9 1.2 1.5 0.9 1.2 1.5 Hysteresis IEN1 IEN2 tEN (1) 50 Enable pullup current V EN1 = V EN2 = 0 V Time from enable to soft-start begin Other EN pin = GND V V mV 6 12 A 6 12 A s 10 BP REGULATOR (BP) BP BPLDO IBP (1) IBPS Regulator voltage 8 V < PVDD2 < 28 V Dropout voltage PVDD2 = 4.5 V; switching, no external load on BP 5 5.25 400 Regulator external load Regulator short circuit 4.5 V < PVDD2 < 28 V 5.6 V mV 2 mA 10 20 30 mA 510 630 750 kHz OSCILLATOR fSW Switching frequency tDEAD (1) Clock dead time 140 ns ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF) VFB1 Feedback input voltage VFB2 IFB1 0C < TA < 85C 788 -40C < TA < 125C 786 Feedback input bias current IFB2 gM1 (1) gM2 (1) Transconductance 800 812 mV 812 mV 3 50 nA 3 50 nA 30 S 30 S SOFT START (SS) TSS1 Soft-start time TSS2 1.5 2.1 2.7 ms 1.5 2.1 2.7 ms 3.6 4.5 5.6 A 3.6 4.5 5.6 OVERCURRENT PROTECTION ICL1 Current limit channel 1 VILIM2 = VBP ICL2 Current limit channel 2 VILIM2 = (floating) VILIM2 = GND VUV1 Low-level output threshold to declare a fault VUV2 tHICCUP (1) tON1(oc) (1) tON2(oc) (1) (1) (2) Measured at feedback pin Hiccup timeout 2.4 3 3.6 1.15 1.5 1.75 670 mV 670 mV 10 Minimum overcurrent pulse duration A ms 90 150 ns 90 150 ns Ensured by design. Not production tested. When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value. More information can be found in the Input UVLO and Startup section. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 3 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) -40C TA 105C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOTSTRAP RBOOT1 Bootstrap switch resistance RBOOT2 From BP to BOOT1 or BP to BOOT2, IEXT = 50 mA 18 TA = 25C, VPVDD2 = 8 V 85 -40C < TA < 125C, VPVDD2 = 8 V 85 165 100 200 OUTPUT STAGE (Channel 1 and Channel 2) rDS(on) (3) MOSFET on-resistance plus bond-wire resistance (3) Minimum controllable pulse duration ISWx peak current > 1 A (4) DMIN Minimum duty cycle VFB = 0.9 V DMAX Maximum duty cycle fSW = 600 kHz ISW Switching-node leakage current (sourcing) Outputs OFF tON(min) m ns 0% 85% 90% 2 12 A THERMAL SHUTDOWN TSD (3) TSD(hys) (3) (4) 4 Shutdown temperature (3) Hysteresis 148 C 20 C Ensured by design. Not production tested. See Figure 14 for ISWx peak current <1 A. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS QUIESCENT CURRENT (NON-SWITCHING) vs JUNCTION TEMPERATURE SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 2.1 140 VBP = 5.25 V VPVDDx = 28 V 120 VPVDDx = 12 V ISD - Shutdown Current - mA IDDQ - Quiescent Current - mA 2.0 1.9 1.8 1.7 1.6 1.5 -50 100 80 60 40 VPVDDx = 4.5 V 20 -25 0 25 50 75 100 0 -50 125 -25 TJ - Junction Temperature - C 0 25 50 75 100 125 100 125 TJ - Junction Temperature - C Figure 1. Figure 2. UNDERVOLTAGE LOCKOUT THRESHOLD vs JUNCTION TEMPERATURE ENABLE THRESHOLDS vs JUNCTION TEMPERATURE 4.2 1.25 4.1 VEN - Enable Threshold Voltage - V VUVLO - Undervoltage Lockout - V EN(Off) UVLO(On) 4.0 3.9 UVLO(Off) 3.8 3.7 3.6 -50 -25 0 25 50 75 100 125 1.23 1.21 EN(On) 1.19 1.17 1.15 -50 -25 TJ - Junction Temperature - C Figure 3. 0 25 50 75 TJ - Junction Temperature - C Figure 4. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 5 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SOFT-START TIME vs JUNCTION TEMPERATURE SWITCHING FREQUENCY (300 kHz) vs JUNCTION TEMPERATURE 3.5 350 VBP = 5.25 V fPWM - PWM Frequency - kHz tSS - Soft Start Time - ms VBP = 5.25 V 3.0 2.5 2.0 1.5 -50 -25 0 25 50 75 100 330 310 290 270 -50 125 -25 0 25 50 75 100 125 100 125 TJ - Junction Temperature - C TJ - Junction Temperature - C Figure 5. Figure 6. SWITCHING FREQUENCY (600 kHz) vs JUNCTION TEMPERATURE FEEDBACK BIAS CURRENT vs JUNCTION TEMPERATURE 680 5 VBP = 5.25 V IFB - Feedback Bias Current - nA fPWM - PWM Frequency - kHz 660 640 620 600 580 -50 -25 0 25 50 75 100 125 3 1 -1 -3 -5 -50 -25 TJ - Junction Temperature - C Figure 7. 6 0 25 50 75 TJ - Junction Temperature - C Figure 8. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL) vs JUNCTION TEMPERATURE 4.8 808 803 ICL - Overcurrent Limit - A VFB - Feedback Voltage - mV VPVDD = 24 V 798 793 788 -50 -25 0 25 50 75 100 4.6 VPVDD = 12 V 4.4 VPVDD = 5 V 4.2 4.0 -50 125 0 -25 25 50 100 Figure 9. Figure 10. OVERCURRENT LIMIT (CH2 MID-LEVEL) vs JUNCTION TEMPERATURE OVERCURRENT LIMIT (CH2 LOW LEVEL) vs JUNCTION TEMPERATURE 125 1.8 3.4 VPVDDx = 24 V VPVDDx = 24 V 3.2 ICL - Overcurrent Limit - A ICL - Overcurrent Limit - A 75 TJ - Junction Temperature - C TJ - Junction Temperature - C 3.0 2.8 1.6 1.4 VPVDDx = 12 V VPVDDx = 12 V VPVDDx = 5 V 2.6 -50 -25 0 25 50 75 VPVDDx = 5 V 100 125 1.2 -50 -25 TJ - Junction Temperature - C Figure 11. 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 12. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 7 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING NODE LEAKAGE CURRENT vs JUNCTION TEMPERATURE MINUMUM CONTROLLABLE PULSE DURATION vs LOAD CURRENT 400 tON - Minimum Controllable Pulse Width - ns ISW(off) - Switching Node Leakage Current - mA 5 4 3 2 1 -50 TA(C) TA = -40C 300 250 TA = 0C 200 150 TA = 25C 100 TA = 85C 50 -25 0 25 50 75 100 0 125 -40 0 25 85 350 0.2 0.4 TJ - Junction Temperature - C 0.6 0.8 1.0 IL - Load Current - A Figure 13. 1.2 1.4 Figure 14. OVERCURRENT LIMIT vs SUPPLY VOLTAGE 5.0 IOC - Overcurrent Limit - A 4.5 4.0 OCL = 3.0 A OCL = 4.5 A 3.5 3.0 2.5 OCL = 1.5 A 2.0 1.5 1.0 4 8 12 16 20 VDD - Supply Voltage - V 24 28 Figure 15. 8 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 DEVICE INFORMATION PIN CONNECTIONS HTSSOP (PWP) (Top View) PVDD1 1 14 PVDD2 BOOT1 2 13 BOOT2 SW1 3 12 SW2 Thermal Pad (bottom side) GND 4 EN1 5 11 BP 10 SEQ EN2 6 9 ILIM2 FB1 7 8 FB2 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BOOT1 2 I Input supply to the high-side gate driver for output 1. Connect a 22-nF to 82-nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 to 3 ) may be placed in series with the bootstrap capacitor. BOOT2 13 I Input supply to the high-side gate driver for output 2. Connect a 22-nF to 82-nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small resistor (1 to 3 ) may be placed in series with the bootstrap capacitor. BP 11 - Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR (4.7-F to 10-F X7R or X5R) ceramic capacitor. I Active-low enable input for output 1. If the voltage on this pin is greater than 1.55 V, output 1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables output 1 and allows soft-start of output 1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for always ON operation. I Active-low enable input for output 2. If the voltage on this pin is greater than 1.55 V, output 2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start of Output 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for always ON operation. I Voltage feedback pin for output 1. The internal transconductance error amplifier adjusts the PWM for output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from output 1 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided internally to the device. See the Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. EN1 EN2 FB1 5 6 7 FB2 8 I Voltage feedback pin for output 2. The internal transconductance error amplifier adjusts the PWM for output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from output 2 to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Compensation for the feedback loop is provided internally to the device. See the Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information. GND 4 - Ground pin for the device. Connect directly to the thermal pad. ILIM2 9 I Current limit adjust pin for output 2 only. This function is intended to allow a user with asymmetrical load currents (output 1 load current much greater than output 2 load current) to optimize component scaling of the lower-current output while maintaining proper component derating in a overcurrent fault condition. The discrete levels are available as shown in Table 3, Current Limit Threshold Adjustment for Output 2. Note: An internal 2-resistor divider (150-k each) connects BP to ILIM2 and to GND. PVDD1 1 I Power input to the output 1 high-side MOSFET only. This pin should be locally bypassed to GND with a low-ESR ceramic capacitor of 10-F or greater. I The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the output 2 high-side MOSFET. This pin should be locally bypassed to GND with a low-ESR ceramic capacitor of 10-F or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.1 V. PVDD2 14 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 9 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION SEQ 10 I This pin configures the output start-up mode. If the SEQ pin is connected to BP, then when output 2 is enabled, output 1 is allowed to start after output 2 has reached regulation; that is, sequential startup where output 1 is slave to output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN1 to ground. If the SEQ pin is connected to GND, then when output 1 is enabled, output 2 is allowed to start after output 1 has reached regulation; that is, sequential start-up where output 2 is slave to output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. For this sequence configuration, tie EN2 to ground. If left floating, output 1 and output 2 start ratiometrically when both outputs are enabled at the same time. They soft-start at a rate determined by their final output voltage and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently. NOTE: An internal two-resistor (150-k each) divider connects BP to SEQ and to GND. See the Sequence States table. SW1 3 O Source (switching) output for output 1 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. SW2 12 O Source (switching) output for output 2 PWM. A snubber is recommended to reduce ringing on this node. See SW Node Ringing for further information. Thermal pad - - This pad must be tied externally to a ground plane and the GND pin. 10 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 BLOCK DIAGRAM CLK1 Level Shift + FB1 BOOT1 1 PVDD1 3 SW1 Current Comparator f(IDRAIN1) + DC(ofst) GND 2 BP 4 + f(IDRAIN1) 7 S Q R R Q Overcurrent Comp + 0.8 VREF RCOMP Soft Start 1 SD1 f(ISLOPE1) BP f(IMAX1) CLK1 CCOMP Anti-Cross Conduction VDD2 Weak Pull-Down MOSFET f(ISLOPE1) Ramp Gen 1 TSD 6 mA EN1 5 EN2 6 1.2 MHz Oscilator 6 mA CLK1 Divide by 2/4 f(ISLOPE2) Ramp Gen 2 SD1 Internal Control SD2 CLK2 UVLO 150 kW SEQ 10 BP 150 kW FB1 Output Undervoltage Detect FB2 CLK2 13 BOOT2 BP Level Shift 14 PVDD2 Current Comparator f(IDRAIN2) + DC(ofst) + GND FB2 4 f(IDRAIN2) 8 RCOMP Soft Start 2 Q R R Q FET Switch Overcurrent Comp + 0.8 VREF + S SD2 f(ISLOPE2) f(IMAX2) CLK2 CCOMP 5.25-V Regulator BP 11 150 kW 12 SW2 BP Anti-Cross Conduction Weak Pull-Down MOSFET PVDD2 BP ILIM2 Level Select 9 150 kW References 0.8 VREF IMAX2 (Set to one of three limits) UDG-07124 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 11 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS54386-Q1 is a dual-output, non-synchronous converter. Each PWM channel contains an internally compensated error amplifier, current-mode pulse-width modulator (PWM), switch MOSFET, enable, and faultprotection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, clock oscillator, and output-voltage sequencing functions. DESIGN HINT The TPS54386-Q1 contains internal slope compensation and loop compensation components; therefore, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externallycompensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. (See the Feedback Loop and L-C Filter Selection section.) NOTE Unless otherwise noted, a label with a lowercase x appended implies the term applies to both outputs of the two modulator channels. For example, the term ENx implies both EN1 and EN2. Unless otherwise noted, all parametric values given are typical. See the Electrical Characteristics for minimum and maximum values. Calculations should be performed with tolerance values taken into consideration. Voltage Reference The band-gap cell common to both outputs, trimmed to 800 mV. Oscillator The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are internally configured to operate on alternating switch cycles (that is, 180 out of phase). Input Undervoltage Lockout (UVLO) and Startup When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turnon threshold, the state of the enable pins determines the remainder of the internal start-up sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start begins, depending on the SEQ mode of operation and the EN1 and EN2 settings. Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higher or lower than PVDD2. (See the Dual Supply Operation section.) Enable and Timed Turnon of the Outputs Each output has a dedicated (active-low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the associated output is enabled and soft-start is initiated. If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is shut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70 A at the 12-V input supply. An R-C circuit connected to an ENx pin may be used to delay the turnon of the associated output after power is applied to PVDDx (see Figure 16). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to PVDD2, then omit these two components and tie the ENx pin to GND directly. 12 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 If an R-C circuit is used to delay the turnon of the output, the resistor value must be much less than 1.2 V / 6 A or 200 k. A suggested value is 51 k. This resistor value allows the ENx voltage to decay below the 1.2-V threshold while the 6-A bias current flows. The capacitor value required to delay the start-up time (after the application of PVDD2) is shown in Equation 1. C= tDELAY farads ae V - 2 IENx R o R ln c IN / e VTH - IENx R o where: * * * R and C are the timing components. VTH is the 1.2-V enable threshold voltage. I ENx is the 6-A enable-pin biasing current. (1) Other enable-pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing section.) PVDD2 6 mA ENx C PVDDx + PVDDx R 1.2-V Threshold 1.2 V TPS5438x ENx VOUTx 0 tDELAY tDELAY + tSS T - Time Figure 16. Start-Up Delay Schematic Figure 17. Start-Up Delay With R-C on Enable DESIGN HINT If delayed output-voltage start-up is not necessary, simply connect EN1 and EN2 to GND. This configuration allows the outputs to start immediately on valid application of PVDD2. If ENx is allowed to go high after output x has been in regulation, the upper MOSFET shuts off, and the output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains in the OFF state. (See the Bootstrap for N-Channel MOSFET section.) Output-Voltage Sequencing The TPS54386-Q1 allows single-pin programming of output-voltage start-up sequencing. During power on, the state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behave as described in Table 2. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 13 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Table 2. Sequence States SEQ PIN STATE MODE EN1 EN2 Ignored by the device.when V EN2 < enable threshold voltage BP Sequential, output 2 then output 1 Tie EN1 to < enable threshold voltage for BP to be active when VEN2 > enable threshold voltage Active Tie EN1 to > enable threshold voltage for low quiescent current (BP inactive) when VEN2 > enable threshold voltage Ignored by the device.when V EN1 < enable threshold voltage GND Sequential, output 1 then output 2 Tie EN2 to < enable threshold voltage for BP to be active when VEN1 > enable threshold voltage Active Tie EN2 to > enable threshold voltage for low quiescent current (BP inactive) when V EN1 > enable threshold voltage (floating) Independent or ratiometric, output 1 and output 2 Active. EN1 and EN2 must be tied together for Ratio-metric startup. Active. EN1 and EN2 must be tied together for ratiometric start-up. If the SEQ pin is connected to BP, then when output 2 is enabled, output 1 is allowed to start approximately 400 s after output 2 has reached regulation; that is, sequential start-up where output 1 is slave to output 2. If EN2 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. If the SEQ pin is connected to GND, then when output 1 is enabled, output 2 is allowed to start approximately 400 s after output 1 has reached regulation; that is, sequential start-up where output 2 is slave to output 1. If EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the output voltages decay according to the load that is present. SEQ = BP Sequential CH2 then CH1 SEQ = GND Sequential CH1 then CH2 5-V VOUT1 (2 V/div) 5-V VOUT1 (2 V/div) 3.3-V VOUT2 (2 V/div) 3.3-V VOUT2 (2 V/div) T - Time - 1 ms/div T - Time - 1 ms/div Figure 18. SEQ Pin Tied to BP Figure 19. SEQ Pin Tied to GND NOTE An R-C network connected to the ENx pin may be used in addition to the SEQ pin in sequential mode to delay the start-up of the first output voltage. This approach may be necessary in systems with a large number of output voltages and elaborate voltagesequencing requirements. See Enable and Timed Turn On of the Outputs. 14 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 If the SEQ pin is left floating, output 1 and output 2 each start ratiometrically when both outputs are enabled at the same time. Output 1 and output 2 soft-start at a rate that is determined by the respective final output voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate independently. 5-V VOUT1 (2 V/div) 3.3-V VOUT2 (2 V/div) T - Time - 1 ms/div Figure 20. SEQ Pin Floating Soft Start Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft-start interval, the TPS54386-Q1 output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains at the reference voltage. NOTE To avoid a disturbance in the output voltage during the stepping of the digital soft-start, a minimum output capacitance of 50 F is recommended. See Feedback Loop and InductorCapacitor (L-C) Filter Selection. Once the filter and compensation components have been established, laboratory measurements of the physical design should be performed to confirm converter stability. During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the Output Overload Protection section.) There is no pulse-skipping if a current-limit pulse is not detected. DESIGN HINT If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed-delay start-up from the ENx pin to delay the start-up of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. See Operating Near Maximum Duty Cycle and Maximum Output Capacitance for related information. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 15 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Output Voltage Regulation Each output has a dedicated feedback loop comprising a voltage-setting divider, an error amplifier, a pulse-width modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (see Figure 21). Assuming the value of the upper resistor of the voltage-setting divider is known, the value of the lower divider resistor for a desired output voltage is calculated by Equation 2. VREF R2 = R1 VOUT - VREF where * VREF is the internal 0.8-V reference voltage. (2) TPS5438x 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 3 SW1 SW2 12 4 GND BP 11 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 OUTPUT1 R1 R2 UDG-07011 Figure 21. Feedback Network for Channel 1 DESIGN HINT There is a leakage current of up to 12 A out of the SW pin when a single output of the TPS54386-Q1 is disabled. Keeping the series impedance of R1 + R2 less than 50 k prevents the output from floating above the reference voltage while the controller output is in the OFF state. 16 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Feedback Loop and Inductor-Capacitor (L-C) Filter Selection In the feedback signal path, the output voltage-setting divider is followed by an internal gM-type error amplifier with a typical transconductance of 30 s. An internal series-connected R-C circuit from the gM amplifier output to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 22. NOTE Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse-width operation, especially at load currents less than 1 A. See SW Node Ringing for further information on reducing noise on the SWx node. TPS5438x BOOT ICOMP - ISLOPE Error Amplifier 0.8 VREF + + FB PWM to Switch x2 ISLOPE ICOMP Offset f(IDRAIN) RCOMP CCOMP SW 11.5 kW RCOMP (kW) CCOMP (pF) TPS54383 700 40 TPS54386 700 20 UDG-07012 Figure 22. Feedback-Loop Equivalent Circuit A more conventional small-signal equivalent block diagram is shown in Figure 23. Here, the full closed-loop signal path is shown. Because the TPS54386-Q1 contains internal slope-compensation and loop-compensation components, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally selected first, and the compensation network is found afterwards. To find the appropriate L and C filter combination, the output-to-Vc signal path plots (see the next section) of gain and phase are used along with other design criteria to aid in finding the combination that best results in a stable feedback loop. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 17 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com VIN VREF VC + VOUT + Modulator _ _ Filter Current Feedback Network Compensation Network Figure 23. Small-Signal Equivalent Block Diagram Inductor-Capacitor (L-C) Selection The following figures plot the TPS54386-Q1 output-to-Vc gain and phase versus frequency for various duty cycles (10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple-current levels. The loop response curve selected to compensate the loop is based on the duty cycle of the application and the ripple current in the inductor. Once the curve has been selected and the inductor value has been calculated, the output capacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A brief example follows the curves. Note that the internal error-amplifier compensation is optimized for output capacitors with an ESR zero frequency between 20 kHz and 60 kHz. See the following sections for further details. GAIN AND PHASE vs FREQUENCY GAIN AND PHASE vs FREQUENCY 100 270 85 225 100 270 225 55 135 40 90 25 45 Duty Cycle % Gain Phase 10 30 50 70 90 10 -5 -20 100 1k 60 -45 -90 1M 90 45 20 0 10 k 100 k f - Frequency - Hz 135 40 0 Figure 24. TPS54386-Q1 at 200-mApp Ripple Current 18 180 Phase - 180 Gain - dB 70 Phase - Gain - dB 80 Duty Cycle % Gain Phase 10 30 50 70 90 -20 100 1k 0 -45 10 k 100 k f - Frequency -Hz -90 1M Figure 25. TPS54386-Q1 at 400-mApp Ripple Current Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 GAIN AND PHASE vs FREQUENCY 85 225 70 180 55 135 40 90 45 25 10 -5 -20 100 Duty Cycle % Gain Phase 10 30 50 70 90 1k Phase - 270 Gain - dB 100 0 -45 10 k 100 k f - Frequency - Hz -90 1M Figure 26. TPS54386-Q1 at 600-mApp Ripple Current Maximum Output Capacitance With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before start-up problems begin to occur. If the output capacitance is large enough so that the device enters a current-limit protection mode during startup, then there is a possibility that the output will never reach regulation. Instead, the TPS54386-Q1 simply shuts down and attempts a restart as if the output were short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by Equation 3: R1 VREF (1 + R2 ) TS tSS R1 1 + ) COUTmax = I - VREF (1 + R2 ) (1 R VREF CLx 2 VIN L LOAD (3) Minimum Output Capacitance Ensure the value of capacitance selected for closed-loop stability is compatible with the requirements of Soft Start. Modifying The Feedback Loop Within the limits of the internal compensation, there is flexibility in the selection of the inductor and outputcapacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, thereby incerasing the required amount of output capacitance. A smaller capacitor could also be used, increasing the resonant frequency, and increasing the overall loop bandwidth--perhaps at the expense of adequate phase margin. The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between 20 kHz and 60 kHz. It is possible, with additional feedback compensation components, to use capacitors with higher or lower ESR zero frequencies. For either case, the components C1 and R3 (see Figure 30) are added to recompensate the feedback loop for stability. In this configuration, a low frequency pole is followed by a higherfrequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used and the desired closed-loop frequency response. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 19 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com TPS5438x 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 3 SW1 SW2 12 4 GND BP 11 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 OUTPUT1 C2 R1 C1 R2 R3 UDG-07013 Figure 27. Optional Loop Compensation Components NOTE Once the filter and compensation components have been established, laboratory measurements of the physical design should be performed to confirm converter stability. Using High-ESR Output Capacitors If a high-ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability. To compensate, a small R-C series connected network is placed in parallel with the lower voltagesetting divider resistor (see Figure 27). The values of the components are determined such that a pole is placed at the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loop stability. The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency to the desired zero frequency. R3 = R2 ae ae fZERO(desired) cc c c fESR(zero) ee o o / - 1/ / / o o where: * * 20 f ESR(zero) is the ESR zero frequency of the output capacitor. f ZERO(desired) is the desired frequency of the zero added to the feedback. This frequency should be placed between 20 kHz and 60 kHz to ensure good loop stability. Submit Documentation Feedback (4) Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 The value of the capacitor is calculated in Equation 5. C1 = 1 2p REQ fESR(zero) where: * REQ is an equivalent impedance created by the parallel combination of the voltage-setting divider resistors (R1 and R2) in series with R3. (5) REQ = R3 + 1 aeae 1 o ae 1 oo cc / + c // e e R1 o e R2 o o (6) Using All Ceramic Output Capacitors With low-ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this case (see Figure 27), resistor R3 is set equal to 1/2 R2. This lowers the gain by 6 dB, reduces the crossover frequency, and improves phase margin. The value of C1 is found by determining the frequency at which to place the low-frequency pole. The minimum frequency at which to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with the internal soft-start (see Soft Start). The upper bound for the pole frequency is determined by the operating frequency of the converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from Equation 7. Keep component tolerances in mind when selecting the desired pole frequency. C1 = 1 2p REQ fPOLE(desired) where: * * f POLE(desired) is the desired pole frequency between 1 kHz and 3 kHz (TPS54x83) or 1 kHz and 6 kHz (TPS54x86). REQ is an equivalent impedance created by the parallel combination of the voltage-setting divider resistors (R1 and R2) in series with R3. (7) REQ = R3 + 1 aeae 1 o ae 1 oo cc / + c // e e R1 o e R2 o o (8) If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage-setting divider resistor (C2 in Equation 9). C2 = 1 R1 1+ 2p fC R1 ae (R2 R3 ) o cc // e (R2 + R3 ) o where * f C is the unity-gain crossover frequency, (approximately 50 kHz for most designs following these guidelines). (9) Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 21 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Example: TPS54386-Q1 Buck Converter Operating at 12-V Input, 3.3-V Output and 400-mA(P-P) Ripple Current First, the steady-state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the duty cycle is approximated using Equation 10. VOUT + VDIODE 3.3 + 0.5 = 30% d= = VIN + VDIODE 12 + 0.5 (10) The filter inductor is then calculated; see Equation 11. V - VOUT 12 - 3.3 1 L = IN d TS = 0.3 = 10.9 mH 0.4 600000 DIL (11) A custom-designed inductor may be used for the application, or a standard value close to the calculated value may be used. For this example, a standard 10-H inductor is used. Using Figure 25, find the 30% duty cycle curve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. This curve is the resonant frequency that must be compensated. Any frequency within an octave of the peak may be used in calculating the capacitor value. In this example, 6 kHz is used. 1 C= 2 L (2 p fRES ) 1 = 10 10 -6 2 = 70 mF (2 3.14 6000 ) (12) A 68-F capacitor should be used as a bulk capacitor, with up to 10 F of ceramic bypass capacitance. To ensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should be placed a decade above the resonant frequency. RESR < 1 1 = 40 mW 2 p 10 fRES C 2 3.14 10 6000 68 (10 )-6 (13) The resulting loop gain and phase are shown in Figure 28. Based on measurement, loop crossover is 45 kHz with a phase margin of 60 degrees. GAIN AND PHASE vs FREQUENCY 80 180 70 Phase 135 60 90 45 40 0 30 20 Phase - Gain - dB 50 -45 10 -90 0 Gain -135 -10 -20 100 1k 10 k 100 k f - Frequency - Hz -180 1M Figure 28. Example Loop Result 22 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Bootstrap for the N-Channel MOSFET A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor. To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the SW node toward ground and allows the bootstrap capacitor to charge. Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per-cycle basis is greater than the gate charge requirement of the MOSFET being used. DESIGN HINT For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and 82 nF. NOTE For 5-V input applications, connect PVDDx to BP directly. This connection bypasses the internal control-circuit regulator and provides maximum voltage to the gate-drive circuitry. In this configuration, shutdown mode IDDSDN is the same as quiescent IDDQ. Light Load Operation There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous converter is to operate in the discontinuous-conduction mode (DCM) at an average load current less than onehalf of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of input voltage, output voltage, inductor value, and operating frequency, as shown in Equation 14. 1 VIN - VOUT IDCM = d TS 2 L (14) Further, during discontinuous-mode operation the commanded pulse duration may become narrower than the capability of the converter to resolve. To maintain the output voltage within regulation, skipping switching pulses at light load conditions is a natural byproduct of that mode. This condition may occur if the output capacitor is charged to a value greater than the output regulation voltage and there is insufficient load to discharge the capacitor. A byproduct of pulse skipping is an increase in the peak-to-peak output ripple voltage. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 23 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com SW Waveform SW Waveform VOUT Ripple Inductor Current VOUT Ripple Skipping VIN = 12 V VOUT = 5 V Inductor Current Steady State VIN = 12 V VOUT = 5 V Figure 29. Steady State Figure 30. Skipping DESIGN HINT If additional output capacitance is required to reduce the output-voltage ripple during DCM operation, be sure to recheck the Feedback Loop and Inductor-Capacitor (L-C) Filter Selection and Maximum Output Capacitance sections. SW Node Ringing A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than 30-ns. In addition to following good printed-circuit board (PCB) layout practices, there are a couple of design techniques for reducing ringing and noise. SW Node Snubber Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range. DESIGN HINT A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 ) connected from SW to GND reduces the ringing on the SW node. Bootstrap Resistor A small resistor in series with the bootstrap capacitor reduces the turnon time of the internal MOSFET, thereby reducing the rising-edge ringing of the SW node. DESIGN HINT A resistor with a value between 1 and 3 may be placed in series with the bootstrap capacitor to reduce ringing on the SW node. DESIGN HINT Placeholders for these components should be placed on the initial prototype PCBs in case they are needed. 24 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Output Overload Protection In the event of an overcurrent during soft-start on either output (such as starting into an output short), pulse-bypulse current limiting and PWM frequency division are in effect for that output until the internal soft-start timer ends. At the end of the soft-start time, a UV condition is declared and a fault is declared. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup-mode time-out before attempting to restart. Frequency division means if an overcurrent pulse is detected, six clock cycles are skipped before the next PWM pulse is initiated, effectively dividing the operating frequency by six and preventing excessive current buildup in the inductor. In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON. This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the other is not loaded. The converter then enters a hiccup-mode timeout before attempting to restart. The overcurrent threshold for output 1 is set nominally at 4.5 A. The overcurrent level of output 2 is determined by the state of the ILIM2 pin. The ILIM setting of output 2 is not latched in place and may be changed during operation of the converter. Table 3. Current Limit Threshold Adjustment for Output 2 ILIM2 Connection OCP Threshold for Output 2 BP 4.5-A nominal setting (floating) 3-A nominal setting GND 1.5-A nominal setting DESIGN HINT The OCP threshold refers to the peak current in the internal switch. Be sure to add onehalf of the peak inductor ripple current to the dc load current in determining how close the actual operating point is to the OCP threshold. Operating Near Maximum Duty Cycle If the TPS54386-Q1 operates at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load-current transient), then there is a possibility that the output voltage will fall from regulation and trip the output UV comparator. If this should occur, the TPS54386-Q1 protection circuitry declares a fault and enters a shut-down-and-restart cycle. DESIGN HINT Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycle to maintain output-voltage regulation. To calculate the operating duty cycle, use Equation 15. d= VOUT + VDIODE VIN + VDIODE where * VDIODE is the voltage drop of the rectifier diode. (15) Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 25 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Dual-Supply Operation It is possible to operate a TPS54386-Q1 from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This level requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1 supplies energy to the output. In addition, output 1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to support output 1 in regulation. (See the Operating Near Maximum Duty Cycle section.) The preferred sequence of events is: 1. PVDD2 rises above the input UVLO voltage. 2. PVDD1 rises with output 1 disabled until PVDD1 rises above the level to support output 1 regulation. With these two conditions satisfied, there is no restriction on PVDD2 to be greater than or less than PVDD1. DESIGN HINT An R-C delay on EN1 may be used to delay the start-up of output 1 for a long-enough period of time to ensure that PVDD1 can support the output 1 load. Cascading Supply Operation It is possible to source PVDD1 from output 2 as depicted in Figure 31 and Figure 32. This configuration may be preferred if the input voltage is high, relative to the voltage on output 1. VIN TPS54383 1 PVDD1 PVDD2 14 2 BOOT1 BOOT2 13 3 SW1 SW2 12 4 GND BP 11 5 EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 OUTPUT2 OUTPUT1 UDG-07015 Figure 31. Schematic Showing Cascading PVDD1 From Output 2 26 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 PVDD2 Output2 PVDD1 Output1 T - Time Figure 32. Waveforms Resulting From Cascading PVDD1 From Output 2 In this configuration, the following conditions must be maintained: 1. Output 2 must be of a voltage high enough to maintain regulation of output 1 under all load conditions. 2. The sum of the current drawn by output 2 load plus the current into PVDD1 must be less than the overload protection current level of output 2. 3. The method of output sequencing must be such that the voltage on output 2 is sufficient to support output 1 before output 1 is enabled. This requrement may be accomplished by: (a) a delay of the enable function (b) selecting sequential sequencing of output 1 starting after output 2 is in regulation Multiphase Operation The TPS54386-Q1 is not designed to operate http://www.power.ti.com for appropriate device selection. as a two-channel multiphase converter. See Bypass and FIltering As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible. 1. PVDD1 to GND: Use a 10-F ceramic capacitor. 2. PVDD2 to GND: Use a 10-F ceramic capacitor. 3. BP to GND: Use a 4.7-F to 10-F ceramic capacitor. Overtemperature Protection and Junction Temperature Rise The overtemperature thermal protection limits the maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation and the thermal impedance from the junction to ambient. If the internal die temperature should reach the thermal shutdown level, the TPS54386-Q1 shuts off both PWMs and remains in this state until the die temperature drops below the hysteresis value, at which time the device restarts. The first step to determine the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the external rectifier diode. To find the conduction loss, first find the rms current through the upper switch MOSFET. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 27 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com 2 ae ae 2 c (D IOUTPUTx ) c IRMS(outputx) = D (IOUTPUTx ) + cc c 12 e e oo // / // oo where * * * D is the duty cycle. IOUTPUTx is the dc output current. IOUTPUTx is the peak ripple current in the inductor for output x. (16) Notice the impact of the operating duty cycle on the result. Multiplying the result by the RDS(on) of the MOSFET gives the conduction loss. PD(cond) = IRMS(outputx)2 RDS(on) (17) The switching loss is approximated by: 2 (VIN) CJ fS PD(SW) = 2 where * * where CJ is the parallel capacitance of the rectifier diode and snubber (if any). fS is the switching frequency. (18) The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator. PD = PD(cond)output1 + PD(SW )output1 + PD(cond)output2 + PD(SW )output2 + VIN Iq (19) The temperature rise of the device junction depends on the thermal impedance from the junction to the mounting pad (see the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient depends on the PCB layout (thermal-pad interface to the PCB, the exposed pad area) and airflow (if any). See the PCB Layout Guidelines, Additional References section. The operating junction temperature is shown in Equation 20. ( TJ = TA + PD qTH(pkg) + qTH(pad-amb) ) (20) Power Derating The TPS54386-Q1 delivers full current at ambient temperatures up to 85C if the thermal impedance from the thermal pad maintains the junction temperature below the thermal shutdown level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 33 illustrates the power derating for elevated ambient temperature under various airflow conditions. Note that these curves assume that the thermal pad is properly soldered to the recommended board. (See the References section for further information.) 28 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 POWER DISSIPATION vs AMBIENT TEMPERATURE 1.8 LFM = 250 1.6 PD - Power Dissipation - W LFM = 500 1.4 LFM = 0 1.2 LFM = 150 1.0 0.8 0.6 LFM 0 150 250 500 0.4 0.2 0 0 20 40 60 80 100 120 TA - Ambient Temperature - C 140 Figure 33. Power-Derating Curves PowerPAD Package The PowerPAD package provides low thermal impedance for heat removal from the device. The thermal pad derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. (See the Additional References section.) PCB Layout Guidelines The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 34 and Figure 35. * The thermal pad must be connected to a low-current (signal) ground plane having a large copper surface area to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal transfer of heat away from the IC. * Connect the GND pin to the thermal pad through a 10-mil (0.010-in, or 0.254-mm) wide trace. * Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces. * Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor, and rectifier diode. Avoid using vias in this loop. * Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power path as possible. Placement directly under the diode and the switch node is recommended. * Locate the bootstrap capacitor close to the BOOT pin to minimize the gate-drive loop. * Locate voltage-setting resistors and any feedback components over the ground plane and away from the switch node and the rectifier diode to the input-capacitor ground connection. * Locate snubber components (if used) close to the rectifier diode with minimal loop area. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 29 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 * * www.ti.com Locate the BP bypass capacitor very close to the IC; a minimal loop area is recommended. Locate the output ceramic capacitor close to the inductor output terminal between the inductor and any electrolytic capacitors, if used. L2 C18 R8 C14 C17 R6 C13 D2 C19 VOUT2 GND C15 R7 R4 R9 C16 C8 C12 C11 C6 U1 1 VIN R2 C10 R5 C1 D1 GND C7 C3 C4 C9 GND C5 R3 VOUT1 L1 Figure 34. Top Layer Copper Layout and Component Placement 30 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Figure 35. Bottom Layer Copper Layout Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 31 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com DESIGN EXAMPLES Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS54386-Q1 converter. Design Example List of Materials and Table 5, Definition of Symbols is found at the end of this section. PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT V INPUT CHARACTERISTICS VIN Input voltage 12 13.2 IIN Input current VIN = nom, IOUT = max 6.9 1.6 2 A No load input current VIN = nom, IOUT = 0 A 12 20 mA OUTPUT CHARACTERISTICS VOUT1 Output voltage 1 VIN = nom, IOUT = nom 4.8 5 5.2 VOUT2 Output voltage 2 VIN = nom, IOUT = nom 3.2 3.3 3.4 Line regulation VIN = min to max 1% Load regulation IOUT = min to max 1% Output voltage ripple VIN = nom, IOUT = max 50 IOUT1 Output current 1 VIN = min to max 0 2 IOUT2 Output current 2 VIN = min to max 0 2 IOCP1 Output overcurrent channel 1 VIN = nom, VOUT = VOUT1 = 5% 2.4 3 3.5 IOCP2 Output overcurrent channel 2 VIN = nom, VOUT = VOUT2 = 5% 2.4 3 3.5 Transient response VOUT from load transient IOUT = 1 A at 3 A/s VOUT(ripple ) Transient response settling time V mVPP A 200 mV 1 ms SYSTEM CHARACTERISTICS fSW Switching frequency Full-load efficiency TJ Operating temperature range 250 310 370 kHz 60 C 85% 0 25 + + + Figure 36. Design Example Schematic 32 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Design Procedure Duty Cycle Estimation The first step is to estimate the duty cycle of each switching FET. VOUT + VFD VIN(min) + VFD Dmax Dmin (21) VOUT + VFD VIN(max) + VFD (22) Using an assumed forward drop of 0.5 V for a Schottky rectifier diode, the channel 1 duty cycle is approximately 40.1% (minimum) to 48.7% (maximum), while the channel 2 duty cycle is approximately 27.7% (minimum) to 32.2% (maximum). Inductor Selection The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far enough from the minimum overcurrent trip level to ensure reliable operation. For both channel 1 and channel 2, the maximum inductor ripple current is 600 mA. The inductor size is estimated in Equation 23. L min VIN(max) - VOUT ILRIP(max) D min 1 fSW (23) The inductor values are * L1 = 18.3 H * L2 = 15.3 H The next-higher standard inductor value of 22 H is used for both inductors. The resulting ripple currents are : IRIPPLE VIN(max) - VOUT 1 Dmin L fSW (24) Peak-to-peak ripple currents of 0.498 A and 0.416 A are estimated for channel 1 and channel 2, respectively. The rms current through an inductor is approximated by Equation 25. (IL(avg) ) + 121 (IRIPPLE )2 2 IL(rms ) = (25) and is approximately 2 A for both channels. The peak inductor current is found using: IL(peak ) IOUT(max) + 1 IRIPPLE 2 (26) An inductor with a minimum rms current rating of 2 A and minimum saturation current rating of 2.25 A is required. A Coilcraft MSS1278-223ML 22-H, 6.8-A inductor is selected. Rectifier Diode Selection A Schottky diode is selected as a rectifier diode for its low forward-voltage drop. Allowing 20% over VIN for ringing on the switch node, the required minimum reverse-breakdown voltage of the rectifier diode is: V(BR )R(min ) 1.2 VIN (27) Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 33 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used. The average current in the rectifier diode is estimated by Equation 28. ID(avg) IOUT(max ) (1 - D ) (28) For this design, 1.2-A (average) and 2.25 A (peak) is estimated for channel 1 and 1.5-A (average) and 2.21-A (peak) for channel 2. An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward voltage drop of 0.4 V at 2 A. The power dissipation in the diode is estimated by Equation 29. PD (m ax ) VFM ID (avg ) (29) For this design, the full-load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2. Output Capacitor Selection The TPS54386-Q1 internal compensation limits the selection of the output capacitors. From , the internal compensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30. COUT = 1 2 2 4 p (fRES ) L (30) Solving for COUT using * fRES = 3 kHz * L = 22 H The resulting is COUT = 128 F. The output ripple voltage of the converter is composed of the ripple voltage across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the maximum ESR allowable to meet the output ripple requirements, the total ripple is partitioned and the equation solved to find the ESR. ESR(max) = VRIPPLE(tot) - VRIPPLE(cap) IRIPPLE = VRIPPLE(tot) IRIPPLE - D fS C OUT (31) Based on 128 F of capacitance, 300-kHz switching frequency, and 50-mV ripple voltage, plus rounding up the ripple current to 0.5 A and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a maximum allowable ESR of 87 m. To meet the ripple-voltage requirements, a low-cost 100-F electrolytic capacitor with 400 m ESR (C5, C17) and two 10-F ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-m ESR are selected. From the data sheets for the ceramic capacitors, the parallel combination provides an impedance of 28 m at 300 kHz for 14 mV of ripple. Voltage Setting The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 k and 50 k to maintain a balance between power dissipation and noise sensitivity. For this design, 20 k is selected. The lower resistors, R4 and R7 are found using the following equations. R4 = R7 = * * 34 VFB R2 VOUT1 - VFB (32) VFB R9 VOUT2 - VFB (33) R2 = R9 = 20 k VFB = 0.8 V Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com * * SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 R4 = 3.8 k (3.83 k standard value is used) R7 = 6.4 k (6.34 k standard value is used) Compensation Capacitors Checking the ESR zero of the output capacitors: fESR(zero) = * * * 1 2 p C ESR C = 100 F ESR = 400 m ESR(zero) = 3980 Hz (34) Because the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4 and R7 to compensate for the ESR of the electrolytic capacitor and add a zero of approximately 40 kHz. R5 = * * * * * * R4 ae ae fZERO(desired) cc c c fESR(zero) ee fESR(zero) = 4 kHz fESR(desired) = 40 kHz R4 = 3.83 k R5 = 424 (422 selected) R7 = 6.34 k R8 = 702 (698 selected) REQ = R5 + * * * C8 = * * o o / - 1/ / / o o (35) 1 aeae 1 o ae 1 oo cc /+c // e e R2 o e R4 o o R2 = R9 = 20 k REQ1 = 3.63 k REQ2 = 5.51 k (36) 1 2 p REQ fESR(zero) C8 = 10.9 nF (10 nF selected) C15 = 7.22 nF (6800 pF selected) (37) Input Capacitor Selection The TPS54386-Q1 data sheet recommends a minimum 10-F ceramic input capacitor on each PVDD pin. These capacitors must be capable of handling the rms ripple current of the converter. The rms current in the input capacitors is estimated by Equation 38. 2 ae ae 2 c (D IOUTPUTx ) c IRMS(outputx) = D (IOUTPUTx ) + cc c 12 e e * oo // / // oo (38) IRMS(CIN) = 0.43 A One 1210 10-F, 25-V, X5R ceramic capacitor with 2-m ESR and a 2-A rms current rating is selected for each PVDD input. Higher-voltage capacitors are selected to minimize capacitance loss at the dc bias voltage to ensure the capacitors maintain sufficient capacitance at the working voltage. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 35 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Bootstrap Capacitor To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nF bootstrap capacitor is used. ILIM Current limit must be set above the peak inductor current IL(peak). Comparing IL(peak) to the available minimum current limits, ILIM is connected to BP for the highest current-limit level. SEQ The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied together, the two supplies start up ratiometrically. Alternatively, SEQ could be connected to BP or GND to provide sequential start-up. Power Dissipation The power dissipation in the TPS54386-Q1 is composed of FET conduction losses, switching losses, and internal regulator losses. The rms FET current is found using Equation 39. 2 ae ae (D I 2 OUTPUTx ) IRMS(outputx) = D c (IOUTPUTx ) + c cc c 12 e e oo // / // oo (39) This results in 1.05 -A rms for channel 1 and 0.87 A rms for channel 2. Conduction losses are estimated by: 2 ( PCON = RDS(on ) IQSW (rms ) ) (40) Conduction losses of 198 mW and 136 mW are estimated for channel 1 and channel 2 respectively. The switching losses are estimated in Equation 41. PSW (V IN(max ) 2 ) (C DJ + COSS ) fSW 2 (41) From the data sheet of the MBRS320, the junction capacitance is 658 pF. Because this is large compared to the output capacitance of the TPS54x8x, the FET capacitance is neglected, leaving switching losses of 17 mW for each channel. The regulator losses are estimated in Equation 42. ( PREG IDD VIN(max ) + IBP VIN(max ) - VBP ) (42) With no external load on BP (IBP = 0), the power dissipation of the regulator is 66 mW. Total power dissipation in the device is the sum of conduction and switching for both channels, plus regulator losses. The total power dissipation is PDISS = 0.198 + 0.136 + 0.017 + 0.017 + 0.066 = 434 mW. Design Example Test Results The following results are from the TPS54386-Q1-001 EVM. 36 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 VIN = 12 V SW 3.3 V SW 5 V t - Time - 40 ns/div Figure 37. Switching-Node Waveforms 100 100 VIN = 9.6 V VIN = 9.6 V 90 90 80 VIN = 13.2 V 70 h - Efficiency - % 70 h - Efficiency - % 80 VIN = 12.0 V 60 50 40 30 VOUT = 5.0 V 20 10 VIN = 13.2 V 60 VIN = 12.0 V 50 40 30 VOUT = 3.3 V VIN (V) 20 VIN (V) 9.6 12.0 13.2 10 9.6 12.0 13.2 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 ILOAD - Load Current - A Figure 38. 5-V Output Efficiency vs Load Current 0.5 1.0 1.5 2.0 2.5 3.0 ILOAD - Load Current - A Figure 39. 3.3-V Output Efficiency vs Load Current Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 37 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com 1.004 1.004 1.003 VOUT - Output Voltage (Normalized) - V 1.005 VOUT - Output Voltage (Normalized) - V 1.005 1.002 VIN = 9.6 V 1.003 VIN = 9.6 V 1.002 VIN = 12.0 V 1.001 VIN = 13.2 V 1.001 1.000 1.000 0.999 0.999 VOUT = 5.0 V 0.998 VIN = 13.2 V 0.997 0.998 VIN (V) 9.6 12.0 13.2 0.996 0.995 VOUT = 3.3 V VIN = 12.0 V 0.997 VIN (V) 0.996 9.6 12.0 13.2 0.995 0.5 1.0 1.5 2.0 2.5 0 3.0 0.5 1.0 Gain - dB Figure 40. 5-V Output Voltage vs Load Current 180 60 135 40 90 20 45 0 0 -20 2.5 3.0 -45 -40 -90 Gain -80 1k 2.0 Figure 41. 3.3-V Output Voltage vs Load Current 80 -60 1.5 IOUT - Load Current - A IOUT - Load Current - A Phase - 0 Phase 5.0 V 3.3 V -135 10 k f - Frequency -Hz 100 k -180 300 k Figure 42. Example 1 Loop Response 38 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Table 4. Design Example List of Materials QTY REFERENCE DESIGNATOR VALUE DESCRIPTION SIZE PART NUMBER MANUFACTURER 1 C1 100 F Capacitor, Aluminum, 25V, 20% E-can EEEFC1E101P Panasonic 2 C10, C11 10 F Capacitor, Ceramic, 25V, X5R 20% 1210 C3216X5R1E106M TDK 1 C12 4.7 F Capacitor, Ceramic, 10V, X5R 20% 0805 Std Std 2 C14, C16 470 pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 1 C15 6.8 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 100 F Capacitor, Aluminum, 10V, 20%, FC Series F-can EEEFC1A101P Panasonic 1 C17, C5 4 C3, C4, C18, C19 10 F Capacitor, Ceramic, 6.3V, X5R 20% 0805 C2012X5R0J106M TDK 1 C8 10 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 2 C9, C13 0.033 F Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std 2 D1, D2 MBRS320 Diode, Schottky, 3-A, 30-V SMC MBRS330T3 On Semi 2 L1, L2 22 H Inductor, Power, 6.8A, 0.038 0.484 x 0.484 MSS1278-153ML Coilcraft 2 R2, R9 20 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R5 422 Resistor, Chip, 1/16W, 1% 0603 Std Std 2 R6, R10 10 Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R8 698 Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R4 3.83 k Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R7 6.34 k Resistor, Chip, 1/16W, 1% 0603 Std Std TPS54386-Q1 DC-DC Switching Converter w/ FET HTSSOP TPS54386-Q1PWP -14 1 U1 TI Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 39 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com Table 5. Definition of Symbols CDJ Average junction capacitance of the rectifier diode from 0 V to VIN(max) COSS Average output capacitance of the switching MOSFET from 0 V to VIN(max) COUT Output capacitor D(max) Maximum steady-state operating duty cycle D(min) Minimum steady-state operating duty cycle ESR(max) Maximum allowable output-capacitor ESR fSW Switching frequency IBP Output current of BP regulator due to external loads IDD Switching quiescent current with no load on BP ID(avg) Average diode conduction current ID(peak) Peak diode conduction current IIN(avg) Average input current IIN(rms) Root mean squared (RMS) input current IL(avg) Average inductor current IL(rms) Root mean squared (RMS) inductor current IL(peak) Peak current in inductor ILRIP(max) Maximum allowable inductor ripple current L(min) Minimum inductor value to maintain desired ripple current IOUT(max) Maximum designed output current IRMS(cin) Root mean squared (RMS) current through the input capacitor IRIPPLE Inductor peak-to-peak ripple current IQSW(rms) Root mean squared current through the switching MOSFET PCON Power loss due to conduction through switching MOSFET PD(max) Maximum power dissipation in diode RDS(on) Drain-to-source resistance of the switching MOSFET when ON PSW Power loss due to switching PREG Power loss due to the internal regulator VBP Output voltage of BP regulator V(BR)R(min) Minimum reverse-breakdown voltage rating for rectifier diode VFB Regulated feedback voltage VFD Forward voltage drop across rectifier diode VIN Power-stage input voltage VOUT Regulated output voltage VRIPPLE(cap) Peak-to-peak ripple voltage due to ideal capacitor (ESR = 0 ) VRIPPLE(tot) Maximum allowable peak-to-peak output ripple voltage 40 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Example 2: 24 V to 12 V and 24 V to 5 V For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch node and a 30-V Schottky diode is selected. A higher-resistance feedback network is chosen for the 12-V output to reduce the feedback current. + + Figure 43. 24 V to 12 V and 24 V to 5 V Using the TPS54386-Q1 VIN = 24 V IOUT = 2 A VIN = 24 V IOUT = 2 A VOUT (5 V/div) VOUT (5 V/div) T - Time - 10 ns / div T - Time - 10 ns / div Figure 44. Switch Node Ringing Without Snubber and Boost Resistor Figure 45. Switch Node Ringing With Snubber and Boost Resistor Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 41 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com 90 80 VOUT = 5 V h - Efficiency - % 70 60 VOUT = 12 V 50 40 30 VIN = 24 V 20 VOUT (V) 5 12 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 IOUT - Load Current - A Figure 46. Efficiency vs Load Current 42 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 TPS54386-Q1 www.ti.com SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 Example 3: 5 V to 3.3 V and 5 V to 1.2 V For a low-input-voltage application, the TPS54386-Q1 is selected for reduced size, and all ceramic output capacitors are used. 22-F input capacitors are selected to reduce input ripple and lead capacitors are placed in the feedback to boost phase margin. Figure 47. 5 V to 3.3 V and 5 V to 1.2 V 80 100 80 70 Gain - dB VOUT = 3.3 V 60 VOUT = 1.2 V 50 40 60 135 40 90 20 45 0 0 -20 -45 -90 30 VIN = 5 V -40 20 VOUT (V) -60 1.2 3.3 10 Gain Phase WIth Lead Without Lead -80 1k 0 0 0.5 1.0 1.5 2.0 2.5 3.0 10 k f - Frequency -Hz 100 k Phase - 90 h - Efficiency - % 180 VOUT = 1.2 V -135 -180 300 k IOUT - Load Current - A Figure 48. Efficiency vs Load Current Figure 49. Example 3 Loop Response Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 43 TPS54386-Q1 SLUSAZ9A - MARCH 2012 - REVISED MARCH 2012 www.ti.com ADDITIONAL REFERENCES Related Devices The following parts have characteristics similar to the TPS54386-Q1 and may be of interest. Table 6. Devices Related to the TPS54386-Q1 TI LITERATURE NUMBER DEVICE DESCRIPTION SLUS642 TPS40222 5-V input, 1.6-A non-synchronous buck converter SLUS749 TPS54283 / TPS54286 2-A dual non-synchronous converter with integrated high-side MOSFET References These references, design tools, and links to additional references, including design software, may be found at http:www.power.ti.com Table 7. References TI LITERATURE NUMBER DESCRIPTION SLMA002 PowerPAD Thermally Enhanced Package Application Report SLMA004 PowerPADTM Made Easy SLUP206 Under the Hood Of Low Voltage DC/DC Converters. SEM1500 Topic 5, 2002 Seminar Series SLVA057 Understanding Buck Power Stages in Switchmode Power Supplies SLUP173 Designing Stable Control Loops. SEM 1400, 2001 Seminar Series Package Outline and Recommended PCB Footprint The following pages outline the mechanical dimensions of the 14-Pin PWP package and provide recommendations for PCB layout. 44 Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Link(s): TPS54386-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS54386TPWPRQ1 ACTIVE Package Type Package Pins Package Drawing Qty HTSSOP PWP 14 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (C) Top-Side Markings (3) CU NIPDAU Level-3-260C-168 HR (4) -40 to 105 54386T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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OTHER QUALIFIED VERSIONS OF TPS54386-Q1 : * Catalog: TPS54386 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54386TPWPRQ1 Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 14 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54386TPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: TPS54386TPWPRQ1