TPS54386TPWPRQ1 - Texas Instruments

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS54386

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1

VIN

GND

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET

Check for Samples: TPS54386-Q1

1FEATURES APPLICATIONS

23• Qualified for Automotive Applications • Power for DSP

• AEC-Q100 Qualified With the Following • Consumer Electronics

Results: CONTENTS

– Device Temperature Grade 2: –40°C to Device Ratings 2

+105°C Ambient Operating Temperature Electrical Characteristics 3

– Device HBM ESD Classification Level H2 Device Information 9

– Device CDM ESD Classification Level C3B Application Information 12

• 4.5-V to 28-V Input Range Design Examples 32

• Output Voltage Range 0.8 V to 90% of Input Additional References 44

Voltage

• Output Current Up to 3 A DESCRIPTION

• Fixed Switching Frequency: 600 kHz The TPS54386-Q1 are dual-output, non-synchronous

• Three Selectable Levels of Overcurrent buck converters capable of supporting 3-A output

applications that operate from a 4.5-V to 28-V input

Protection (Output 2) supply voltage, and require output voltages between

• 0.8-V 1.5% Voltage Reference 0.8 V and 90% of the input voltage.

• 2.1-ms Internal Soft Start With an internally-determined operating frequency,

• Dual PWM Outputs 180° Out-of-Phase soft-start time, and control-loop compensation, these

• Ratiometric or Sequential Startup Modes converters provide many features with a minimum of

Selectable by a Single Pin external components. Channel-1 overcurrent

protection is set at 4.5 A, whereas the channel-2

• 85-mΩInternal High-Side MOSFETs overcurrent protection level is selected by connecting

• Current Mode Control a pin to ground, to BP, or left floating. The setting

• Internal Compensation levels are used to allow for scaling of external

components for applications that do not need the full

• Pulse-by-Pulse Overcurrent Protection load capability of both outputs.

• Thermal Shutdown Protection at 148°C The outputs may be enabled independently, or may

• 14-Pin PowerPAD™ HTSSOP Package be configured to allow either ratiometric or sequential

start-up sequencing. Additionally, the two outputs

may be powered from different sources.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Table 1. ORDERING INFORMATION(1)

PART NUMBER OPERATING FREQUENCY (kHz) PACKAGE MEDIA UNITS TOP-SIDE MARKING

TPS54386TPWPRQ1 600 14-HTSSOP package Tape and reel 2000 54386T

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

DEVICE RATINGS

ABSOLUTE MAXIMUM RATINGS(1)

VALUE UNIT

PVDD1, PVDD2, EN1, EN2 30

BOOT1, BOOT2 VSW+ 7

SW1, SW2 –2 to 30

Input voltage range SW1, SW2 transient (< 50 ns) –3 to 31 V

BP 6.5

SEQ, ILIM2 –0.3 to 6.5

FB1, FB2 –0.3 to 3

SW1, SW2 output current 7 A

BP load current 35 mA

Tstg Storage temperature –55 to 165 °C

TAOperating temperature –40 to 105 °C

Human Body Model (HBM) AEC-Q100 Classification Level H2 2 kv

ESD ratings Charged Device Model (CDM) AEC-Q100 Classification Level C3B 750 V

(1) Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the

Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended

periods of time may affect device reliability.

RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT

VPVDD2 Input voltage 4.5 28 V

Operating junction

TA–40 125 °C

temperature

PACKAGE DISSIPATION RATINGS(1) (2) (3)

THERMAL IMPEDANCE

JUNTION-TO-THERMAL PAD TA= 25°C TA= 105°C

PACKAGE (°C/W) POWER RATING (W) POWER RATING (W)

Plastic 14-Pin HTSSOP (PWP) 2.07(4) 1.6 0.8

(1) For more information on the PWP package, see TI Technical Brief (SLMA002A).

(2) TI device packages are modeled and tested for thermal performance using printed circuit board designs outlined in JEDEC standards

JESD 51-3 and JESD 51-7.

(3) For application information, see the Power Derating section.

(4) TJ-A = 40°C/W.

Product Folder Link(s): TPS54386-Q1

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

ELECTRICAL CHARACTERISTICS

–40°C ≤TA≤105°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLY (PVDD)

VPVDD1 4.5 28 V

Input voltage range

VPVDD2 4.5 28 V

IDDSDN Shutdown V EN1 = V EN2 = VPVDD2 70 150 μA

IDDQQuiescent, non-switching VFB = 0.9 V, outputs off 1.8 3 mA

SW node unloaded; Measured as BP sink

IDDSW Quiescent, while-switching 5

current

VUVLO Minimum turnon voltage PVDD2 only 3.8 4.1 4.4 V

VUVLO(hys) Hysteresis 400 mV

CBP = 10 μF, EN1 and EN2 go low

tSTART (1) (2) Time from start-up to soft-start begin 2 ms

simultaneously

ENABLE (EN)

VEN1 0.9 1.2 1.5 V

Enable threshold

VEN2 0.9 1.2 1.5 V

Hysteresis 50 mV

IEN1 6 12 μA

Enable pullup current V EN1 = V EN2 = 0 V

IEN2 6 12 μA

tEN(1) Time from enable to soft-start begin Other EN pin = GND 10 μs

BP REGULATOR (BP)

BP Regulator voltage 8 V < PVDD2 < 28 V 5 5.25 5.6 V

PVDD2 = 4.5 V; switching, no external load on

BPLDO Dropout voltage 400 mV

IBP(1) Regulator external load 2 mA

IBPS Regulator short circuit 4.5 V < PVDD2 < 28 V 10 20 30 mA

OSCILLATOR

fSW Switching frequency 510 630 750 kHz

tDEAD(1) Clock dead time 140 ns

ERROR AMPLIFIER (EA) and VOLTAGE REFERENCE (REF)

VFB1 0°C < TA< 85°C 788 800 812 mV

Feedback input voltage

VFB2 –40°C < TA< 125°C 786 812 mV

IFB1 3 50 nA

Feedback input bias current

IFB2 3 50 nA

gM1(1) 30 μS

Transconductance

gM2(1) 30 μS

SOFT START (SS)

TSS1 1.5 2.1 2.7 ms

Soft-start time

TSS2 1.5 2.1 2.7 ms

OVERCURRENT PROTECTION

ICL1 Current limit channel 1 3.6 4.5 5.6 A

VILIM2 = VBP 3.6 4.5 5.6

ICL2 Current limit channel 2 VILIM2 = (floating) 2.4 3 3.6 A

VILIM2 = GND 1.15 1.5 1.75

VUV1 670 mV

Low-level output threshold to declare a fault Measured at feedback pin

VUV2 670 mV

tHICCUP(1) Hiccup timeout 10 ms

tON1(oc)(1) 90 150 ns

Minimum overcurrent pulse duration

tON2(oc)(1) 90 150 ns

(1) Ensured by design. Not production tested.

(2) When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower

BP capacitor value. More information can be found in the Input UVLO and Startup section.

Product Folder Link(s): TPS54386-Q1

TPS54386-Q1

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ELECTRICAL CHARACTERISTICS (continued)

–40°C ≤TA≤105°C, VPVDD1 = VPVDD2 = 12 V, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

BOOTSTRAP

RBOOT1 From BP to BOOT1 or BP to BOOT2,

Bootstrap switch resistance 18 Ω

IEXT = 50 mA

RBOOT2

OUTPUT STAGE (Channel 1 and Channel 2)

TA= 25°C, VPVDD2 = 8 V 85

rDS(on) (3) MOSFET on-resistance plus bond-wire resistance mΩ

–40°C < TA< 125°C, VPVDD2 = 8 V 85 165

tON(min) (3) Minimum controllable pulse duration ISWx peak current > 1 A(4) 100 200 ns

DMIN Minimum duty cycle VFB = 0.9 V 0%

DMAX Maximum duty cycle fSW = 600 kHz 85% 90%

ISW Switching-node leakage current (sourcing) Outputs OFF 2 12 μA

THERMAL SHUTDOWN

TSD (3) Shutdown temperature 148 °C

TSD(hys) (3) Hysteresis 20 °C

(3) Ensured by design. Not production tested.

(4) See Figure 14 for ISWx peak current <1 A.

Product Folder Link(s): TPS54386-Q1

-50 -25 0 25 50 75 100 125

1.6

1.7

1.9

1.5

2.0

2.1

1.8

T JunctionTemperature C°

J- -

I QuiescentCurrent mA

DDQ - -

V 5.25V

BP =

100

120

-50 -25 0 25 50 75 100 125

140

T JunctionTemperature C°

J- -

I ShutdownCurrent Am

SD - -

VPVDDx 12V=

VPVDDx 4.5V=

V 28V

PVDDx =

3.6

3.7

3.8

3.9

4.1

4.2

4.0

UVLO(Off)

UVLO(On)

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VUVLO - -UndervoltageLockout V

1.15

1.17

1.21

1.23

1.19

1.25

-50 -25 0 25 50 75 100 125

EN(Off)

EN(On)

T JunctionTemperature C°

J- -

V EnableThresholdVoltage V

EN - -

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT (NON-SWITCHING) SHUTDOWN CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2.

UNDERVOLTAGE LOCKOUT THRESHOLD ENABLE THRESHOLDS

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

Product Folder Link(s): TPS54386-Q1

270

310

350

290

330

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

V 5.25V

BP =

f PWMFrequency kHz

PWM - -

1.5

2.0

2.5

3.0

3.5

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

t SoftStartTime ms

SS - -

V 5.25V

BP =

580

640

680

600

660

-50 -25 0 25 50 75 100 125

620

T JunctionTemperature C°

J- -

f PWMFrequency kHz

PWM - -

V 5.25V

BP =

-50 -25 0 25 50 75 100 125

-3

-5

-1

T JunctionTemperature C°

J- -

I FeedbackBiasCurrent nA

FB - -

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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TYPICAL CHARACTERISTICS (continued)

SOFT-START TIME SWITCHING FREQUENCY (300 kHz)

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 5. Figure 6.

SWITCHING FREQUENCY (600 kHz) FEEDBACK BIAS CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

Product Folder Link(s): TPS54386-Q1

4.8

4.6

4.4

4.2

4.0

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDD =24V

VPVDD =5V

VPVDD =12V

I OvercurrentLimit A

CL - -

788

793

798

803

808

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

V FeedbackVoltage mV

FB - -

2.6

2.8

3.0

3.2

3.4

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDDx 24V=

VPVDDx 12V=

VPVDDx 5V=

I OvercurrentLimit A

CL - -

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100 125

T JunctionTemperature C°

J- -

VPVDDx =24V

VPVDDx =12V

VPVDDx =5V

I OvercurrentLimit A

CL - -

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

TYPICAL CHARACTERISTICS (continued)

FEEDBACK VOLTAGE OVERCURRENT LIMIT (CH1, CH2 HIGH LEVEL)

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 9. Figure 10.

OVERCURRENT LIMIT (CH2 MID-LEVEL) OVERCURRENT LIMIT (CH2 LOW LEVEL)

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 11. Figure 12.

Product Folder Link(s): TPS54386-Q1

200

250

300

350

400

100

0 0.2 0.4 0.6 0.8 1.0 1.4

TA= 0°C

IL- Load Current - A

tON - Minimum Controllable Pulse Width - ns

–40

TA(°C)

TA= –40°C

TA= 25°C

TA= 85°C

1.2

150

-50 -25 0 25 50 75 100 125

TJ- Junction Temperature - °C

ISW(off) - Switching Node Leakage Current - mA

4 8 12 16 20 24 28

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

OCL = 4.5 A

OCL = 3.0 A

OCL = 1.5 A

VDD - Supply Voltage - V

IOC - Overcurrent Limit - A

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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TYPICAL CHARACTERISTICS (continued)

SWITCHING NODE LEAKAGE CURRENT MINUMUM CONTROLLABLE PULSE DURATION

vs vs

JUNCTION TEMPERATURE LOAD CURRENT

Figure 13. Figure 14.

OVERCURRENT LIMIT

SUPPLY VOLTAGE

Figure 15.

Product Folder Link(s): TPS54386-Q1

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

SEQ

ILIM2

FB2

EN1

EN2

FB1

Thermal Pad

(bottom side)

HTSSOP (PWP)

(Top View)

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

DEVICE INFORMATION

PIN CONNECTIONS

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

Input supply to the high-side gate driver for output 1. Connect a 22-nF to 82-nF capacitor from this pin

to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is

BOOT1 2 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small

resistor (1 Ωto 3 Ω) may be placed in series with the bootstrap capacitor.

Input supply to the high-side gate driver for output 2. Connect a 22-nF to 82-nF capacitor from this pin

to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is

BOOT2 13 I turned ON during the OFF time of the converter. To slow down the turn ON of the internal FET, a small

resistor (1 Ωto 3 Ω) may be placed in series with the bootstrap capacitor.

Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR (4.7-μF

BP 11 – to 10-μF X7R or X5R) ceramic capacitor.

Active-low enable input for output 1. If the voltage on this pin is greater than 1.55 V, output 1 is disabled

(high-side switch is OFF). A voltage of less than 0.9 V enables output 1 and allows soft-start of output 1

EN1 5 I to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND for

always ON operation.

Active-low enable input for output 2. If the voltage on this pin is greater than 1.55 V, output 2 is disabled

(high-side switch is OFF). A voltage of less than 0.9 V enables Output 2 and allows soft start of Output

EN2 6 I 2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND

for always ON operation.

Voltage feedback pin for output 1. The internal transconductance error amplifier adjusts the PWM for

output 1 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from

FB1 7 I output 1 to ground, with the center connection tied to this pin, determines the value of the regulated

output voltage. Compensation for the feedback loop is provided internally to the device. See the

Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.

Voltage feedback pin for output 2. The internal transconductance error amplifier adjusts the PWM for

output 2 to regulate the voltage at this pin to the internal 0.8-V reference. A series resistor divider from

FB2 8 I output 2 to ground, with the center connection tied to this pin, determines the value of the regulated

output voltage. Compensation for the feedback loop is provided internally to the device. See the

Feedback Loop and Inductor-Capacitor ( L-C) Filter Selection section for further information.

GND 4 – Ground pin for the device. Connect directly to the thermal pad.

Current limit adjust pin for output 2 only. This function is intended to allow a user with asymmetrical load

currents (output 1 load current much greater than output 2 load current) to optimize component scaling

ILIM2 9 I of the lower-current output while maintaining proper component derating in a overcurrent fault condition.

The discrete levels are available as shown in Table 3,Current Limit Threshold Adjustment for Output 2.

Note: An internal 2-resistor divider (150-kΩeach) connects BP to ILIM2 and to GND.

Power input to the output 1 high-side MOSFET only. This pin should be locally bypassed to GND with a

PVDD1 1 I low-ESR ceramic capacitor of 10-μF or greater.

The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2

pins and provides power to the output 2 high-side MOSFET. This pin should be locally bypassed to

PVDD2 14 I GND with a low-ESR ceramic capacitor of 10-μF or greater. The UVLO function monitors PVDD2 and

enables the device when PVDD2 is greater than 4.1 V.

Product Folder Link(s): TPS54386-Q1

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TERMINAL FUNCTIONS (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

This pin configures the output start-up mode. If the SEQ pin is connected to BP, then when output 2 is

enabled, output 1 is allowed to start after output 2 has reached regulation; that is, sequential startup

where output 1 is slave to output 2. If EN2 is allowed to go high after the outputs have been operating,

then both outputs are disabled immediately, and the output voltages decay according to the load that is

present. For this sequence configuration, tie EN1 to ground.

If the SEQ pin is connected to GND, then when output 1 is enabled, output 2 is allowed to start after

output 1 has reached regulation; that is, sequential start-up where output 2 is slave to output 1. If EN1 is

allowed to go high after the outputs have been operating, then both outputs are disabled immediately,

SEQ 10 I and the output voltages decay according to the load that is present. For this sequence configuration, tie

EN2 to ground.

If left floating, output 1 and output 2 start ratiometrically when both outputs are enabled at the same

time. They soft-start at a rate determined by their final output voltage and enter regulation at the same

time. If the EN1 and EN2 pins are allowed to operate independently, then the two outputs also operate

independently.

NOTE: An internal two-resistor (150-kΩeach) divider connects BP to SEQ and to GND. See the

Sequence States table.

Source (switching) output for output 1 PWM. A snubber is recommended to reduce ringing on this node.

SW1 3 O See SW Node Ringing for further information.

Source (switching) output for output 2 PWM. A snubber is recommended to reduce ringing on this node.

SW2 12 O See SW Node Ringing for further information.

Thermal pad – – This pad must be tied externally to a ground plane and the GND pin.

Product Folder Link(s): TPS54386-Q1

7FB1

Soft Start

1CCOMP

S Q

Current

Comparator

f(IDRAIN1) + DC(ofst)

Anti-Cross

Conduction

1.2 MHz

Oscilator

Divide

by 2/4

Ramp

Gen 1

Ramp

Gen 2

CLK1

CLK2

CLK1

Weak

Pull-Down

MOSFET

5EN1

6EN2

6mA6 mA

VDD2

Internal

Control

10SEQ

150 kW

Output

Undervoltage

Detect

BP FB1

FB2

CLK1

4GND

8FB2

Soft Start

2CCOMP

S Q

Current

Comparator

Anti-Cross

Conduction

CLK2

Weak

Pull-Down

MOSFET

11BP

9ILIM2

150 kW

CLK2

4GND

Level

Select

5.25-V

Regulator

References

BOOT1

PVDD1

SW1

BOOT2

PVDD2

SW2

f(IDRAIN2) + DC(ofst)

0.8 VREF

IMAX2 (Set to one of three limits)

f(IDRAIN1)

f(IMAX1)

Overcurrent Comp

f(ISLOPE1)

Level

Shift

Level

Shift

f(IDRAIN2)

f(IMAX2)

f(ISLOPE2)

FET

Switch

TSD

PVDD2

f(ISLOPE1)

f(ISLOPE2)

SD1

SD2

UVLO

0.8 VREF

SD2

0.8 VREF

SD1

UDG-07124

Overcurrent Comp

RCOMP

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

BLOCK DIAGRAM

Product Folder Link(s): TPS54386-Q1

TPS54386-Q1

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APPLICATION INFORMATION

FUNCTIONAL DESCRIPTION

The TPS54386-Q1 is a dual-output, non-synchronous converter. Each PWM channel contains an internally

compensated error amplifier, current-mode pulse-width modulator (PWM), switch MOSFET, enable, and fault-

protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, clock

oscillator, and output-voltage sequencing functions.

DESIGN HINT

The TPS54386-Q1 contains internal slope compensation and loop compensation

components; therefore, the external L-C filter must be selected appropriately so that the

resulting control loop meets criteria for stability. This approach differs from an externally-

compensated controller, where the L-C filter is generally selected first, and the

compensation network is found afterwards. (See the Feedback Loop and L-C Filter

Selection section.)

NOTE

Unless otherwise noted, a label with a lowercase xappended implies the term applies to

both outputs of the two modulator channels. For example, the term ENx implies both EN1

and EN2. Unless otherwise noted, all parametric values given are typical. See the

Electrical Characteristics for minimum and maximum values. Calculations should be

performed with tolerance values taken into consideration.

Voltage Reference

The band-gap cell common to both outputs, trimmed to 800 mV.

Oscillator

The oscillator frequency is internally fixed at two times the SWx node switching frequency. The two outputs are

internally configured to operate on alternating switch cycles (that is, 180° out of phase).

Input Undervoltage Lockout (UVLO) and Startup

When the voltage at the PVDD2 pin is less than 4.1 V, a portion of the internal bias circuitry is operational, and

all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises

above the UVLO turnon threshold, the state of the enable pins determines the remainder of the internal start-up

sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with

a 20-mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start begins, depending on the

SEQ mode of operation and the EN1 and EN2 settings.

Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be

higher or lower than PVDD2. (See the Dual Supply Operation section.)

Enable and Timed Turnon of the Outputs

Each output has a dedicated (active-low) enable pin. If left floating, an internal current source pulls the pin to

PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.2 V with an external circuit, the

associated output is enabled and soft-start is initiated.

If both enable pins are left in the high state, the device operates in a shutdown mode, where the BP regulator is

shut down and minimal functions are active. The total standby current from both PVDD pins is approximately 70

μA at the 12-V input supply.

An R-C circuit connected to an ENx pin may be used to delay the turnon of the associated output after power is

applied to PVDDx (see Figure 16). After power is applied to PVDD2, the voltage on the ENx pin slowly decays

towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup

sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to

PVDD2, then omit these two components and tie the ENx pin to GND directly.

Product Folder Link(s): TPS54386-Q1

DELAY

IN ENx

TH ENx

C farads

V 2 I R

R n V I R

=æ ö

- ´ ´

´ç ÷

- ´

è ø

TPS5438x

ENx

PVDD2

PVDDx

6mA

1.2V

T Time-

tDELAY

0tDELAY +tSS

PVDDx

ENx

VOUTx

1.2-V

Threshold

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

If an R-C circuit is used to delay the turnon of the output, the resistor value must be much less than 1.2 V / 6 μA

or 200 kΩ. A suggested value is 51 kΩ. This resistor value allows the ENx voltage to decay below the 1.2-V

threshold while the 6-μA bias current flows.

The capacitor value required to delay the start-up time (after the application of PVDD2) is shown in Equation 1.

where:

• R and C are the timing components.

• VTH is the 1.2-V enable threshold voltage.

• I ENx is the 6-μA enable-pin biasing current. (1)

Other enable-pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing

section.)

Figure 16. Start-Up Delay Schematic Figure 17. Start-Up Delay With R-C on Enable

DESIGN HINT

If delayed output-voltage start-up is not necessary, simply connect EN1 and EN2 to GND.

This configuration allows the outputs to start immediately on valid application of PVDD2.

If ENx is allowed to go high after output x has been in regulation, the upper MOSFET shuts off, and the output

decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains in the

OFF state. (See the Bootstrap for N-Channel MOSFET section.)

Output-Voltage Sequencing

The TPS54386-Q1 allows single-pin programming of output-voltage start-up sequencing. During power on, the

state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs

behave as described in Table 2.

Product Folder Link(s): TPS54386-Q1

5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

SEQ = BP

Sequential

CH2 then CH1

T - Time - 1 ms/div

SEQ = GND

Sequential

CH1 then CH2

5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

TPS54386-Q1

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Table 2. Sequence States

SEQ PIN STATE MODE EN1 EN2

Ignored by the device.when V EN2 <

enable threshold voltage

Tie EN1 to < enable threshold voltage

for BP to be active when VEN2 >

BP Sequential, output 2 then output 1 Active

enable threshold voltage

Tie EN1 to > enable threshold voltage

for low quiescent current (BP inactive)

when VEN2 > enable threshold voltage Ignored by the device.when V EN1 <

enable threshold voltage

Tie EN2 to < enable threshold voltage

for BP to be active when VEN1 >

GND Sequential, output 1 then output 2 Active enable threshold voltage

Tie EN2 to > enable threshold voltage

for low quiescent current (BP inactive)

when V EN1 > enable threshold voltage

Independent or ratiometric, output 1 Active. EN1 and EN2 must be tied Active. EN1 and EN2 must be tied

(floating) and output 2 together for Ratio-metric startup. together for ratiometric start-up.

If the SEQ pin is connected to BP, then when output 2 is enabled, output 1 is allowed to start approximately 400

μs after output 2 has reached regulation; that is, sequential start-up where output 1 is slave to output 2. If EN2 is

allowed to go high after the outputs have been operating, then both outputs are disabled immediately, and the

output voltages decay according to the load that is present.

If the SEQ pin is connected to GND, then when output 1 is enabled, output 2 is allowed to start approximately

400 μs after output 1 has reached regulation; that is, sequential start-up where output 2 is slave to output 1. If

EN1 is allowed to go high after the outputs have been operating, then both outputs are disabled immediately,

and the output voltages decay according to the load that is present.

Figure 18. SEQ Pin Tied to BP Figure 19. SEQ Pin Tied to GND

NOTE

An R-C network connected to the ENx pin may be used in addition to the SEQ pin in

sequential mode to delay the start-up of the first output voltage. This approach may be

necessary in systems with a large number of output voltages and elaborate voltage-

sequencing requirements. See Enable and Timed Turn On of the Outputs.

Product Folder Link(s): TPS54386-Q1

5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

TPS54386-Q1

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If the SEQ pin is left floating, output 1 and output 2 each start ratiometrically when both outputs are enabled at

the same time. Output 1 and output 2 soft-start at a rate that is determined by the respective final output voltages

and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently, then the

two outputs also operate independently.

Figure 20. SEQ Pin Floating

Soft Start

Each output has a dedicated soft-start circuit. The soft-start voltage is an internal digital reference ramp to one of

two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total

ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft-start interval, the

TPS54386-Q1 output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the

output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the

internal 0.8-V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains

at the reference voltage.

NOTE

To avoid a disturbance in the output voltage during the stepping of the digital soft-start, a

minimum output capacitance of 50 μF is recommended. See Feedback Loop and Inductor-

Capacitor (L-C) Filter Selection.Once the filter and compensation components have been

established, laboratory measurements of the physical design should be performed to

confirm converter stability.

During the soft-start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six

PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the

Output Overload Protection section.) There is no pulse-skipping if a current-limit pulse is not detected.

DESIGN HINT

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to

support the desired regulation voltage by the time soft-start has completed, then the

output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a

timed-delay start-up from the ENx pin to delay the start-up of the output until the PVDDx

voltage has the capability of supporting the desired regulation voltage. See Operating

Near Maximum Duty Cycle and Maximum Output Capacitance for related information.

Product Folder Link(s): TPS54386-Q1

VREF

VOUT -VREF

R2=R1´

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS5438x

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1

UDG-07011

TPS54386-Q1

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Output Voltage Regulation

Each output has a dedicated feedback loop comprising a voltage-setting divider, an error amplifier, a pulse-width

modulator, and a switching MOSFET. The regulation output voltage is determined by a resistor divider

connecting the output node, the FBx pin, and GND (see Figure 21). Assuming the value of the upper resistor of

the voltage-setting divider is known, the value of the lower divider resistor for a desired output voltage is

calculated by Equation 2.

where

• VREF is the internal 0.8-V reference voltage. (2)

Figure 21. Feedback Network for Channel 1

DESIGN HINT

There is a leakage current of up to 12 μA out of the SW pin when a single output of the

TPS54386-Q1 is disabled. Keeping the series impedance of R1 + R2 less than 50 kΩ

prevents the output from floating above the reference voltage while the controller output is

in the OFF state.

Product Folder Link(s): TPS54386-Q1

TPS5438x

CCOMP

11.5kW

Error Amplifier

0.8VREF

BOOT

RCOMP

Offset f(IDRAIN)

PWMto

Switch

ISLOPE

ICOMP

TPS54383

TPS54386

RCOMP

(kW)

CCOMP

(pF)

700

UDG-07012

ICOMP -ISLOPE

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

Feedback Loop and Inductor-Capacitor (L-C) Filter Selection

In the feedback signal path, the output voltage-setting divider is followed by an internal gM-type error amplifier

with a typical transconductance of 30 μs. An internal series-connected R-C circuit from the gMamplifier output to

ground serves as the compensation network for the converter. The signal from the error amplifier output is then

buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node.

Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal to drive

the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 22.

NOTE

Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow

pulse-width operation, especially at load currents less than 1 A. See SW Node Ringing for

further information on reducing noise on the SWx node.

Figure 22. Feedback-Loop Equivalent Circuit

A more conventional small-signal equivalent block diagram is shown in Figure 23. Here, the full closed-loop

signal path is shown. Because the TPS54386-Q1 contains internal slope-compensation and loop-compensation

components, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria

for stability. This approach differs from an externally-compensated controller, where the L-C filter is generally

selected first, and the compensation network is found afterwards. To find the appropriate L and C filter

combination, the output-to-Vc signal path plots (see the next section) of gain and phase are used along with

other design criteria to aid in finding the combination that best results in a stable feedback loop.

Product Folder Link(s): TPS54386-Q1

VREF

VIN

VOUT

Compensation

Network

Modulator

Filter

Current

Feedback

Network

100 1 M1 k 100 k10 k

-90

135

180

-45

270

225

f - Frequency -Hz

Phase - °

-20

100

Gain - dB

Duty Cycle %

Gain Phase

100 1M1k 100k10k

f Frequency Hz- -

-20

100

-5

-90

135

180

-45

270

225

GainPhase

Gain dB-

Phase -°

DutyCycle%

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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Figure 23. Small-Signal Equivalent Block Diagram

Inductor-Capacitor (L-C) Selection

The following figures plot the TPS54386-Q1 output-to-Vc gain and phase versus frequency for various duty

cycles (10%, 30%, 50%, 70%, 90%) at three (200 mA, 400 mA, 600 mA) peak-to-peak ripple-current levels. The

loop response curve selected to compensate the loop is based on the duty cycle of the application and the ripple

current in the inductor. Once the curve has been selected and the inductor value has been calculated, the output

capacitor is found by calculating the L-C resonant frequency required to compensate the feedback loop. A brief

example follows the curves.

Note that the internal error-amplifier compensation is optimized for output capacitors with an ESR zero frequency

between 20 kHz and 60 kHz. See the following sections for further details.

GAIN AND PHASE GAIN AND PHASE

vs vs

FREQUENCY FREQUENCY

Figure 24. TPS54386-Q1 at 200-mApp Ripple Figure 25. TPS54386-Q1 at 400-mApp Ripple

Current Current

Product Folder Link(s): TPS54386-Q1

100 1M1k 100k10k

-90

135

180

-45

270

225

f Frequency Hz- -

GainPhase

-20

100

-5

Gain dB-

Phase -°

DutyCycle%

C =

OUTmax

tSS

VREF

ICLx V-REF(1 + )

VREF(1 + ) ´ TS

2 VIN

´ ´ LRLOAD

(1 -)

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

GAIN AND PHASE

FREQUENCY

Figure 26. TPS54386-Q1 at 600-mApp Ripple Current

Maximum Output Capacitance

With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance

which may be used before start-up problems begin to occur. If the output capacitance is large enough so that the

device enters a current-limit protection mode during startup, then there is a possibility that the output will never

reach regulation. Instead, the TPS54386-Q1 simply shuts down and attempts a restart as if the output were

short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the

load) is given by Equation 3:

(3)

Minimum Output Capacitance

Ensure the value of capacitance selected for closed-loop stability is compatible with the requirements of Soft

Start.

Modifying The Feedback Loop

Within the limits of the internal compensation, there is flexibility in the selection of the inductor and output-

capacitor values. A smaller inductor increases ripple current, and raises the resonant frequency, thereby

incerasing the required amount of output capacitance. A smaller capacitor could also be used, increasing the

resonant frequency, and increasing the overall loop bandwidth—perhaps at the expense of adequate phase

margin.

The internal compensation of the TPS54x8x is designed for capacitors with an ESR zero frequency between 20

kHz and 60 kHz. It is possible, with additional feedback compensation components, to use capacitors with higher

or lower ESR zero frequencies. For either case, the components C1 and R3 (see Figure 30) are added to re-

compensate the feedback loop for stability. In this configuration, a low frequency pole is followed by a higher-

frequency zero. The placement of this pole-zero pair is dependent on the type of output capacitor used and the

desired closed-loop frequency response.

Product Folder Link(s): TPS54386-Q1

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS5438x

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1

UDG-07013

ZERO(desired)

ESR(zero)

=æ ö

æ ö

ç ÷

è ø

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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Figure 27. Optional Loop Compensation Components

NOTE

Once the filter and compensation components have been established, laboratory

measurements of the physical design should be performed to confirm converter stability.

Using High-ESR Output Capacitors

If a high-ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to

instability. To compensate, a small R-C series connected network is placed in parallel with the lower voltage-

setting divider resistor (see Figure 27). The values of the components are determined such that a pole is placed

at the same frequency as the ESR zero and a new zero is placed at a frequency location conducive to good loop

stability.

The value of the resistor is calculated using a ratio of impedances to match the ratio of ESR zero frequency to

the desired zero frequency.

where:

•fESR(zero) is the ESR zero frequency of the output capacitor.

•fZERO(desired) is the desired frequency of the zero added to the feedback. This frequency should be placed

between 20 kHz and 60 kHz to ensure good loop stability. (4)

Product Folder Link(s): TPS54386-Q1

EQ ESR(zero)

C1 2 R

=p´ ´

R R3

1 1

R1 R2

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

EQ POLE(desired)

C1 2 R

=p´ ´

R R3

1 1

R1 R2

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

( )

1 R1

C2 1

2 R1 R2 R3

R2 R3

= ´ +

p´ ´ æ ö

ç ÷

è ø

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

The value of the capacitor is calculated in Equation 5.

where:

• REQ is an equivalent impedance created by the parallel combination of the voltage-setting divider resistors (R1

and R2) in series with R3. (5)

(6)

Using All Ceramic Output Capacitors

With low-ESR ceramic capacitors, there may not be enough phase margin at the crossover frequency. In this

case (see Figure 27), resistor R3 is set equal to 1/2 R2. This lowers the gain by 6 dB, reduces the crossover

frequency, and improves phase margin.

The value of C1 is found by determining the frequency at which to place the low-frequency pole. The minimum

frequency at which to place the pole is 1 kHz. Any lower, and the time constant will be too slow and interfere with

the internal soft-start (see Soft Start). The upper bound for the pole frequency is determined by the operating

frequency of the converter. It is 3 kHz for the TPS54x83, and 6 kHz for the TPS54x86. C1 is then found from

Equation 7. Keep component tolerances in mind when selecting the desired pole frequency.

where:

•fPOLE(desired) is the desired pole frequency between 1 kHz and 3 kHz (TPS54x83) or 1 kHz and 6 kHz

(TPS54x86).

• REQ is an equivalent impedance created by the parallel combination of the voltage-setting divider resistors (R1

and R2) in series with R3. (7)

(8)

If it is necessary to increase phase margin, place a capacitor in parallel with the upper voltage-setting divider

resistor (C2 in Equation 9).

where

•fCis the unity-gain crossover frequency, (approximately 50 kHz for most designs following these guidelines).(9)

Product Folder Link(s): TPS54386-Q1

VOUT DIODE

VIN +VDIODE

3.3 0.5+

12 0.5+

d===30%

IN OUT

V V 12 3.3 1

L T 0.3 10.9 H

I 0.4 600000

= ´ d ´ = ´ ´ = m

( ) ( )

2 2

RES

1 1

C 70 F

10 10 2 3.14 6000

L 2 f -

= = = m

´ ´ ´ ´

´ ´ p´

( )

ESR 6

RES

1 1

R 40 m

2 10 C 2 3.14 10 6000 68 10 -

< = » W

´ p´ ´ ´ ´ ´ ´ ´ ´

100 1M1k 100k10k

-20

-180

-90

-45

-135

180

135

f Frequency Hz- -

Gain

Phase

-10

Gain dB-

Phase -°

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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Example: TPS54386-Q1 Buck Converter Operating at 12-V Input, 3.3-V Output and 400-mA(P-P) Ripple

Current

First, the steady-state duty cycle is calculated. Assuming the rectifier diode has a voltage drop of 0.5 V, the duty

cycle is approximated using Equation 10.

(10)

The filter inductor is then calculated; see Equation 11.

(11)

A custom-designed inductor may be used for the application, or a standard value close to the calculated value

may be used. For this example, a standard 10-μH inductor is used. Using Figure 25, find the 30% duty cycle

curve. The 30% duty cycle curve has a down slope from low frequency and rises at approximately 6 kHz. This

curve is the resonant frequency that must be compensated. Any frequency within an octave of the peak may be

used in calculating the capacitor value. In this example, 6 kHz is used.

(12)

A 68-μF capacitor should be used as a bulk capacitor, with up to 10 μF of ceramic bypass capacitance. To

ensure the ESR zero does not significantly impact the loop response, the ESR of the bulk capacitor should be

placed a decade above the resonant frequency.

(13)

The resulting loop gain and phase are shown in Figure 28. Based on measurement, loop crossover is 45 kHz

with a phase margin of 60 degrees. GAIN AND PHASE

FREQUENCY

Figure 28. Example Loop Result

Product Folder Link(s): TPS54386-Q1

IDCM =´

2´ d ´ TS

V V

IN OUT

TPS54386-Q1

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Bootstrap for the N-Channel MOSFET

A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully

enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%,

allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and

BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the

MOSFET gate is derived from the voltage on this capacitor.

To allow the bootstrap capacitor to charge each switching cycle, an internal pulldown MOSFET (from SW to

GND) is turned ON for approximately 140 ns at the beginning of each switching cycle. In this way, if, during light

load operation, there is insufficient energy for the SW node to drive to ground naturally, this MOSFET forces the

SW node toward ground and allows the bootstrap capacitor to charge.

Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It

must be sized such that the energy stored in the capacitor on a per-cycle basis is greater than the gate charge

requirement of the MOSFET being used.

DESIGN HINT

For the bootstrap capacitor, use a ceramic capacitor with a value between 22 nF and 82

nF.

NOTE

For 5-V input applications, connect PVDDx to BP directly. This connection bypasses the

internal control-circuit regulator and provides maximum voltage to the gate-drive circuitry.

In this configuration, shutdown mode IDDSDN is the same as quiescent IDDQ.

Light Load Operation

There is no special circuitry for pulse skipping at light loads. The normal characteristic of a nonsynchronous

converter is to operate in the discontinuous-conduction mode (DCM) at an average load current less than one-

half of the inductor peak-to-peak ripple current. Note that the amplitude of the ripple current is a function of input

voltage, output voltage, inductor value, and operating frequency, as shown in Equation 14.

(14)

Further, during discontinuous-mode operation the commanded pulse duration may become narrower than the

capability of the converter to resolve. To maintain the output voltage within regulation, skipping switching pulses

at light load conditions is a natural byproduct of that mode. This condition may occur if the output capacitor is

charged to a value greater than the output regulation voltage and there is insufficient load to discharge the

capacitor. A byproduct of pulse skipping is an increase in the peak-to-peak output ripple voltage.

Product Folder Link(s): TPS54386-Q1

Inductor

Current

VOUT

Ripple

SW Waveform

Steady State

VIN = 12 V

VOUT = 5 V

SW Waveform

VOUT

Ripple Inductor

Current

Skipping

VIN = 12 V

VOUT = 5 V

TPS54386-Q1

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Figure 29. Steady State Figure 30. Skipping

DESIGN HINT

If additional output capacitance is required to reduce the output-voltage ripple during DCM

operation, be sure to recheck the Feedback Loop and Inductor-Capacitor (L-C) Filter

Selection and Maximum Output Capacitance sections.

SW Node Ringing

A portion of the control circuitry is referenced to the SW node. To ensure jitter-free operation, it is necessary to

decrease the voltage waveform ringing at the SW node to less than 5 volts peak and of a duration of less than

30-ns. In addition to following good printed-circuit board (PCB) layout practices, there are a couple of design

techniques for reducing ringing and noise.

SW Node Snubber

Voltage ringing observable at the SW node is caused by fast switching edges and parasitic inductance and

capacitance. If the ringing results in excessive voltage on the SW node, or erratic operation of the converter, an

R-C snubber may be used to dampen the ringing and ensure proper operation over the full load range.

DESIGN HINT

A series-connected R-C snubber (C = between 330 pF and 1 nF, R = 10 Ω) connected

from SW to GND reduces the ringing on the SW node.

Bootstrap Resistor

A small resistor in series with the bootstrap capacitor reduces the turnon time of the internal MOSFET, thereby

reducing the rising-edge ringing of the SW node.

DESIGN HINT

A resistor with a value between 1 Ωand 3 Ωmay be placed in series with the bootstrap

capacitor to reduce ringing on the SW node.

DESIGN HINT

Placeholders for these components should be placed on the initial prototype PCBs in case

they are needed.

Product Folder Link(s): TPS54386-Q1

OUT DIODE

IN DIODE

V V

d = +

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Output Overload Protection

In the event of an overcurrent during soft-start on either output (such as starting into an output short), pulse-by-

pulse current limiting and PWM frequency division are in effect for that output until the internal soft-start timer

ends. At the end of the soft-start time, a UV condition is declared and a fault is declared. During this fault

condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON.

This process ensures that both outputs discharge to GND in the event that overcurrent is on one output while the

other is not loaded. The converter then enters a hiccup-mode time-out before attempting to restart. Frequency

division means if an overcurrent pulse is detected, six clock cycles are skipped before the next PWM pulse is

initiated, effectively dividing the operating frequency by six and preventing excessive current buildup in the

inductor.

In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is

in effect for that output. In addition, an output undervoltage (UV) comparator monitors the FBx voltage (that

follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault

condition, both PWM outputs are disabled and the small pulldown MOSFETs (from SWx to GND) are turned ON.

This design ensures that both outputs discharge to GND, in the event that overcurrent is on one output while the

other is not loaded. The converter then enters a hiccup-mode timeout before attempting to restart.

The overcurrent threshold for output 1 is set nominally at 4.5 A. The overcurrent level of output 2 is determined

by the state of the ILIM2 pin. The ILIM setting of output 2 is not latched in place and may be changed during

operation of the converter.

Table 3. Current Limit Threshold Adjustment for

Output 2

ILIM2 Connection OCP Threshold for Output 2

BP 4.5-A nominal setting

(floating) 3-A nominal setting

GND 1.5-A nominal setting

DESIGN HINT

The OCP threshold refers to the peak current in the internal switch. Be sure to add one-

half of the peak inductor ripple current to the dc load current in determining how close the

actual operating point is to the OCP threshold.

Operating Near Maximum Duty Cycle

If the TPS54386-Q1 operates at maximum duty cycle, and if the input voltage is insufficient to support the output

voltage (at full load or during a load-current transient), then there is a possibility that the output voltage will fall

from regulation and trip the output UV comparator. If this should occur, the TPS54386-Q1 protection circuitry

declares a fault and enters a shut-down-and-restart cycle.

DESIGN HINT

Ensure that under ALL conditions of line and load regulation, there is sufficient duty cycle

to maintain output-voltage regulation.

To calculate the operating duty cycle, use Equation 15.

where

• VDIODE is the voltage drop of the rectifier diode. (15)

Product Folder Link(s): TPS54386-Q1

PVDD2

BOOT2

SW2

PVDD1

BOOT1

SW1

GND

TPS54383

SEQ

ILIM2

FB2

EN1

EN2

FB1

OUTPUT1 OUTPUT2

VIN

UDG-07015

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Dual-Supply Operation

It is possible to operate a TPS54386-Q1 from two supply voltages. If this application is desired, then the

sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise.

This level requirement ensures that the internal regulator and the control circuitry are in operation before PVDD1

supplies energy to the output. In addition, output 1 must be held in the disabled state (EN1 high) until there is

sufficient voltage on PVDD1 to support output 1 in regulation. (See the Operating Near Maximum Duty Cycle

section.)

The preferred sequence of events is:

1. PVDD2 rises above the input UVLO voltage.

2. PVDD1 rises with output 1 disabled until PVDD1 rises above the level to support output 1 regulation.

With these two conditions satisfied, there is no restriction on PVDD2 to be greater than or less than PVDD1.

DESIGN HINT

An R-C delay on EN1 may be used to delay the start-up of output 1 for a long-enough

period of time to ensure that PVDD1 can support the output 1 load.

Cascading Supply Operation

It is possible to source PVDD1 from output 2 as depicted in Figure 31 and Figure 32. This configuration may be

preferred if the input voltage is high, relative to the voltage on output 1.

Figure 31. Schematic Showing Cascading PVDD1 From Output 2

Product Folder Link(s): TPS54386-Q1

T Time-

Output1

Output2

PVDD1

PVDD2

TPS54386-Q1

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Figure 32. Waveforms Resulting From Cascading PVDD1 From Output 2

In this configuration, the following conditions must be maintained:

1. Output 2 must be of a voltage high enough to maintain regulation of output 1 under all load conditions.

2. The sum of the current drawn by output 2 load plus the current into PVDD1 must be less than the overload

protection current level of output 2.

3. The method of output sequencing must be such that the voltage on output 2 is sufficient to support output 1

before output 1 is enabled. This requrement may be accomplished by:

(a) a delay of the enable function

(b) selecting sequential sequencing of output 1 starting after output 2 is in regulation

Multiphase Operation

The TPS54386-Q1 is not designed to operate as a two-channel multiphase converter. See

http://www.power.ti.com for appropriate device selection.

Bypass and FIltering

As with any integrated circuit, supply bypassing is important for jitter-free operation. To improve the noise

immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible.

1. PVDD1 to GND: Use a 10-μF ceramic capacitor.

2. PVDD2 to GND: Use a 10-μF ceramic capacitor.

3. BP to GND: Use a 4.7-μF to 10-μF ceramic capacitor.

Overtemperature Protection and Junction Temperature Rise

The overtemperature thermal protection limits the maximum power to be dissipated at a given operating ambient

temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is

limited by the maximum allowable junction operating temperature. The device junction temperature is a function

of power dissipation and the thermal impedance from the junction to ambient. If the internal die temperature

should reach the thermal shutdown level, the TPS54386-Q1 shuts off both PWMs and remains in this state until

the die temperature drops below the hysteresis value, at which time the device restarts.

The first step to determine the device junction temperature is to calculate the power dissipation. The power

dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by

each MOSFET is composed of conduction losses and output (switching) losses incurred while driving the

external rectifier diode. To find the conduction loss, first find the rms current through the upper switch MOSFET.

Product Folder Link(s): TPS54386-Q1

( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

D(cond) RMS(outputx) DS(on)

P I R= ´

PD(SW) =

(V ) C f

IN J S

2´ ´

D D(cond)output1 D(SW )output1 D(cond)output2 D(SW )output2 IN

P P P P P V Iq= + + + + ´

( )

J A D TH(pkg) TH(pad amb)

T T P -

= + ´ q + q

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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where

• D is the duty cycle.

• IOUTPUTx is the dc output current.

•ΔIOUTPUTx is the peak ripple current in the inductor for output x. (16)

Notice the impact of the operating duty cycle on the result.

Multiplying the result by the RDS(on) of the MOSFET gives the conduction loss.

(17)

The switching loss is approximated by:

where

• where CJis the parallel capacitance of the rectifier diode and snubber (if any).

• fSis the switching frequency. (18)

The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal

regulator.

(19)

The temperature rise of the device junction depends on the thermal impedance from the junction to the mounting

pad (see the Package Dissipation Ratings table), plus the thermal impedance from the thermal pad to ambient.

The thermal impedance from the thermal pad to ambient depends on the PCB layout (thermal-pad interface to

the PCB, the exposed pad area) and airflow (if any). See the PCB Layout Guidelines, Additional References

section.

The operating junction temperature is shown in Equation 20.

(20)

Power Derating

The TPS54386-Q1 delivers full current at ambient temperatures up to 85°C if the thermal impedance from the

thermal pad maintains the junction temperature below the thermal shutdown level. At higher ambient

temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the

thermal shutdown level. Figure 33 illustrates the power derating for elevated ambient temperature under various

airflow conditions. Note that these curves assume that the thermal pad is properly soldered to the recommended

board. (See the References section for further information.)

Product Folder Link(s): TPS54386-Q1

0.4

0.6

0.8

1.0

1.8

0.2

0 20 40 60 14080 100 120

TA- Ambient Temperature - °C

PD- Power Dissipation - W

150

250

500

LFM

1.2

1.6

1.4

LFM = 0

LFM = 150

LFM = 250

LFM = 500

TPS54386-Q1

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POWER DISSIPATION

AMBIENT TEMPERATURE

Figure 33. Power-Derating Curves

PowerPAD Package

The PowerPAD package provides low thermal impedance for heat removal from the device. The thermal pad

derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit

board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend

on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and

should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via

is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the

package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13

mils) work well when 1-oz. copper is plated at the surface of the board while simultaneously plating the barrel of

the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material

should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping

prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the

package. (See the Additional References section.)

PCB Layout Guidelines

The layout guidelines presented here are illustrated in the PCB layout examples given in Figure 34 and

Figure 35.

• The thermal pad must be connected to a low-current (signal) ground plane having a large copper surface

area to dissipate heat. Extend the copper surface well beyond the IC package area to maximize thermal

transfer of heat away from the IC.

• Connect the GND pin to the thermal pad through a 10-mil (0.010-in, or 0.254-mm) wide trace.

• Place the ceramic input capacitors close to PVDD1 and PVDD2; connect using short, wide traces.

• Maintain a tight loop of wide traces from SW1 or SW2 through the switch node, inductor, output capacitor,

and rectifier diode. Avoid using vias in this loop.

• Use a wide ground connection from the input capacitor to the rectifier diode, placed as close to the power

path as possible. Placement directly under the diode and the switch node is recommended.

• Locate the bootstrap capacitor close to the BOOT pin to minimize the gate-drive loop.

• Locate voltage-setting resistors and any feedback components over the ground plane and away from the

switch node and the rectifier diode to the input-capacitor ground connection.

• Locate snubber components (if used) close to the rectifier diode with minimal loop area.

Product Folder Link(s): TPS54386-Q1

VIN

GND

C1 C10

C16

C17

C14

C11

C13

C18

C19

C12

C15

GND

VOUT1

VOUT2

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• Locate the BP bypass capacitor very close to the IC; a minimal loop area is recommended.

• Locate the output ceramic capacitor close to the inductor output terminal between the inductor and any

electrolytic capacitors, if used.

Figure 34. Top Layer Copper Layout and Component Placement

Product Folder Link(s): TPS54386-Q1

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Figure 35. Bottom Layer Copper Layout

Product Folder Link(s): TPS54386-Q1

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DESIGN EXAMPLES

Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter

The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual

non-synchronous buck regulator using the TPS54386-Q1 converter. Design Example List of Materials and

Table 5, Definition of Symbols is found at the end of this section.

PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT

INPUT CHARACTERISTICS

VIN Input voltage 6.9 12 13.2 V

IIN Input current VIN = nom, IOUT = max 1.6 2 A

No load input current VIN = nom, IOUT = 0 A 12 20 mA

OUTPUT CHARACTERISTICS

VOUT1 Output voltage 1 VIN = nom, IOUT = nom 4.8 5 5.2 V

VOUT2 Output voltage 2 VIN = nom, IOUT = nom 3.2 3.3 3.4

Line regulation VIN = min to max 1%

Load regulation IOUT = min to max 1%

VOUT(ripple Output voltage ripple VIN = nom, IOUT = max 50 mVPP

)

IOUT1 Output current 1 VIN = min to max 0 2

IOUT2 Output current 2 VIN = min to max 0 2

Output overcurrent channel A

IOCP1 VIN = nom, VOUT = VOUT1 = 5% 2.4 3 3.5

Output overcurrent channel

IOCP2 VIN = nom, VOUT = VOUT2 = 5% 2.4 3 3.5

Transient response ΔVOUT ΔIOUT = 1 A at 3 A/μs 200 mV

from load transient

Transient response settling 1 ms

time

SYSTEM CHARACTERISTICS

fSW Switching frequency 250 310 370 kHz

ηFull-load efficiency 85%

Operating temperature

TJ0 25 60 °C

range

Figure 36. Design Example Schematic

Product Folder Link(s): TPS54386-Q1

OUT FD

max

IN(min) FD

V V

DV V

»+

OUT FD

min

IN(max) FD

V V

DV V

»+

IN(max) OUT

min m in

LRIP(max) SW

V V 1

L D

I f

» ´ ´

IN(max) OUT

RIPPLE min

V V 1

I D

L f

» ´ ´

( ) ( ) ( )

L(avg) RIPPLE

L rms

I I I

= +

( ) OUT(max) RIPPLE

L peak

I I I

» +

( ) ( ) IN

BR R min

V 1.2 V³ ´

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

Design Procedure

Duty Cycle Estimation

The first step is to estimate the duty cycle of each switching FET.

(21)

(22)

Using an assumed forward drop of 0.5 V for a Schottky rectifier diode, the channel 1 duty cycle is approximately

40.1% (minimum) to 48.7% (maximum), while the channel 2 duty cycle is approximately 27.7% (minimum) to

32.2% (maximum).

Inductor Selection

The peak-to-peak ripple is limited to 30% of the maximum output current. This places the peak current far

enough from the minimum overcurrent trip level to ensure reliable operation.

For both channel 1 and channel 2, the maximum inductor ripple current is 600 mA. The inductor size is estimated

in Equation 23.

(23)

The inductor values are

• L1 = 18.3 μH

• L2 = 15.3 μH

The next-higher standard inductor value of 22 μH is used for both inductors.

The resulting ripple currents are :

(24)

Peak-to-peak ripple currents of 0.498 A and 0.416 A are estimated for channel 1 and channel 2, respectively.

The rms current through an inductor is approximated by Equation 25.

(25)

and is approximately 2 A for both channels.

The peak inductor current is found using:

(26)

An inductor with a minimum rms current rating of 2 A and minimum saturation current rating of 2.25 A is required.

A Coilcraft MSS1278-223ML 22-μH, 6.8-A inductor is selected.

Rectifier Diode Selection

A Schottky diode is selected as a rectifier diode for its low forward-voltage drop. Allowing 20% over VIN for

ringing on the switch node, the required minimum reverse-breakdown voltage of the rectifier diode is:

(27)

Product Folder Link(s): TPS54386-Q1

( ) ( ) ( )

D avg OUT max

I I 1 D» ´ -

( ) ( )

D m ax D a vg

P V I» ´

( )

OUT 2

2RES

4 f L

=´ p ´ ´

OUT

RIPPLE(tot) RIPPLE(cap) RIPPLE(tot)

(max)

RIPPLE RIPPLE S

V V V D

ESR I I f C

= = - ´

OUT1 FB

V R2

V V

OUT2 FB

V R9

V V

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The diode must have reverse breakdown voltage greater than 15.8 V, therefore a 20-V device is used.

The average current in the rectifier diode is estimated by Equation 28.

(28)

For this design, 1.2-A (average) and 2.25 A (peak) is estimated for channel 1 and 1.5-A (average) and 2.21-A

(peak) for channel 2.

An MBRS320, 20-V, 3-A diode in an SMC package is selected for both channels. This diode has a forward

voltage drop of 0.4 V at 2 A.

The power dissipation in the diode is estimated by Equation 29.

(29)

For this design, the full-load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2.

Output Capacitor Selection

The TPS54386-Q1 internal compensation limits the selection of the output capacitors. From , the internal

compensation has a double zero resonance at about 3 kHz. The output capacitor is selected by Equation 30.

(30)

Solving for COUT using

• fRES = 3 kHz

• L = 22 μH

The resulting is COUT = 128 μF. The output ripple voltage of the converter is composed of the ripple voltage

across the output capacitance and the ripple voltage across the ESR of the output capacitor. To find the

maximum ESR allowable to meet the output ripple requirements, the total ripple is partitioned and the equation

solved to find the ESR.

(31)

Based on 128 μF of capacitance, 300-kHz switching frequency, and 50-mV ripple voltage, plus rounding up the

ripple current to 0.5 A and the duty cycle to 50%, the capacitive portion of the ripple voltage is 6.5 mV, leaving a

maximum allowable ESR of 87 mΩ.

To meet the ripple-voltage requirements, a low-cost 100-μF electrolytic capacitor with 400 mΩESR (C5, C17)

and two 10-μF ceramic capacitors (C3 and C4; and C18 and C19) with 2.5-mΩESR are selected. From the data

sheets for the ceramic capacitors, the parallel combination provides an impedance of 28 mΩat 300 kHz for 14

mV of ripple.

Voltage Setting

The primary feedback divider resistors (R2, R9) from VOUT to FB should be between 10 kΩand 50 kΩto

maintain a balance between power dissipation and noise sensitivity. For this design, 20 kΩis selected.

The lower resistors, R4 and R7 are found using the following equations.

(32)

(33)

• R2 = R9 = 20 kΩ

• VFB = 0.8 V

Product Folder Link(s): TPS54386-Q1

fESR(zero)

2 C ESR

=´ p´ ´

ZERO(desired)

ESR(zero)

=æ ö

æ ö

ç ÷

è ø

R R5

1 1

R2 R4

= + æ ö

æ ö æ ö

ç ÷

ç ÷ ç ÷

è ø è ø

è ø

EQ ESR(zero)

C8 2 R

=´ p´ ´

( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

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• R4 = 3.8 kΩ(3.83 kΩstandard value is used)

• R7 = 6.4 kΩ(6.34 kΩstandard value is used)

Compensation Capacitors

Checking the ESR zero of the output capacitors:

• C = 100 μF

• ESR = 400 mΩ

• ESR(zero) = 3980 Hz (34)

Because the ESR zero of the main output capacitor is less than 20 kHz, an R-C filter is added in parallel with R4

and R7 to compensate for the ESR of the electrolytic capacitor and add a zero of approximately 40 kHz.

• fESR(zero) = 4 kHz

• fESR(desired) = 40 kHz

• R4 = 3.83 kΩ

• R5 = 424 Ω(422 Ωselected)

• R7 = 6.34 kΩ

• R8 = 702 Ω(698 Ωselected) (35)

• R2 = R9 = 20 kΩ

• REQ1 = 3.63 kΩ

• REQ2 = 5.51 kΩ(36)

• C8 = 10.9 nF (10 nF selected)

• C15 = 7.22 nF (6800 pF selected) (37)

Input Capacitor Selection

The TPS54386-Q1 data sheet recommends a minimum 10-μF ceramic input capacitor on each PVDD pin. These

capacitors must be capable of handling the rms ripple current of the converter. The rms current in the input

capacitors is estimated by Equation 38.

(38)

• IRMS(CIN) = 0.43 A

One 1210 10-μF, 25-V, X5R ceramic capacitor with 2-mΩESR and a 2-A rms current rating is selected for each

PVDD input. Higher-voltage capacitors are selected to minimize capacitance loss at the dc bias voltage to ensure

the capacitors maintain sufficient capacitance at the working voltage.

Product Folder Link(s): TPS54386-Q1

( ) ( )2

2OUTPUTx

RMS(outputx) OUTPUTx

I D I 12

æ ö

ç ÷

= ´ +

ç ÷

è ø

( ) ( )

()

CON DS on QSW rms

P R I= ´

( )

()( )

DJ OSS SW

IN max

V C C f

´ + ´

( ) ( )

()

REG DD BP BP

IN max IN max

P I V I V V» ´ + ´ -

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Bootstrap Capacitor

To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 33-nF

bootstrap capacitor is used.

ILIM

Current limit must be set above the peak inductor current IL(peak). Comparing IL(peak) to the available minimum

current limits, ILIM is connected to BP for the highest current-limit level.

SEQ

The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied

together, the two supplies start up ratiometrically. Alternatively, SEQ could be connected to BP or GND to

provide sequential start-up.

Power Dissipation

The power dissipation in the TPS54386-Q1 is composed of FET conduction losses, switching losses, and

internal regulator losses. The rms FET current is found using Equation 39.

(39)

This results in 1.05 -A rms for channel 1 and 0.87 A rms for channel 2.

Conduction losses are estimated by:

(40)

Conduction losses of 198 mW and 136 mW are estimated for channel 1 and channel 2 respectively.

The switching losses are estimated in Equation 41.

(41)

From the data sheet of the MBRS320, the junction capacitance is 658 pF. Because this is large compared to the

output capacitance of the TPS54x8x, the FET capacitance is neglected, leaving switching losses of 17 mW for

each channel.

The regulator losses are estimated in Equation 42.

(42)

With no external load on BP (IBP = 0), the power dissipation of the regulator is 66 mW.

Total power dissipation in the device is the sum of conduction and switching for both channels, plus regulator

losses.

The total power dissipation is PDISS = 0.198 + 0.136 + 0.017 + 0.017 + 0.066 = 434 mW.

Design Example Test Results

The following results are from the TPS54386-Q1-001 EVM.

Product Folder Link(s): TPS54386-Q1

SW 3.3 V

SW 5 V

VIN = 12 V

t − Time − 40 ns/div

100

ILOAD - Load Current - A

h- Efficiency - %

VIN = 13.2 V

VIN = 9.6 V

VIN = 12.0 V

VOUT = 5.0 V

VIN (V)

9.6

12.0

13.2

0 0.5 1.0 1.5 2.0 2.5 3.0

100

ILOAD - Load Current - A

h- Efficiency - %

VIN = 9.6 V

VOUT = 3.3 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

TPS54386-Q1

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Figure 37. Switching-Node Waveforms

Figure 38. 5-V Output Efficiency vs Load Current Figure 39. 3.3-V Output Efficiency vs Load Current

Product Folder Link(s): TPS54386-Q1

0.995

0.997

0.999

1.001

0.996

0.998

1.000

1.003

1.005

1.002

1.004

VOUT - Output Voltage (Normalized) - V

VOUT = 5.0 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 9.6 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

0.995

0.997

0.999

1.001

0.996

0.998

1.000

1.003

1.005

1.002

1.004

VOUT - Output Voltage (Normalized) - V

VOUT = 3.3 V

VIN (V)

9.6

12.0

13.2

VIN = 12.0 V

VIN = 9.6 V

VIN = 13.2 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

1 k 10 k 100 k

f - Frequency -Hz

-80

-20

-60

Gain - dB

-40

-180

-90

-45

-135

180

135

Phase - °

300 k

Gain Phase

5.0 V

3.3 V

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

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Figure 40. 5-V Output Voltage vs Load Current Figure 41. 3.3-V Output Voltage vs Load Current

Figure 42. Example 1 Loop Response

Product Folder Link(s): TPS54386-Q1

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Table 4. Design Example List of Materials

REFERENCE

QTY VALUE DESCRIPTION SIZE PART NUMBER MANUFACTURER

DESIGNATOR

1 C1 100 μF Capacitor, Aluminum, 25V, 20% E-can EEEFC1E101P Panasonic

2 C10, C11 10 μF Capacitor, Ceramic, 25V, X5R 20% 1210 C3216X5R1E106M TDK

1 C12 4.7 μF Capacitor, Ceramic, 10V, X5R 20% 0805 Std Std

2 C14, C16 470 pF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std

1 C15 6.8 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std

Capacitor, Aluminum, 10V, 20%, FC

1 C17, C5 100 μF F-can EEEFC1A101P Panasonic

Series

4 C3, C4, C18, C19 10 μF Capacitor, Ceramic, 6.3V, X5R 20% 0805 C2012X5R0J106M TDK

1 C8 10 nF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std

2 C9, C13 0.033 μF Capacitor, Ceramic, 25V, X7R, 20% 0603 Std Std

2 D1, D2 MBRS320 Diode, Schottky, 3-A, 30-V SMC MBRS330T3 On Semi

0.484 x

2 L1, L2 22 μH Inductor, Power, 6.8A, 0.038 ΩMSS1278-153ML Coilcraft

0.484

2 R2, R9 20 kΩResistor, Chip, 1/16W, 1% 0603 Std Std

1 R5 422 ΩResistor, Chip, 1/16W, 1% 0603 Std Std

2 R6, R10 10 ΩResistor, Chip, 1/16W, 5% 0603 Std Std

1 R8 698 ΩResistor, Chip, 1/16W, 1% 0603 Std Std

1 R4 3.83 kΩResistor, Chip, 1/16W, 1% 0603 Std Std

1 R7 6.34 kΩResistor, Chip, 1/16W, 1% 0603 Std Std

TPS54386-Q1 DC-DC Switching HTSSOP

1 U1 TPS54386-Q1PWP TI

Converter w/ FET -14

Product Folder Link(s): TPS54386-Q1

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Table 5. Definition of Symbols

CDJ Average junction capacitance of the rectifier diode from 0 V to VIN(max)

COSS Average output capacitance of the switching MOSFET from 0 V to VIN(max)

COUT Output capacitor

D(max) Maximum steady-state operating duty cycle

D(min) Minimum steady-state operating duty cycle

ESR(max) Maximum allowable output-capacitor ESR

fSW Switching frequency

IBP Output current of BP regulator due to external loads

IDD Switching quiescent current with no load on BP

ID(avg) Average diode conduction current

ID(peak) Peak diode conduction current

IIN(avg) Average input current

IIN(rms) Root mean squared (RMS) input current

IL(avg) Average inductor current

IL(rms) Root mean squared (RMS) inductor current

IL(peak) Peak current in inductor

ILRIP(max) Maximum allowable inductor ripple current

L(min) Minimum inductor value to maintain desired ripple current

IOUT(max) Maximum designed output current

IRMS(cin) Root mean squared (RMS) current through the input capacitor

IRIPPLE Inductor peak-to-peak ripple current

IQSW(rms) Root mean squared current through the switching MOSFET

PCON Power loss due to conduction through switching MOSFET

PD(max) Maximum power dissipation in diode

RDS(on) Drain-to-source resistance of the switching MOSFET when ON

PSW Power loss due to switching

PREG Power loss due to the internal regulator

VBP Output voltage of BP regulator

V(BR)R(min) Minimum reverse-breakdown voltage rating for rectifier diode

VFB Regulated feedback voltage

VFD Forward voltage drop across rectifier diode

VIN Power-stage input voltage

VOUT Regulated output voltage

VRIPPLE(cap) Peak-to-peak ripple voltage due to ideal capacitor (ESR = 0 Ω)

VRIPPLE(tot) Maximum allowable peak-to-peak output ripple voltage

Product Folder Link(s): TPS54386-Q1

VOUT

(5 V/div)

VIN = 24 V

IOUT = 2 A

T − Time − 10 ns / div

VOUT

(5 V/div)

VIN = 24 V

IOUT = 2 A

T − Time − 10 ns / div

TPS54386-Q1

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SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

Example 2: 24 V to 12 V and 24 V to 5 V

For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch

node and a 30-V Schottky diode is selected. A higher-resistance feedback network is chosen for the 12-V output

to reduce the feedback current.

Figure 43. 24 V to 12 V and 24 V to 5 V Using the TPS54386-Q1

Figure 44. Switch Node Ringing Without Snubber Figure 45. Switch Node Ringing With Snubber and

and Boost Resistor Boost Resistor

Product Folder Link(s): TPS54386-Q1

h- Efficiency - %

VOUT = 12 V

VOUT = 5 V

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

VIN = 24 V

VOUT (V)

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

www.ti.com

Figure 46. Efficiency vs Load Current

Product Folder Link(s): TPS54386-Q1

1 k 10 k 100 k 300 k

-180

-90

-45

-135

180

135

f - Frequency -Hz

Phase - °

-80

-20

-60

Gain - dB

-40

VOUT = 1.2 V

Gain Phase

WIth Lead

Without Lead

100

h- Efficiency - %

0 0.5 1.0 1.5 2.0 2.5 3.0

IOUT - Load Current - A

VOUT = 1.2 V

VOUT = 3.3 V

VIN = 5 V

VOUT (V)

1.2

3.3

TPS54386-Q1

www.ti.com

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

Example 3: 5 V to 3.3 V and 5 V to 1.2 V

For a low-input-voltage application, the TPS54386-Q1 is selected for reduced size, and all ceramic output

capacitors are used. 22-μF input capacitors are selected to reduce input ripple and lead capacitors are placed in

the feedback to boost phase margin.

Figure 47. 5 V to 3.3 V and 5 V to 1.2 V

Figure 48. Efficiency vs Load Current Figure 49. Example 3 Loop Response

Product Folder Link(s): TPS54386-Q1

TPS54386-Q1

SLUSAZ9A –MARCH 2012–REVISED MARCH 2012

www.ti.com

ADDITIONAL REFERENCES

Related Devices

The following parts have characteristics similar to the TPS54386-Q1 and may be of interest.

Table 6. Devices Related to the TPS54386-Q1

TI LITERATURE DEVICE DESCRIPTION

NUMBER

SLUS642 TPS40222 5-V input, 1.6-A non-synchronous buck converter

TPS54283 /

SLUS749 2-A dual non-synchronous converter with integrated high-side MOSFET

TPS54286

References

These references, design tools, and links to additional references, including design software, may be found at

http:www.power.ti.com

Table 7. References

TI LITERATURE DESCRIPTION

NUMBER

SLMA002 PowerPAD Thermally Enhanced Package Application Report

SLMA004 PowerPAD™ Made Easy

SLUP206 Under the Hood Of Low Voltage DC/DC Converters. SEM1500 Topic 5, 2002 Seminar Series

SLVA057 Understanding Buck Power Stages in Switchmode Power Supplies

SLUP173 Designing Stable Control Loops. SEM 1400, 2001 Seminar Series

Package Outline and Recommended PCB Footprint

The following pages outline the mechanical dimensions of the 14-Pin PWP package and provide

recommendations for PCB layout.

Product Folder Link(s): TPS54386-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

TPS54386TPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 54386T

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54386-Q1 :

•Catalog: TPS54386

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS54386TPWPRQ1 HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS54386TPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Feb-2016

Pack Materials-Page 2

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TPS54386TPWPRQ1