Cover 88PL810/88PL815/88PL830 High Current, Adjustable 8 Level LDO Regulator Datasheet Doc. No. MV-S102944-00, Rev. E January 21, 2008 Marvell. Moving Forward Faster Document Classification: Proprietary 88PL810/88PL815/88PL830 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 1.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S102944-00 Rev. E Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 1 List of Tables .............................................................................................................................................. 1 List of Figures............................................................................................................................................. 1 1 Signal Description ......................................................................................................................... 5 1.1 Pin Configuration...............................................................................................................................................5 1.2 Pin Description ..................................................................................................................................................6 1.2.1 Pin Types ............................................................................................................................................6 2 Electrical Specifications ............................................................................................................... 7 2.1 Absolute Maximum Ratings ..............................................................................................................................7 2.2 Recommended Operating Conditions ...............................................................................................................7 2.3 Electrical Characteristics ...................................................................................................................................8 3 Functional Description................................................................................................................ 11 3.1 Output Voltage - AnyVoltageTM Technology...................................................................................................12 3.2 Soft Start .........................................................................................................................................................13 3.3 Hiccup Current Limit........................................................................................................................................14 3.4 Output Capacitor (COUT) Selection................................................................................................................15 3.5 Input Capacitor ................................................................................................................................................15 3.6 Enable .............................................................................................................................................................15 3.7 Minimum Load Current....................................................................................................................................15 3.8 Undervoltage Lockout (UVLO) ........................................................................................................................16 3.9 Thermal Shutdown ..........................................................................................................................................16 3.10 Thermal Considerations ..................................................................................................................................17 4 Functional Characteristics ......................................................................................................... 19 5 Typical Characteristics ............................................................................................................... 21 5.1 IC Case and Board Temperature ....................................................................................................................21 6 Mechanical Drawings .................................................................................................................. 25 6.1 Mechanical Dimensions ..................................................................................................................................25 6.1.1 MSOP-8 Package .............................................................................................................................25 6.1.2 5x5mm QFN-5L Package .................................................................................................................27 6.2 Typical Pad Layout Dimensions ......................................................................................................................29 7 Ordering Information................................................................................................................... 33 7.1 Ordering Part Numbers and Package Markings..............................................................................................33 Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 1 88PL810/88PL815/88PL830 Datasheet 7.2 Sample Ordering Part Number........................................................................................................................33 7.3 Package Markings...........................................................................................................................................34 7.3.1 5 X 5 QFN-5 Package Marking .........................................................................................................34 7.3.2 3 X 3 MSOP-8 Package Marking ......................................................................................................34 A Revision History .......................................................................................................................... 35 Doc. No. MV-S102944-00 Rev. E Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 List of Tables List of Tables Table 1: Product Table .....................................................................................................................................5 Table 2: Pin Type Definitions ............................................................................................................................6 Table 4: Absolute Maximum Ratings ................................................................................................................7 Table 5: Recommended Operating Conditions.................................................................................................7 Table 6: Electrical Characteristics ....................................................................................................................8 Table 7: Output Voltage ..................................................................................................................................12 Table 8: Recommended Capacitors ...............................................................................................................15 Table 9: MSOP-8L Dimensions ......................................................................................................................26 Table 10: 5x5mm QFN-5L Dimensions ............................................................................................................28 Table 11: Order Samples Table........................................................................................................................33 Table 12: Revision History ................................................................................................................................35 Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 1 88PL810/88PL815/88PL830 Datasheet Doc. No. MV-S102944-00 Rev. E Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 List of Figures List of Figures Figure 1: Typical LDO Regulator .......................................................................................................................3 Figure 2: 3x3mm MSOP-8 - Top View ...............................................................................................................5 Figure 3: 5x5mm QFN-5 - Top View ..................................................................................................................5 Figure 4: 88PL810/88PL815/88PL830 Simplified Block Diagram....................................................................11 Figure 5: Startt-Up Sequence ..........................................................................................................................12 Figure 6: VSET Voltage Steps for 2.5V Output................................................................................................12 Figure 7: Rise Time with COUT = 10mF..........................................................................................................13 Figure 8: Rise Time with COUT = 1000mF......................................................................................................13 Figure 9: Hiccup Period ...................................................................................................................................14 Figure 10: Current Limit Response Time ...........................................................................................................14 Figure 11: Startt-Up Using the Enable Pin .........................................................................................................19 Figure 12: Turn Off Using the Enable Pin ..........................................................................................................19 Figure 13: Input Voltage Soft Start.....................................................................................................................19 Figure 14: Input Voltage Hot Plug ......................................................................................................................19 Figure 15: UVLO Thresholds .............................................................................................................................20 Figure 16: Load Transient Response.................................................................................................................20 Figure 17: 5x5mm QFN-5L Package .................................................................................................................21 Figure 18: Input Voltage Graphs ........................................................................................................................22 Figure 19: Temperature Graphs ........................................................................................................................23 Figure 20: Temperature Graphs (Continued).....................................................................................................24 Figure 21: 88PL810/88PL815/88PL830 MSOP Mechanical Dimensions ..........................................................25 Figure 22: 88PL810/88PL815/88PL830 5x5mm QFN-5L Mechanical Dimensions ...........................................27 Figure 23: Recommended Solder Pad Layout for MSOP-8 ...............................................................................29 Figure 24: Recommended Solder Pad Layout for QFN-5 ..................................................................................30 Figure 25: Ordering Part Numbers and Package Markings ...............................................................................33 Figure 26: Package Marking and Pin 1 Location for 5 X 5mm QFN-5 ...............................................................34 Figure 27: Package Marking and Pin 1 Location for 3 X 3mm MSOP-8 ............................................................34 Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 1 88PL810/88PL815/88PL830 Datasheet Doc. No. MV-S102944-00 Rev. E Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 88PL810/88PL815/88PL830 High Current, Adjustable 8 Level LDO Regulator Datasheet PRODUCT OVERVIEW The 88PL810/88PL815/88PL830 family of devices are high current ultra-low-dropout linear (LDO) regulators, featuring up to 235mV at 3A dropout voltage and very low ground current. Quiescent current is typically 1.5mA and drops to 0.1A in shutdown. The devices protect themselves from short circuit conditions by turning OFF for about 6ms and ON ("hiccup"), thereby limiting temperature rise. In "Hot-Swap" applications, no additional circuitry is required since these devices have an integrated "Soft Start" mode. Additionally, a unique output voltage programming technique is used to provide eight output voltage options. Features The whole 88PL810/15/30 family's output voltage can be adjusted to 8 different levels between 2.4V and 2.75V (2% or 50mV per step), for an input voltage range of 2.7V to 3.6V. This voltage is defined by the user with a single external resistor (RVSET). The 88PL810 device is adjustable in 30mV steps and the 88PL815 device is adjustable in 36mV steps. 88PL810: 1.5V/1.0A; 88PL815: 1.8V/1.5A; 88PL830: 2.5V/3.0A Ultra-low dropout (235mV @ 3A typ.) Input voltage range 2.7V to 3.6V One resistor sets the output voltage level Fixed Soft start ramp with any output capacitor up to 1000F "Hiccup" short circuit protection Stable with ceramic output capacitors Adjustable 8 level, programmable output voltage in 2% steps Logic controlled shutdown 0.1A supply current in shutdown Stable with 0A load current Lead-free MSOP-8L and QFN-5L packages -40C to +125C junction temperature range Applications The 88PL810/88PL815/88PL830 devices are stable with a 10F ceramic output capacitor. However, any other type of capacitor up to 1000F can be placed in parallel with it as long as the 10F ceramic output capacitor is placed next to the 88PL810/88PL815/88PL830. Adjustable linear regulator for low-voltage digital ICs PC add-in cards Backup power supplies and 3.3V PCI Express Bus TAB EP Figure 1: Typical LDO Regulator VSET GND VIN EN VOUT 88PL830 Enable 5 Disable Vin 3.3V 4 C1 10uF/6.3V 3 2 1 C2 10uF/6.3V Copyright (c) 2008 Marvell January 21, 2008, 1.00 Vout 2.5V/3A Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 3 88PL810/88PL815/88PL830 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102944-00 Rev. E Page 4 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: 3x3mm MSOP-8 - Top View Figure 3: 5x5mm QFN-5 - Top View Table 1: Product Table P r od u c t N u m b e r O ut pu t Vo lta ge O u t p u t C ur r e n t 88PL830 2.40, 2.45, 2.50 , 2.55, 2.60, 2.65, 2.70, 2.75 3.0A 88PL815 1.728, 1.764, 1.80, 1.836, 1.872, 1.908, 1.944, 1.980 1.5A 88PL810 1.44, 1.47, 1.50, 1.53, 1.56, 1.59, 1.62, 1.65 1.0A Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 5 88PL810/88PL815/88PL830 Datasheet 1.2 Pin Description 1.2.1 Pin Types This section provides the pin description of the 88PL810/88PL815/88PL830 devices. Table 2 shows the pin types used in Table 3. Table 2: Pin Type Definitions Pi n Typ e D e f in it io n I Input only O Output Only S Supply NC Not Connected GND Ground Table 3: Pin Description 5x5 QFN-5 3x3 MSOP-8 P in # Pi n # Pin Name P i n Ty p e P in F u n ct io n 5 1, 2 PVIN S Input Voltage: Input voltage supplies current to output. Connect a 10F decouple capacitor (CIN) between this pin and GND pin. 4 3 EN I Enable: CMOS compatible input. Logic low = Disable, Logic high = Enable. 3 4 GND GND 1 5 VSET 2 6, 7, 8 VOUT Ground: Tab is connected to GND. Voltage Setting: Connect to an external resistor that is connected to ground to set the output voltage of the resistor. The total capacitance across this pin and GND should be less than 25pF. Use a resistor with tolerance better than 2%. If this pin is connected to GND, the output voltage will be set to 2.5V. If this pin is PVIN, the output voltage will be set to 3.3V. Do not float this pin. O Output Voltage: Adjustable regulator output. A 10F capacitor is connected between this pin and the GND pin. Doc. No. MV-S102944-00 Rev. E Page 6 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 4: Absolute Maximum Ratings1 Parameter Sy m b o l Range U ni ts Input Voltage to GND VIN -0.6 to 4.2 V Enable voltage (VEN) to GND VEN -0.6 to max (VIN + 0.6, 4.2) V Voltage set to GND VSET -0.6 to max (VIN + 0.6, 4.2) V Output Voltage to GND VOUT -0.6 to max (VIN + 0.6, 4.2) V TOP -40 to 85 C Storage Temperature Range TSTOR -65 to 150 C Maximum Junction Temperature TJMAX 150 C Operating Temperature Range ESD 2 Rating3 2 kV 1. Exceeding the absolute the maximum rating may damage the device. 2. Specifications over the -40 C to 85 C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5k, in series with 100pF. 2.2 Table 5: Recommended Operating Conditions Recommended Operating Conditions1 Parameter S y m bo l R a n ge U n i ts Input Voltage VIN 2.7 to 3.6 V MSOP Package Thermal Resistance JA 150.88 C/W 5 X 5mm QFN-5L Package Thermal Resistance JA See Section 5 C/W Maximum Operating Junction Temperature TJMAX 125 C 1. This device is not guaranteed to function outside the specified operating range Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 7 88PL810/88PL815/88PL830 Datasheet 2.3 Table 6: Electrical Characteristics Electrical Characteristics NOTE: The following table applies unless otherwise noted: CIN = 10F; COUT = 10F (Ceramic); IOUT = 10mA; TA = 25 C; VIN = 3.3V. Bold values indicate -40 C TA 85 C. Parameter S ym bo l Input Voltage Range VIN C o n d iti o n M in Max U n its 2.7 Typ 3.6 V -2 2 % 1mA [ IOUT[ 3A (88PL830) Output Voltage Accuracy 1mA [ IOUT [ 1.5A (88PL815) VOUT 1mA [ IOUT [ 1A (88PL810) 10mA [ IOUT [ 3A (88PL830) Output Voltage Load Regulation DVOUT/VOUT 10mA [ IOUT [ 1.5A (88PL815) 0.1 % 0.01 % IOUT = 1A, Output voltage variation=1% 75 mV IOUT = 2A, Output voltage variation=1% 156 mV IOUT = 3A, Output voltage variation=1% 235 mV IOUT = 0mA 1.2 10mA [ IOUT [ 1A (88PL810) Output Voltage Line Regulation Dropout Voltage (88PL830 only) DVOUT/VOUT VIN-VOUT VIN = 3.0V-3.6V, IOUT = 10 mA Quiescent Current (88PL810) Quiescent Current (88PL815) 1.0 IQ Quiescent Current (88PL830) Shutdown Input Current 1.5 ISHDN VEN = GND 0.1 VOUT = 1.5V 3.0 IOUT(LIM) VOUT = 1.8V 3.0 VOUT = 2.5V 7.0 Output Current Limit (88PL810) Output Current Limit (88PL815) mA Output Current Limit (88PL830) 50 mA A En a b le In p u t Enable Input Logic low Enable Input Logic high Enable Pin Input Current LDO Shutdown VEN IEN LDO Enable 1.1 2.2 V V VEL = 1.1V 1 10 mA VEH = 2.2V 1 10 mA High threshold (UTH), VIN increasing 2.60 2.70 V Low threshold (UTL), VIN increasing 2.45 V 150 mV U n d e r Vol ta g e L o c k o u t Under Voltage Lockout VUVLO Under Voltage Lockout Hysteresis Doc. No. MV-S102944-00 Rev. E Page 8 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Electrical Specifications Electrical Characteristics Table 6: Electrical Characteristics NOTE: The following table applies unless otherwise noted: CIN = 10F; COUT = 10F (Ceramic); IOUT = 10mA; TA = 25 C; VIN = 3.3V. Bold values indicate -40 C TA 85 C. Parameter S ym bo l C o n d iti o n M in Typ Max U n its RSET = 11K 2.352 2.40 2.448 V RSET = 18.7K 2.401 2.45 2.499 V RSET = 31.6k or 0 2.450 2.50 2.550 V RSET = 53.6K 2.499 2.55 2.601 V RSET = 97.6K 2.548 2.60 2.652 V RSET = 165K 2.597 2.65 2.703 V RSET = 280K 2.646 2.70 2.754 V RSET = 475K 2.695 2.75 2.805 V RSET = 11K 1.693 1.728 1.763 V RSET = 18.7K 1.729 1.764 1.799 V RSET = 31.6k or 0 1.764 1.800 1.836 V RSET = 53.6K 1.799 1.836 1.873 V RSET = 97.6K 1.835 1.872 1.909 V RSET = 165K 1.870 1.908 1.946 V RSET = 280K 1.905 1.944 1.983 V RSET = 475K 1.940 1.980 2.020 V RSET = 11K 1.411 1.44 1.469 V RSET = 18.7K 1.441 1.47 1.499 V RSET = 31.6k or 0 1.470 1.50 1.530 V RSET = 53.6K 1.499 1.53 1.561 V RSET = 97.6K 1.529 1.56 1.591 V RSET = 165K 1.558 1.59 1.622 V RSET = 280K 1.588 1.62 1.652 V RSET = 475K 1.617 1.65 1.683 V L D O O u tp u t Vo lta g e Output Voltage (88PL830) Output Voltage (88PL815) Output Voltage (88PL810) So ft Start VOUT = 2.5V 3 Start-up Time (88PL815) Start-up Time (88PL830) tSS VOUT = 1.8V 2.2 Start-up Time (88PL810) VOUT = 1.5V 2.1 ms L ow D r o p O u t A u t o - r e s ta r t LDO Auto-restart1 Time to restart after current limit shut down 6 30 ms O v e r Te m p e r a t u r e P r o t e c t io n Over-temperature Protection TOT TJ increasing (Disable IC) 150 C TJ decreasing (Enable IC) 120 C 1. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 9 88PL810/88PL815/88PL830 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102944-00 Rev. E Page 10 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Functional Description 3 Functional Description Figure 4: 88PL810/88PL815/88PL830 Simplified Block Diagram Vin 2.7V to 3.6V C1 Vout HICCUP CURRENT LIMIT C2 + OFF - EN ON BAND-GAP VOLTAGE REFERENCE & SOFTSTART UNDERVOLTAGE LOCK-OUT THERMAL SHUTDOWN 150 C RESISTOR SENSING CIRCUITRY GND VSET R1 Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 11 88PL810/88PL815/88PL830 Datasheet 3.1 Output Voltage - AnyVoltageTM Technology For 88PL830, the output voltage is set by using a single resistor (RVSET) to provide eight output voltage options from 2.40V to 2.75V in 50mV steps (See Table 4). The Rresistor is only read once during start-up before the output voltage is turned on; therefore, the output voltage cannot be changed on-the-fly. To configure the output to a different voltage either power has to recycle or the enable input has to turn OFF and back ON. Table 7: Output Voltage Ste p V OUT 88PL830 (V) V OUT 88PL815 (V) V OUT 88PL810 (V) R V S E T (k ) 1 2.50 1.80 1.50 0 2 2.75 1.980 1.65 475 3 2.70 1.944 1.62 280 4 2.65 1.908 1.59 165 5 2.60 1.872 1.56 97.6 6 2.55 1.836 1.53 53.6 7 2.50 1.80 1.50 31.6 8 2.45 1.764 1.47 18.8 9 2.40 1.728 1.44 11 Figure 3 shows the startup sequence of the 88PL830. Once the input voltage (VIN) is above the under voltage lockout (UVLO) upper threshold (UTH) of 2.65V, the VSET pin becomes active. Current is sourced out of this pin in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below this reference voltage, the current source proceeds to the next set. Once the VSET voltage is above the reference voltage the sequence stops and the output voltage (Vout) is allowed to turn-on. Figure 4 shows the VSET waveform for a 2.5V output. The 88PL830 keeps track of how many steps were required to determine the appropriate output voltage. Table 4 provides the number of steps necessary for each output voltage option. Using a 31.6k resistor requires the current source to step 7 times, see Figure 4. Figure 5: Startt-Up Sequence Figure 6: VSET Voltage Steps for 2.5V Output 2V/DIV VOUT 1V/DIV VIN VSET 0.5V/DIV 1V/DIV VSET 2ms/DIV 100 s/DIV Doc. No. MV-S102944-00 Rev. E Page 12 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Functional Description Soft Start The 88PL810/88PL815/88PL830 devices provide an innovative technique to set the output voltage. The output voltage is determined during startup by the device reading the value of an external resistor that is located outside the regulator's feedback loop. By placing the output voltage-programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. The 88PL810/88PL815/88PL830 initial accuracy is 2% for any of the eight output voltages. The VSET pin is sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination that introduces excessive leakage current on the VSET pin, especially for a RVSET of 475k. The parasitic resistance on the node must be greater than 3M and the stray capacitance must be equal to 25pF or less. 3.2 Soft Start Soft start is a highly desirable property in "Hot-Swap" applications. Most LDOs start-up within 100s, producing large inrush currents on the input power supply. The 88PL810/88PL815/88PL830 device controls the rise time of the output voltage, thereby dramatically reducing the inrush current. The 88PL830 device rise time is typically 3ms and it is independent of output capacitance and load current. Figure 5 shows the rise time with a 10F output capacitor at 50mA load and Figure 6 shows the rise time with a 1000F output capacitor at 500mA load. Even with these extreme loading conditions and different inrush current, the output voltage rise time difference is less than 0.1ms. Also note that the output voltage starts at near 0V while other LDO soft start techniques typically start at 1.25V. . Figure 7: Rise Time with COUT = 10F Figure 8: Rise Time with COUT = 1000F 1V/DIV 1V/DIV VOUT VOUT IIN 100mV/DIV ILOAD = 50mA 500mV/D IV IIN ILOAD = 50mA 1ms/DIV 1ms/DIV Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 13 88PL810/88PL815/88PL830 Datasheet 3.3 Hiccup Current Limit The "Hiccup" short-circuit protection is a feature that is not common among other LDOs. When the current-sense circuit sees an over-current condition, the 88PL810/88PL815/88PL830 device shuts off for about 6ms and then tries to start up again, see Figure 7. If the over-load condition is removed, the 88PL810/88PL815/88PL830 devices will start-up normally; otherwise, the 88PL810/88PL815/88PL830 device will see another over-current event and shut off again, repeating the previous cycle. . Figure 9: Hiccup Period IOUT Figure 10: Current Limit Response Time 5A/DIV IOUT 2ms/DIV 5A/DIV 200s/DIV Hiccup mode protection offers protection against over current situations, since it limits the average current to the load at a low level, reducing power dissipation and case temperature of the IC. The 88PL810/88PL815/88PL830 device case temperature will only rise about 20C and have a case temperature of around 45C at room, reducing the thermal stress on the device. Figure 8 shows the response time of the current limit circuitry. The response time of the protection circuit must be quick enough to prevent damage from overloads, yet allow enough time to response to transient loads without prematurely tripping the protection circuit. Doc. No. MV-S102944-00 Rev. E Page 14 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Functional Description Output Capacitor (COUT) Selection 3.4 Output Capacitor (COUT) Selection The 88PL810/88PL815/88PL830 device requires a 10F ceramic output capacitor as part of the frequency compensation. However, any other type of capacitor up to 1000F can be placed in parallel with it as long as the 10F ceramic output capacitor is placed next to the 88PL810/88PL815/88PL830 device. Additional output capacitance further improves load-transient response and power supply rejection. X7R and X5R type ceramic capacitors are recommended because of their performance over temperature. Capacitance of the X7R type capacitors changes only 15% over their operating temperature range. Y5V and Z5U type ceramic capacitors change value by as much as 60% and 50%, respectively, over their operating temperature range. If Y5V type ceramic capacitors are used, then higher value capacitor in comparison with X7R and X5R capacitors must be used to ensure a sufficient capacitance value over the operating temperature range. The following capacitors are some of the capacitors recommended to be used with the 88PL810/88PL815/88PL830. Table 8: Recommended Capacitors Manufacturer Part Number D ie l e c t r i c C a pac i ta n c e (F ) Vol ta g e (V) Case S iz e (inch) Max H ei gh t (mm) Murata GRM188R60G106M X5R 10 4.0 0603 0.9 Murata GRM219R60J106K X5R 10 6.3 0805 0.95 Murata GRM21BR60J106K X5R 10 6.3 0805 1.35 CE JMK212BJ106MG-T X5R 10 6.3 0805 1.40 C2012X5R0J106MT X5R 10 6.3 0805 1.55 Taiyo-Yuden TDK 3.5 Input Capacitor An input capacitor of 1F or greater is required between the 88PL810/88PL815/88PL830 device's VIN pin and ground. It must be placed as close as possible to the 88PL810/88PL815/88PL830 device for stable operation. While 1F will provide adequate bypassing of the VIN supply, larger value input capacitors (10F) can improve bypassing to handle fast transient response requirements. 3.6 Enable The 88PL810/88PL815/88PL830 devices feature an active high enable (EN) input that allows ON/OFF control of the device. Near "zero" current drain is achieved when the device is disabled, with only microamperes of leakage current flow. The EN input includes TTL/CMOS compatible thresholds for simple interfacing with logic, or that may be directly tied to VIN for a constant ON state. The enable input must not be left floating; it must be tied either high or low. 3.7 Minimum Load Current The 88PL810/88PL815/88PL830 device, unlike most other high current regulators, does not require a minimum load to maintain output voltage regulation. Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 15 88PL810/88PL815/88PL830 Datasheet 3.8 Undervoltage Lockout (UVLO) The 88PL810/88PL815/88PL830 incorporates undervoltage-lockout circuitry to disable the LDO when the input voltage is below 2.45V (typical). The LDO is enabled when the input voltage is above 2.60V (typical). 3.9 Thermal Shutdown When the junction temperature of the 88PL810/88PL815/88PL830 device exceeds 150 C (typical), the thermal shutdown circuitry disables the LDO. The LDO is enabled when the junction temperature is decreased to 120 C (typical). Doc. No. MV-S102944-00 Rev. E Page 16 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Functional Description Thermal Considerations 3.10 Thermal Considerations The power handling capability of the device is limited by the maximum rated junction temperature (125C). The power dissipated by the device is made up of two components: 1. Output current multiplied by the differential of input and output voltage: (IOUT) (VIN-VOUT). 2. Input current into the device (used by internal circuitry in mA) multiplied by the input voltage: (IQ)(VIN) The actual power dissipation (PD) will be the sum of the two components listed above: PD = (IOUT) (VIN - VOUT) + (IQ) (VIN) To determine the maximum power dissipation (PD (max)) of the package, use the junction-to-ambient thermal resistance ( JA) of the device and the following equation: ( T J ( max ) - T A ( max ) ) P D ( max ) = --------------------------------------------- JA Where TJ (max) is the maximum junction temperature of the die (125 C) and TA (max) is the ambient operating temperature. Note that JA is layout dependent. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the air. Each material in the heat flow between the IC and the outside environment has a thermal resistance. Starting from the die, we have JC (junction to case), CS (case to heat sink), and SA (heat sink to ambient). These thermal resistances are added together to determine the total thermal resistance between the die and the air, JA. JA = JC + CS+ SA The value for SA is dependent on the heat sink, where the CS is dependent on the package type and contact between heat sink and package. The proper heat sink can be selected based on the following equation: T J ( max ) - T A ( max ) SA = ----------------------------------------- - ( JC + CS ) P D ( max ) The JA can be calculated after the proper heat sink is selected. To prevent the device from entering Thermal Shutdown, the actual power dissipation needs to be equal or less than the maximum power dissipation: T J ( max ) - T A ( max ) ------------------------------------------- ( I OUT ) x ( V IN - V OUT ) JA Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 17 88PL810/88PL815/88PL830 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102944-00 Rev. E Page 18 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Functional Characteristics 4 Functional Characteristics The following is used CIN = 10F; COUT = 10F (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise noted. . Figure 11: Startt-Up Using the Enable Pin Figure 12: Turn Off Using the Enable Pin 1V/DIV VSET VOUT 1V/DIV VSET 1V/DIV 2V/DIV EN EN 2V/DIV 1ms/DIV 1ms/DIV ILOAD = 50 ILOAD = 50 . Figure 13: Input Voltage Soft Start Figure 14: Input Voltage Hot Plug 1V/DIV 1V/DIV 1V/DIV 1V/DIV VIN VIN VOUT VOUT 1V/DIV VSET VSET 2ms/DIV ILOAD = No Load 1V/DIV 1ms/DIV ILOAD = No Load . Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 19 88PL810/88PL815/88PL830 Datasheet Figure 15: UVLO Thresholds Figure 16: Load Transient Response VOUT 20mV/D VOUT 1V/DIV VIN ILOAD 1V/DIV 1A/DIV 100ms/DIV VHTH = 2.60V VLTH = 2.45V 200 s/DIV ILOAD = 0.01A to 3.0A COUT = 10F Doc. No. MV-S102944-00 Rev. E Page 20 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Typical Characteristics IC Case and Board Temperature 5 Typical Characteristics 5.1 IC Case and Board Temperature Actual results depend upon the size of the PCB and proximity to other heat emitting components. The following test data used a 3/4 in2 PCB, 1 oz copper, and 88PL830 part. Figure 17: 5x5mm QFN-5L Package IC Case Temprature vs. Output Current Vin = 3.3V, Vout =2.5V IC Temperature vs. Output Current Vin = 3.3V, @25C 120 85C 140 65C 120 45C 100 IC Temp(C) IC Temprature (C) 160 25C 100 80 80 60 60 40 40 20 Vout=2.4V Vout=2.5V Vout=2.6V Vout=2.75V 20 0 0.5 1 1.5 2 2.5 0 3 0 Output Current (A) 0.5 IC Case Temprature vs. Power Dissipation Vin = 3.3V 2 2.5 3 110 Board Temprature (C) 85C 140 65C 120 45C 100 25C Linear (25C) 80 60 y = 30.184x + 26.597 40 100 y = 30.184x + 26.597 90 80 70 60 PCB_25C 50 IC_25C 40 y = 20.783x + 26.905 Linear (PCB_25C) 30 Linear (IC_25C) 20 20 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 0.5 1.0 IC Power Loss vs. Output Current Vin = 3.3V, Vout = 2.5V LDO Dropout (V) 2.5 85C 65C 1.5 45C 25C 1.0 0.5 0.0 0 0.5 1 1.5 2 2.5 3 3.5 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.5 3.0 85C 25C -40C 0 Output Current (A) 0.5 1 1.5 2 Output Current (A) Copyright (c) 2008 Marvell January 21, 2008, 1.00 2.0 Dropout vs. Load Current Vin = 2.7, Vout = 2.7V 3.0 2.0 1.5 IC Power Loss (W) IC Power Loss (W) IC Ploss (W) 1.5 Iout(A) PCB Board & IC Temperature vs. Power Dissipation Vin = 3.3V, Vout = 2.5V, @ 25C 160 IC Temprature (C) 1 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 21 88PL810/88PL815/88PL830 Datasheet Figure 18: Input Voltage Graphs The following data applies to 88PL830; CIN = 10F; COUT = 10F (Ceramic); unless otherwise noted. Supply Current vs. Input Voltage Shutdow n Current vs. Input Voltage 0.4 Shutdown Current (uA) Supply Current (mA) 1.6 1.5 1.4 1.3 0.3 0.2 0.1 0.0 1.2 2.7 3.0 3.3 2.7 3.6 3.0 3.3 3.6 Input Voltage (V) Input Voltage (V) Load = No Load Output Voltage vs. Input Voltage Load Regulation vs. Input Voltage 0.20% Load Regulation (%) Output Voltage (V) 2.600 2.550 2.500 2.450 0.10% 0.00% -0.10% -0.20% 2.400 2.7 2.7 3.0 3.3 3.0 3.6 3.3 3.6 Input Voltage (V) Input Voltage (V) VOUT(LDO) = 2.5V IOUT(LDO) = 10mA - 3.0A IOUT(LDO) = 10mA Output Current Lim it vs. Input Voltage 10.0 1.60 8.0 Current Limit (A) Enable Threshold (V) Enable Threshold vs. Input Voltage 1.70 1.50 1.40 1.30 6.0 4.0 88PL830 2.0 1.20 88PL815/10 0.0 1.10 2.7 3.0 3.3 3.6 2.7 3.3 3.6 Input Voltage (V) Input Voltage (V) Doc. No. MV-S102944-00 Rev. E Page 22 3.0 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Typical Characteristics IC Case and Board Temperature Figure 19: Temperature Graphs The following data applies to 88PL830; CIN = 10F; COUT = 10F (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise noted. Supply Current vs. Tem perature Shutdown Current vs. Temperature 1 Shutdown Current (uA) Supply Current (mA) 1.5 1.4 1.3 1.2 -40 -20 0 20 40 60 0.5 0.25 0 -40 80 Tem perature (C) IOUT(LDO) = No Load 0.75 -20 60 80 Line Regulation vs. Tem perature Output Voltage vs. Tem perature 0.20% Line Regulation (%) 2.550 Output Voltage (V) 20 40 Tem perature (C) IOUT(LDO) = 10mA 2.575 2.525 2.500 2.475 2.450 2.425 -40 -20 0 20 40 60 80 0.10% 0.00% -0.10% -0.20% -0.30% -40 -20 Tem perature (C) IOUT(LDO) = 10mA 0 20 40 Tem perature (C) 60 80 VIN = 3.0V - 3.6V Enable Threshold vs. Temperature Load Regulation vs. Tem perature 2.00 0.40% 0.30% Enable Threshold (V) Load Regulation (%) 0 0.20% 0.10% 0.00% -0.10% -0.20% -40 -20 0 20 40 60 80 1.75 1.50 1.25 1.00 -40 Tem perature (C) -20 0 20 40 Tem perature (C) 60 80 IOUT(LDO) = 10mA - 3A Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 23 88PL810/88PL815/88PL830 Datasheet Figure 20: Temperature Graphs (Continued) The following data applies to 88PL830; CIN = 10F; COUT = 10F (Ceramic); VIN=3.3V; VOUT=2.5V; unless otherwise noted. Current Lim it vs. Tem perature UVLO vs. Tem perature 8 2.8 7 Current Limit (A) UVLO (V) 2.7 2.6 2.5 2.4 2.3 -40 -20 0 20 40 60 80 6 5 4 3 2 88PL830 1 88PL815/10 0 -40 -20 Tem perature (C) 0 20 40 60 80 Tem perature (C) I OUT(LDO) = 10mA Doc. No. MV-S102944-00 Rev. E Page 24 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Mechanical Drawings Mechanical Dimensions 6 Mechanical Drawings 6.1 Mechanical Dimensions 6.1.1 MSOP-8 Package Figure 21: 88PL810/88PL815/88PL830 MSOP Mechanical Dimensions Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 25 88PL810/88PL815/88PL830 Datasheet Table 9: S ym bo l MSOP-8L Dimensions D i m e n si o n i n m m MIN NOM A D im e ns i on in i n c h MAX MIN NOM 1.10 A1 0.05 A2 0.76 b C D E E1 0.043 0.15 0.002 0.85 0.95 0.030 0.033 0.037 0.25 0.30 0.35 0.010 0.012 0.014 0.13 0.15 0.23 0.005 0.006 0.09 2.90 3.00 3.10 0.114 0.118 0.122 4.80 4.90 5.00 0.189 0.193 0.197 2.90 3.00 3.10 0.114 0.118 0.122 e 0.65 L MAX 0.40 0.53 y 0.006 0.0256 0.66 0.016 0.021 0.10 0 3 6 0.026 0.004 0 3 6 Notes: 3. 4. 5. 7. Controlling Dimension: mm Lead Frame Material: OLIN C7025 Dimension "D" does not include mold flash, tie bar burrs and gate burrs. Mold flash, tie bar burrs and gate burrs shall not exceed 0.006" [0.15mm] per end. Dimension "E1" does not include interlead flash. Interlead flash shall not exceed 0.010" [0.25mm] per side. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.003" [0.08mm] total in excess of the "b" dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead to be 0.0028" [0.07mm]. Tolerance: 60.010" [0.25mm] unless otherwise specified. 8. Otherwise dimensions follow acceptable specifications. 6. Doc. No. MV-S102944-00 Rev. E Page 26 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Mechanical Drawings Mechanical Dimensions 6.1.2 5x5mm QFN-5L Package Figure 22: 88PL810/88PL815/88PL830 5x5mm QFN-5L Mechanical Dimensions Notes: 1. 2. Controlling Dimension: Millimeter Refence Document: JEDEC MO-229 Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 27 88PL810/88PL815/88PL830 Datasheet Table 10: 5x5mm QFN-5L Dimensions S ym bo l D i m e ns i on in m m Di m e nsi o n in in ch MIN NOM MAX M IN NOM MAX A 0.80 0.85 1.00 0.031 0.033 0.039 A1 0.00 0.02 0.05 0.00 0.001 0.002 A2 0.60 0.65 0.50 0.024 0.026 0.031 A3 0.020 REF b1 0.25 B2 0.45 0.008 REF 0.30 0.35 0.010 0.50 0.55 0.018 0.014 0.020 0.022 D/E 5.00 BSC 0.197 BSC D1/E1 4.95 BSC 0.187 BSC D2A 3.43 3.58 3.73 0.135 0.141 0.147 D2B 2.03 2.18 2.33 0.080 0.086 0.092 E 2A 3.90 4.05 4.20 0.154 0.159 0.165 E 2B 2.95 3.10 3.25 0.116 0.122 0.128 e 1.00 BSC L 0.35 K 0.20 0 0.55 0.039 BSC 0.75 0.014 0.022 0.030 0.008 12 0 12 aaa 0.15 0.006 b bb 0.10 0.004 ccc 0.10 0.004 d dd 0.05 0.002 Doc. No. MV-S102944-00 Rev. E Page 28 0.012 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Mechanical Drawings Typical Pad Layout Dimensions 6.2 Typical Pad Layout Dimensions Figure 23: Recommended Solder Pad Layout for MSOP-8 0.90 1.34 1 0.65 2.37 1.40 0.42 3.43 5.23 3X3 MSOP-8L Land Pattern (mm) Notes: 1. 2. 3. 4. Top View Drawing Not to Scale Dimensions are in millimeters Tolerance 0.05mm Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 29 88PL810/88PL815/88PL830 Datasheet Figure 24: Recommended Solder Pad Layout for QFN-5 Package Outline 0.475 2.18 3.58 5.15 0.50 0.70 1.00 1.50 0.30 3.10 4.05 5X5 QFN-5L Land Pattern (mm) Notes: 1. 2. 3. 4. Top View Drawing Not to Scale Dimensions are in millimeters Tolerance 0.05mm Doc. No. MV-S102944-00 Rev. E Page 30 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 88PL810/88PL815/88PL830 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S102944-00 Rev. E Page 31 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 88PL810/88PL815/88PL830 Datasheet Doc. No. MV-S102944-00 Rev. E Page 32 Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 Ordering Information Ordering Part Numbers and Package Markings 7 Ordering Information 7.1 Ordering Part Numbers and Package Markings Figure 11 shows the ordering part numbering scheme of the 88PL810/88PL815/88PL830. For complete information, contact Marvell FAE or sales representative. Figure 25: Ordering Part Numbers and Package Markings 7.2 Sample Ordering Part Number The standard ordering part numbers for the respective solutions are as follows: Table 11: Order Samples Table Part Number M a r k in g LDO Output Vol ta g e LDO Output Current A m b i e n t Te m p R a ng e 1 Package2 88PL810-NAK1 L10 1.5V 1.0A -40 C to +85 C 5x5 QFN-5 88PL815-NAK1 L15 1.8V 1.5A -40 C to +85 C 5x5 QFN-5 88PL830-NAK1 L30 2.5V 3.0A -40 C to +85 C 5x5 QFN-5 88PL810-MAE1 L10 1.5V 1.0A -40 C to +85 C 3x3 MSOP-8 88PL815-MAE1 L15 1.8V 1.5A -40 C to +85 C 3x3 MSOP-8 88PL830-MAE1 L30 2.5V 3.0A -40 C to +85 C 3x3 MSOP-8 1. Specifications over the -40 C to 85 C operating temperature range are assured by design, characterization and correlation with statistical process controls. 2. Package dimensions are in milimeters. Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 33 88PL810/88PL815/88PL830 Datasheet 7.3 Package Markings Figures 12 and 13 show a typical package marking and pin 1 location for the 88PL810/88PL815/88PL830 part in 5 X 5mm QFN-5 and 3 X 3mm MSOP-8. 7.3.1 5 X 5 QFN-5 Package Marking Figure 26: Package Marking and Pin 1 Location for 5 X 5mm QFN-5 7.3.2 3 X 3 MSOP-8 Package Marking Figure 27: Package Marking and Pin 1 Location for 3 X 3mm MSOP-8 MRVL L30 L YY WW Work Week Last two Digits of the year Pin 1 Location Doc. No. MV-S102944-00 Rev. E Page 34 Assembly Code Marking Copyright (c) 2008 Marvell Document Classification: Proprietary January 21, 2008, 1.00 A Revision History Table 12: Revision History D o c u m e n t Ty p e D o c u m e n t R e v i s io n Release Rev. E Document brought over from MS Word Updated Template Added new MSOP-8 package and removed DPAK package. Changes included: Section 1. Signal Description Section 2. Electrical Specifications Section 6. Mechanical Drawings Section 7. Ordwering Information Copyright (c) 2008 Marvell January 21, 2008, 1.00 Doc. No. MV-S102944-00 Rev. E Document Classification: Proprietary Page 35 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster