LTM8056
11
8056f
For more information www.linear.com/LTM8056
applicaTions inForMaTion
For most applications, the design process is straight for-
ward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended CIN, COUT, RFB1/RFB2 and RT
values.
3. Apply the output sense resistor to set the output current
limit. The output current is limited to 58mV/RSENSE,
where RSENSE is the value of the output current sense
resistor in ohms.
While these component combinations have been tested for
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
output current is limited by junction temperature, the rela-
tionship between the input and output voltage magnitude
and other factors. Please refer to the graphs in the Typical
Performance Characteristics section for guidance.
The maximum frequency (and attendant RT value) at
which the LTM8056 should be allowed to switch is given
in Table 1 in the fMAX column, while the recommended
frequency (and RT value) for optimal efficiency over the
given input condition is given in the fOPTIMAL column.
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
Note that Table 1 calls out both ceramic and electrolytic
output capacitors. Both of the capacitors called out in
the table must be applied to the output. The electrolytic
capacitors in Table 1 are described by voltage rating,
value and ESR. The voltage rating of the capacitor may
be increased if the application requires a higher voltage
stress derating. The LTM8056 can tolerate variation
in the ESR; other capacitors with different ESR may
be used, but the user must verify proper operation
over line, load and environmental conditions. Table 2
gives the description and part numbers of electrolytic
capacitors used in the LTM8056 development testing and
design validation.
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN RANGE VOUT CIN COUT RFB1/RFB2 fOPTIMAL (kHz) RT(OPTIMAL) fMAX (kHz) RT(MAX)
5V to 24V 3.3V 2 × 4.7µF, 50V, 0805 22µF, 6.3V, X5R, 0805
100µF, 6V, 75mΩ, Electrolytic
100k/56.2k 650 31.6k 800 24.9k
5V to 22V 5V 2 × 4.7µF, 50V, 0805 22µF, 6.3V, X5R, 0805
100µF, 6V, 75mΩ, Electrolytic
100k/31.6k 450 53.6k 800 24.9k
5V to 28V 8V 2 × 4.7µF, 50V, 0805 22µF, 10V, X7R, 1206
100µF, 16V, 100mΩ, Electrolytic
100k/17.4k 500 45.3k 800 24.9k
5V to 41V 12V 2 × 4.7µF, 50V, 0805 22µF, 25V, X5R, 0805
68µF, 16V, 200mΩ, Electrolytic
100k/11k 650 31.6k 800 24.9k
5.8V to 58V 18V 3 × 2.2µF, 100V, 1206 22µF, 25V, X5R, 0805
47µF, 25V, 900mΩ, Electrolytic
100k/6.98k 650 31.6k 800 24.9k
7V to 58V 24V 3 × 2.2µF, 100V, 1206 22µF, 25V, X5R, 0805
33µF, 35V 300mΩ, Electrolytic
100k/5.23k 525 43.2k 800 24.9k
8.5V to 58V 36V 3 × 2.2µF, 100V, 1206 10µF, 50V, X5R, 1206
10µF, 50V 120mΩ, Electrolytic
100k/3.40k 500 45.3k 800 24.9k
12.5V to 58V 48V 3 × 2.2µF, 100V, 1206 10µF, 50V, X5R, 1206
10µF, 63V 120mΩ, Electrolytic
100k/2.55k 475 49.9k 800 24.9k
Notes: An input bulk capacitor is required. The output capacitance uses a combination of a ceramic and electrolytic in parallel. Other combinations of
resistor values for the RFB network are acceptable.