iso2-cmos MT8870D/MT8870D-1 HO MITEL. Integrated DTMF Receiver Features Complete DTMF Receiver Low power consumption Internal gain setting amplifier Adjustable guard time Central office quality Power-down mode Inhibit mode Backward compatible with MT8870C/MT8870C-1 Applications Receiver system for British Telecom (BT) o CEPT Spec (MT8870D-1) Paging systems Repeater systems/mobile radio Credit card systems Remote control ISSUE 5 March 1997 Ordering Information MT8870DE/DE-1 18 Pin Plastic DIP MT8870DS/DS-1 18 Pin SOIC MT8870DN/DN-1 20 Pin SSOP -40 C to +85 C Description The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone- pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus * Personal computers interface. * Telephone answering machine Bias DP Circuit a VRef Buffer Power Bas High Group OT Digital Code Filter Detection Converter Algorithm and Latch Dial Tone Zero Crossing Filter Detectors Low Group Filter TT > Chip Steering Clocks Logic Vv SVGT Est Figure 1 - Functional Block DiagramMT8870D/MT8870D-1 |so2-cMos C IN+ CO IN- as VRef 7 INH CJ PWDN[] osce1 osc2 vss] OOANDORWON = OOANDORWON = 4 o 18 PIN PLASTIC DIP/SOIC 20 PIN SSOP igure 2 - Pin Connections Pin Description Pin # 18 | 20 Name Description 1] 4 IN+ Non-Inverting Op-Amp (Input). 2/2 IN- Inverting Op-Amp (Input). GS Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. 4 | 4 Veet |Reference Voltage (Output). Nominally Vpp/2 is used to bias inputs at mid-rail (see Fig. 6 and Fig. 10). 5 |] 5 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. 6 | 6 | PWDN_|Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. 8 OSC1_ |Clock (Input). 8 | 9 OSC2_ |Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. 9 | 10 Vss _ |Ground (Input). OV typical. 10 | 11 TOE |Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally. 11-]12-| Q1-Q4 |Three State Data (Output). When enabled by TOE, provide the code corresponding to the 14/15 last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. 15117 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below Vrst- 16} 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 17|19]| SVGT_ |Steering Input/Guard time (Output) Bidirectional. A voltage greater than V7; detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than Vys; frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 18 | 20 Vpp Positive power supply (Input). +5V typical. 7, NC No Connection. 16ISo?-CMOS MT8870D/MT8870D-1 Functional Description The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection (see Figure 3). Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. Decoder Section Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while ATTENUATION (dB) AB C D R ae MT8870D/ MT8870D-1 tgta=(RO)IN(Vpp/Vrsp) ltgtp=(RC)In[ Vpp/(Vop-Vrspy] igure 4 - Basic Steering providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the signal condition in some industry specifications) the Early Steering (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state (see Steering Circuit). Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes v, (see Figure 4) to rise as the capacitor discharges. Provided signal PRECISE DIAL TONES X=350 Hz Y=440 Hz DTMF TONES A=697 Hz B=770 Hz C=852 Hz D=941 Hz E=1209 Hz F=1336 Hz G=1477 Hz H=1633 Hz 1kHz FREQUENCY (Hz) Figure 3 - Filter ResponseMT8870D/MT8870D-1 ISO2-CMOS condition is maintained (ESt remains high) for the validation period (tgtp), V. reaches the threshold (V+s;) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives v, to Vpp. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 4 is applicable. Component values are chosen according to the formula: tRec=lpptlatp tip=lpatteta The value of tpp is a device parameter (see Figure 11) and trec is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 UF is tatp=(RpC1)IN[Vop/(Vpp-Vrspl Vv DD O tata=(RyCy)In(Vop/Vrsp C, Rp=(RyRo\(Ry+Ro) svaTO a) decreasing tetp; (tetp<teta) terp=(RyC1)In[Vop/Vop-Vrsp] Vv pp tera=(RpC1)in(Vpp/Vrsy) C, Rp=(RyR2)(Ry+R2) svGTC) > Zz < Zz = Mm OQ sy OD a OD nN 1 2 3 4 5 6 7 8 9 0 ef-/-]/4}/4}/4}/4]/ 4}; 4] 0}a]lolololololIn ofAajalalalololo}lofa}]a}/4]}/4-}o0}oloINn ofAalalolof=a][alolofa}|a}o}]o}/a}alolIn ofAalo|lAalo/=alof/a};ofa};o}/a};o}sa}olaIin undetected, the output code will remain the same as the previous detected code Try rpo] cy oy oy] cy LY] Lo] Ly] LD] Ly] oY] oy] rT] co] LT] rc] Tt xy cy cy cy] oy] Ly] Lc] LD] Ll] Ly] Ly] LD] LD] Ly] Ly] Ly] LD] LT] ty] rye xy cy cy cyl} ry eye] KY] KY] OK] KY] OK] KOK] OK] OK] KCK) OX | OX O/O;/ aD) PrP] O;O!] wm] >|] L e unctiona able L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON'T CARE recommended for most applications, leaving R to be selected by the designer. Different steering arrangements may be used to select independently the guard times for tone present (tetp) and tone absent (teqa). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing trec improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short taec with a long tpg would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 5.ISo?-CMOS MT8870D/MT8870D-1 Power-down and Inhibit Mode A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1). Differential Input Configuration The input arrangement of the MT8870D/MT8870D-1 provides a differential-input operational amplifier as well as a bias source (Vpez) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 10 with the op-amp connected for unity gain and Vpes biasing the input at "lpVpp. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor Rs. Crystal Oscillator The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is normally connected as shown in Figure 10 (Single- Ended Input Configuration). However, it is possible to configure several MT8870D/MT8870D-1 devices employing only a single oscillator crystal. The oscillator output of the first device in the chain is coupled through a 30 pF capacitor to the oscillator input (OSC1) of the next device. Subsequent devices are connected in a similar fashion. Refer to Figure 7 for details. The problems associated with unbalanced loading are not a concern with the arrangement shown, i.e., precision balancing capacitors are not required. MT8870D/ MT8870D-1 + Differential Input Amplifier C, =C5=1 OnF Ry=Ry=R5=100 kO Ro=60kQ, R3=37.5 k RoRs Rot Rs All resistors are +1% tolerance. All capacitors are +5% tolerance. R3= R VOLTAGE GAIN (A, diff}= = 1 INPUT IMPEDANCE , (Zinpier) = 2 yf Ry?+ ( Figure 6 - Differential Input Configuration To OSC1 of next T8870D/MT8870D-1 VJ OSC2 C=30 pF X-tal=3.579545 MHz igure / - Oscillator Connection Parameter Unit Resonator R1 Ohms 10.752 L4 mH 432 C1 pF 4.984 Co pF 37.915 Qm - 896.37 Af % +0.2% Table 2. Recommended Resonator Specifications Note: Qm=quaility factor of RLC model, i.e., 1/2T1fR1C1.MT8870D/MT8870D-1 |so2-cMos Applications RECEIVER SYSTEM FOR BRITISH TELECOM SPEC POR 1151 tgrp=(RpCy)In[Vpp/(Vop- Vise] The circuit shown in Fig. 9 illustrates the use of _ MT8870D-1 device in a typical receiver system. BT ferar(PrCi)in(Voo Vrs) Spec defines the input signals less than -34 dBm as the non-operate level. This condition can be attained Ooh Fip=(RyR2)(R, +R) by choosing a suitable values of R, and Re to Cy provide 3 dB attenuation, such that -34 dBm input signal will correspond to -37 dBm at the gain setting pin GS of MT8870D-1. As shown in the diagram, the component values of R3 and Cz are the guard time requirements when the total component tolerance is Note K Ot 19% 6%. For better performance, it is recommended to Rin? 2MOQ+1% a= . a oO use the non-symmetric guard time circuit in Fig. 8. C1=100nF + 5% MT8870D-1 IN+ Vpp IN- SUVGT GS Est VRet StD INH Q4 PWDN Q3 OSC 1 a2 NOTES: OSC 2 ey Ry = 102KQ+ 1% Ro =71.5KQ+ 1% Rg = 390KQ +1 % Cy,Co = 100 nF+ 5% X; = 3.579545 MHz +0.1% Vpp = 5.0V 45% Vss Figure 9 - Single-Ended Input Configuration for BT or CEPT SpecISo?-CMOS MT8870D/MT8870D-1 Absolute Maximum Ratings? Parameter Symbol Min Max Units 1 | DC Power Supply Voltage Vpp 7 Vv 2 | Voltage on any pin V; Vgg-0.3 Vppt+0.3 Vv 3 | Current at any pin (other than supply) I; 10 mA 4 | Storage temperature TstG -65 +150 C 5 | Package power dissipation Pp 500 mw + Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Derate above 75 C at16 mW/C. All leads soldered to board. Recommended Operating Conditions - Voltages are with respect to ground (Vgs) unless otherwise stated. Parameter Sym | Min Typt | Max | Units Test Conditions 1 | DC Power Supply Voltage Vpop 4.75 5.0 5.25 Vv 2 | Operating Temperature To -40 +85 C 3 | Crystal/Clock Frequency fc 3.579545 MHz 4 | Crystal/Clock Freq. Tolerance Afc +0.1 % + Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. DC Electrical Characteristics - vjp=5.0v+ 5%, Vgg=0V, -40C < To < +85C, unless otherwise stated. Characteristics Sym Min Typt Max Units Test Conditions 1 | S | Standby supply current Ippa 10 25 HA | PWDN=Vpp P Operating supply current lbp 3.0 9.0 mA f Power consumption Po 15 mW |fc=3.579545 MHz Y 4 High level input Vin 3.5 Vo | Vpp=5.0V 5 Low level input voltage Vit 1.5 Vi | Vpp=5.0V 6 | , {Input leakage current ladle 0.1 WA | Vin=Vss OF Vpp 7 i. Pull up (source) current Iso 7.5 20 HA een 0)=0, U DD=Y- 8 4 Pull down (sink) current Is 15 45 WA |INH=5.0V, PWDN=5.0V, Vpp=5.0V 9 Input impedance (IN+, IN-) Rin 10 MQ |@1 kHz 10 Steering threshold voltage Vist 2.2 2.4 2.5 Vs |Vpp = 5.0V 14 Low level output voltage VoL Vgg+0.03 V___|No load 12 5 High level output voltage Vou | Vpp-0.03 V__ _|No load 13 | T | Output low (sink) current lot 1.0 2.5 MA | VouT=0.4 V 14 u Output high (Source) current lou 0.4 0.8 mA |Vout=4.6 V 15 5 VRet Output voltage VRet 2.3 2.5 2.7 Vv No load, Vpp = 5.0V 16 VRet Output resistance Ror 1 kQ + Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.MT8870D/MT8870D-1 ISO2-CMOS Operating Characteristics - vp5=5.0v45%, Vsg=0V, -40C < To < +85C ,unless otherwise stated. Gain Setting Amplifier Characteristics Sym Min | Typ* | Max | Units Test Conditions 1 | Input leakage current lin 100 nA Vss < Vin < Vpp 2 | Input resistance Rin 10 MQ 3 | Input offset voltage Vos 25 mV 4 | Power supply rejection PSRR 50 dB 1 kHz 5 | Common mode rejection CMRR | 40 dB 0.75 V< Vin < 4.25 V biased at Vref =2.5 V 6 | DC open loop voltage gain AvoL 32 dB 7 | Unity gain bandwidth fc 0.30 MHz 8 | Output voltage swing Vo 4.0 Vpp | Load > 100 kQ to Vsg @ GS 9 | Maximum capacitive load (GS) CL 100 pF 10 | Resistive load (GS) Ry 50 kQ 11 | Common mode range Vem 2.5 Vop No Load MT8870D AC Electrical Characteristics - Vpp=5.0v +5%, Vgg=0V, -40C < To < +85C , using Test Circuit shown in Figure 10. Characteristics Sym Min Typ* | Max Units Notes* 1 tone of eomnaite signal) -29 +1 dBm 1,2,3,5,6,9 27.5 869 | MVamus | 1,2,3,5,6,9 2 | Negative twist accept 8 dB 2,3,6,9,12 3 | Positive twist accept 8 dB 2,3,6,9,12 4 | Frequency deviation accept +1.5% + 2 Hz 2,3,5,9 5 | Frequency deviation reject +3.5% 2,3,5,9 6 | Third tone tolerance -16 dB 2,3,4,5,9,10 7 | Noise tolerance -12 dB 2,3,4,5,7,9,10 8 | Dial tone tolerance +22 dB 2,3,4,5,8,9,11 + Typical figures are at 25 C and are for design aid only: *NOTES 1 2 3 4 5 6 7 8 9. Tone pair is deviated by +1.5 %+ 2 Hz. Bandwidth limited (3 kHz ) Gaussian noise. The precise dial tone frequencies are (350 Hz and 440 Hz) 42%. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Guaranteed by design and characterization. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. Digit sequence consists of all DTMF tones. Tone duration= 40 ms, tone pause= 40 ms. Signal condition consists of nominal DTMF frequencies. Both tones in composite signal have an equal amplitude. not guaranteed and not subject to production testing.ISo?-CMOS MT8870D/MT8870D-1 MT8870D-1 AC Electrical Characteristics - vpp=5.0v+5%, Vgg=0V, -40C < To < +85C , using Test Circuit shown in Figure 10. Characteristics Sym Min Typ* | Max Units Notes* , | Valid input signal levels (each 31 +1 dBm Teste at gbo=2.OV tone of composite signal) 21.8 869 mVaus 12,9,9,0, ; -37 dBm Tested at Vpp=5.0V 2 | Input Signal Level Reject 123569 10.9 mVems Toe 3 | Negative twist accept dB 2,3,6,9,13 4 | Positive twist accept dB 2,3,6,9,13 5 | Frequency deviation accept +1.5%+ 2 Hz 2,3,5,9 6 | Frequency deviation reject +3.5% 2,3,5,9 7 | Third zone tolerance -18.5 dB 2,3,4,5,9,12 8 | Noise tolerance -12 dB 2,3,4,5,7,9,10 9 | Dial tone tolerance +22 dB 2,3,4,5,8,9,114 + Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing. *NOTES 1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by +1.5 %+ 2 Hz. 7. Bandwidth limited (3 kHz ) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) +2 %. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz. 13. Guaranteed by design and characterization.MT8870D/MT8870D-1 |so2-cMos AC Electrical Characteristics - vpp=5.0v+5%, Vgg=0V, -40C < To < +85C , using Test Circuit shown in Figure 10. Characteristics Sym Min Typt Max | Units Conditions 1 Tone present detect time top 5 14 14 ms_ |Note 1 2 | 7 | Tone absent detect time tba 0.5 4 8.5 ms_ |Note 1 3 \ Tone duration accept tREc 40 ms_ |Note 2 4 Tone duration reject tREG 20 ms_ |Note 2 5 | & |Interdigit pause accept tip 40 ms_ |Note 2 6 Interdigit pause reject topo 20 ms_ |Note 2 7 Propagation delay (St to Q) tea 8 11 us |TOE=Vpp 8 | oO |Propagation delay (St to StD) tesip 12 16 us |TOE=Vpp 9 t Output data set up (Q to StD) tasip 3.4 us |TOE=Vpp 10 j Propagation delay (TOE to Q ENABLE) | tpte 50 ns__|load of 10 kQ, + 50 pF 11 S Propagation delay (TOE to Q DISABLE)| tpqp 300 ns__|load of 10 kQ, 50 pF 12 | P |Power-up time tpu 30 ms_ |Note 3 13 w Power-down time tpp 20 ms 14 Crystal/clock frequency fo | 3.5759 | 3.5795 | 3.5831 | MHz 15 Clock input rise time tLHCL 110 ns | Ext. clock 16 | |Clock input fall time tuteL 110 ns | Ext. clock 17 K Clock input duty cycle DCg 40 50 60 % |Ext. clock 18 Capacitive load (OSC2) CLo 30 pF + Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *NOTES: 2. These user adjustable parameters, are not device specifications, The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, tpy equals time from PDWN going low until ESt going high. MT8870D/MT8870D-1 IN+ Vpp IN- SUGT Gs ESt VRet SiD INH Q4 PDWN Q3 osc 1 Q2 NOTES: at Ry,Ro=100KQ + 1% Rg=300KQ + 1% Cy,Cp=100 nF + 5% X-tal=3.579545 MHz + 0.1% 4-20ISo?-CMOS MT8870D/MT8870D-1 EVENTS | > Rec | TONE #n lpr 4 tpomp| lem 7 los , HIGH IMPEDANCE DECODED TONE # (n-1) iX, #n #(n+1) | tpspl ! le | PLL | | I t > + beter | | | tore tetp EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID TONE. D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED. G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. EXPLANATION OF SYMBOLS Vin DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. SVGT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. Q,-Q, 4-BIT DECODED TONE OUTPUT. StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q,-Q, TO ITS HIGH IMPEDANCE STATE. tREG MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID tREc MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION MAXIMUM TIME BETWEEN VALID DTMF SIGNALS. MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. GUARD TIME, TONE PRESENT. GUARD TIME, TONE ABSENT. Figure 11 - Timing Diagram 4-21MT8870D/MT8870D-1 |so2-cMos Notes: 4-22Package Outlines Pin 1 E / - \ A po L < H e | I < D oY L | | t 4 mils (lead coplanarity) Notes: b 1) Not to scale A, 2) Dimensions in inches 3) (Dimensions in millimeters) * | |< 4) A&B Maximum dimensions include allowable mold flash B DIM 16-Pin 18-Pin 20-Pin 24-Pin 28-Pin Min Max Min Max Min Max Min Max Min Max A 0.093 0.104 0.093 0.104 0.093 0.104 0.093 0.104 0.093 0.104 (2.35) (2.65) (2.35) (2.65) (2.35) (2.65) (2.35) (2.65) (2.35) (2.65) Ay 0.004 0.012 0.004 0.012 0.004 0.012 0.004 0.012 0.004 0.012 (0.10) (0.30) (0.10) (0.30) (0.10) (0.30) (0.10) (0.30) (0.10) (0.30) B 0.013 0.020 0.013 0.030 0.013 0.020 0.013 0.020 0.013 0.020 (0.33) (0.51) (0.33) (0.51) (0.33) (0.51) (0.33) (0.51) (0.33) (0.51) Cc 0.009 0.013 0.009 0.013 0.009 0.013 0.009 0.013 0.009 0.013 (0.231) (0.318) (0.231) (0.318) (0.231) (0.318) (0.231) (0.318) (0.231) (0.318) D 0.398 0.413 0.447 0.4625 0.496 0.512 0.5985 0.614 0.697 0.7125 (10.1) (10.5) (11.35) (11.75) (12.60) (13.00) (15.2) (15.6) (17.7) (18.1) E 0.291 0.299 0.291 0.299 0.291 0.299 0.291 0.299 0.291 0.299 (7.40) (7.40) (7.40) (7.40) (7.40) (7.40) (7.40) (7.40) (7.40) (7.40) e 0.050 BSG 0.050 BSG 0.050 BSG 0.050 BSG 0.050 BSG (1.27 BSC) (1.27 BSC) (1.27 BSC) (1.27 BSC) (1.27 BSC) H 0.394 0.419 0.394 0.419 0.394 0.419 0.394 0.419 0.394 0.419 (10.00) (10.65) (10.00) (10.65) (10.00) (10.65) (10.00) (10.65) (10.00) (10.65) L 0.016 0.050 0.016 0.050 0.016 0.050 0.016 0.050 0.016 0.050 (0.40) (1.27) (0.40) (1.27) (0.40) (1.27) (0.40) (1.27) (0.40) (1.27) Lead SOIC Package - S Suffix NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters. 2. Converted inch dimensions are not necessarily exact. General-7Package Outlines HAA AAA AA" O HHOBEOE a c >| | m IX | ( Je) = Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard MO0-150/M0118 for 48 Pin 5) A & B Maximum dimensions include allowable mold flash 20-Pin 24-Pin 28-Pin 48-Pin Dim Min Max Min Max Min Max Min Max A 0.079 - 0.079 0.079 | 0.095 | 0.110 (2) (2) (2) (2.41) | (2.79) A, | 0.002 0.002 0.002 0.008 | 0.016 (0.05) (0.05) (0.05) (0.2) | (0.406) B | 0.0087 | 0.013 | 0.0087 | 0.013 | 0.0087 | 0.013 | 0.008 | 0.0135 (0.22) | (0.33) | (0.22) | (0.33) | (0.22) | (0.33) (0.2) | (0.342) Cc 0.008 0.008 0.008 0.010 (0.21) (0.21) (0.21) (0.25) D 0.27 0.295 0.31 0.33 0.39 0.42 0.62 0.63 (6.9) (7.5) (7.9) (8.5) (9.9) (10.5) | (15.75) | (16.00) E 0.2 0.22 0.2 0.22 0.2 0.22 0.291 0.299 (5.0) (5.6) (5.0) (5.6) (5.0) (5.6) (7.39) | (7.59) e 0.025 BSC 0.025 BSC 0.025 BSC 0.025 BSC (0.635 BSC) (0.635 BSC) (0.635 BSC) (0.635 BSC) Ay | 0.065 | 0.073 | 0.065 | 0.073 | 0.065 | 0.073 | 0.089 | 0.099 (1.65) | (1.85) | (1.65) | (1.85) | (1.65) | (1.85) | (2.26) | (2.52) H 0.29 0.32 0.29 0.32 0.29 0.32 0.395 0.42 (7.4) (8.2) (7.4) (8.2) (7.4) (8.2) | (10.03) | (10.67) L 0.022 | 0.037 | 0.022 | 0.037 | 0.022 | 0.037 0.02 0.04 (0.55) | (0.95) | (0.55) | (0.95) | (0.55) | (0.95) | (0.51) | (1.02) Small Shrink Outline Package (SSOP) - N Suffix General-11Package Outlines E, D n-2n-1n Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Y mile | D, Cc k *a Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin 16-Pin 18-Pin 20-Pin DIM Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max A 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) Ao 0.115 (2.92) | 0.195 (4.95) | 0.115 (2.92) | 0.195 (4.95) | 0.115 (2.92) | 0.195 (4.95) | 0.115 (2.92) | 0.195 (4.95) b 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) bo 0.045 (1.14) | 0.070 (1.77) | 0.045 (1.14) | 0.070 (1.77) | 0.045 (1.14) | 0.070 (1.77) | 0.045 (1.14) | 0.070 (1.77) Cc 0.008 0.014 (0.356) | 0.008 (0.203) | 0.014(0.356) | 0.008 (0.203) | 0.014 (0.356) | 0.008 (0.203) | 0.014 (0.356) (0.203) D 0.355 (9.02) | 0.400 (10.16) | 0.780 (19.81) | 0.800 (20.32) | 0.880 (22.35) | 0.920 (23.37) | 0.980 (24.89) | 1.060 (26.9) D, 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) E 0.300 (7.62) | 0.325 (8.26) | 0.300 (7.62) | 0.325 (8.26) | 0.300 (7.62) | 0.325 (8.26) | 0.300 (7.62) | 0.325 (8.26) E, 0.240 (6.10) | 0.280 (7.11) | 0.240 (6.10) | 0.280 (7.11) | 0.240 (6.10) | 0.280 (7.11) | 0.240 (6.10) | 0.280 (7.11) e 0.100 BSG (2.54) 0.100 BSC (2.54) 0.100 BSG (2.54) 0.100 BSC (2.54) en 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) L 0.115 (2.92) | 0.150 (3.81) | 0.115 (2.92) | 0.150 (3.81) | 0.115 (2.92) | 0.150 (3.81) | 0.115 (2.92) | 0.150 (3.81) ep 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) ec 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) NOTE: Controlling dimensions in parenthesis () are in millimeters. General-8Package Outlines Notes: 1) Not to scale 2) Dimensions E, D n-2n-1 n D, in inches 3) (Dimensions in millimeters) Y mile | a Cc kK *a>| eB Plastic Dual-In-Line Packages (PDIP) - E Suffix 22-Pin 24-Pin 28-Pin 40-Pin DIM Plastic Plastic Plastic Plastic Min Max Min Max Min Max Min Max A 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) Ao 0.125 (3.18) | 0.195 (4.95) | 0.125 (3.18) | 0.195 (4.95) | 0.125 (3.18) | 0.195 (4.95) | 0.125 (3.18) | 0.195 (4.95) b 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) | 0.014 (0.356) | 0.022 (0.558) bo 0.045 (1.15) | 0.070 (1.77) | 0.030 (0.77) | 0.070 (1.77) | 0.030 (0.77) | 0.070 (1.77) | 0.030 (0.77) | 0.070 (1.77) Cc 0.008 (0.204) | 0.015 (0.381) | 0.008 (0.204) | 0.015 (0.381) | 0.008 (0.204) | 0.015 (0.381) | 0.008 (0.204) | 0.015 (0.381) D 1.050 (26.67) | 1.120 (28.44) | 1.150 (29.3) | 1.290 (32.7) | 1.380 (35.1) | 1.565 (39.7) | 1.980 (50.3) | 2.095 (53.2) D, 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) E 0.390 (9.91) | 0.430 (10.92) | 0.600 (15.24) | 0.670 (17.02) | 0.600 (15.24) | 0.670 (17.02) | 0.600 (15.24) | 0.670 (17.02) E, 0.330 (8.39) | 0.380 (9.65) | 0.485 (12.32) | 0.580 (14.73) | 0.485 (12.32) | 0.580 (14.73) | 0.485 (12.32) | 0.580 (14.73) E, 0.246 (6.25) | 0.254 (6.45) e 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) Cn 0.400 BSC (10.16) 0.600 BSC (15.24) 0.600 BSC (15.24) 0.600 BSC (15.24) Cn 0.300 BSC (7.62) ep 0.430 (10.92) L 0.115 (2.93) | 0.160 (4.06) | 0.115 (2.93) | 0.200 (5.08) | 0.115 (2.93) | 0.200 (5.08) | 0.115(2.93) | 0.200 (5.08) a 15 15 15 15 Shaded areas for 300 Mil Body Width 24 PDIP only64 MITEL SEMICONDUCTOR http://www. mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Asia/Pacific Europe, Middle East, Tel: +1 (770) 486 0194 Tel: +65 333 6193 and Africa (EMEA) Fax: +1 (770) 631 8213 Fax: +65 333 6192 Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 South America Tel/Fax: +55 (48) 225 2061 Preliminary and Advance Data/Information: Some datasheets carry the designation Preliminary or Advance. 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