PRELIMINARY TECHNICAL DATA a 14-BIT, 500kSPS Differential ADC in SO/CSP Preliminary Technical Data AD7947* FEATURES GENERAL DESCRIPTION 14-bit Resolution with No Missing Codes T h r o u g h p u t : 500kSPS (Warp mode) 450kSPS (Normal mode) 380kSPS (Impulse mode) 0.0043 % of INL: 0.25LSB Typ, 0.7LSB Max ( FSR) DNL: 0.2LSB Typ, 0.5LSB Max S/(N+D): 85dB Typ @ 20kHz THD: -100dB Typ @ 20kHz True Differential Analog input range: V REF 0V to VREF with V REF up to VDD on Both Inputs No Pipeline Delay Single Supply Operation 2V to 5.5V with 1.8V/2.5V/3V/5V logic interface Daisy Chain Multiple ADCs and Busy Indicator Programmable Input Bandwidth Serial Interface SPI/QSPI/Wire/DSP compatible Typical Power Dissipation: 2mW @ 3V/100kSPS, 20mW @ 5V/380ksps, 1.6W @ 2.5V/100SPS Stand-by current: 1 nA Typ 10-pin Package: -SOIC ( -SO8 size ) and CSP ( 3mm x 3mm same space as SOT-23 ) Pin-for-Pin Compatible with the 16-bit AD7688 The AD7947 is a 14-bit, 500kSPS, charge redistribution successive-approximation, fully differential Analog-toDigital Converter which operates from a single power supply, VDD, between 2V to 5.5V. It contains a very low power high-speed 14-bit sampling ADC with no missing codes, an internal conversion clock and a versatile serial interface port. The part also contains a differential low noise, wide bandwidth, very short aperture delay track/ hold circuit. On the CNV rising edge, it samples the VREF difference between the two analog input IN+ and IN-. The reference voltage REF is applied externally, can be set up to the supply voltage. It features a very high sampling rate mode (Warp) for synchronous applications, a fast mode (Normal) for asynchronous applications and a reduced power mode (Impulse) where the power scales linearly with throughput. The SPI compatible serial interface also features the ability, using the SDI input, to "Daisy chain" several ADCs on a single 3 wire bus and provides an optional Busy indicator. It is compatible with 1.8V, 2.5V, 3V or 5V logic using the separate supply OVDD. The AD7947 is housed in a 10-lead SOIC or 10-lead CSP (Chip Scale package) with operation specified from -40C to +85C. APPLICATIONS Battery Powered Equipment Data Acquisition Instrumentation Medical Instruments Process Control FUNCTIONAL BLOCK DIAGRAM SO, CSP/SOT23 16 and 14 Bit ADC VDD REF Type 16 Bit True Differential 16 Bit Pseudo Differential 16 Bit Unipolar 14 Bit True Differential 14 Bit Pseudo Differential 14 Bit Unipolar 100 kSPS AD7684 250 kSPS AD7687 500 kSPS AD7688 AD7647 IN+ AD7683 AD7686 IN- AD7944 AD7947 GND AD7942 AD7946 AD7685 SWITCHED CAP DAC CONTROL LOGIC AD7680 OVDD SDI CLOCK SCK SDO CNV AD7940 *Patent pending. REV. Pr A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2004 PRELIMINARY TECHNICAL DATA AD7947-SPECIFICATIONS Parameter ( VDD = 2.3V to 5.5 V, OVDD = 2.3V to VDD, VREF = VDD, TA = -40 C to +85 C, unless otherwise noted.) Conditions Min RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25 C Input Impedance DC ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error 2, T MIN to T MAX Gain Error Temperature Drift Zero Error 2, T MIN to T MAX Zero Temperature Drift Power Supply Sensitivity REFERENCE Voltage Range Load Current SAMPLING DYNAMICS -3 dB Input Bandwidth Typ 14 IN+ - ININ+ INf IN = TBD kHz acquisition phase -V REF -0.1 -0.1 +V REF VDD + 0.3 VDD + 0.3 TBD TBD See Analog Input Section 14 -0.5 -0.75 REF = VDD = 5V +0.5 +0.75 TBD high bandwidth VDD = VDD 5% 0.5 TBD VDD+0.3 V V V dB nA Bits LSB1 LSB LSB % of FSR ppm/C LSB ppm/C LSB 500kSPS, V IN+-V IN- = 0V TBD V A Low Bandwidth High Bandwidth 2 9 TBD TBD MHz MHz ns ps rms -0.3 0.7 * OVDD -1 -1 DIGITAL OUTPUTS Data Format Pipeline Delay TEMPERATURE RANGE 6 Specified Performance 0.2 0.25 0.33 TBD TBD TBD TBD DIGITAL INPUTS Logic Levels V IL V IH I IL I IH POWER SUPPLIES VDD OVDD VDD Range OVDD Range Operating Current VDD OVDD Standby Current 4,5 Power Dissipation Unit Bits Aperture Delay Aperture Jitter VOL V OH Max ISINK = 500 A ISOURCE = -500 A Specified Performance Specified Performance V V A A Serial 14-Bits Two's Complement Conversion Results Available Immediately After Completed Conversion 0.4 OVDD - 0.3 V V 2.3 2.3 2 1.8 V V V V 500 kSPS Throughput3 VDD = 5V OVDD = 3.3V VDD and OVDD = 5V, 25C VDD= 2.5V, 100SPS Throughput4 VDD= 3V, 100 kSPS Throughput4 VDD= 5V, 380 kSPS Throughput4 VDD= 5V, 500 kSPS Throughput3 TMIN to TMAX 0.3 * OVDD OVDD + 0.3 +1 +1 5.5 VDD + 0.3 5.5 5.5 TBD TBD 1 1.6 2 20 TBD -40 TBD TBD TBD mA A nA W mW mW mW +85 C TBD NOTES 1 LSB means Least Significant Bit. With the 5 V input range, one LSB is 610.4 V. 2 See Definition of Specifications section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. 3 In Warp mode. 4 In Impulse mode. With all digital inputs forced to OVDD or GND as required. 5 During acquisition phase in Impulse mode only. 6 Contact Analog Devices for extended temperature range. Specifications subject to change without notice. REV. Pr A -2- PRELIMINARY TECHNICAL DATA VDD = 5 V (TA = -40 C to +85 C, VREF = 5V, OVDD = 2.3V to VDD, unless otherwise noted.) Parameter THROUGHPUT Conversion rate Conditions Min Typ AD7947 Max Unit 2 500 2.3 450 2.6 380 400 s kSPS s kSPS s kSPS ns TBD dB 8 dB dB dB dB 7 Warp Mode 1 Conversion rate Normal Mode Conversion rate Impulse Mode Transient Response Full-Scale Step 0 0 AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) fIN fIN = 20 kHz, fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz = 20 kHz,-60 dB Input 84 84 Intermodulation Distortion Second Order Terms Third Order Terms TBD TBD VDD = 2.5V dB dB (TA = -40 C to +85 C, VREF = 2.5V, OVDD = 2.3V to VDD, unless otherwise noted.) Parameter THROUGHPUT SPEED Conversion rate 85 100 -100 85 25 Conditions Min Typ Max Unit TBD TBD TBD TBD TBD TBD TBD s kSPS s kSPS s kSPS ns TBD dB 8 dB dB dB dB 7 Warp Mode 1 Conversion rate Normal Mode Conversion rate Impulse Mode Transient Response Full-Scale Step 0 0 AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) fIN fIN = 20 kHz, fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz = 20 kHz,-60 dB Input TBD TBD Intermodulation Distortion Second Order Terms Third Order Terms TBD 100 -100 TBD TBD TBD TBD dB dB NOTES 7 Using high bandwidth. See timing specifications for low bandwidth. 8 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. Specifications subject to change without notice. -3- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947-SPECIFICATIONS TIMING SPECIFICATIONS (-40 C to +85 C, VDD = 4.5 V to 5.5V, OVDD = 2.3 V to 5.5 V, unless otherwise stated) O O Symbol Conversion Time: CNV Rising Edge to Data available high bandwidth, (Warp mode / Normal mode / Impulse mode) Acquisition Time: high Bandwidth low Bandwidth Time Between Conversions high bandwidth, (Warp mode / Normal mode / Impulse mode) CNV Pulse width ( CS mode ) SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data remains Valid SCK Falling Edge to Data Valid delay OVDD above 4.75V OVDD above 3V OVDD above 2.7V OVDD above 2.3V CNV or SDI Low to SDO D15 MSB Valid (CS mode) OVDD above 4.75V OVDD above 2.7V OVDD above 2.3V CNV or SDI High or last SCK Falling Edge to SDO High Impedance (CS mode) SDI valid Setup Time from CNV rising edge (CS mode) SDI valid Hold Time from CNV rising edge (CS mode) SCK valid Setup Time from CNV rising edge (Chain mode) SCK valid Hold Time from CNV rising edge (Chain mode) SDI valid Setup Time from SCK falling edge (Chain mode) SDI valid Hold Time from SCK falling edge (Chain mode) SDI High to SDO High (Chain mode with Busy indicator) OVDD above 4.75V OVDD above 2.7V OVDD above 2.3V Min t CONV 0.7/0.9/1.1 t ACQ 400 1.5 2/2.3/2.6 t CYC t CNVH t SCK t SCKH t SCKL t HSDO t DSDO Typ -4- 1.6/1.9/2.2 Unit s ns s note 1 s 5 15 7 7 5 ns ns ns ns ns 13 20 27 TBD ns ns ns ns 15 30 TBD ns ns ns 30 ns ns ns ns ns ns ns 15 30 TBD ns ns ns t EN t DIS t SSDICNV t HSDICNV t SSCKCNV t HSCKCNV t SSDISCK t HSDISCK t DSDOSDI 8 0 8 5 8 0 NOTES 1 In Warp mode, the maximum time between conversion is 1ms; otherwise, there is no required maximum time. Specifications subject to change without notice. REV. Pr A Max PRELIMINARY TECHNICAL DATA AD7947 ABSOLUTE MAXIMUM RATINGS1 Analog Inputs IN+2 , IN- 2, REF, . . . . . GND -0.3 V to VDD + 0.3 Supply Voltages VDD, OVDD to GND . . . . . . . . . . . . . . . . -0.3 V to 7 VDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital Inputs to GND . . . . . . -0.3 V to OVDD + 0.3 Digital Outputs to GND . . . . -0.3 V to OVDD + 0.3 V V V V V Storage Temperature Range . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C JA Thermal Impedance . . . . . . . . . . 200C/W (SOIC-10) JC Thermal Impedance . . . . . . . . . . . 44C/W (SOIC-10) TBDC/W (CSP-10) Lead Temperature Range Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. ORDERING GUIDE Model Temperature Range Package Description Package Option Brand AD7947BRM AD7947BRMRL7 AD7947BCP EVAL-AD7947CB1 EVAL-CONTROL BRD2 2 EVAL-CONTROL BRD3 2 -40C to +85C -40C to +85C -40C to +85C SOIC-10 SOIC-10 CSP-10 Evaluation Board Controller Board Controller Board RM-10 RM-10 (reel) C1F C1F C1F NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 2 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. AD7947 PIN CONFIGURATION 500A IOL 10-Lead SOIC and 10-Lead CSP +1.4V To SDO CL REF 1 VDD 2 50pF 500A IN+ 3 IN- 4 IOH GND 5 Figure 1. Load Circuit for Digital Interface Timing. 10 AD7647 OVDD 9 SDI 8 7 SCK SDO 6 CNV 70% OVDD 30% OVDD tDELAY tDELAY 2V or OVDD-0.5V1 0.8V or 0.5V 2 2V or OVDD-0.5V 0.8V or 0.5V2 1 Note 1 : 2V if OVDD above 2.5V, OVDD-0.5V if OVDD below 2.5V. Note 2 : 0.8V if OVDD above 2.5V, 0.5V if OVDD below 2.5V. Figure 2. Voltage Reference Levels for Timing. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7947 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -5- WARNING! ING! ESD SENSITIVE DEVICE REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 PIN FUNCTION DESCRIPTIONS Pin # Mnemonic Function 1 REF AI 2 3 4 5 6 VDD IN+ INGND CNV P AI AI P DI 7 SDO DO 8 SCK DI 9 SDI DI 10 OVDD P Reference Input Voltage. The REF range is from 0.5V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10F capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, Chain or CS mode. In CS mode, it enables the SDO pin when low. In Chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result or the programming configuration word are ouput on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. If less than 14 pulses are applied during selection, the programming configuration is updated. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 14 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low and if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8V, 2.5V, 3V or 5V). NOTES AI = Analog Input DI = Digital Input DO = Digital Output P = Power REV. Pr A -6- PRELIMINARY TECHNICAL DATA AD7947 DEFINITION OF SPECIFICATIONS EFFECTIVE NUMBER OF BITS (ENOB) INTEGRAL NONLINEARITY ERROR (INL) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale". The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (figure 4). DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. ENOB = (S/[N+D] dB - 1.76)/6.02) and is expressed in bits. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. SIGNAL-TO-NOISE RATIO (SNR) ZERO ERROR SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. The zero error is the difference between the ideal midscale voltage ( i.e., 0V) from the actual voltage producing the midscale output code (i.e., 0LSB). SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D]) GAIN ERROR The first transition (from 100...00 to 100...01) should occur at a level 1/2 LSB above the nominal negative full scale (-4.999695V for the 5 V range). The last transition (from 011 . . . 10 to 011 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999084 V for the 5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. SPURIOUS FREE DYNAMIC RANGE (SFDR) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. APERTURE DELAY Aperture delay is a measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. TRANSIENT RESPONSE The time required for the AD7947 to accurately acquire its input after a full-scale step function was applied. The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. -7- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 IN+ LSB MSB 8,192C 4,096C 4C 2C C SW + SWITCHES CONTROL C BUSY REF COMP CONTROL LOGIC OUTPUT CODE GND 8,192C 4,096C 4C 2C MSB C C SW LSB CNV IN - Figure 3. ADC Simplified Schematic are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/16384). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. CIRCUIT INFORMATION The AD7947 is a fast, low-power, single-supply, precise 14-bit analog-to-digital converter (ADC) using a successive approximation architecture. It features different modes to optimize performance according to the application. In Warp mode, the AD7947 is capable of converting 500,000 samples per second (500kSPS). In Impulse mode, the AD7947 is capable of converting 380,000 samples per second (380kSPS) and powers down between conversions. When operating at 100SPS, for example, it consumes typically 1.6W with a 2.5V supply, ideal for battery-powered applications. Because the AD7947 has an on-board conversion clock, the serial clock SCK is not required for the conversion process. The AD7947 provides the user with an on-chip track/hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. Modes of Operation The AD7947 features three modes of operations, Warp, Normal, and Impulse. Each of these modes is optimized for specific applications. The AD7947 can be operated from a single 2V to 5.5V supply, specified from 2.3V to 5.5V, and can be interfaced to either 5 V or 3.3 V or 2.5 V or 1.8V digital logic. It is housed in a 10-lead SO or a tiny 10-lead CSP (chip scale package) that combines space savings and allows flexible configurations. - Warp mode allows the fastest conversion rate up to 500kSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1ms. If the time between two consecutive conversions is longer than 1ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the AD7947 ideal for applications where fast sample rates are required. It is pin-for-pin-compatible with the 16-bit AD7688. CONVERTER OPERATION The AD7947 is a successive approximation ADC based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 14 binary weighted capacitors which are connected to the two comparator inputs. - Normal mode is the fastest mode (450kSPS) without any limitation in the time between conversions. This mode makes the AD7947 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rates are required. During the acquisition phase, terminals of the array tied to the comparator's input are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN- inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SWREV. Pr A - Impulse mode, the lowest power dissipation mode, powers down between conversions. The maximum throughput in this mode is 380kSPS. When operating at 100SPS and 2.5V, for example, it typically consumes only 1.6W. This feature makes the AD7947 ideal for battery-powered applications. -8- PRELIMINARY TECHNICAL DATA AD7947 The mode of operation is unknown at power-up and must be selected using a programming sequence (see table II). Transfer Functions ADC CODE - Two's Complement The ideal transfer characteristic for the AD7947 is shown in Figure 4 and Table I. 011...111 011...110 011...101 100...010 100...001 100...000 -FS -FS+1 LSB +FS-1 LSB -FS+0.5 LSB +FS-1.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function Table I. Output Codes and Ideal Input Voltages Description FSR -1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Analog Input VREF = 5V 4.999390V 610.4V 0V -610.4V -4.999390V -5V Digital Output Code Hexa 1FFF1 0001 0000 3FFF 2001 2000 2 NOTES 1 This is also the code for an overranged analog input (V IN+ - V INabove V REF - V GND ). 2 This is also the code for an underranged analog input (V IN+ - V INbelow -V REF + V GND ). -9- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 CS MODE 3 wires, no Busy indicator DIGITAL INTERFACE Though the AD7947 has a reduced number of pins, it offers flexibility in its serial interface modes: This mode is usually used when a single AD7947 is connected to an SPI compatible digital host. The connection diagram is shown in figure 5 and the corresponding timing is given in figure 6. With SDI tied to OVDD, a rising edge on CNV initiates a conversion, selects the CS mode and forces SDO to high impedance. Once a conversion is initiated, it will continue to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices such as analog multiplexers but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7947 enters the acquisition phase and powers down if in impulse mode. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK driving edges. The driving edge can be either falling or rising depending on how the part is programmed (see table II). The data is valid on both SCK edges. Although the non-driving edge can be used to capture the data, a digital host also using the SCK driving edge will allow a faster reading rate provided it has an acceptable hold time. After the 14th SCK driving edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. The AD7947, when in "CS mode", is compatible with SPI, QSPI digital hosts and DSPs (e.g.Blackfin ADSPBF53x or ADSP-219x). This interface can use either 3 or 4 wires. A three wire interface using the CNV, SCK and SDO signals, minimizes wiring connections useful, for instance, in isolated applications. A four wire interface using the SDI, CNV, SCK and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The AD7947, when in "Chain mode", provides a "daisy chain" feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7947 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. CONVERT CNV SDI The busy indicator feature is enabled as follows: In CS mode, if CNV or SDI is low when the ADC conversion ends (figure 8 and 12). In Chain mode, if SCK is high during the CNV rising edge (figure 16). Digital Host AD7647 OVDD SDO DATA IN SCK CLK Figure 5. CS mode 3 wires, no busy indicator connection diagram ( SDI high ). SDI = 1 tCYC tCNVH CNV tACQ tCONV ACQUISITION CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 tHSDO 13 14 tSCKH tDSDO tEN SDO 12 D13 D12 D11 tDIS D1 D0 Figure 6. CS mode 3 wires, no busy indicator serial interface timing ( SDI high ). REV. Pr A -10- PRELIMINARY TECHNICAL DATA AD7947 CS MODE 3 wires with Busy indicator the digital host. The AD7947 then enters the acquisition phase and powers down if in impulse mode. The data bits are then clocked out, MSB first, by subsequent SCK driving edges. The SCK driving edge, either falling or rising, can be selected using a programming sequence (see table II). The data is valid on both SCK edges. Although the non-driving edge can be used to capture the data, a digital host also using the SCK driving edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 15th SCK driving edge or when CNV goes high whichever is earlier, SDO returns to high impedance. This mode is usually used when a single AD7947 is connected to an SPI compatible digital host having an interrupt input. The connection diagram is shown in figure 7 and the corresponding timing is given in figure 8. With SDI tied to OVDD, a rising edge on CNV initiates a conversion, selects the CS mode and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices such as analog multiplexers but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by CONVERT OVDD CNV AD7647 OVDD SDI Digital Host 47k SDO DATA IN SCK IRQ CLK Figure 7. CS mode 3 wires with busy indicator connection diagram ( SDI high ). SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL SCK 1 2 3 tHSDO 13 14 15 tSCKH tDSDO SDO tDIS D13 D12 D1 D0 Figure 8. CS mode 3 wires with busy indicator serial interface timing ( SDI high ). -11- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 CS MODE 4 wires, no Busy indicator the conversion is complete, the AD7947 enters the acquisition phase and powers down if in impulse mode. Each ADC result can be read by bringing low its SDI input which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK driving edges. The SCK driving edge, either falling or rising, can be selected using a programming sequence (see table II). The data is valid on both SCK edges. Although the non-driving edge can be used to capture the data, a digital host also using the SCK driving edge will allow a faster reading rate provided it has an acceptable hold time. After the 14th SCK driving edge or when SDI goes high whichever is earlier, SDO returns to high impedance and another AD7947 can be read. This mode is usually used when multiple AD7947's are connected to an SPI compatible digital host. A connection diagram example using two AD7947's is shown in figure 9 and the corresponding timing is given in figure 10. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers but SDI must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. When CS2 CS1 CONVERT CNV CNV AD7647 AD7647 SDI SDO SDI Digital Host SDO SCK SCK DATA IN CLK Figure 9. CS mode 4 wires, no busy indicator connection diagram. tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 SCK 2 3 12 tHSDO 14 15 16 27 28 tSCKH D13 D12 D11 tDIS D1 D0 D13 D12 Figure 10. CS mode 4 wires, no busy indicator serial interfacetiming. REV. Pr A 26 tDSDO tEN SDO 13 -12- D1 D0 PRELIMINARY TECHNICAL DATA AD7947 CS MODE 4 wires with Busy indicator guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on SDO line, this transition can be used as an interrupt signal to intiate the data readback controlled by the digital host. The AD7947 then enters the acquisition phase and powers down if in impulse mode. The data bits are then clocked out, MSB first, by subsequent SCK driving edges. The SCK driving edge, either falling or rising, can be selected using a programming sequence (see table II). The data is valid on both SCK edges. Although the non-driving edge can be used to capture the data, a digital also host using the SCK driving edge will allow a faster reading rate provided it has an acceptable hold time. After the optional 15th SCK driving edge or SDI going high, whichever is earlier, the SDO returns to high impedance. This mode is usually used when a single AD7947 is connected to an SPI compatible digital host having an interrupt input and it is desired to keep CNV, used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in figure 11 and the corresponding timing is given in figure 12. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to CS1 OVDD CNV CONVERT 47k AD7647 SDI Digital Host DATA IN SDO SCK IRQ CLK Figure 11. CS mode 4 wires with busy indicator connection diagram . tCYC CNV tACQ tCONV ACQUISITION CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 SCK 2 3 tHSDO 13 14 15 tSCKH tDSDO tEN SDO tDIS D13 D12 D1 D0 Figure 12. CS mode 4 wires with busy indicator serial interface timing. -13- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 enters the acquisition phase and powers down if in impulse mode. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK driving edges. The SCK driving edge, either falling or rising, can be selected using a programming sequence (see table II). For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK driving edge. Each ADC in the chain output its data MSB first, and 14*N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the non-driving edge can be used to capture the data, a digital host also using the SCK driving edge will allow a faster reading rate and, consequently more AD7947s in the chain provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 5ns digital host set-up time and 5V interface, up to four AD7947's running at a conversion rate of 370 kSPS in warp mode can be daisy-chained on a 3 wire port. Chain MODE, no Busy indicator This mode can be used to "daisy-chain" multiple AD7947's on a 3 wire serial interface. This feature is useful for reducing component count and wiring connections e.g. in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7947's is shown in figure 13 and the corresponding timing is given in figure 14. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects Chain mode and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7947 CONVERT CNV CNV AD7647 AD7647 A B SDI SDI SDO Digital Host SDO DATA IN SCK SCK CLK Figure 13. Chain mode, no busy indicator connection diagram . SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV 1 SCK 2 3 tHSCKCNV 13 tSSDISCK 14 15 16 DA13 DA12 26 27 28 D A1 D A0 tSCKH tHSDISC tEN SDOA = SDIB 12 DA13 DA12 DA11 DA1 DA0 DB12 DB11 DB1 DB0 tHSDO tDSDO SDOB DB13 Figure 14. Chain mode, no busy indicator Serial InterfaceTiming. REV. Pr A -14- PRELIMINARY TECHNICAL DATA AD7947 host. The AD7947 then enters the acquisition phase and powers down in impulse mode. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK driving edges. The SCK driving edge, either falling or rising, can be selected using a programming sequence (see table II). For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK driving edge. Each ADC in the chain outputs its data MSB first, and 14*N +1 clocks are required to readback the N ADCs. Although the non-driving edge can be used to capture the data, a digital host also using the SCK driving edge will allow a faster reading rate and, consequently more AD7947s in the chain provided the digital host has an acceptable hold time. For instance, with a 5ns digital host set-up time and 5V interface, up to four AD7947's running at a conversion rate of 370 kSPS in warp mode can be daisy-chained to a single 3 wire port. Chain MODE with Busy indicator This mode can also be used to "daisy-chain" multiple AD7947's on a 3 wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections e.g. in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7947's is shown in figure 15 and the corresponding timing is given in figure 16. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects Chain mode and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the "nearend" ADC ( ADC C in figure 15 ) SDO will be driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital CONVERT SDI CNV CNV CNV AD7647 AD7647 AD7647 A B C SDI SDO SDO SDI SCK SCK Digital Host SDO DATA IN IRQ SCK CLK Figure 15. Chain mode with busy indicator connection diagram . tCYC CNV = SDIA tACQ tCONV ACQUISITION CONVERSION ACQUISITION tSCK tSCKH tSSCKCNV 1 SCK 2 3 tHSCKCNV 4 tSSDISCK 13 15 16 17 27 28 29 30 31 41 42 43 DA1 D A0 tSCKL tHSDISC tEN DA13 SDOA = SDIB 13 DA12 DA11 DA1 DA0 DB13 DB12 DB11 DB1 DB0 DA13 DA12 D A1 D A0 DC13 DC12 DC13 DC1 DC0 DB13 DB12 DB1 D B0 tHSDO tDSDO SDOB = SDIC tDSDOSDI SDO C DA13 DA12 Figure 16. Chain mode with busy indicator serial interface timing. -15- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 Programming the configuration of the AD7947 In Chain mode (figure 17): - The SCK rising edges are counted after the completion of the conversion when CNV is high. - The AD7947 is deselected and the configuration is updated when CNV goes low. - Only one single change of the configuration can be done per conversion. The AD7947 offers the following features which can be selected by the user via a truncated readback: - The modes of operation: Warp, Normal or Impulse. - An internal input low pass filter with selectable bandwidth for anti-aliasing and external noise filtering. - The driving edge polarity used to output the data on SDO. - Synchronizing the busy indicator to SCK. - A single command "reset to default settings". - Current configuration readback. In CS mode, 3 wire (figure 18): - While SDI is high, the SCK rising edges are counted after the completion of the conversion when CNV is taken low. - The AD7947 is deselected and the configuration is updated when CNV is taken high. - If CNV and SDI are simultaneously low, SDO is forced low, any SCK rising edges are ignored and the configuration is not changed when the part is deselected. - Only one single change of the configuration can be done per conversion. The programming configuration is modified only if less than 14 rising edges are applied on the SCK input after the conversion while the part is selected. The configuration is actually updated when the part is deselected. The number of SCK rising edges programs the feature selection according to table II. Reset SDI=0 CNV ACQUISITION CONVERSION ACQUISITION SCK SDO D13 D12 D11 D10 D9 D8 D7 D6 Figure 17. Programming example using in Chain mode ( "Reset to default settings"). Reset SDI=1 CNV ACQUISITION CONVERSION ACQUISITION SCK SDO D13 D12 D11 D10 D9 D8 D7 D6 Figure 18. Programming example using CNV in CS mode ( "Reset to default settings"). REV. Pr A -16- PRELIMINARY TECHNICAL DATA AD7947 In CS mode, 4 wire (figure 19): - While CNV is high, the SCK rising edges are counted after the completion of the conversion when SDI is taken low. - The AD7947 is deselected and the configuration is updated every time SDI is taken high. - In this mode, the selected feature depends on the total number of SCK rising edges seen since the end of conversion. - If CNV and SDI are simultaneously low, SDO is forced low, any SCK rising edges are ignored and the configuration is not changed when the part is deselected. - A complete new configuration could be selected during a single conversion. The data on the SDO output is still the valid ADC result and the complete 14 bit result can be read. In the example shown in figure 19, the selected configuration is high bandwidth, synchronous busy indicator, falling SCK driving edge, warp mode and the configuration is be readback after the subsequent conversion. Programming details (all modes): The settings are undefined at power-up, therefore a "reset to default settings" programming of the AD7947 must be done after power-up. However, a "Reset to default settings" command ( 3 or 8 SCK pulses ) changes the configuration to a factory predefined state ( warp mode, high bandwidth, asynchronous busy indicator and falling SCK driving edge ). SPI compatible digital hosts offer the possibility to send 8 SCK pulses by software. A truncated valid ADC result is still available on the SDO output. When the mode of operation is changed to warp mode, the next conversion result should be ignored. When the mode of operation is changed to normal mode, the next conversion should be initiated after a tACQ delay to provide a valid result otherwise the next conversion result should be ignored. When the mode of operation is changed to impulse mode, the next conversion can be initiated immediately and provides a valid result. When the readback command is selected, the configuration will be output on the SDO pin in place of the ADC result during the readback of the following conversion as shown in figure 19. The configuration can also be changed when it is readback. CNV ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION SCK Reset Synchronous Busy Readback SDI SDO D13 D12 D11 D11 D10 D10 D9 D8 D7 D6 D1 D0 D8 Figure 19. Programming example using SDI in CS mode ( high bandwidth, synchronous busy indicator, falling SCK driving edge, warp mode followed by a configuration readback). -17- REV. Pr A PRELIMINARY TECHNICAL DATA AD7947 Table II. Programming Configuration Number of SCK rising edges REV. Pr A Program Feature Readback Value Default Settings at Reset 0 No effect 1 No effect 1 (D13=MSB) 2 No effect ( do not use ) 1 (D12) 3 Reset to Default settings 0 (D11) 4 Toggle Bandwidth High Bandwidth = 1, Low Bandwidth = 0 High Bandwidth 5 Toggle Busy Indicator synchronisation Synchronous = 1, Asynchronous = 0 Asynchronous 6 Toggle SCK Driving edge synchronisation Rising = 1, Falling = 0 Falling edge 7 Readback content 0 (D7) 8 Reset to Default settings 0 (D6) 9 Set Impulse Impulse = 1, Warp or Normal = 0 10 No effect 0 (D5) 11 Set Normal Normal = 1, Impulse or Warp = 0 12 No effect X 13 Set Warp Warp = 1, Impulse or Normal = 0 14 No effect X >14 No effect X -18- 0, Warp 0, Warp 1, Warp PRELIMINARY TECHNICAL DATA AD7947 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 10-Lead SOIC (RM-10) 0.124 (3.15) 0.112 (2.84) 6 10 0.124 (3.15) 0.112 (2.84) 0.199 (5.05) 0.187 (4.75) 1 5 PIN 1 0.0197 (0.50) BSC 0.038 (0.97) 0.030 (0.76) 0.122 (3.10) 0.110 (2.79) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 6 SEATING 0.006 (0.15) 0.016 (0.41) PLANE 0 0.011 (0.28) 0.002 (0.05) 0.006 (0.15) 0.003 (0.08) 0.022 (0.56) 0.021 (0.53) 10-Lead CSP (CP-10) Dimensions shown in mm. INDEX AREA 0.50 BSC 3.00 BSC SQ 0.20 R 1.50 BCS SQ 5 1 1.74 1.64 1.49 EXPOSED PAD (BOTTOM VIEW) TOP VIEW 0.50 0.40 0.30 0.23 6 10 1.00 0.90 0.80 SEATING PLANE 2.48 2.38 2.23 1.00 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF -19- REV. Pr A