15/40
M95160, M95080
Write Status Regist er (WRSR)
The Write Status Register (WRSR) instruction al-
lows new val ues to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been d ecoded and ex ecuted, the de vice se ts
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the dat a byt e on Serial
Data Input (D).
The instruct i on sequence is shown in Figure 10..
The Write Stat us Regi ster (WRSR) i nstruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are alway s read as 0.
Chip Select (S) must be driven High aft er the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
time d Writ e Status Registe r cycle (who se d u ra tio n
is tW) is initiate d. W hile the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. T he Wri te I n Progress (WIP) bit i s 1 dur-
ing th e self-ti med Write Status Re g i ste r cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enabl e Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that i s to be treated as read-only, as d efined
in Table 3..
The Write Status Register (WRSR) instruction also
allows the user to set or reset the S tatus Regi ster
Write Disable (SRWD ) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in th e Hardware
Protected Mode (HP M). The Writ e Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Stat us Register Write Disable
(SRWD) and Bloc k Protect (BP1, BP0) bit s are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of complet ion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
Table 6. Protection Mode s
Note: 1. As def i ned by th e values in the Block Pr ot ect (BP1, BP0) bi ts of t h e Status Regist er, as sh own in Tab l e 6. .
The prot ection f eatures of t he device are su mma-
rized in Table 4..
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Regi ster
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, rega rd less o f the wh ether W ri te Prote ct
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered , depending on t he state of
Write Protect (W):
– If Write Protect (W) is driven High, i t is
pos sible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write E nable
(WREN ) instruction.
– If Write Protect (W) is driven Low, it is not
poss ible to write to the Status Regist er even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enabl e
(WREN ) instruction. (Attempts to write to the
Stat us Register are rejected, and are not
accept ed for execution). As a consequence,
all the data bytes in the memory area t hat are
software protected (SPM) by the Block Protect
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the BP1 and
BP0 bits can be changed
Write Protected Ready to accept Write
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1 and
BP0 bits cannot be
changed
Write Protected Ready to accept Write
instructions