1/40October 2004
M95160
M95080
16Kbit and 8Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
■Compat ible with SPI Bus Seri al In te r fa ce
(Positive Clock SPI Modes)
■Sin gle Supply Vo ltage:
– 4.5 to 5.5V for M95xxx
– 2.5 to 5.5V for M95xxx-W
– 1.8 to 5.5V for M95xxx-R
■Hi gh S peed
– 10MHz Clock Rate, 5ms Write Time
■Status Register
■H ardware Protection of the Status Register
■BYTE and P AG E WR ITE (up to 32 Bytes)
■Self-Timed Programming Cycle
■Adjustable Size Read-Only EEPROM Area
■Enh anced ESD P rotection
■More than 1 Million Erase/Write Cycles
■More than 40-Ye ar Data Retention
Table 1. Product List
Figure 1. Packages
Reference Part Number
M95160
M95160
M95160-W
M95160-R
M95080
M95080
M95080-W
M95080-R
PDIP8 (BN)
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSO P)
8
1
UFDFPN8 (MB)
2x3mm² (MLP)
M95160, M95080
2/40
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP, SO, TSSOP and MLP Conne ctions (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus M aster an d Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Mod es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. SPI Modes Supp orted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset: VCC Lock-Ou t Write Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Standby Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Status Register F ormat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2
Write Enable (WR EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/40
M95160, M95080
Figure 7. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Write Disable (WRDI) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
Table 7. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Write Status Register (WRSR) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.Read f rom Memo ry Array (READ ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write to Memory Array (WRITE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12.B yte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13.P age Write (WRITE ) Sequen ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up Sta te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initial Delive ry State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Table 9. Operating C onditions (M9 5xxx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Op erating Conditions (M9 5xxx-W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Op erating Conditions (M9 5xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. AC Measurem ent Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14.AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Capaci tance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3
Table 14 . DC Characteristics (M95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15 . DC Characteristics (M95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16 . DC Characteristics (M95xxx-W, De vice G rade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17 . DC Characteristics (M95xxx-W, De vice G rade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18 . DC Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. A C Characteristics (M 95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. A C Characteristics (M 95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. AC Characteristics (M95xxx-W, Device Grad e 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 22. AC Characteristics (M95xxx-W, Device Grad e 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23 . A C Characteristics (M95xxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15.S erial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
M95160, M95080
4/40
PACKAGE M ECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3
Figure 18.P DIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outlin e . . . . . . . . . . . . . . . . . 33
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package M echanical Data. . . . . . . . . . 33
Figure 19.S O8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 34
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechan ical Data . . . . 34
Figure 20.UFDFPN8 (MLP8) 8-lead Ultra thin Fi ne pitch Dual Flat Package No lead 2x3mm², Outline
35
Table 26. UF DFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.
35
Figure 21.TSS OP 8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 36
Table 27. TSSOP 8 – 8 lead Thin Shrink Sma ll Outline, Packag e Mechani cal Data . . . . . . . . . . . . 36
Figure 22.TSS OP 8 3x3m m² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
37
Table 28. TSSOP8 3x3mm² – 8 lead Thin Shri nk Small Outline, 3x3mm² body size, Mechani cal Data
37
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 30. How to Identify Present and Previous P roducts by the Process Ide ntification Letter . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 31. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5/40
M95160, M95080
S UM MARY DESCR IPTION
These electrical ly erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 2048 x 8 bit (M95160), and 1024 x 8
bit (M95080) .
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 2. and Figur e 2..
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
Figure 3. DIP, SO, TSSO P and ML P
Connections (To p View)
Not e: See PACKAGE MECHANICAL section for package dimen-
si ons, and how to ident i fy pi n-1.
Table 2. Signal Names
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
C Serial Clock
D Serial Data Input
Q Serial Data Outp ut
SChip Select
W Write Protect
HOLD Hold
VCC Supply Vo ltage
VSS Ground
DVSS C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
M95160, M95080
6/40
SIGNAL DESCRIPTION
During all operations, VCC must be held stable and
within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held
High or Low (according to voltages of VIH, VOH, V IL
or VOL, as specified in Table 14. to Table 18.).
These signals are described next.
Serial Data O utp ut (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data In put (D). This input signal i s used to
transfer data seriall y into t he devi ce. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the s erial interface. Instructions, addres s-
es, or data present at Serial Data Input (D) are
latched on the ris ing edge of Serial Clock (C) . Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Selec t (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving C hip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecti ng the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hol d condit ion, the device must be se-
lected, wit h C h ip S e lec t (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of m em-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write in structions.
7/40
M95160, M95080
CONNECTING TO TH E SPI B US
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Se rial Clock (C) after Chip
Se l e c t ( S) goe s Low.
All output data by tes are shift ed out of the device,
most significant bit first. The Serial Data Output
(Q) is lat ch ed on the fi rst fa lling edge of the Se rial
Clock (C) after the instruction (such as the Read
from Mem ory Array and Read S tatus Re gister in-
structions) have been cloc ked int o the dev ice.
Figure 4. shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) li ne at a t ime, all the o thers be ing h igh
impedance.
Figure 4. Bus Master and Memo ry Devices on the SPI Bus
Note: The Write Protect (W) and Hol d (HOLD) signals should be driven, Hi gh or Low as appropri at e.
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
M95160, M95080
8/40
SPI Modes
These dev ices can be drive n by a microcont roller
with its SPI peripheral running in either of the two
following modes:
– CP OL=0, CPHA=0
– CP OL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between t he two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA =0)
– C remains at 1 for (CPOL=1, CPHA =1)
Figure 5 . S PI Modes Suppor te d
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
9/40
M95160, M95080
OPERAT ING FEA TURES
Power-up
When the power supply is turned on, VCC rises
fro m V SS to VCC.
During this time, the Chip Select (S) must be al-
lowed to follow t he V CC v ol tage . It mu st not be al-
lowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feat ure, Chi p Selec t (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Selec t
(S). This ensures that Ch ip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power On Reset: VCC Lock-Out Write Protec t
In order to prevent data corruption and inadvertent
Write instructions during Power-up, a Power On
Reset (POR) circuit is included. The in ternal reset
is held activ e unt il VCC has reached the Power On
Reset (POR) threshold voltage, and all operations
are disabled – the device will not respond to any
instruction. In t he same way, when VCC drops from
the operating voltage, below the P ower On Reset
(POR) threshold voltage, all operations are dis-
abled and the device will not respond to any in-
struction.
A stable and valid VCC must be applied before ap-
plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage appli ed on VCC.
Active Power and S t an db y Power M ode s
When Chip Select (S) is Low, the device is select -
ed, and in the Active Power mode. The device
consumes ICC, as specified in Table 14. to Table
18..
When Chip Sel ec t ( S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
Power mode, and the device consumption drops
to I CC1.
Hold Condition
The Hold (HOLD) signal is used t o pause any se-
rial communications with the device wi thou t reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
sele c te d , wit h C hip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of t he Hol d condition. Deselecting the de-
vice while it is in the Hold condi tion, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already bein g Low.
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already bein g Low.
M95160, M95080
10/40
Status Reg ister
Figure 6. shows the position of the Status Register
in the control logic o f the d ev ice. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Regi st er cycle.
WE L bi t. The W rite Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Latch.
BP1, BP0 b its. The B lock Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in th e Hardware
Protected mode. In this mode, the non-volatile bits
of t he Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 3. Status Regi ster Format
Dat a Pro t ec ti on a n d Protoc ol Co ntrol
Non-volatile memory devices can be used in envi-
ronments that are particular ly noisy, and wi thin ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
■Wri t e and Write Status Register instructions
are checked that they consist of a number of
cloc k pulses that is a multipl e of eight, before
they are accep ted for execution.
■All instructions that modify data must be
prece ded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WE L) bit. This bit is returned to its reset state
by the following events:
– Power-up
– W rite Disable (WRDI) instruction
completion
– Write Stat us Register (WRSR) i nstr uction
completion
– W rite (WRITE) instruction completion
■The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
■The Write Protect (W) si gnal allows the Bl ock
Protect (BP1, BP0) bits to be protected. This is
the Hardware Prote cted Mode (HPM).
For any instruction to be ac cept ed, and e xe cuted,
Chip Select (S) must be driven High aft er the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and bef ore the next rising edge of Serial
Clock (C).
Two points need to be noted in the p revious s en-
tence:
– The ‘last bi t of the instruction’ can be the
eighth bi t of the instruction code, or the eighth
bit of a data byt e, depending on the instruction
(except for Read Status Register (RDSR) and
R ead (READ) instructions).
– The ‘next rising edge of Serial Clock (C)’ might
(or might not) be the next bus trans action for
some other device on the SPI bus.
Table 4. Write-Protected Block Size
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Status Regis ter Bits Protected Block Array Addresses Protected
BP1 BP0 M95160 M95080
0 0 none none none
0 1 Upper quarter 0600h - 07FFh 0300h - 03FFh
1 0 Upper half 0400h - 07FFh 0200h - 03FFh
1 1 Whole memory 0000h - 07FFh 0000h - 03FFh
M95160, M95080
12/40
INSTRUCTIONS
Each instruction starts with a single-b yte code, as
summarized in Ta ble 5..
If an inval id instruction is sent (on e not con tained
in Table 5.), the device automatically deselects it-
self.
Table 5. Instruction Set
Instruc
tion Description Instruction
Format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
13/40
M95160, M95080
Write Enable (WREN)
The Write Enabl e Latch (WEL) bi t must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enabl e instruction
to the device.
As shown in Figure 7., to send this instruction to
the de v ic e, Chip Sele c t ( S ) i s driven Low, and the
bits of the instruction byte are s hifted in, on Se rial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip S ele c t ( S) being driven High.
Figure 7. Write Enable (WRE N) Seq uen ce
Write Disabl e (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 8., to send this instruction to
the de v ic e, Chip Sele c t ( S ) i s driven Low, and the
bits of the instruction byte are s hifted in, on Se rial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the follow ing events:
–Power-up
– WRDI instruction execution
– WRSR instruction completion
– WRI TE instruction c ompletion.
Figure 8. Write Disable (WRDI) Sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M95160, M95080
14/40
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Wri te St at us Reg ister cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also pos sible to read the Status Register con-
tinuously, as shown in Figure 9..
The status and cont rol bits of t he Status Register
are as fol l ows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WE L bi t. The W rite Enable Latch (WEL) bit indi-
cates the status of the int ernal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when s et to 0 the inte rnal W r ite Enabl e Lat c h
is reset and no Write o r W rite Status Register in-
struction is accepted.
BP1, BP0 b its. The B lock Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written wit h the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 3.) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Har dware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in th e Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1 , and W rite Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Regi ster (SRWD, BP1, BP0) be-
come read-only bit s and the Write St atus Register
(WRSR) instruction is no longer acc epted for exe-
cution.
Figure 9. Read Statu s Register (RDSR) Sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
15/40
M95160, M95080
Write Status Regist er (WRSR)
The Write Status Register (WRSR) instruction al-
lows new val ues to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Wri te Enable (WREN) instruction
has been d ecoded and ex ecuted, the de vice se ts
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the dat a byt e on Serial
Data Input (D).
The instruct i on sequence is shown in Figure 10..
The Write Stat us Regi ster (WRSR) i nstruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are alway s read as 0.
Chip Select (S) must be driven High aft er the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
time d Writ e Status Registe r cycle (who se d u ra tio n
is tW) is initiate d. W hile the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. T he Wri te I n Progress (WIP) bit i s 1 dur-
ing th e self-ti med Write Status Re g i ste r cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enabl e Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that i s to be treated as read-only, as d efined
in Table 3..
The Write Status Register (WRSR) instruction also
allows the user to set or reset the S tatus Regi ster
Write Disable (SRWD ) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in th e Hardware
Protected Mode (HP M). The Writ e Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Stat us Register Write Disable
(SRWD) and Bloc k Protect (BP1, BP0) bit s are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of complet ion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
Table 6. Protection Mode s
Note: 1. As def i ned by th e values in the Block Pr ot ect (BP1, BP0) bi ts of t h e Status Regist er, as sh own in Tab l e 6. .
The prot ection f eatures of t he device are su mma-
rized in Table 4..
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Regi ster
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, rega rd less o f the wh ether W ri te Prote ct
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered , depending on t he state of
Write Protect (W):
– If Write Protect (W) is driven High, i t is
pos sible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write E nable
(WREN ) instruction.
– If Write Protect (W) is driven Low, it is not
poss ible to write to the Status Regist er even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enabl e
(WREN ) instruction. (Attempts to write to the
Stat us Register are rejected, and are not
accept ed for execution). As a consequence,
all the data bytes in the memory area t hat are
software protected (SPM) by the Block Protect
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the BP1 and
BP0 bits can be changed
Write Protected Ready to accept Write
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1 and
BP0 bits cannot be
changed
Write Protected Ready to accept Write
instructions
M95160, M95080
16/40
(BP1, BP0) bits of the Status Register, are
also hardware protected again st data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– b y setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
– o r by driving Write Protect (W) Low aft er
setting th e Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (B P1, BP 0) bi ts of
the Status Register, can be used.
Table 7. Addre ss Range Bits
Note: b15 t o b11 are Don’t Ca re on the M95 160.
b15 to b10 are Don’t Care on the M 95080.
Figure 10. Write Status Register (WRSR) Sequence
Device M95160 M95080
Address Bits A10-A0 A9-A0
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
17/40
M95160, M95080
Read from Memory Array (READ)
As shown in Figure 11., to send this instruction t o
th e device , Chi p Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is s hifte d out,
on Serial Data Output (Q).
If Chip Select (S) co ntinues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at t he new address is
shifted out.
When the highes t address is reached, the address
counter rolls over to zero, allowing the Read cycl e
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated b y driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) si gnal can occur at any time duri ng the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not e xe cut-
ed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) Sequence
Note: Dep ending on t h e memory size, as shown i n Tabl e 7., th e most si gnificant address bits are Don’ t C are.
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
M95160, M95080
18/40
Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction t o
th e device , Chi p Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect ( S) High at a byt e b oundary of the input data.
In the case of Figure 12., this occurs after the
eighth bit of the data byte ha s been l atched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period tWC (as specified i n Ta-
ble 19. to T able 23.), at the end of which the Write
in Progress (WIP) bit is reset to 0 .
If, though, Chip Select (S) continues to be driven
Low, as shown in Fi gure 13. , t he next byte of input
data i s s hifted in , so t hat m ore t han a single by te,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycl e.
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds t he page b oundary, the in ter-
nal address counter rolls over to the be ginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not e xe cut-
ed, under the following conditions:
– if the Write Enabl e Latch (WEL) bit has not
been se t to 1 (by ex ecut ing a Write Enable
instruction just be fore)
– if a Write cycle is already in progress
– if the device has not been deselect ed, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)
– if t he address ed page is in the region
prot ected by the Block Protect (BP1 and BP 0)
bits.
Figure 12. Byte Write (WRITE) Sequence
Note: Dep ending on t h e memory size, as shown i n Tabl e 7., th e most si gnificant address bits are Don’ t C are.
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
19/40
M95160, M95080
Figu re 13 . P age Write (WR I TE ) Seq uence
Note: Dep ending on t h e memory size, as shown i n Tabl e 7., th e most si gnificant address bits are Don’ t C are.
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
M95160, M95080
20/40
P OWER-UP AND DELI VERY STATE
Po w e r-up S tate
After Power-up, the device is in the following state:
– St andby P ower mode
– deselected (after Power-up, a falling edge is
required on Chip Select (S) before any
instructions can be starte d).
– n ot in the Hold Condition
– the Write En able Latch (WEL) is reset to 0
– W rite In Progress (WIP) is reset to 0
The S RWD, BP 1 and BP0 b its of th e S tatu s Reg-
ister are unchanged from the previous power-
down (they are non-volatile bits).
In it ial D e l ive ry Stat e
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
21/40
M95160, M95080
MAXI MUM RAT IN G
Stressing the device outside the ratings listed in
Table 8. may cause permanent damage to the de-
vice. These are s tress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may af fect device rel iability. Refer also to
the STMicroelectroni cs SURE Program and ot her
relevant quali ty documents.
Table 8. Absolute Maxi mum Ratings
Note : 1. Compli ant wit h JED EC Std J- ST D-020 B (for small body, Sn-Pb or Pb asse mbl y), the ST ECOP ACK ® 7191395 s pecificat i on, and
the Eu ropean di rectiv e on Restr i ct i ons on Haz ardous S ubstan ces (RoH S ) 2002/95/EU
2. AEC-Q100-002 (compliant wit h JE DEC Std JESD22-A11 4A, C1= 100pF, R1=1500Ω, R2=500Ω)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VOOutput Voltage –0.50 VCC+0.6 V
VIInput Voltage –0.50 6.5 V
VCC Supply Voltage –0.50 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–4000 4000 V
M95160, M95080
22/40
DC AND A C PARAMETE RS
This section summarizes the operating and mea-
surement condition s, and the DC and AC charac-
teristics o f the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions in t heir circuit matc h the measurem ent
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions (M95xxx)
Table 10. Operating Conditions (M95xxx-W)
Table 11. Oper ating Conditions (M9 5xxx-R)
Note: 1. T hi s product is unde r develo pm ent. For more in fo rm atio n, pl ease cont act your nearest ST sal es office.
Table 12. AC Measurement Conditions
Note: Out put Hi-Z is defined as the poin t where dat a out is no l onger driven.
Figu re 14. AC Measurement I/O W av eform
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. 1 Max. 1 Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operati ng Temperatur e –40 85 °C
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC to 0.7VCC V
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
23/40
M95160, M95080
Table 13. Capacitanc e
Note: Sampled onl y, not 100% tested, at TA= 25°C and a frequen cy of 5 MHz .
Table 14. DC Characteristics (M95 xxx, Device Grade 6)
Note: 1. F or al l 5V range devices, the device meets the outpu t requirem ents f or both TTL and CMOS standa rds.
2. Pr evious product: identified by Process Identificat i on l et ter L.
3. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capa citanc e (D) VIN = 0V 8 pF
Input Capacitance (other pins) VIN = 0V 6 pF
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C=0.1V
CC/0.9VCC at 5MHz,
VCC = 5 V, Q = open, Previous Product 2 4mA
C = 0.1VCC/0.9VCC at 10MHz,
VCC = 5 V, Q = open, Present Product 3 5mA
ICC1 Supply Curre nt
(Standby Power mode)
S = VCC, VCC = 5 V,
VIN = VSS or VCC, Previous Product 2 10 µA
S = VCC, VCC = 5 V,
VIN = VSS or VCC, Present Product 3 2µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL1Output Low Vo ltage IOL = 2 mA, VCC = 5 V 0.4 V
VOH1O utput High Voltage IOH = –2 mA, VCC = 5V 0.8V
CC V
M95160, M95080
24/40
Table 15. DC Characteristics (M95 xxx, Device Grade 3)
Note: 1. F or al l 5V range devices, the device meets the outpu t requirem ents f or both TTL and CMOS standa rds.
2. Pr evious product: identified by Process Identificat i on l et ter L.
3. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Table 16. DC Characteristics (M95xxx-W, Device Grade 6)
Note: 1. Pr evious product: id entified by Process Identification letter L.
2. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 5 V, Q = open, Previous Product 2 4mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open, Present Product 3 3mA
ICC1 Supply Curre nt
(Standby Power mode)
S = VCC, VCC = 5 V,
VIN = VSS or VCC, Previous Product 2 10 µA
S = VCC, VCC = 5 V,
VIN = VSS or VCC, Present Product 3 5µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL1Output Low Vo ltage IOL = 2 mA, VCC = 5 V 0.4 V
VOH1O utput High Voltage IOH = –2 mA, VCC = 5V 0.8V
CC V
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Previous Product 1 2mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, Present Product 2 2mA
ICC1 Supply Curre nt
(Standby Power mode)
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC, Previous Product 1 2µA
S = VCC, VCC = 2.5 V
VIN = VSS or VCC, Present Product 2 1µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH Output High Voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
25/40
M95160, M95080
Table 17. DC Characteristics (M95xxx-W, Device Grade 3)
Note: 1. Pr evious product: id entified by Process Identification letter L.
2. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Table 18. DC Characteristics (M95xxx-R)
Note: 1. T hi s product is unde r develo pm ent. For more in fo rm atio n, pl ease cont act your nearest ST sal es office.
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt
C = 0.1VCC/0.9VCC at 2 MHz,
VCC = 2.5 V, Q = open, Previous Product 1 5mA
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 2.5 V, Q = open, Present Product 2 2mA
ICC1 Supply Curre nt
(Standby Power mode) S = VCC, VCC = 2.5 V, VIN = VSS or VCC 2µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V
VOH Output High Voltage IOH = –0.4 mA, VCC = 2.5 V 0.8 VCC V
Symbol Parameter Test Condition Min. 1 Max. 1 Unit
ILI Input Leakage Current VIN = VSS or VCC ± 2 µA
ILO Output Leak age Curren t S = VCC, VOUT = VSS or VCC ± 2 µA
ICC Supply Curre nt C = 0.1VCC/0.9VCC at 2 MHz,
VCC= 1.8 V, Q = open 1mA
ICC1 Supply Curre nt
(Standby Power mode) S = VCC, VIN = VSS or VCC, VCC = 1.8 V 0.5 µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7 VCC VCC+1 V
VOL Output Low Voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
VOH Output High Voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 VCC V
M95160, M95080
26/40
Table 19. AC Characteristics (M95 xxx, Device Grade 6)
Note: 1. tCH + tCL must never b e less than the shortest possible clock period, 1 / fC(max)
2. Va l ue guaranteed by characterization, not 100% tested i n product i on.
3. T o be charac terized.
4. Pr evious product: identified by Process Identificat i on l et ter L.
5. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Test conditions specified in Table 12. and Table 9.
Symbol Alt. Parameter Min.4Max.4Min.5Max.5Unit
fCfSCK Clock Frequency D.C. 5 D.C. 10 MHz
tSLCH tCSS1 S Active Setup Time 90 15 ns
tSHCH tCSS2 S Not Active Setup Time 90 15 ns
tSHSL tCS S Deselect Time 100 40 ns
tCHSH tCSH S Active Hold Time 90 25 ns
tCHSL S Not Active Hold Time 90 15 ns
tCH 1tCLH Clock High Time 90 40 ns
tCL 1tCLL Clock Low Time 90 40 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 20 15 ns
tCHDX tDH Data In Hold Time 30 15 ns
tHHCH Clock Low Hold Time after HOLD not Active 70 15 ns
tHLCH Clock Low Hold Time after HOLD Active 40 20 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 0 ns
tSHQZ 2tDIS Output Disable Time 100 25 ns
tCLQV tVClock Low to Output Valid 60 35 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 50 20 n s
tQHQL 2tFO Output Fall Time 50 20 n s
tHHQV tLZ HOLD High to Output Valid 50 25 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 100 35 ns
tWtWC Write Time 10 5 ms
27/40
M95160, M95080
Table 20. AC Characteristics (M95 xxx, Device Grade 3)
Note: 1. tCH + tCL must never b e less than the shortest possible clock period, 1 / fC(max)
2. Va l ue guaranteed by characterization, not 100% tested i n product i on.
3. T o be charac terized.
4. Pr evious product: identified by Process Identificat i on l et ter L.
5. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Test conditions specified in Table 12. and Table 9.
Symbol Alt. Parameter Min.4Max.4Min.5Max.5Unit
fCfSCK Clock Frequency D.C. 2 D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 200 90 ns
tSHCH tCSS2 S Not Active Setup Time 200 90 ns
tSHSL tCS S Deselect Time 200 100 ns
tCHSH tCSH S Active Hold Time 200 90 ns
tCHSL S Not Active Hold Time 200 90 ns
tCH 1tCLH Clock High Time 200 90 ns
tCL 1tCLL Clock Low Time 200 90 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 40 20 ns
tCHDX tDH Data In Hold Time 50 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 70 ns
tHLCH Clock Low Hold Time after HOLD Active 90 40 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns
tCLHH Clock Low Set-up Time before HOLD not
Active 00ns
tSHQZ 2tDIS Output Disable Time 250 100 ns
tCLQV tVClock Low to Output Valid 150 60 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 100 50 ns
tQHQL 2tFO Output Fall Time 100 50 ns
tHHQV tLZ HOLD High to Output Valid 100 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 100 ns
tWtWC Write Time 10 5 ms
M95160, M95080
28/40
Table 21. AC Characteristics (M95xxx-W, Device Grade 6)
Note: 1. tCH + tCL must never b e less than the shortest possible clock period, 1 / fC(max)
2. Va l ue guaranteed by characterization, not 100% tested i n product i on.
3. T o be charac terized.
4. Pr evious product: identified by Process Identificat i on l et ter L.
5. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Test conditions specified in Table 12. and Table 10.
Symbol Alt. Parameter Min.4Max.4Min.5Max.5Unit
fCfSCK Clock Frequency D.C. 2 D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 200 90 ns
tSHCH tCSS2 S Not Active Setup Time 200 90 ns
tSHSL tCS S Deselect Time 200 100 ns
tCHSH tCSH S Active Hold Time 200 90 ns
tCHSL S Not Active Hold Time 200 90 ns
tCH 1tCLH Clock High Time 200 90 ns
tCL 1tCLL Clock Low Time 200 90 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 40 20 ns
tCHDX tDH Data In Hold Time 50 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 70 ns
tHLCH Clock Low Hold Time after HOLD Active 90 40 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 0 ns
tSHQZ 2tDIS Output Disable Time 250 100 ns
tCLQV tVClock Low to Output Valid 150 60 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 100 50 ns
tQHQL 2tFO Output Fall Time 100 50 ns
tHHQV tLZ HOLD High to Output Valid 100 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 100 ns
tWtWC Write Time 10 5 ms
29/40
M95160, M95080
Table 22. AC Characteristics (M95xxx-W, Device Grade 3)
Note: 1. tCH + tCL must never b e less than the shortest possible clock period, 1 / fC(max)
2. Va l ue guaranteed by characterization, not 100% tested i n product i on.
3. T o be charac terized.
4. Pr evious product: identified by Process Identificat i on l et ter L.
5. Pr esent p roduct : id entified by Proces s Identific at i on le tt er W or G.
Test conditions specified in Table 12. and Table 10.
Symbol Alt. Parameter Min.4Max.4Min.5Max.5Unit
fCfSCK Clock Frequency D.C. 2 D.C. 5 MHz
tSLCH tCSS1 S Active Setup Time 200 90 ns
tSHCH tCSS2 S Not Active Setup Time 200 90 ns
tSHSL tCS S Deselect Time 200 100 ns
tCHSH tCSH S Active Hold Time 200 90 ns
tCHSL S Not Active Hold Time 200 90 ns
tCH 1tCLH Clock High Time 200 90 ns
tCL 1tCLL Clock Low Time 200 90 ns
tCLCH 2tRC Clock Rise Time 1 1 µs
tCHCL 2tFC Clock Fall Time 1 1 µs
tDVCH tDSU Data In Setup Time 40 20 ns
tCHDX tDH Data In Hold Time 50 30 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 70 ns
tHLCH Clock Low Hold Time after HOLD Active 90 40 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 0 ns
tCLHH Clock Low Set-up Time before HOLD not
Active 00ns
tSHQZ 2tDIS Output Disable Time 250 100 ns
tCLQV tVClock Low to Output Valid 150 60 ns
tCLQX tHO Output Hold Time 0 0 ns
tQLQH 2tRO Output Rise Time 100 50 ns
tQHQL 2tFO Output Fall Time 100 50 ns
tHHQV tLZ HOLD High to Output Valid 100 50 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 100 ns
tWtWC Write Time 10 5 ms
M95160, M95080
30/40
Table 23. AC Characteristics (M95xxx-R)
Note: 1. tCH + tCL must never b e less than the shortest possible clock period, 1 / fC(max)
2. Va l ue guaranteed by characterization, not 100% tested i n product i on.
3. T o be charac terized.
4. T hi s product is unde r develo pm ent. For m ore info rm ation, please contact your nearest ST sale s of f ic e.
5. This is pr eliminary data.
Test conditions specified in Table 12. and Table 11.
Symbol Alt. Parameter Min.4,5 Max.4,5 Unit
fCfSCK Cl ock Frequen cy D.C. 2 MHz
tSLCH tCSS1 S Active Setup Time 200 ns
tSHCH tCSS2 S Not Active Setup Time 200 ns
tSHSL tCS S Dese lect Time 200 ns
tCHSH tCSH S Active Hold Time 200 ns
tCHSL S Not Active Hold Time 200 ns
tCH 1tCLH Clock High Time 200 ns
tCL 1tCLL Cl ock Low Tim e 200 ns
tCLCH 2tRC Cl ock Rise Time 1 µs
tCHCL 2tFC Cl ock Fall Time 1 µs
tDVCH tDSU Data In Setup Time 40 ns
tCHDX tDH Data In Hold Time 50 ns
tHHCH Clock Low Hold Time after HOLD not Active 140 ns
tHLCH Clock Low Hold Time after HOLD Active 90 ns
tCLHL Clock Low Set-up Time before HOLD Active 0 ns
tCLHH Clock Low Set-up Time before HOLD not Active 0 ns
tSHQZ 2tDIS Output Disable Time 250 ns
tCLQV tVClock Low to Output Valid 150 ns
tCLQX tHO O utput Hold Time 0 ns
tQLQH 2tRO Output Rise Time 100 ns
tQHQL 2tFO Output Fall Time 1 00 ns
tHHQV tLZ HOLD High to Output Valid 100 ns
tHLQZ 2tHZ HOLD Low to Output High-Z 250 ns
tWtWC Write Time 10 ms
31/40
M95160, M95080
Figu re 15 . Seri a l Input Timing
Figu re 16 . Hol d T im i ng
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
Q
AI01448B
S
D
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
M95160, M95080
32/40
Figu re 17. Ou t pu t Tim i ng
C
Q
AI01449D
S
LSB OUT
D
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
33/40
M95160, M95080
P ACKAGE MECHANI CAL
Figure 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead fram e, Packag e Outline
No te : Drawi ng is not to scal e.
Table 24. PDIP8 – 8 pin Plastic DIP, 0.25mm l ead frame, Package M ech anical Data
Symb. mm inches
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e2.54––0.100––
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
M95160, M95080
34/40
Figure 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width , Packag e Outline
No te : Drawi ng is not to scal e.
Table 25. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
ddd 0.10 0.004
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N8 8
SO-A
E
8
ddd
Be
A
D
C
LA1 α
1
H
h x 45˚
A2
35/40
M95160, M95080
Figure 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
Note : 1. Dra wing is not to scale .
2. T he centr al pad (the area E2 b y D2 in th e above illustra tion) is pul l ed, internal l y, to VSS. I t must not be al lo wed to be c onnect ed to
any ot her vol t age or si gnal line on the PCB, f or exampl e during the solderi ng process.
Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3m m², Data
Symbol mm inches
Typ. Min. Max. Typ. Min. Max.
A 0.55 0.50 0.60 0.022 0.020 0.024
A1 0.00 0.05 0.000 0.002
b 0.25 0.20 0.30 0.010 0.008 0.012
D 2.00 0.079
D2 1.55 1.65 0.061 0.065
ddd 0.05 0.002
E 3.00 0.118
E2 0.15 0.25 0.006 0.010
e 0.50 – – 0.020 – –
L 0.45 0.40 0.50 0.018 0.016 0.020
L1 0.15 0.006
L3 0.30 0.012
N8 8
D
E
UFDFPN-01
A
A1 ddd
L1
eb
D2
L
E2
L3
M95160, M95080
36/40
Figure 21. TSS OP8 – 8 lead Thin Shrink S mall Outline, Packa ge Ou tline
No te : Drawi ng is not to scal e.
Table 27. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechan ical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
N8 8
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
37/40
M95160, M95080
Figure 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
No te : Drawi ng is not to scal e.
Table 28. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α0° 6° 0° 6°
N8 8
TSSOP8BM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M95160, M95080
38/40
PART NUMBERING
Table 29. Ordering Information Scheme
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotiv e environment. The High Reliability Cer-
tified F l ow (HRCF) is described i n the quality note QNEE9801. Please ask your nearest ST sales of fice fo r a copy.
2. T SSOP8, 1 69 m i l width, package is not available for t he M 95160 id entified by the pr ocess identific at i on letter L.
3. T SSOP8, 3 x3mm body si ze, package is ava i l abl e for the M95080 ser i es only.
4. Used only f or Device Grade 3
For a list of available options (speed, package,
etc.) or for further i nf ormation on any aspect of this device, please contact y our nearest ST Sales O f-
fice.
Table 30. How to Identify Present a nd Previous Products by the Process Identification Letter
Note: 1. T hi s exampl e comes from the S08 pac kage. Other packages ha ve simil ar i nformation. For further informati on, please ask your ST
Sales Office for Process Change Notice PC N M P G/EE/0 034 (PCE E 0034).
Example: M95160 – W MN 6 T P /W
Device Type
M95 = SPI serial access EEPROM
Device Function
160 = 16 Kbit (2048 x 8)
080 = 8 Kbit (1024 x 8)
Operating Voltage
blank = VCC = 4.5 to 5.5V
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW2 = TSSOP8
DS3 = TSSOP8 (3x3mm body size, MSOP)
MB = MLP8 (UFDFPN8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow1.
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Process4
blank = F6SP20%
/W = F6SP36%
Markings on Present Products1Markings on Pr evious Products 1
95160W6
AYWWW (or AYWWG)95160W6
AYWWL
39/40
M95160, M95080
REVISION HISTORY
Table 31. Document Revi sion History
Date Rev. Description of Revision
19-Jul-2001 1.0 Document written from previous M95640/320/160/080 datasheet
06-Feb-2002 1.1 Announcement made of planned upgrade to 10MHz clock for the 5V, –40 to 85°C, range
18-Oct-2002 1.2 TSSOP8 (3x3mm body size, MSOP8) package added
04-Nov-2002 1.3 New products, identified by the process letter W, added
13-Nov-2002 1.4 Correction to footnote in Ordering Information table
21-Nov-2003 2.0 Table of contents, and Pb-free options added. VIL(min) improved to –0.45V
08-Jun-2004 3.0
MLP8 package added. Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices. Device Grade 3
clarified, with reference to HRCF and automotive environments. Process identification letter
“G” information added. SO8 narrow and TSSOP8 Package mechanical specifications updated.
07-Oct-2004 4.0 Product List summary table added. AEC-Q100-002 compliance. tHHQX corrected to tHHQV.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified
M95160, M95080
40/40
Information furnished is believed to b e accurate and reliable. However, S TMicroelectronics assumes no re sponsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication ar e s ub j ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMi croelectronics product s are not
authorized for us e as critical com ponents in lif e support devices or sy stems without express written approval of STMicroel ectro nics.
The ST l ogo is a registered tra dem ark of STM icroel ectronic s.
All other names are th e property of their respective o wners
© 200 4 STMicr oel ectro ni cs - All ri ghts reserved
STM i croelectron ics group of compan i es
Aus tralia - B el gium - Brazil - Canada - China - Czech Rep ubl i c - Finland - Fra nce - Germ any - Hong Kong - I ndia - Israel - Italy - Japan -
Malaysia - M a l t a - Moroc co - Sing apore - Sp ai n - Sweden - Swit zerlan d - United Kingd om - United States of Americ a
www.st.com
