M500IT mSATA NAND Flash SLC SSD
MTFDDAT032SBD, MTFDDAT064SBD, MTFDDAT128SBD
Features
Micron® 20nm NAND Flash
RoHS-compliant package
SATA 6 Gb/s interface
TCG/Opal 2.0-compliant self-encrypting drive
(SED)
Hardware-based AES-256 encryption engine
ATA modes supported
PIO mode 3, 4
Multiword DMA mode 0, 1, 2
Ultra DMA mode 0, 1, 2, 3, 4, 5, 6
Industry-standard, 512-byte sector size support
Device sleep (DEVSLP), extreme low-power mode
Native command queuing support with 32-com-
mand slot support
ATA-8 ACS3 command set compliant
ATA security feature command set and password
login support
Secure erase (data page) command set: fast and se-
cure erase
Sanitize device feature set support
Self-monitoring, analysis, and reporting technology
(SMART) command set
Adaptive thermal monitoring
Power loss protection for data-at-rest
Performance1, 2
Sequential 128KB READ: Up to 500 MB/s
Sequential 128KB WRITE: Up to 400 MB/s
Random 4KB READ: Up to 75,000 IOPS
Random 4KB WRITE: Up to 60,000 IOPS
READ/WRITE latency: 160µs/40µs (TYP)
Reliability
MTTF: 3.0 million device hours3
Static and dynamic wear leveling
Uncorrectable bit error rate (UBER): <1 sector
per 1016 bits read
Low power consumption
150mW TYP4
Endurance: Total bytes written (TBW)
Up to 1600TB
Capacity (unformatted): 32GB, 64GB, 128GB
mSATA form factor
Secure firmware update with digitally signed firm-
ware image
Operating temperature
Extended range (–40°C to +85°C)5
Notes: 1. Typical I/O performance numbers as meas-
ured fresh-out-of-the-box (FOB) using Iome-
ter with a queue depth of 32 and write
cache enabled.
2. 4KB transfers used for READ/WRITE latency
values.
3. The product achieves a mean time to failure
(MTTF) based on population statistics not
relevant to individual units.
4. Active average power measured during exe-
cution of MobileMark® with DIPM (device-
initiated power management) enabled.
5. Temperature measured by SMART attribute
194.
Warranty: Contact your Micron sales representative
for further information regarding the product,
including product warranties.
M500IT mSATA NAND Flash SLC SSD
Features
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Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Micron’s M500IT SSD is available in different configurations and densities. The chart below is a comprehensive list
of options for the M500IT series devices; not all options listed can be combined to define an offered product. Visit
www.micron.com for a list of valid part numbers.
Figure 1: Part Number Chart
MT FD D AK 060 S BD - 1 AH 1 ES
Micron Technology
Product Family
FD = Flash drive
Drive Interface
D = SATA 6.0 Gb/s
Drive Form Factor
AK = 2.5-inch (7mm)
AT = mSATA
Drive Density
032 = 32GB
NAND Flash Type
M = MLC
S = SLC
Product Family
BD = M500IT
Production Status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
Customer Designator
YY = Standard hardware
Additional Feature Set
IT = Industrial temperature and grade
Extended Firmware Features
Z = Standard
2 = SED (self-encrypting drive)
Sector Size
1 = 512-byte
NAND Flash Component
AH = 64Gb, x8, 3.3V (20nm)
AK = 128Gb, x8, 3.3V (20nm)
BOM Revision
For example:
A = ES
1 = 1st generation
2 = 2nd generation
2 IT YY
060 = 60GB
128 = 128GB
240 = 240GB
064 = 64GB
120 = 120GB
256 = 256GB
Table 1: Part Ordering Information
Capacity (GB) Valid part number Availability
32 MTFDDAT032SBD-1AH12ITYY 1st generation
64 MTFDDAT064SBD-1AK12ITYY 1st generation
128 MTFDDAT128SBD-1AK12ITYY 1st generation
32 MTFDDAT032SBD-AAH12ITYYES ES
64 MTFDDAT064SBD-AAK12ITYYES ES
128 MTFDDAT128SBD-AAK12ITYYES ES
M500IT mSATA NAND Flash SLC SSD
Features
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General Description
Micron’s solid state drive (SSD) uses a single-chip controller with a SATA interface on
the system side and eight channels of Micron NAND Flash internally. Packaged in an
HDD replacement enclosure, the SSD integrates easily in existing storage infrastruc-
tures.
The SSD is designed to use the SATA interface efficiently during both READs and
WRITEs while delivering bandwidth-focused performance. SSD technology enables en-
hanced boot times, faster application load times, reduced power consumption, and ex-
tended reliability.
The self-encrypting drive (SED) features a FIPS-compliant, AES-256 encryption engine,
providing hardware-based, secure data encryption, with no loss of SSD performance.
This SED follows the TCG/Opal specification for trusted peripherals.
When TCG/Opal features are not enabled, the device can perform alternate data en-
cryption by invoking the ATA security command set encryption features, to provide full-
disk encryption (FDE) managed in the host system BIOS. TCG/Opal and ATA security
feature sets cannot be enabled simultaneously.
The data encryption is always running; however, encryption keys are not managed and
the data is not secure until either TCG/Opal or ATA security feature sets are enabled.
Figure 2: Functional Block Diagram
NAND
SATA
NAND
NAND
NAND
SSD
controller
DRAM
buffer
NAND
M500IT mSATA NAND Flash SLC SSD
General Description
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Logical Block Address Configuration
The drive is set to report the number of logical block addresses (LBA) that will ensure
sufficient storage space for the specified capacity. Standard LBA settings, based on the
IDEMA standard (LBA1-03), are shown below.
Table 2: Standard LBA Settings
Capacity (GB)
Total LBA Max LBA
User Available
Bytes
Decimal Hexadecimal Decimal Hexadecimal (Unformatted)
32 62,533,296 3BA2EEB0 62,533,295 3BA2EAF 32,017,047,552
64 125,045,424 7740AB0 125,045,423 7740AAF 64,023,257,088
128 250,069,680 EE7C2B0 250,069,679 EE7C2AF 128,035,676,160
M500IT mSATA NAND Flash SLC SSD
Logical Block Address Configuration
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Physical Configuration
Product mass: 10 grams MAX
Physical dimensions conform to the applicable form factor specifications as listed in
the figure below.
Figure 3: mSATA Package
Primary side
Secondary side
P1
P15
P17
P51
P2
P18
P52
P16
A MAX
C MAX
L ±0.15
W ±0.15
B ±0.10
(2X 2.60 DIA)
(2X 2.75)
(24.20)
(5.80)
(Both sides)
(5.80)
(Both sides)
(5.80)
(Both sides)
Note: 1. All dimensions are in millimeters.
M500IT mSATA NAND Flash SLC SSD
Physical Configuration
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Table 3: mSATA Package Dimensions
Density (GB) W L A B C Unit
32 29.85 50.80 2.40 1.00 1.35 mm
64
128
Note: 1. Dimension values in millimeter per SERIAL ATA Rev. 3.2.
Interface Connectors
Figure 4: SSD Interface Connections
P1
P15
Primary side Secondary side
P17 P51 P52 P18
P16
P2
Table 4: Signal Assignments
Primary Side Secondary Side
Pin # Signal Name Description Pin # Signal Name Description
1 Reserved No connect 2 3V3 +3.3V
3 Reserved No connect 4 GND Ground
5 Reserved No connect 6 1V5 No connect
7 Reserved No connect 8 Reserved No connect
9 GND Ground 10 Reserved No connect
11 Reserved No connect 12 Reserved No connect
13 Reserved No connect 14 Reserved No connect
15 GND Ground 16 Reserved No connect
17 Reserved No connect 18 GND Ground
19 Reserved No connect 20 Reserved No connect
21 GND Ground 22 Reserved No connect
23 +B Differential signal pair +B
and -B
24 3V3 +3.3V
25 -B 26 GND Ground
27 GND Ground 28 1V5 No connect
29 GND Ground 30 TWI Two-wire interface
31 -A Differential signal pair +A
and -A
32 TWI
33 +A 34 GND Ground
35 GND Ground 36 Reserved No connect
M500IT mSATA NAND Flash SLC SSD
Interface Connectors
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Table 4: Signal Assignments (Continued)
Primary Side Secondary Side
Pin # Signal Name Description Pin # Signal Name Description
37 GND Ground 38 Reserved No connect
39 3V3 +3.3V 40 GND Ground
41 3V3 +3.3V 42 Reserved No connect
43 NC No connect 44 DEVSLP Device sleep
45 Optional No connect 46 Reserved No connect
47 Optional No connect 48 1V5 No connect
49 DA/DSS Drive activity LED 50 GND Ground
51 Presence Presence detection 52 3V3 +3.3V
M500IT mSATA NAND Flash SLC SSD
Interface Connectors
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Performance
Measured performance can vary for a number of reasons. The major factors affecting
drive performance are the capacity of the drive and the interface of the host. Addition-
ally, overall system performance can affect the measured drive performance. When
comparing drives, it is recommended that all system variables are the same, and only
the drive being tested varies.
Performance numbers will vary depending on the host system configuration.
For SSDs designed for the industrial market, Micron specifies performance in fresh-out-
of-box (FOB) state. Data throughput measured in "steady state" may be lower than FOB
state, depending on the nature of the data workload.
For a description of these performance states and of Micron's best practices for per-
formance measurement, refer to Micron's technical marketing brief "Best Practices for
SSD Performance Measurement"
(www.micron.com/products/solid-state-storage/).
Table 5: Drive Performance
Capacity 32GB 64GB 128GB
UnitInterface Speed 6 Gb/s 6 Gb/s 6 Gb/s
Sequential read (128KB transfer) 500 500 500 MB/s
Sequential write (128KB transfer) 350 350 400 MB/s
Random read (4KB transfer) 65,000 65,000 75,000 IOPS
Random write (4KB transfer) 60,000 60,000 60,000 IOPS
READ latency (TYP) 160 160 160 µs
WRITE latency (TYP) 40 40 40 µs
Notes: 1. Performance numbers are maximum values, except as noted.
2. Typical I/O performance numbers as measured using Iometer with a queue depth of 32
and write cache enabled. Fresh-out-of-box (FOB) state is assumed. For performance
measurement purposes, the SSD may be restored to FOB state using the SECURE ERASE
command.
3. Iometer measurements are performed on an 20GB span of logical block addresses
(LBAs).
4. 4KB transfers with a queue depth of 1 are used to measure READ/WRITE latency values
with write cache enabled.
M500IT mSATA NAND Flash SLC SSD
Performance
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Reliability
Micron’s SSDs incorporate advanced technology for defect and error management.
They use various combinations of hardware-based error correction algorithms and
firmware-based static and dynamic wear-leveling algorithms.
Over the life of the SSD, uncorrectable errors may occur. An uncorrectable error is de-
fined as data that is reported as successfully programmed to the SSD but when it is read
out of the SSD, the data differs from what was programmed.
Table 6: Uncorrectable Bit Error Rate
Uncorrectable Bit Error Rate Operation
<1 sector per 1016 bits read READ
Mean Time To Failure
Mean time to failure (MTTF) for the SSD can be predicted based on the component reli-
ability data using the methods referenced in the Telcordia SR-332 reliability prediction
procedures for electronic equipment.
Table 7: MTTF
Capacity (GB) MTTF (Operating Hours)1
32 3.0 million
64 3.0 million
128 3.0 million
Note: 1. The product achieves a mean time to failure (MTTF) of 3.0 million hours, based on popu-
lation statistics not relevant to individual units.
Endurance
Endurance for the SSD can be predicted based on the usage conditions applied to the
device, the internal NAND component cycles, the write amplification factor, and the
wear-leveling efficiency of the drive. For each SSD capacity, the table below shows drive
lifetime and sequential input based on predefined usage conditions.
Table 8: Drive Lifetime
Capacity (GB) Drive Lifetime (Total Bytes Written)
32 400TB
64 800TB
128 1600TB
Notes: 1. Total bytes written validated with the drive 90% full.
2. Access patterns used during reliability testing are 25% sequential and 75% random and
consist of the following: 50% are 4KB; 40% are 64KB; and 10% are 128KB.
3. Host workload parameters, including write cache settings, I/O alignment, transfer sizes,
randomness, and percent full, that are substantially different than the described notes
may result in varied endurance results.
M500IT mSATA NAND Flash SLC SSD
Reliability
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4. GB/day can be calculated by dividing the total bytes written value by (365 × number of
years). For example: 100TB/5 years/365 days = 54GB/day for 5 years.
M500IT mSATA NAND Flash SLC SSD
Reliability
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Electrical Characteristics
Environmental conditions beyond those listed may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Table 9: SATA Power Consumption
Capacity (GB)
Device Sleep
Typical Idle Average Active Average
Active Maximum
(128KB transfer) Unit
32 10 100 150 2300 mW
64 10 100 150 2400 mW
128 10 100 150 3600 mW
Notes: 1. Data taken at 25°C using a 6 Gb/s SATA interface.
2. Active average power measured while running MobileMark productivity suite.
3. DIPM (device-initiated power management) enabled. DIPM slumber supported.
4. Active maximum power is an average power measurement performed using Iometer
with 128KB sequential write transfers.
Table 10: Maximum Ratings
Parameter/Condition Symbol Min Max Unit Notes
Voltage input 3V3 3.14 3.46 V
Operating temperature TC–40 85 °C 1
Non-operating temperature –40 85 °C
Rate of temperature change 20 °C/hour
Relative humidity (non-condensing) 5 95 %
Note: 1. Operating temperature is best measured by reading the SSD's on-board temperature
sensor, which is recorded in SMART attribute 194 (or 0xC2).
Table 11: Shock and Vibration
Parameter/Condition Specification
Non-operating shock 1500G/0.5ms (10x shocks per axis)
Non-operating vibration 7 – 2000Hz @ 20 Grms (30 minutes per axis)
Note: 1. Stress qualification tests are not intended for operational or continuous use. Exposure
to these conditions may affect reliability.
M500IT mSATA NAND Flash SLC SSD
Electrical Characteristics
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Adaptive Thermal Monitoring
The device features adaptive thermal monitoring. While most host computers exhibit
operating environments that keep an SSD running in the range of 40°C to 45°C, adap-
tive thermal monitoring enables the SSD device to operate in a wide variety of environ-
ments by helping to prevent the host computer from running at excessive temperatures.
Adaptive thermal monitoring reduces total SSD power consumption by the device con-
troller, as well as the NAND media, by injecting time-based delays between internal
processing of media commands when the device temperature reaches 85 °C. The delay
times used are bound to the millisecond range, and are based on a proportional and dif-
ferential control equation of the general form shown here.
Figure 5: Adaptive Thermal Monitoring Control Equation
u(t) = Kp × Tp(t) + Kd × dTd
dt
The delay-control equation is tuned for a steady-state temperature target, which has
been designed as an optimum balance of hardware temperature tolerances and drive
performance. Steady-state temperature targets are hardware-configuration dependant,
and may range from 85 °C to 95 °C. Temperatures below the intended steady-state target
will not produce a proportional component to delay, but may produce a differential
component based on the current rate of temperature change according to the control
equation. When the feature is active, DRAM refresh rates are also adjusted to improve
data integrity and stability while operating outside of temperature specifications.
When the device temperature falls below 95 °C, normal operation will continue without
induced delays. If temperature continues to rise above the temperature target and ex-
ceeds a hardware-dependant critical threshold, the device will abort all commands at
101C or higher.
Device temperature values used by the adaptive thermal monitoring feature are based
on an internal temperature sensor located on the device PCB, and may differ from case
or package temperatures as measured by thermistor. Device temperature is accessible
through SMART attribute 194, though usage of the SMART feature is not necessary for
adaptive thermal monitoring functionality.
Adaptive thermal monitoring does not change the current negotiated speed of the SATA
bus, nor require or cause any new commands to be issued on the SATA bus. Rated-
throughput performance is not guaranteed at any point above the maximum specified
operating temperature.
M500IT mSATA NAND Flash SLC SSD
Adaptive Thermal Monitoring
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TCG/Opal Support
Table 12: TCG/Opal Support Parameters
Property Supported? Comments
TCG Storage Specifications
OPAL: TCG Storage Security SubSystem
Class
Specification 2.00 Revision 1.00, Feb 24, 2012
TCG Core Specification Specification 2.00 Revision 2.00, Nov 4, 2011
TCG Storage Interface Interactions Specifi-
cation
TCG Reference
Specification
Specification Version 1.02 Revision 1.00 30 Decem-
ber, 2011
OPAL SSC 1.00 (backward compatibility) Not supported
OPAL SSC Additional Feature Set Specification
Additional DataStore Table Supported Specification 1.00 Revision 1.00, Feb 24, 2012
Single User Mode Supported Specification 1.00 Revision 1.00, Feb 24, 2012
TCG Storage Protection Mechanisms for
Secrets
Supported Specification Version 1.00 Revision 1.07 17 August,
2011
PSID – Physical Presence SID Supported Specification Version 1.00 Committee Draft Revi-
sion 1.05 February 9, 2011
GUDID (Globally Unique Serial Number) Supported Mandatory GUDID Proposal 11/03/2011 (Microsoft)
SID Authority Disable Supported SID Authority Disable Proposal 9/26/2011 (Micro-
soft)
Modifiable CommonName Columns Supported Modifiable CommonName Columns Proposal
7/22/2010 (Microsoft)
OPAL SSC Feature Set – Specific List
ALL OPAL Mandatory Features Supported
Close Session (optional) Supported Allows Tper to notify the host it has aborted a ses-
sion
Restricted Command & Table (optional) Not Supported The interface control template enables TPer control
over selected interface commands; the benefit is
the reduction of undesired side effects
Type Table (not required) Not Supported
Activate Method Supported
Revert Method Supported
Revert SP Method Supported
Activate Method Within Transactions Not Supported As per OPAL, this behavior is out of the scope
Revert Method within Transactions Not Supported As per OPAL, this behavior is out of the scope
Revert SP Method within Transactions Not Supported As per OPAL, this behavior is out of the scope
Creation/Deletion of Tables/Rows after
Manufacturing
Not Supported As per OPAL, this behavior is out of the scope
Tper Feature
COM ID Management Support Not Supported Dynamic COM ID allocation & management not
supported
Buffer Management Support Not Supported Flow control
M500IT mSATA NAND Flash SLC SSD
TCG/Opal Support
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Table 12: TCG/Opal Support Parameters (Continued)
Property Supported? Comments
ACK/NACK Support Not Supported Session reliability
Async Support Not Supported Asynchronous protocol support with multiple com-
mands per session
Geometry Reporting Feature
ALIGN Supported OPAL 2.0 (only)
Logical Block Size 512 bytes Logical block size = 512 Bytes
Alignment Granularity 4096 Bytes Page or Descriptor size <<Minimum AES LU size>>
Lowest Aligned LBA 0
OPAL SSC V2.00 Feature Descriptor
Base COM ID 0x1000 0x1000-0xFFFF defined for COM ID management
Number of COM IDs 1
Range Crossing Behavior 0 If drive receives a READ or WRITE command that
spans multiple LBA ranges and the LBA ranges are
not locked, then:
1. Process the data transfer, if Range Crossing = 0
2. Terminate the command with “Other Invalid
Command Parameter” if Range Crossing = 1
Number of Locking SP Admin Authorities
Supported
4 As per OPAL 2.0, drive should support at least 4 ad-
min
Number of Locking SP User Authorities
Supported
9 As per OPAL 2.0, drive should support at least 8
users
Initial C_PIN_SID PIN Indicator 0x00 0x00 = The initial C_PIN_SID PIN value is equal to
the C_PIN_MSID PIN value
0xFF = The initial C_PIN_SID PIN value is VU, and
MAY not be equal to the C_PIN_MSID PIN value
OPAL 2.0 (only)
Customer-specific SID – Configurable
Behavior of C_PIN_SID PIN upon Ter Revert 0x00 0x00 = The C_PIN_SID PIN value becomes the value
of the C_PIN_MSID PIN column after successful in-
vocation of revert on the admin SP’s object in the
SP table
0xFF = The C_PIN_SID PIN value changes to a VU
value after successful invocation of revert on the
admin SP’s object in the SP table and MAY not be
equal to the C_PIN_MSID PIN value OPAL 2.0 (only)
DataStore Table Feature
Maximum number of DataStore Tables 9 The maximum number of the DataStore tables that
the TPer supports, including the DataStore table
defined in OPAL SSC 2.0
Maximum total size of DataStore Tables 90MB Specifies the maximum total size in bytes of all of
the DataStore tables that TPer supports, including
the DataStore table defined in OPAL SSC 2.0
MBR Table 128MB
M500IT mSATA NAND Flash SLC SSD
TCG/Opal Support
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Table 12: TCG/Opal Support Parameters (Continued)
Property Supported? Comments
Byte Table Access Granularity
Mandatory Write Granularity 1 TPer enforces when the host invokes the set meth-
od on byte tables; it should be less than or equal to
8192; it should be less than or equal to Recommen-
ded Access Granularity, OPAL 2.0 (only)
Recommended Access Granularity 8192 Tper recommends when the host invokes the set or
get method on byte tables; it should be less than or
equal to 8192
Cryptographic Features
AES Key Size 256 Bits AES key is generated by using CTR DRBG algorithm
(FIPS Compliant)
AES Mode CBC IV swapped
Number of Ranges/Band Supported 16
(15 user definable,
1 global range)
Now supporting 15 LBA ranges; range cross read
and write allowed if LBA ranges are unlocked
Re-Encryption Not Supported
Key Management Cryptographic
Crypto Erase Completion Time <1s Yes
Cryptographic Algorithms are Certified by
FIPS-197
No Designed to meet, no plans for certification
AES 256-Bit CBC/ECB Mode Supported ECB mode used only for generating the random
key by CTR DRBG
CTR DRBG Supported
SHA 256 Supported
RSA 2048 Signature Verification Supported
TPer Communication Properties
Max ComPacket Size 131072 256 sectors (128K)
Max Response ComPacket Size 131072 256 sectors (128K)
Max Packet Size 128512
Max Individual Token Size 123904
Max Packets 1
Max SubPackets 1
Max Sessions 1 Each session requires a set of buffers and variables
Max Transaction Limit 1 Transaction are inside sessions
Max Methods 1 Methods are contained in a transaction
Max Authentications 14
Def Session Timeout Yes The session timeout length (in milliseconds) used
by the TPer by default
IEEE1667
Probe Silo Supported
M500IT mSATA NAND Flash SLC SSD
TCG/Opal Support
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Table 12: TCG/Opal Support Parameters (Continued)
Property Supported? Comments
TCG Storage Silo Supported
Other than Probe and TCG Storage Silo Not Supported
IEEE1667 Major Version TBD As per current draft specification, major and minor
versions are not yet decided
IEEE1667 Minor Version TBD
Maximum P_OUT Transfer Size 131072 256 sectors (128K)
Others
FDE (ATA Security with Key Management) Yes
Secure Firmware Download Supported Firmware image is validated by using SHA256 and
RSA2048 algorithm
M500IT mSATA NAND Flash SLC SSD
TCG/Opal Support
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Device ID
Table 13: Identify Device
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
0 General configuration bit-significant information
15 F 0b 0 = ATA device
14–8 X 0000100b Retired
7 F 0b 1 = Removable media device
6 X 1b 1 = Not removable device
5–3 X 000b Retired
2 V 0b Response incomplete
1 X 0b Retired
0 F 0b Reserved
1 3FFFh Obsolete
2 F C837h Specific configuration
3 F 0010h Obsolete
4 F 0000h 0000h Retired
6 F 003Fh Obsolete
7 (O)V 0000h 0000h Reserved for assignment by the CompactFlash™ Association
9 ( )X 0000h Retired
10 (M)F varies Serial number (20 ASCII characters)
20 ( )X 0000h 0000h
0000h
Retired/Obsolete
23 (M)F varies Firmware revision (8 ASCII characters)
27 (M)F varies Model number (40 ASCII characters)
47 15–8 F 80h 80h
7–0 F 10h 00h = Reserved
01h-FFh = Maximum number of logical sectors that shall be
transferred per DRQ data block on READ/WRITE MULTIPLE
commands
48 Trusted Computing feature set options
15 F 0b Shall be cleared to zero
14 F 1b Shall be set to one
13–1 F 0000000000000b Reserved for the Trusted Computing Group
0 F 1b 1=Trusted Computing feature set is support
M500IT mSATA NAND Flash SLC SSD
Device ID
CCMTD-731836775-10446
m500it_mSATA_industrial_ssd.pdf - Rev. B 5/17 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 13: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
49 Capabilities
15–14 F 00b Reserved for the IDENTIFY PACKET DEVICE command.
13 F 1b 1 = Standby timer values as specified in this standard are
supported
0 = Standby timer values shall be managed by the device
12 F 0b Reserved for the IDENTIFY PACKET DEVICE command.
11 F 1b 1= IORDY supported
0 = IORDY may be supported
10 F 1b 1 = IORDY may be disabled
9 1b 1 = LBA supported
8 F 1b 1 = DMA supported.
7–0 F 00000000b Retired
50 Capabilities
15 F 0b Shall be cleared to zero
14 F 1b Shall be set to one
13–2 F 000000000000b Reserved
1 X 0b Obsolete
0 F 1b Shall be set to one to indicate a vendor specific standby tim-
er value minimum.
51 ( )X 0000h 0000h Obsolete
53 15–3 F 0000000000000b Reserved
2 F 1b 1 = The fields reported in word 88 are valid
0 = the fields reported in word 88 are not valid
1 F 1b 1 = The fields reported in words (70:64) are valid
0 = the fields reported in words (70:64) are not valid
0 X 1b Obsolete
54 ()X 3FFFh 0010h
003Fh FC10h
00FBh
Obsolete
59 15 F 1b 1 = The BLOCK ERASE EXT command is supported
14 F 0b 1 = The OVERWRITE EXT command is supported
13 F 1b 1 = The CRYPTO SCRAMBLE EXT command is supported
12 F 1b 1 = The Sanitize feature set is supported
11–9 F 000b Reserved
8 V 1b 1 = Multiple sector setting is valid
7–0 V 00010000b xxh = Current setting for number of logical sectors that shall
be transferred per DRQ data block on READ/WRITE MULTI-
PLE commands
60–61 M(F) Varies by capacity Total number of user addressable logical sectors
M500IT mSATA NAND Flash SLC SSD
Device ID
CCMTD-731836775-10446
m500it_mSATA_industrial_ssd.pdf - Rev. B 5/17 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 13: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
62 ()X 0000h Obsolete
63 15–11 F 00000b Reserved
10 V 0b 1 = Multiword DMA mode 2 is selected
0 = Multiword DMA mode 2 is not selected
9 V 0b 1 = Multiword DMA mode 1 is selected
0 = Multiword DMA mode 1 is not selected
8 V 0b 1 = Multiword DMA mode 0 is selected
0 = Multiword DMA mode 0 is not selected
7–3 F 0000b Reserved
2 F 1b 1 = Multiword DMA mode 2 and below are supported
1 F 1b 1 = Multiword DMA mode 1 and below are supported
0 F 1b 1 = Multiword DMA mode 0 is supported
64 15–8 F 0 Reserved
7–0 F 00000011b PIO modes supported
65 F 0078h Minimum Multiword DMA transfer cycle time per word
Cycle time in nanoseconds
66 F 0078h Manufacturer's recommended Multiword DMA transfer cy-
cle time
Cycle time in nanoseconds
67 F 0078h Minimum PIO transfer cycle time without flow control
Cycle time in nanoseconds
68 F 0078h Minimum PIO transfer cycle time with IORDY flow control
Cycle time in nanoseconds
M500IT mSATA NAND Flash SLC SSD
Device ID
CCMTD-731836775-10446
m500it_mSATA_industrial_ssd.pdf - Rev. B 5/17 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 13: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
69 F Additional Supported
15 F 0b 1 = CFast Specification Support
14 F 1b 1 = Deterministic read after Trim is supported
13 F 0b 1 = Long Physical Sector Alignment Error Reporting Control
is supported
12 F 0b 1 = DEVICE CONFIGURATION IDENTIFY DMA and DEVICE
CONFIGURATION SET DMA are supported
11 F varies 1 = READ BUFFER DMA is supported
10 F varies 1 = WRITE BUFFER DMA is supported
9 F 0b 1 = SET MAX PASSWORD DMA and SET MAX UNLOCK DMA
are supported
8 F varies 1 = DOWNLOAD MICROCODE DMA is supported
7 F 1b Reserved for IEEE-1667
6 F 0b 1 = Optional ATA device 28-bit commands supported
5 F 1b 1 = Read zero after Trim is supported
4 F varies 1 = Device encrypts all user data
3 F 1b 1 = Extended number of user addressable sectors is suppor-
ted
2–0 F 000b Reserved
70 F 0000h Reserved
71 F 0000h 0000h
0000h 0000h
Reserved for the IDENTIFY PACKET DEVICE command
75 Queue depth
15–5 F 00000000000b Reserved
4–0 F 11111b Maximum queue depth - 1
M500IT mSATA NAND Flash SLC SSD
Device ID
CCMTD-731836775-10446
m500it_mSATA_industrial_ssd.pdf - Rev. B 5/17 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Table 13: Identify Device (Continued)
See Note 1 for setting definitions
Word Bit(s) Setting Default Value Description
76 Serial ATA capabilities
15 F 1b 1 = Supports READ LOG DMA EXT as equivalent to READ
LOG EXT
14 F 0b 1 = Supports device automatic partial to slumber transitions
13 F 0b 1 = Supports host automatic partial to slumber transitions
12 F 1b Supports Native Command Queuing priority information
11 F 0b Supports Unload while NCQ commands outstanding
10 F 1b Supports Phy event counters
9 F 0b Supports receipt of host initiated interface power manage-
ment requests
8 F 1b Supports native Command Queueing
7–4 F 0000b Reserved for future Serial ATA signaling speed grades
3 F 1b 1 = Supports Serial ATA Gen-3 speed (6.0 Gb/s)
2 F 1b 1 = Supports Serial ATA Gen-2 speed (3.0 Gb/s)
1 F 1b 1 = Supports Serial ATA Gen-1 speed (1.5 Gb/s)
0 F 0b Reserved (set to 0)
77 Serial ATA additional capabilities
15–8 F 00000000b Reserved for future Serial ATA definition
7 F 1b 1 = Supports DEVSLP_to_ReducedPwrState
6 F 1b Supports RECEIVE FPDMA QUEUED and SEND FPDMA
QUEUED commands
5 F 0b Supports NCQ Queue Management Command
4 F 0b Supports NCQ Streaming
3–1 V varies Coded value indicating current negotiated Serial ATA signal
speed
0 F 0b Shall be cleared to zero
78 Serial ATA features supported
15–9 F 0000000b Reserved
8 F 1b 1 = Device sleep supported
7 F 0b 1 = Supports NCQ Autosense
6 F 1b 1 = Supports software settings preservation
5 F 1b 1 = HARDWARE FEATURE CONTROL SUPPORTED bit
4 F 0b 1 = Supports in-order data delivery
3 F 1b 1 = Supports dev initiate interface power management
2 F 1b 1 = Supports DMA Setup Auto-Activate optimization
1 F 0b 1 = Supports non-zero buffer offsets in DMA Setup FIS
0 F 0b Reserved (set to 0)
M500IT mSATA NAND Flash SLC SSD
Device ID
CCMTD-731836775-10446
m500it_mSATA_industrial_ssd.pdf - Rev. B 5/17 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.