Rev.4.00 Jun 15, 2005 page 1 of 39
HA16107P/FP, HA16108P/FP
PWM Switching Regulator for
High-performance Voltage Mode Control REJ03F0141-0400
(Previous: ADE-204-0 12C)
Rev.4.00
Jun 15, 2005
Description
The IC products in this series are primary control switching regulator control IC’s appropriate for obtaining stabilized
DC voltages from commercial AC power.
These IC’s can directly drive power MOS FET’s, they have a timer function built in to the secondary overcurrent
protection, and they ca n per for m intermittent op eration or d ela yed latched shutd o wn as protection op erations in unusual
conditions. They ca n be used to implement switchin g power supp lies with a high level of safe ty due to the wide range
of built-in functionality.
Functions
• 6.45 V reference voltage
• Tr ia ngle wave ge ner a to r
• Error amplifier
• Under voltage lockout protector
• PWM comparator
• Pulse-by-pulse current limitting
• Timer-latch current limitting (HA16107)
• ON/OFF timer function (HA16108)
• Soft start and quick shutdown
• Output circuit for power MOS FET driving
Features
• Operating frequencies up to a high 600 kHz
• Built-in pre-driver circuit for driving power MOS FET
• Built-in timer latch over-current protection function (HA16107)
• The OCL enables intermittent operation by an ON/OFF timer for prevention of secondary overcurrent. (HA16108)
• The UVL function (under voltage lockout) is applied to b o th Vin and Vref.
• ON/OFF reset: an auto-rese t function which is based on the time constant of an external capacito r and observation
of drops in Vin.
• Since the over-voltage protection function OVP (the TL pin) only observes voltage drops in Vin, it is possible to use
the OVP and ON/OFF pin for independent purposes.
• Built-in 34 V Zener diode between Vin and ground.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 2 of 39
Ordering Information
Typical Threshold Voltage
Product UVL1 OVP Notes Package Code
(Previous Code)
HA16107P DP-16
HA16107FP Hi: 16.2 V
Lo: 9.5 V 7.0 V Timer latch protection PRSP0016DH-A
(FP-16DA)
HA16108P DP-16
HA16108FP Hi: 16.2 V
Lo: 9.5 V Hi: 7.0 V
Lo: 1.3 V On-off timer
protection PRSP0016DH-A
(FP-16DA)
Pin Arrangement
V
IN
OUT
CL(+)
V
E
CL(−)
R
T1
C
T
R
T2
TL, ON/OFF
E/O
IN(−)
NC
GND
IN(+)
ST
Vref
(Top view)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Note 1
Note 2
Notes: 1.
2.
In the SOP package models (HA16107FP and HA16108FP) pins 4, 5, and 13 are connected
inside the IC. However, all must be connected to the system ground.
Pin 16 is TL (HA16107), ON/OFF (HA16108).
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 3 of 39
Pin Functions
• HA16107P, HA16108P
Pin No. Symbol Pin Functions
1 VIN Input voltage
2 OUT Pulse output
3 CL (+) Current limiter
4 VE Output ground
5 CL (–) Current limiter
6 RT1 Timing resistor (rising time)
7 CT Timing capacitor
8 RT2 Timing resistor (falling time)
9 Vref Reference voltage output
10 ST Soft start
11 IN (+) Error amp (+) input
12 GND Ground
13 NC NC
14 IN (–) Error amp (–) input
15 E/O Error output
16 TL, ON/OFF Timer latch (HA16107), ON/OFF (HA16108)
• HA16107FP, HA16108FP
Pin No. Symbol Pin Functions
1 VIN Input voltage
2 OUT Pulse output
3 CL (+) Current limiter
4 GND Ground
5 GND Ground
6 RT1 Timing resistor (rising time)
7 CT Timing capacitor
8 RT2 Timing resistor (falling time)
9 Vref Reference voltage output
10 ST Soft start
11 IN (+) Error amp (+) input
12 GND Ground
13 GND Ground
14 IN (–) Error amp (–) input
15 E/O Error output
16 TL, ON/OFF Timer latch (HA16107), ON/OFF (HA16108)
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 4 of 39
Block Diagram
6.45 V
zener type
Ref.
voltage
Gen.
UVL1
H
LVL VH
R
SQ
TL
16
E/O
15
IN (−)
14
NC
13
GND
12
IN (+)
11
ST
10
Vref
9
1
VIN
2
OUT
3
CL (+)
4
VE
5
CL (−)
6
RT1
7
CT
8
RT2
16 µA
4µAOn/Off latch
(VTH = 7 V)
O
V
P
UVL2
H
L4 V 5 V
UVL1
ST
Triangle waveform
UVL1 and UVL2
Pulse-by-pulse latch
Q
Q
R
S
OUT VE
VC
QCLM
++−PWM Comparator
Current
limiter
Triangle waveform OSC
Triangle waveform
Latch reset pulse
ON duty pulse
3.4 V 10 µA
34 V
VIN
UVL2
Vref
Vref
Error amp.
EA +
−
140 µA
6.45 V
zener type
Ref.
voltage
Gen.
UVL1
H
LVL VH
R
SQ
ON/OFF
16
E/O
15
IN (−)
14
NC
13
GND
12
IN (+)
11
ST
10
Vref
9
1
VIN
2
OUT
3
CL (+)
4
VE
5
CL (−)
6
RT1
7
CT
8
RT2
16 µA
4µAOn/Off latch
(VTH = 7 V)
O
V
P
UVL2
H
L4 V 5 V
UVL1
ST
Triangle waveform
UVL1 and UVL2
Pulse-by-pulse latch
Q
Q
R
S
OUT VE
VC
QCLM
++−PWM Comparator
Current
limiter
Triangle waveform OSC
Triangle waveform
Latch reset pulse
ON duty pulse
3.4 V 10 µA
34 VVIN
UVL2
Note: Dotted lines apply to the SOP package model (pins 4, 5, and 13: ground)
Vref
Vref
Error amp.
EA +
−
140 µA
• HA16107P/FP
• HA16108P/FP
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 5 of 39
Function and Timing Chart
Triangle Waveform and PWM Output
V
TH
4.2 V typ Triangle waveform
is output to C
T
pin
E/O
C
T
V
RT2
OUT
0 V
0 V
V
TL
2.2 V typ
Dead band
t
DB
t
ON
I
1
= Vref − 2V
BE
R
T1
C
T
× R
T1
× 2V
Vref − 2V
BE ≈
0.4 × C
T
× R
T1
(s)
I
2
=
9
8
76
2×
2×
2×
I
1
I
1
2I
2
I
2
R
T1
C
T
Vref
(connected internally)
−
+
−
+
Comparator for
triangle waveform
oscillation
0.6 V
The 2s are transistors whose emitter area is doubled.×
t
DB
= R
T2
2R
T1
Du max =
R
T2
2R
T1
− R
T2
t
ON ≈
t
DB
1 − Du max
t
DB
f
OSC ≈
(s) (Hz)
Note: When f
OSC
is high, the actual value will differ from that given by the formula due to the delay time.
Determine the correct constants after constructing a test circuit.
R
T2
V
RT2
2×
• Timing chart (during normal operation)
• Oscillator equivalent circuit
V
IN
2V
BE
Vref − 2V
BE
R
T2
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 6 of 39
1. Timing in Normal Operation
Timing in these ICs is based on a triangular voltage waveform. The rising edge (leading edge) defines the deadband
time tDB. The falling edge (trailing edge) defines the ON-duty control band tON. PWM output is on in the area
within tON t hat is bounded above by the triangle wave VCT and error output VE/O.
The following pin outputs are related to PWM control:
CT (pin 7): triangle-wave voltage output
E/O (pin 15): error output voltage
RT2 (pin 8): ON-duty pulse output voltage
OUT (pin 2): PWM pulse output (for driving the gate of a power MOS FET)
2. Triangle Oscillator, Waveform and Frequency
The triangle oscillator in these ICs ge nerates a triangular waveform by charging and discharging timing capacitor CT
with a constant current, as shown in the equivalent circuit. The CT charge current is:
I(CTchg) = I1 = VREF − 2VBE
RT1
The discharge current is:
I(CTdischg) = 2I2 − I1, where I2 = VREF − 2VBE
RT2
In these equations Vref (reference voltage) is typically 6.45 V, and VBE (base-emitter voltage of internal transistors)
is about 0.7 V.
The deadband time is:
+ 0.25 µs
C
T
× R
T1
× 2V
V
REF
− 2V
BE
t
DB
=
≈ 0.4 × C
T
× R
T1
+ 0.25 µs
The ON-duty time is:
RT2
2RT1 − RT2
tON = tDB ×
The 0.25 µs in these equations is a correction term for internal circuit delays.
The maximum ON-duty is
R
T2
2R
T1
Du max =
The oscillating frequenc y is:
f
OSC
=1
0.4 C
T
R
T1
+ 0.25 µ
1 – R
T2
2R
T1
+ 0.25 µ
=1
0.8 C
T
R
T12
+ 0.25µ × 2R
T1
2R
T1
− R
T2
+ 0.25 µ
(Hz)
When RT1 = RT2, the maximum ON-duty is 50%, and:
1
0.8 C
T
R
T1
+ 0.25 µ × 2 + 0.25 µ
f
OSC
≈
1
0.8 C
T
R
T1
+ 0.75 µ(Hz)=
This appro ximation is fairly clo se, but it sho uld b e checked i n-circuit.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 7 of 39
3. Programming of Maximum ON-Duty (D u Max)
The preceding equations should be used to program the deadband or maximum ON-duty. The following table gives
a summary.
Condition RT1 > RT2 R
T1 = RT2 R
T1 < RT2
Triangle
waveform
Du max Less than 50% 50% Greater than 50%*
Note: In a primary-control switching regulator, Du Max > 50% is dangerous because the transformer will saturate.
Soft Start and Quick Shutdown
One purpose of the soft-start function is to protect the switching controller and power MOS FET from surges at power-
up. A nother purp ose is to let the se condary-side DC voltage rise smoothly.
When power goes off, the quick-shutdown function rapidly discharges the capacitor in the soft-start circuit (and at the
same time switches the P WM output off) to prepare for the next power-on.
The soft-start function in these ICs lets the PWM output develop smoothly from zero to the designated pulse width at
power-up. The soft-start voltage is the 3.8 V voltage value of an inter nal Zener diod e, so the PWM output is able to
start widening gradually a s soon as the soft-start functio n starts operating. The soft-start f unction will start pr omptly
even if CST is lar ge.
The soft-start and quick-shutdown modes are selected automatically in the IC, under control of the UVL signal.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 8 of 39
Level determined by transformer
• T iming waveforms
16.2 V
9.5 V
6.45 V
5 V
4 V
0 V
V
IN
(Time t)
Normal operationSoft start
V
IN
V
ST
V
CT
C
ST
discharge
ST
Quick shutdown
V
E/O
4.2 V
3.8 V
2.2 V
0 V
0 V
V
CT
, V
ST
,
V
E/O
V
OUT
(PWM pulse)
+
+
−
Vref from Vref
from UVL2
(Effective for
quick shutdown)
PWM comparator
V
CT
E/O
15 7
10
9
10 µA
Zener
diode
3.8 V
Vref
C
ST
ST
Note: The soft-start time constant is determined by
C
ST
and the constant-current value (typically 10 µA).
Vref
Vref
V
IN
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 9 of 39
Vref Protection Functions: Overvoltage and Undervoltage
Vref overvoltage and undervoltage conditions are detected by the overvoltage detectio n circuit and UVL2 circuit.
PW M outp ut shuts down wh en Vr ef ≥ 8 V. UVL2 detects undervoltage with hysteresis between approximately 4 V and
5 V. PWM output also shuts down below these voltages. It follows that PWM output will shut off whene ver the Vref
pin is shorted to the power supply (VIN) or ground (GND). PWM output also shuts off when VIN is turned on or off.
The following diagram shows how these protection functions operate when power comes on and goes off (Vref < 6.45
V), and when a high external voltage is applied to the Vref pin (Vref > 6.45 V).
PWM output shut-
down region PWM output
operating region
Power-off,
or shorted
to ground
PWM
OUT
PWM output
shut-down region
Power-up
Shorted to
power supply
0 4 V 5 V 6.45 V 8 V 10 V
UVL2 Vref
OVP
Vref
1. Current-Limiter Circuit
The current limiter pin (CL) is connected to the emitter of an npn transistor, as shown in the block diagram. The
threshold voltage is 240 mV typ. The switching speed of this circuit is approximately 100 ns from detection of
overcurrent to shut-down of PWM output. Switching speed increases with the strength of the signal input to the CL
pin.
Instead of simple pulse-by-pulse current limiting, in these ICs the current limiting circuit is linked to the timer-and-
latch or ON/OFF timer circuit, and also detects the degree of overcurrent. The overcurrent value is determined from
the point at which current limiting is triggered in the ON-duty cycle. With a large overcurrent (causing current
limiting to operate even at a small ON-dut y), the IC automatically shortens the timer ti me.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 10 of 39
Undervoltage Lock out and PWM Output
The undervoltage lockout function turns off the P WM pulse output when the controller’s supply voltage goes belo w a
designated value. These ICs have two undervoltage lockout circuits. The UVL1 circuit senses the supply voltage VIN.
The UVL2 circuit senses the Vref voltage. A feature of these ICs is that PWM output is turned on only when both
voltages are above designated values. Otherwise, the IC operates in standby mode.
The two built-in undervoltage lockout circuits make it possible to configure an extremely safe power supply system.
PWM output will shut down under a variety of abnormal conditions, such as if Vre f is shorted to ground while VIN is
applied.
0 10 V 20 V 30 V 34 V
IIN 9.5 V 16.2 V
*1
0 10 V 20 V 30 V
*2
6.45 V Notes: 1.
2.
Breakdown voltage of
the internal Zener
diode (Vz = 34 V typ).
Hysteresis characteristic.
0 10 V 20 V 30 V
Vref 6.45 V
0 10 V 20 V 30 V
OUT
5 V
4 V
PWM output shut-down region
Operating region
VIN
VIN
VIN
VIN
VIN (UVL1)
Vref (UVL2)
PWM OUT
Standby mode
Note: Double circles indicate standby mode.
L
L
L
H
L
L
H
H
OUT
L
H
L
• UVL1 (VIN and Vref)
• UVL2 (Vref and PWM output)
• UVL1 and UVL2
Vref
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 11 of 39
Timer Latch and ON/OFF Timer
The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function.
The timer-latch function is a n overvoltage protection function that combines latched shutdown of PWM output with a
timer function to vary the time until latched shutdown occurs according to the overcurrent value. A dedicated voltage
detection pin is provided in addition to Vref overvoltage protectio n.
The ON/OFF timer function is eq uivalent to the above ti mer-latch function without the latc h. If overcurrent is detected
continuously, PWM output shuts down temporarily, then normal operation resumes. This process repeats, temporary
shutd o wn alte r na ti ng wi th no r mal op e ra tio n.
Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an interval after
overcurrent detection before shutting down PWM output. The interval is determined by capacitor CTM and the value of
the charge/discharge current supplied internally from the IC. Normal operation therefore continues if a single
overcurrent spike is detected, while if continuous overcurrent is detected, the current and voltage droop curves for the
secondary-side output have sharp characteristics.
1. Use of Timer-Latch Pin (HA16107)
Timer-Latch Usage
See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns on,
charging CTM with 12 µA. PWM output shuts down when the voltage at pin 15 exceeds 7 V.
Overvoltage Protection Usage
See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an OVP
signal received through an optocoupler from the DC output on the secondary side of an AC/DC converter.
PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7 V. The shutdown is
latched. VIN must go below approximately 6.5 V (VINR2) to release the latched state.
CTM
15
16 µA
4 µA
from CML
OVP with
latch timer
HA16107
VIN
OVP signal
(from secondary)
• External circuit 1
TL
VTH Latch
(PWM output shuts down)7.0 V
0 V
VTL
A
B
t
OCL detected continuously
(activating pulse-by-pulse current limiter)
Notes: 1.
2.
3. The latch function is cleared when VIN goes below approximately 7.0 V.
Path A is followed if the OCL input stops before VTH is reached.
Path B is followed if OCL is detected continuously until the latch point is reached.
• External circuit 2
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 12 of 39
2. Use of ON/OFF Timer Pin (HA16108)
External Circuit
16
16 µA
4 µA
from CML
OVP with
latch timer
HA16108
ION
IOFF
+
ON/OFF Ti mer Operation
V
THH
7.0 V
0 V t
1.2 V V
THL
t
OFF
t
ON
OCL detected
(PWM output on) PWM
output
shut down
OCL detected
(PWM output on)
Pulse-by-pulse current limiting
Notes: 1.
2.
3.
4.
t
ON
≈C × 5.8 V
(0.9 − Du) × 16 µA − 4 µA
t
OFF
≈C × 5.8 V
4 µA
C is the capacitance of an external timing capacitor connected between this pin and ground.
Du is the ON-duty of the PWM output when overcurrent limiting is triggered.
The values of t
ON
and t
OFF
for TL can be determined by the same equations as given for
the ON/OFF timer, except that 5.8 V (V
THH
− V
THL
) becomes V
THH
= 7 V.
If the timer goes off during soft start or in the undervoltage lockout region, after recovery,
output will come on after the soft-start time or after the rise time to the undervoltage lockout
release point, which is determined by the time constant.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 13 of 39
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Rating Value Units Notes
Supply voltage VIN 30 V
Output current (DC) IO ±0.2 A
Output current (peak) Iopeak ±2 A
Current limiter voltage VCL +4, –1 V
Error amp input voltage VIEA Vref V
E/O output voltage VIE/O Vref V
RT1 pin current IRT1 500 µA
RT2 pin current IRT2 5 mA
Power dissipation PT 680 mW 1, 2
Operating temperature range Topr –20 to +85 °C
Storage temperature range Tstg –55 to +125 °C
Notes: 1. For the “FP” products (SOP package), this value is when mounted on a 40 by 40 by 1.6 mm glass epoxy
substrate. However, this value must be derated by 8.3 mW/°C from Ta = 45°C. When the wiring density is
10%, and 11.1 mW/°C from Ta = 64°C when the wiring density is 30%.
2. For the “P” products (DIP package), this value is valid up to 45°C, and must be derated by
8.3 mW/°C above 45°C.
3. In the case of SOP, use center 4 pins, (4), (5), (12), (13) for solder-mounting and connect the wide ground
pattern, because these pins are available for heat sink of this IC.
700
600
500
400
300
200
100
−20 0 20 40 60 80 100 120 140
45°C 64°C30% Wiring density
10% Wiring density
Ambient temperature Ta (°C)
Power dissipation PT (mW)
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 14 of 39
Electrical Characteristics
(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)
Section Item Symbol Min Typ Max Unit Test Conditions Note
Output voltage Vref 6.10 6.45 6.80 V
Line regulation Line – 30 60 mV 12 V ≤ VIN ≤ 30 V
Load regulation Load – 30 60 mV 0 mA ≤ IO ≤ 10 mA
Temperature
stability ∆Vref/
∆Ta – 40 – ppm/
°C
Short circuit current IOS 30 50 – mA Vref = 0 V
Reference
voltage
Over voltage protec-
tion (Vref OVP
voltage)
Vrovp 7.4 8.0 9.0 V
Maximum frequency fmax 600 – – kHz
Minimum frequency fmin – – 1 kHz
Voltage stability ∆f/fo1 – ±1 ±3 % 12 V ≤ VIN ≤ 30 V
fo1 = (fmax + fmin)/2
Temperature stability ∆f/fo2 – ±1 – % –20°C ≤ Ta ≤ +85°C
fo2 = (fmax + fmin)/2
Triangle
wav e
generator
Frequency accuracy fOSC 270 300 330 kHz RT1 = RT2 = 27 kΩ
CT = 120 pF
Minimum deadband
pulse width tDB – – 1.0 µs
Low level threshold
voltage VTL 1.9 2.2 2.5 V
High level threshold VTH 3.8 4.2 4.6 V
Differential threshold ∆VTH 1.7 2.0 2.3 V
Deadband width
initial accura cy ∆DB1 – ±1 ±3 % RT1 = RT2 = 27 kΩ
CT = 470 pF
Deadband width
voltage stabil ity ∆DB2 – ±0.2 ±2.0 % 12 V ≤ VIN ≤ 30 V
(Dmax – Dmin)/2
PWM
comparator
Deadband width
temperature stability ∆DB3 – ±1 – % –20°C ≤ Ta ≤ +85°C
(Dmax – Dmin)/2
Input offset voltage VIO – 2 10 mV
Input bias current IIB – 0.8 2.0 µA
Input sink current Iosink 80 140 – µA VO = 2 V
Output source current Iosource 80 140 – µA VO = 5 V
High level output
voltage VOH Vref –
1.5 – – V IO = 10 µA
Low level output
voltage VOL – – 0.5 V IO = 10 µA
Voltage gain GV – 55 – dB f = 10 kHz
Band width BW – 15 – MHz
(–) Common mode
voltage VCM– 1.2 – – V
Error amp
(+) Common mode
voltage VCM+ – – Vref –
1.5 V
(+) Threshold voltage VTH+ 0.216 0.240 0.264 V
(+) Bias current IB+ – 180 250 µA VCL+ = 0 V
(–) Threshold voltage VTH– –0.264 –0.240 –0.216 V 1, 2
(–) Bias current IB– – 950 1350 µA VCL = –0.3 V 1, 2
Over-
current
detector
Response tim e toff – 100 – ns CL; open
VCL = +0.35 V
Notes: 1. Only applies to the HA16107P, HA16108P
2. The terminal should not be applied under –1.0 V.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 15 of 39
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)
Section Item Symbol Min Typ Max Unit Test Conditions Note
High level voltage VSTH 3.2 3.8 4.4 V Isink = 1 mA Soft start Sink current Isink 7 10 13 µA VST = 2.0 V
VIN high level thre-
shold voltage VINTH 14.7 16.2 17.7 V
VIN low level thre-
shold voltage VINTL 8.5 9.5 10.5 V
Under
voltage
lockout 1
Threshold differential
voltage ∆VTH 5.2 6.2 7.2 V (VINTH – VINTL)
Vref high level thre-
shold voltage VrTH 4.5 5.0 5.5 V Under
voltage
lockout 2 Vref low level thre-
shold voltage VrTL 3.5 4.0 4.5 V
Latch threshold
voltage VTHH 6.5 7.0 7.5 V Latch threshold
voltage
VIN reset voltage VINR2 6.0 6.5 7.0 V
Reset voltage VTHL2 1.0 1.3 1.6 V 1
Differential threshold to
UVL low voltage ∆V 2.0 3.0 – V (VINTL – VINR2)
Source current
(OCL mode) Isource 8 12 16 µA Over current
detection mode
Timer
latch,
ON/OFF
timer *2
Sink current
(latch mode) Isink 2.5 4 5.5 µA TL(ON/OFF)
terminal = 4 V
Low voltage VOL1 – 1.7 2.2 V Iosink = 0.2 A
High voltage VOH V
IN –
2.2 – – V Iosource = 0.2 A
Low voltage
(standby mode) VOL2 – – 0.5 V Iosink = 1 mA
Rising time tr – 40 — ns CL = 1000 pF
Output
Falling time tf – 60 — ns CL = 1000 pF
Standby current Ist – 160 250 µA VIN = 14 V
Operation current IIN1 – 16 20 mA VIN = 30 V,
CL = 1000 pF,
f = 100 kHz
Operation current IIN2 – 12 16 mA VIN = 30 V,
f = 100 kHz,
Output open
ON/OFF latch
current IIN3 – 350 460 µA VIN = 14 V
Total
VIN – GND Zener
voltage VZ 30 34 – V
Notes: 1. Only applies to the HA16108P/FP.
2. Timer latch: HA16107P/FP.
ON/OFF timer: HA16108P/FP.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 16 of 39
Note on Standby Current
In the test circuit shown in figure 1, the operating current at the start of PWM pulse output is the standby current.
If the resistance connected externally to the Vref pin (including RT2) is smaller than that of the test circuit, the appa rent
standby current will increase.
VIN
CIN IIN
Vref
Rref
HA16107
Series
↑
Ist
+↑
Figure 1 Standby Current Test Circuit
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 17 of 39
Application Note
• Case:
When DC power is applied directly as the power supply of the HA16107/HA16108, without using the transformer
backup coil.
• Phenomenon:
The IC may not be activated in the case of a circuit in which VIN rises quickly (10 V/100 µs or faster), such as tha t
shown in figure 2.
• Reason:
Because of the IC circuit configuration, the timer latch block operates first.
• Remedy (counter measure):
Take remedial action such as configuring a time constant circuit as shown in fi gure 3, to keep the VIN rise spe ed
below 10 V/100 µs.
If the IC power supply consists of an activation resistance and backup coil, as in an AC/DC converter, The VIN rise
speed is usually around 1 V/100 µs, and there is no risk of this phenomenon occurring.
Input
V
IN
V
IN
HA16107
Series
GND
Feedback
Output
Figure 2 Example of Circuit with Fast VIN Rise Time
Input
VIN
VIN
18 V
1 µFC
HA16107
Series
GND
Feedback
Output
R 51Ω
Time constant
circuit
Figure 3 Sample Remedial Circuit
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 18 of 39
Characteristic Curves
0 10203040
10
20
30
40 Ta = 25°C
R
T1
=
R
T2
= 27 kΩ
C
T
= 470 pF
f
OSC
= 100 kHz
Operating current (mA)
Operating Current vs. Power Supply Voltage
Latch Current vs. Power Supply Voltage
010203040
0.5
1.0
1.5
2.0 Ta = 25°C
R
T1
= R
T2
= 27 kΩ
C
T
=470 pF
f
OSC
= 100 kHz
Latch current (mA)
Power supply voltage (V)
Power supply voltage (V)
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 19 of 39
048 1620
100
200
300
400
12
024 810
5
10
15
20
6
Ta = 25°C
VIN = 20 V
CT = 470 pF
Standby current (µA)
Power supply voltage (V)
Output VOH (V)
Reference voltage (V)
Output VOH vs. Reference Voltage
Vref
UVL
2
Voltage Vref
OVP Voltage
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
fOSC = 100 kHz
Standby Current vs. Power Supply Voltage
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 20 of 39
V
CL
(V)
Output OFF Time vs. V
CL
0102030
2
4
6
8
Reference voltage (V)
Power supply voltage (V)
Ta = 25°C
R
T1
= R
T2
= 27 kΩ
C
T
=470 pF
f
OSC
= 100 kHz
0 0.2 0.3 0.4
100
200
300
400
V
CL
Output OFF time (ns)
C
L
= 100 pF
C
L
= unloaded
Ta = 25°C
R
T1
= R
T2
= 27 kΩ
C
T
=470 pF
f
OSC
= 100 kHz
Reference Voltage vs. Power Supply Voltage
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 21 of 39
01 3 5
20
40
60
10
30
50
24
Output ON duty (%)
Error input voltage (V)
Output ON Duty vs. Error Input Voltage
Ta = 25°C
R
T1
= R
T2
= 27 kΩ
C
T
=470 pF
f
OSC
= 100 kHz
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 22 of 39
0 0.1 0.2 0.3 0.4 3.0
Vref
0 0.1 0.2 0.3 0.4 3.0
PWM OUT
0−0.1 −0.2 −0.3 −0.4 −1.0
VrefPWM OUT
0−0.1 −0.2 −0.3 −0.4 −1.0
Reference Voltage and PWM Out vs. C
L
(+)
Reference Voltage and PWM Out vs. C
L
(−)
C
L
(+)
C
L
(−)
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 23 of 39
30 40 50 60 70
5
10
15
20
80
Ta
=
25°C
0
R
T1
RT2
−1000
0
1000
2000
−2000
−20 0 25 50 75 85
Timing resistance R
T1,
RT2
(
kΩ)
Deadband duty (%)
Timing Resistance vs. Deadband Duty
Temperature Fluctuation vs. Ambient Temperature
Temperature fluctuation (ppm)
Ambient temperature (°C)
V
IN
=
18V
R
T1
=
RT2
=
27 kΩ
C
T
=
470 pF
f
OSC
=
100 kHz
V
IN
=
18V
C
T
=
470 pF
f
OSC
≈ 100 kHz
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 24 of 39
02550 85
−5
0
5
10
75−20
−10
02550 85
−5
0
5
10
75−20
−10
Frequency variance (%)
Ambient temperature (°C)
Frequency Variance vs. Ambient Temperature
Frequency Variance vs. Ambient Temperature
Frequency variance (%)
Ambient temperature (°C)
V
IN
=
18V
R
T1
=
R
T2
=
27 kΩ
C
T
=
120 pF
f
OSC
= 3
00 kHz
V
IN
=
18V
R
T1
=
R
T2
=
27 kΩ
C
T
=
470 pF
f
OSC
=
100 kHz
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 25 of 39
02550 85
−5
0
5
10
75−20
−10
02550 85
−5
0
5
10
V
IN
= 18V
75−20
−10
f = 100 kHz
f = 300 kHz
f = 600 kHz
Frequency variance (%)Output ON duty variance (%)
V
IN
= 18V
R
T1
= R
T2
= 13 kΩ
C
T
= 120 pF
f
OSC
= 600 kHz
Output ON Duty Variance vs. Ambient Temperature
Ambient temperature (°C)
Ambient temperature (°C)
Frequency Variance vs. Ambient Temperature
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 26 of 39
600
500
300
100
90
70
50
30
10
9
7
5 7 10 30 50 70 100
3300 pF
820 pF
470 pF
270 pF
C
T
= 120 pF
Oscillator frequency (kHz)
Timing resistance R
T1
(= R
T2
) (kΩ)
Oscillator Frequency vs. Timing Resistance
V
IN
= 18 V
Ta = 25°C
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 27 of 39
−500
0
500
0
10
20
30
I
O
(mA)
200 ns/div
−500
0
500
0
10
20
30
IO(mA) Vout (V)
Vout (V)
Vout Output Rising Waveform
Vout Output Falling Waveform
40
40
200 ns/div
V
IN
OUT
CL (+)
RT1
C
T
S
T
R
T2
Vref
TL 1 µF
+
+C
ST
1 µF
27 kΩ
470 pF
27 kΩ
1000 pF
C
L
I
O
Current probe
* Current probe: Tektronix AM503
Test circuit Ta
=
25°C
R
T1 =
RT2
=
27 kΩ
C
T =
470 pF
f
OSC =
100 kHz
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 28 of 39
0
1
2
3
4
5
6
V
TL
(V)
0.5 sec/div
7
t
ON
t
OFF
SW ON SW OFF
When overcurrent is input at the point
where the duty cycle is 0%.
0
1
2
3
4
5
6
V
TL
(V)
7
When overcurrent is input at the point
where the duty cycle is 30%.
Operating waveform at the TL pin
Output pulse shutdown region
t
ON
t
OFF
SW ON SW OFF
Output pulse shutdown region
A
B
A
B
0.5 sec/div
V
IN
OUT
CL(+)
R
T1
C
T
S
T
R
T2
Vref
TL
1 µF
+
+C
ST
1 µF
27 kΩ
470 pF
1000 pF
C
L
SW
t2
t1
Du = ×100 (%)
t1
t2
t
V
TL
A
b c
t
V
TL
Test circuit
Triangle
wave
CL(+) when
input at a
duty of 0%
CL(+) when
input at a
duty of 30%
Enlargement of section
CTL discharged at 4 µA
CTL discharged at 12 µA
CTL discharged at 4 µA
: PWM pulse output is High
: The point where overcurrent
is detected
: PWM pulse output is Low.
a
to
b
b
b
to
c
B
Enlargement of section
a
Clock
27 kΩ
V
IN
= 18V
HA16107
R
T1
= R
T2
= 27 kΩ
C
T
= 470 pF
f
OSC
= 100 kHz
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 29 of 39
OUT
Output pulse shutdown region
Triangle
wave
CL(+) when
input at a
duty of 0%
CL(+) when
input at a
duty of 30%
Du = × 100 (%)
Enlargement of section
CTL discharged at 4 µA
CTL discharged at 12 µA
t
1
t
2
0.5 sec/div
0.5 sec/div
SW OFFSW ON
ON/OFF
Clock
CL(+)
R
T1
tOFF
tON
tOFF
tON tOFF
t
1
t
2
tON
+
+
C
T
V
t
TL
C
ST
C
L
V = 18V
IN
R = R = 27 k½
T1 T2
C = 470 pF
T
f = 100kHz
OSC
S
1 µF
1 µF
T
R
27 k½
27 k½ 470 pF
1000 pF
T2
Operating waveform at the ON/OFF pin
7
6
5
4
3
2
1
0
V ON/OFF (V)
B
A
Output pulse shutdown region
SW OFFSW ON
tOFF
tON tOFF
tON
7
6
5
4
3
2
1
0
V ON/OFF (V)
B
A
A
ab
a
b
b
c
c
b
Enlargement of section
CTL discharged at 4 µA
to : PWM pulse output is High.
: The point where overcurrent
is detected.
to : PWM pulse output is Low.
V
t
TL
B
V
IN
Test circuit HA16108
When overcurrent is input at the point
where the duty cycle is 0%.
When overcurrent is input at the point
where the duty cycle is 30%.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 30 of 39
Error Amplifi er Characteri stic
10 k
0
20
40
180
90
0
A
VO
φ
45
135
60
30 k 100 k 300 k 1 M
Input signal frequency f
IN
(Hz)
Open Loop Gain A
VO
(dB)
Phase Change φ (deg)
3 M 10 M 30 M 100 M
Examples of Drooping Characteristics of Power Supplies Using these Ics
Normal operation
0
2.5
5.0
1
V
OUT
(DC) (V)
2
I
OUT
(DC) (A)
I
OUT
(DC) (A)
HA16107 (Latch shut-down)
34
0 1234
Pulse by pulse
Current limiter operation
A Heavy load
B Light load
ON
ON
OFF
OFF
A
A
B
B
2.5
5.0
V
OUT
(DC) (V)
Pulse by pulse
Current limiter operation
A Heavy load
B Light load
Latch state here
HA16108 (Intermittent operation by means of ON/OFF timer)
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 31 of 39
Operating Circuit Example
AC
INPUT
+
−
+
+
+
−
++−
+
+
−
−
−
Bridge Diode
•
82 kΩ
1 W
51 Ω
40T
23T
1.5 Ω
3 W
50 V
HZP 16
TL
E/O
IN(−)
IN(+)
NC
GND
ST
1 µF
1 µF
Vref
110 Ω
51 Ω
27 kΩHA16107P/FP
27 kΩ
CL(−)
CL(+)
V
E
R
T1
R
T2
C
T
V
OUT
IN
470 pF
4700 pF
22 µF
16 V
330
kΩ
33kΩ33kΩ
68
kΩ
510 kΩ
16 V
16 V
3.225 V
6.45 V
6.45 V
Zener type
reference
voltage
generation
circuit
34 V
Error amp.
3.4 V 10 µA
1 µF
6T
2SK1567
140 V El-30
Trans former
470 µF5 V
OUTPUT
HRP 24
HRP 32
18.9 V
Schottky barrier diode
HZP 16
Start-up Resistor
Current Sense
Current
Sense
L.P.F.
OVP
Detector
Timerlatch
Capacitor
Phase
Comp.
Frequency,
Max, Duty
Setting
fosc = 100 kHz,
Dumax = 50%
Flyback Transforrmer Application Example
(IC Vref used as system as reference voltage)
RFI
FILTER
1112 10 913141516
65 7 84321
Soft Start
Cap.
OUT
V
QCLM
C
V
Vref
Vref
UVL2
4
µ
A
16
µ
A
140
µ
A
Current
limiter
E
QR
R
SQ
O
V
P
UVL1
UVL1
UVL1&UVL2
PWM Comparator Triangle wave
P{ulse by pulse latch
ON/OFF Latch
(V = 7V) ST
H
L
L
TH
H
V
IN
V
VUVL2
H
L
4V 5V
SQ
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 32 of 39
AC
INPUT
Bridge diode Power thermister
200 V
100 µFDFG1C8 HRW26F 47 µH
0.5 φ
8 T
*
0.5 φ
8 T
*
0.3 φ
50 T
0.3 φ
50 T 50 V
22 µF
+
–
16 V
1000 µF
3.3 µF
1.8 kΩ
4.7 kΩ
B
Secondary error amplifier
TLP521
* Bifiler transfomer core size
EI-30 equivalent product
DC
OUT
(5 V)
330 Ω
3.3 kΩ
+
−
+
−
+
−
+
−
HZP16
13 kΩ
+
+
+
0.47 µF
1 W 82 kΩ
10 kΩ
1 µF
1 µF
(Start-up resistor)
(Soft start
capacitor) −
−
−
13 kΩ
12345678
910111213141516
TL
R
B
V
OUT
R
T1
C
T
C
T2
E/O IN
(−)
CL
(+)
HA16107P/108P
IN
(+)
NC ST Vref
51 Ω
51 Ω
4700 pF
470 pF 110 Ω
2SK1567
3 W
1.5 Ω(Current sense)
(Current sense filter)
Timer latch
capacitor
• Forward Transformer Application Example
HA17431P
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 33 of 39
V
IN
R
B
OVP detector
1 µF
+
TL
V
IN
OUT
CL(+)
• When OVP signal is inserted at CL(+) pin
When the OVP detection Zener diode turns on, latch shutdown of the output
is performed after the elapse of the time determined by the capacitance
connected the TL pin.
HA16107P/FP, HA16108P/FP
Rev.4.00 Jun 15, 2005 page 34 of 39
Application
1. Use of Error Amplifier for Flyback Transformer Primary-Side Control
In this example, the fact that the transformers winding ratio and voltage ratio in Figure 4 are mutually proportional is
made use of in a flyback transformer type AC-DC converter. As fluctuation of output voltage V2 also appears in IC
power supply voltage V3, this is divided by a resistance and amplified by an error amplifier. An advantage of this
method is that a photocoupler need not be used, making it possible to configure a power supply with a small number of
parts (this example cannot be applied to a forward transformer).
14
11
15
Commercial AC input
V
3
(IC power supply voltage)
Error amp.
2.5V
R
2
R
1
R
4
R
3
−
+E/O Flyback
transformer
N
1
N
3
N
2
Start-up
resistance
To switch element
C
1
•V
1
(input voltage)
V
2
(output voltage)
Output
R
1
+ R
2
R
2
N
3
N
2
× V
3
=2
1Vref
V
3
= × V
2
,Where
Figure 4 Error Amplifier Peripheral Circuitry Diagram
<Determining External Constants around Error Amplifier>
1. Detrrrmining DC Characteristics
In Figure 4, the relational expression in the box is satisfied, and therefore parameters are determined based on this.
The absolute value of the number of transformer windings is determined based on the equation N1:N2:N3 = V1:V2:V3,
taking primary inductance into consideration.
Next, IC operating voltage V3 is made around 11V to 18V, taking the UVL voltage into consideration. If V3 is too
large, the power consumption of the IC will increase, causing heat emission problems. If V3 is too small, on the
other hand, there will be problems with defective power supply start-up.
2. Determining Error Amplifier Gain vs. Frequency Characteristic
Taking the configuration in Figure 4, the error amplifier gain characteristic with respect to fluctuation of output
voltage V2 is as shown in Figure 5.
G
1
f
1
f
AC
f
2
G
2
R
6
≠ 0
R
6
= 0
f
OSC
Frequency f (Hz)
Gain G (dB)
Figure 5 Error Amplifier Characteristic
HA16107P/FP, HA16108P/FP
Rev.4.00 Jun 15, 2005 page 35 of 39
In Figure 5, the parameters are given by the following equations.
Gain
G1 = V3/V2 × R3/R1
G2 = V3/V2 × R4/R1
Corner frequencies
f1 = 1/(2π C1 R3)
f2 = 1/(2π C1 R4)
Where R3>>R4 (10:1 or above)
G1 is made around 30 to 50 dB, taking both regulation and stability into consideration.
f1 is made a lower value than commercial frequency ripple fAC, thus preventing hunting (a system instability
phenomenon).
Next, G2 is set to 0 dB or less as a guideline, so that there is no gain in IC operating frequency fOSC (several tens to
several hundreds of kHz). f2 should be set to a value that is substantially smaller than fOSC, and that is appropriate for
the power supply response speed (several kHz). In the case of a bridge type rectification circuit, the commercial
frequency ripple is twice the input frequency (with a 50 Hz commercial frequency, fAC = 100 Hz).
2. External Constant Design for Current Detection Section (HA16107, HA16108, HA16666)
In the above IC models, which incorporate a current detection function, a low-pass filter such as shown in Figure 6 must
be inserted between switch element current detection resistance RCS and the current detection pin of the IC.
Output
Switch element
power MOS FET
Floating capacitance
Input voltage
From PWM
output pin
of IC
To current
detection pin
of IC
Current detection resistance
Several hundred mΩ
to several Ω
Filter (LPF)
C
A
R
B
R
CS
R
A
I
D
C
X
V
B
140V
V
11
V
12
Figure 6 Current Detection Circuit
HA16107P/FP, HA16108P/FP
Rev.4.00 Jun 15, 2005 page 36 of 39
The reason for this is that, when the switch element is on in each cycle, there is an impulse current associated with
charging of transformer floating capacitance CX, and IC current detection malfunctions (see Figure 7).
V
11
V
TH
V
12
Figure 7 Current Detection Waveform
<Setting Numeric Values>
If the switch element current to be detected is designated ID, and the current detection resistance RCS, then the following
equation is satisfied using the parameters in Figure 6.
ID × RCS = ((RA + RB)/RB) VTH
VTH is the detection level voltage of the IC (240 mV in the case of the HA16107, for example). RA and RB are set to
values on the order of several hundred Ω to several kΩ, so that RCS is not affected.
Next, the filter cutoff frequency is set according to the following equation.
fC = 1/(2π CA (RA/RB))
fC can be found with the following guideline, using IC operating frequency fOSC, power supply rating on-duty D, and
power MOS element turn-on time tON.
fosc/D ≤ fC ≤ 1/(100 × tON)
Value 100 in the above equation provides a margin for noise, ringing, and so forth.
<Actual Example>
In an SW power supply using an HA16107, with a 100 kHz operating frequency and a D value of 30%, the relevant
values were as follows: VB = 140 V, CX = 80 pF, tON = 10 ns. Thus, when RCS = 1 Ω, the V11 level peak value reaches
the following figure.
V11 (peak) = RCS × ID peak
= RCS × (VB × CX)/tON
= 1Ω × (140 V × 80 pF)/10 ns
= 1.12 (V)
A filter with the following constants was then inserted.
RA = RB = 1 kΩ, CA = 1000 pF
At this time, the detectable drain current is 0.48 (A), and the filter cutoff frequency is 318 (kHz). Note that increasing a
filter time constant is effective against noise, but if the value is too large, error will arise in the switch element current
detection level.
HA16107P/FP, HA16108P/FP
Rev.4.00 Jun 15, 2005 page 37 of 39
3. IC Heat Emission Problem and Countermeasures (HA16107 Series, HA16114 Series)
While the above ICs can directly drive a power MOS FET gate, if the method of use is not thoroughly investigated,
there will be a tendency for the gate drive power to increase and a problem of heat emission by the IC may occur.
This section should therefore be noted and appropriate measures taken to prevent this kind of problem.
1. Power MOS FET Drive Characteristics
When power MOS FET drive is performed, in order to lower the on-resistance sufficiently, overdrive is normally
performed with a voltage considerably higher than 5 V, for example, such as the 15 V power supply voltage of the
IC.
At this time, the power that should be supplied from the IC to the power MOS FET is determined by gate load Qg in
Figure 9.
2. IC Heat-Emission Power Calculation (Figure 9)
The power that contributes to IC heat emission is calculated by means of the following equation.
Pd = VIN IQ + 2Qg VIN f
Where VIN : Power supply voltage of IC
I
Q : Operating current of IC (unloaded)
Qg : Above-mentioned gate load
f : Operating frequency of IC
The coefficient, 2, indicates that gate discharging also contributes to heat emission.
4. Power MOS FET Gate Resistance Design (HA16107 Series, HA16114 Series)
There are the following three purposes in connecting a gate resistance, and the circuit is generally of the kind shown in
Figure 8.
(1) To suppress peak current due to gate charging
(2) To protect IC output pins
(3) To provide drive appropriate to power MOS FET input characteristics
R
G1
D
G
OUT
C
S
R
CS
IC
output pin
To transforme
r
Power
MOS FET
R
G2
Figure 8 Gate Drive Circuit
HA16107P/FP, HA16108P/FP
Rev.4.00 Jun 15, 2005 page 38 of 39
This gate resistance RG is given by the following equation.
RG = (VG/IG) – (VG × tON)/Qg, RG = RG1 + RG2
IG : Gate input peak current
VG : Gate drive voltage wave high value (equal to power supply voltage of IC)
tON : Power MOS FET turn-on time
tOFF : Power MOS FET turn-off time
Qg : Gate charge according to Figure 9
V
DS
V
DS
(V) V
GS
V
GS
(V)
Qg (nc)
Figure 9 Power MOS FET Dynamic Input Characteristics
Refer to the power MOS FET catalog for information on tON and Qg.
By dividing RG into RG1 and RG2, it is possible for speed to be slowed when the power MOS FET is on, and
increased when off.
Power MOS FET on and off times when mounted, tON’ and tOFF’, are as follows.
tON’ = tON + Qg(RG1 + RG2)/VG
tOFF’ = tOFF + Qg ⋅ RG2/VG
<Actual Example>
When driving a power MOS FET and 2SK1567 with an HA16107, etc.
(RG1 = 100 Ω, RG2 = 20 Ω, VG = 15 V)
tON’ = 70 ns + 36 nc ⋅ (100 Ω + 20 Ω)/(15 V) = 360 (ns)
tOFF’ = 135 ns + 36 nc ⋅ (20 Ω)/(15 V) = 183 (ns)
Generally, the gate resistance values in the case of this circuit configuration are on the order of 100 to 470 Ω for RG1
and 10 to 47 Ω for RG2.
HA16107P/FP , HA16108P/FP
Rev.4.00 Jun 15, 2005 page 39 of 39
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-16
Conforms
Conforms
1.07 g
6.30
19.20
16 9
81 1.3
20.00 Max
7.40 Max
7.62
0.25+ 0.13
− 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0° − 15°
1.11 Max
As of January, 2003
Unit: mm
F
E
1
y
xM
p
*3
*2
*1
8
916
Index mark
b
Z
AH
E
D
Terminal cross section
p
1
1
c
b
b
c
Detail F
1
1
L
L
A
θ
0.80
0.15
1.27
7.50 8.00
0.420.34
p
A
1
10.5
FP-16DA
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
0.20
5.5
0.200.100.00
0.50
0.40
0.270.220.17
7.80
8
°
0
°
0.12
1.15
10.06
0.24g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP16-5.5x10.06-1.27 PRSP0016DH-A
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
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