UPD789112AMC-XXX-5A4 - Renesas Electronics - Datasheet.Directory

DATA SHEET

8-BIT SINGLE-CHIP MICROCONTROLLERS

MOS INTEGRATED CIRCUITS

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),

102A(A),104A(A),111A(A),112A(A),114A(A)

Document No. U14590EJ1V0DS00 (1st edition)

Date Published January 2000 N CP(K)

Printed in Japan ©2000

The

µ

PD789101A, 789102A, and 789104A (

µ

PD78910xA hereafter) are

µ

PD789104A Subseries products of the

78K/0S Series.

The

µ

PD789111A, 789112A, and 789114A (

µ

PD78911xA hereafter) are

µ

PD789114A Subseries products of the

78K/0S Series.

Besides an 8-bit CPU, these microcontrollers incorporate a variety of hardware such as I/O ports, timers, a serial

interface, A/D converters, and interrupt control.

A stricter quality assurance program (called special grade in NEC’s grade classification) is applied to the

µ

PD789101A(A), 789102A(A), 789104A(A) (

µ

PD78910xA(A) hereafter), and

µ

PD789111A(A), 789112A(A),

789114A(A) (

µ

PD78911xA(A) hereafter), compared to the

µ

PD78910xA and 78911xA, which are classified as

standard grade.

In addition, a flash memory version (

µ

PD78F9116A) that can operate within the same power supply voltage range

as the mask ROM version, and a range of development tools are also being prepared.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µ

µµ

µ

PD789104A, 789114A, 789124A, 789134A Subseries User’s Manual: To be prepared

78K/0S Series User's Manual Instruction: U11047E

FEATURES

•On-chip multiplier: 8 bits × 8 bits = 16 bits

•ROM and RAM sizes

Item

Part Number Program Memory

(ROM) Data Memory

(Internal Hi gh-Speed RAM) Package

µ

PD789101A, 789111A , 789101A(A), 789111A (A) 2 Kbytes

µ

PD789102A, 789112A , 789102A(A), 789112A (A) 4 Kbytes

µ

PD789104A, 789114A , 789104A(A), 789114A (A) 8 Kbytes

256 bytes 30-pin plast i c SSOP

(7.62 mm (300))

•Minimum instruction execution time can be changed from high-speed (0.4

µ

s) to low-speed (1.6

µ

s) (@ 5.0-MHz

operation with system clock)

•I/O ports: 20

•Serial interface: 1 channel: Switchable between 3-wire serial I/O and UART modes

•8-bit resolution A/D converter: 4 channels (

µ

PD78910xA, 78910xA(A))

•10-bit resolution A/D converter: 4 channels (

µ

PD78911xA, 78911xA(A))

•Timers: 3 channels

•16-bit timer: 1 channel

•8-bit timer/event counter: 1 channel

•Watchdog timer: 1 channel

•Power supply voltage: VDD = 1.8 to 5.5 V

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Data Sheet U14590EJ1V0DS00

2

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

APPLICATIONS

Cleaners, washing machines, and refrigerators

ORDERING INFORMATION

Part Number Package Quality grade

µ

PD789101AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789102AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789104AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789111AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789112AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789114AMC-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Standard

µ

PD789101AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

µ

PD789102AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

µ

PD789104AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

µ

PD789111AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

µ

PD789112AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

µ

PD789114AMC(A)-×××-5A4 30-pin plastic SSOP (7.62 mm (300)) Special

Remark ××× indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Data Sheet U14590EJ1V0DS00 3

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

78K/0S SERIES LINEUP

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

78K/0S

series

Small, general-purpose

Small, general-purpose + A/D

For inverter control

For driving LCD

For ASSP

44/48 pins

44/48 pins

44 pins

44 pins

42/44 pins

28 pins

44 pins

30 pins

30 pins

30 pins

30 pins

30 pins

30 pins

44 pins

Products under mass production

Products under development

Y subseries supports SMB.

PD789014

80 pins

80 pins

64 pins

64 pins

64 pins

64 pins

64 pins

64 pins

44 pins

44 pins

20 pins

20 pins

µ

PD789026

µ

PD789046 PD789026 with subsystem clock added

PD789014 with timer reinforced and ROM and RAM expanded

UART. Low-voltage (1.8-V) operation

RC oscillation model of PD789197AY

PD789177 with internal EEPROM

TM

PD789167 with improved A/D

PD789104A with improved timer

PD789146 with improved A/D

PD789104A with EEPROM added

PD789124A with improved A/D

RC oscillation model of PD789104A

PD789104A with improved A/D

PD789026 with A/D and multiplier added

PD789407A with improved A/D

PD789456 with improved I/O

PD789446 with improved A/D

PD789426 with improved display output

PD789426 with improved A/D

PD789306 with A/D added

RC oscillation model of PD789306

Basic subseries for driving LCD

For PC keyboard. Internal USB function

For key pad. Internal POC

RC oscillation model of PD789860

For keyless entry. Internal POC and key return circuit

Internal inverter control circuit and UART

µ

PD789104A

µ

PD789114A

µ

PD789842

µ

PD789124A

µ

PD789134A

µ

PD789146

µ

PD789156

µ

PD789167

µ

PD789177

µ

PD789306

µ

PD789316

µ

PD789426

µ

PD789436

µ

PD789860

µ

PD789861

µ

PD789840

µ

PD789800

µ

PD789446

µ

PD789456

µ

PD789167Y

µ

PD789177Y

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µ

µµ

µ

µ

PD789197AY

µ

µµ

PD789407A

µ

PD789417A

µ

PD789217AY

88 pins Segment: 40 pins, common: 16 pins

PD789830

µ

144 pins Segment/common output: 96 pins

PD789835

µ

For driving Dot LCD

52 pins

52 pins For remote controller. Internal LCD controller/driver

PD789327

µ

PD789467

µ

PD789327 with A/D added

µ

Data Sheet U14590EJ1V0DS00

4

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

The major differences between subseries are shown below.

Timer

ROM

Capacity 8-bit 16-bit Watch WDT

8-bit

A/D 10-bit

A/D Serial Interface I/O VDD

MIN

Value Remark

µ

PD789046 16 K 1 ch

µ

PD789026 4 K-16 K

1 ch 1 ch 34 pins

Small,

general-

purpose

µ

PD789014 2 K-4 K 2 ch −

−

1 ch −−

1 ch (UART:1 c h)

22 pins

1.8 V −

µ

PD789177 −8 ch

µ

PD789167

16 K-24 K 3 ch 1 ch

8 ch −

31 pins −

µ

PD789156 −4 ch

µ

PD789146

8 K-16 K

4 ch −

Internal

EEPROM

µ

PD789134A

4 ch

µ

PD789124A

4 ch −

RC oscillation

version

µ

PD789114A

−4 ch

Small,

general-

purpose

+ A/D

µ

PD789104A

2 K-8 K

1 ch

1 ch

−

1 ch

4 ch −

1 ch (UART: 1 c h)

20 pins

1.8 V

−

For

inverter

control

µ

PD789842 8 K-16 K 3 ch Note 1 ch 1 ch 8 c h −1 ch (UART: 1 ch) 30 pins 4.0 V −

µ

PD789417A

7 ch

µ

PD789407A

12 K-24 K 3 ch

7 ch −

43 pins

µ

PD789456 −6 ch

µ

PD789446 6 ch −

30 pins

µ

PD789436 −6 ch

µ

PD789426

12 K-16 K

6 ch

1 ch (UART: 1 c h)

40 pins

−

µ

PD789316

RC oscillation

version

For LCD

driving

µ

PD789306

8 K to

16K

2 ch

1 ch 1 ch 1 ch

−

−

2 ch (UART: 1 ch) 23 pins

1.8 V

−

µ

PD789835 24 K-60 K 6 ch −2 c h 1 ch 27 pins 1.8 VFor Dot

LCD

driving

µ

PD789830 24 K 1 ch 1 ch

1 ch 1 ch

−

−

1 ch (UART: 1 ch) 30 pins 2.7 V

−

µ

PD789467 1 ch −18 pins

µ

PD789327

4 K-24 K 2 ch −1 ch 1 ch

−1 ch 21 pins

1.8 V Internal

LCD

µ

PD789800 −2 ch (USB : 1 ch) 31 pins 4.0 V

µ

PD789840

8 K 1 ch

4 ch 1 ch 29 pins 2.8 V

−

µ

PD789861

RC oscillation

version,

Internal

EEPROM

ASSP

µ

PD789860

4 K

2 ch

−

−1 ch

−

−

−14 pins 1.8 V

Internal

EEPROM

Note 10-bit timer: 1 channel

Function

Subseries Name

Data Sheet U14590EJ1V0DS00 5

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

OVERVIEW OF FUNCTIONS

Item

µ

PD789101A

µ

PD789111A

µ

PD789101A(A)

µ

PD789111A(A)

µ

PD789102A

µ

PD789112A

µ

PD789102A(A)

µ

PD789112A(A)

µ

PD789104A

µ

PD789114A

µ

PD789104A(A)

µ

PD789114A(A)

ROM 2 Kbytes 4 Kbytes 8 K bytesInternal memory

High-speed RAM 256 bytes

Minimum i nstruct i on execution time 0.4/1.6

µ

s (@ 5.0-MHz operation with system clock)

General-purpose regis ters 8 bi t s × 8 regist ers

Instruction set •16-bit operati ons

•Bit m ani pul at i ons (set, reset, and t est)

Multiplier 8 bits × 8 bits = 16 bi t s

I/O ports Total: 20

•CMOS input : 4

•CMOS I/O: 12

•N-ch open-drain (12-V wi t hstand vol t age): 4

A/D c onverters •8-bit resol ut i on × 4 channels (

µ

PD78910xA, 78910xA(A))

•10-bit resol ut i on × 4 channels (

µ

PD78911xA, 78911xA(A))

Serial i nterface •Switc habl e between 3-wire serial I /O and UART modes

Timer •16-bit ti m er: 1 channel

•8-bit ti m er/ event counter: 1 channel

•Watchdog ti mer: 1 channel

Timer output 1 output (16-bit/8-bi t timer alt ernate funct i on)

Maskabl e Internal: 6, Ext ernal : 3Vectored i nterrupt

sources Non-maskable Internal: 1

Power supply voltage VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Package •30-pi n pl astic S SOP (7.62 m m (300))

Data Sheet U14590EJ1V0DS00

6

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW).............................................................................................. 7

2. BLOCK DIAGRAM ........................................................................................................................... 8

3. PIN FUNCTIONS............................................................................................................................... 9

3.1 Port Pins.................................................................................................................................................. 9

3.2 Non-Port Pins.......................................................................................................................................... 10

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins...................................................... 11

4. MEMORY SPACE............................................................................................................................. 13

5. PERIPHERAL HARDWARE FUNCTIONS...................................................................................... 14

5.1 Ports ........................................................................................................................................................ 14

5.2 Clock Generator...................................................................................................................................... 14

5.3 Timer........................................................................................................................................................ 15

5.4 A/D Converter ......................................................................................................................................... 17

5.5 Serial Interface 20................................................................................................................................... 18

5.6 Multiplier.................................................................................................................................................. 19

6. INTERRUPT FUNCTION .................................................................................................................. 20

7. STANDBY FUNCTION ..................................................................................................................... 22

8. RESET FUNCTION........................................................................................................................... 22

9. INSTRUCTION SET OVERVIEW..................................................................................................... 23

9.1 Conventions............................................................................................................................................ 23

9.2 Operations............................................................................................................................................... 25

10. ELECTRICAL SPECIFICATIONS .................................................................................................... 30

11. CHARACTERISTICS CURVES (REFERENCE VALUES)............................................................. 41

12. PACKAGE DRAWING...................................................................................................................... 44

13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 45

APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 46

APPENDIX B RELATED DOCUMENTS.............................................................................................. 48

Data Sheet U14590EJ1V0DS00 7

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

1. PIN CONFIGURATION (TOP VIEW)

•30-pin plastic SSOP (7.62 mm (300))

µ

PD789101AMC-×××-5A4

µ

PD789102AMC-×××-5A4

µ

PD789104AMC-×××-5A4

µ

PD789111AMC-×××-5A4

µ

PD789112AMC-×××-5A4

µ

PD789114AMC-×××-5A4

µ

PD789101AMC(A)-×××-5A4

µ

PD789102AMC(A)-×××-5A4

µ

PD789104AMC(A)-×××-5A4

µ

PD789111AMC(A)-×××-5A4

µ

PD789112AMC(A)-×××-5A4

µ

PD789114AMC(A)-×××-5A4

P23/INTP0/CPT20/SS20

P24/INTP1/TO80/TO20

P25/INTP2/TI80

AVDD

P60/ANI0

P61/ANI1

P62/ANI2

P63/ANI3

AVSS

P50

IC0

P51

P52

P53

P00

28

27

26

30

29

25

24

23

22

21

20

19

18

16

P22/SI20/RXD20

P21/SO20/TXD20

P20/SCK20/ASCK20

P11

P10

VDD

VSS

X1

X2

IC0

IC0

RESET

P03

P02

P01

1

2

3

4

5

6

7

8

9

10

11

12

13

1714

15

Cautions 1. Connect the IC0 (Internally Connected) pin directly to VSS.

2. Connect the AVDD pin to VDD.

3. Connect the AVSS pin to VSS.

ANI0 to ANI3: Analog Input RESET: Reset

ASCK20: Asynchronous Serial Input RXD20: Receive Data

AVDD: Analog Power Supply SCK20: Serial Clock Input/Output

AVSS: Analog Ground SI20: Serial Data Input

CPT20: Capture Trigger Input SO20: Serial Data Output

IC0: Internally Connected SS20: Chip Select Input

INTP0 to INTP2: Interrupt from Peripherals TI80: Timer Input

P00 to P03: Port0 TO20, TO80: Timer Output

P10, P11: Port1 TXD20: Transmit Data

P20 to P25: Port2 VDD: Power Supply

P50 to P53: Port5 VSS: Ground

P60 to P63: Port6 X1, X2: Crystal 1, 2

Data Sheet U14590EJ1V0DS00

8

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

2. BLOCK DIAGRAM

78K/0S

CPU CORE

ROM

RAM

V

DD

V

SS

IC0

TI80/INTP2/P25

8-BIT TIMER/

EVENT COUNTER 80

TO80/TO20

/INTP1/P24

P00 to P03

PORT 0

P10, P11

PORT 1

P20 to P25

PORT 2

P50 to P53

PORT 5

P60 to P63

PORT 6

SYSTEM

CONTROL

TO20/TO80

/INTP1/P24

CPT20/INTP0

/SS20/P23

16-BIT TIMER 20

WATCHDOG TIMER

SERIAL

INTERFACE 20

SCK20/ASCK20

/P20

SI20/RxD20/P22

SO20/TxD20/P21

SS20/INTP0

/CPT20/P23

A/D CONVERTER

ANI0/P60 to

ANI3/P63

AV

DD

AV

SS

RESET

X1

X2

INTERRUPT

CONTROL

INTP0/CPT20

/P23/SS20

INTP1/TO80

/TO20/P24

INTP2/TI80/P25

Remark The internal ROM capacity varies depending on the product.

Data Sheet U14590EJ1V0DS00 9

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternate Funct i on

P00 to

P03 I/O Port 0

4-bit input / output port

Input/output can be s pecified i n 1-bi t units

When used as an input port, an on-c hi p pul l -up resistor can be

specified by means of sof t ware.

Input –

P10, P11 I/O Port 1

2-bit input / output port

Input/output can be s pecified i n 1-bi t units

When used as an input port, an on-c hi p pul l -up resistor can be

specified by means of sof t ware.

Input –

P20 SCK20/ASCK20

P21 SO20/TxD20

P22 SI20/RxD20

P23 INTP0/CPT20

/SS20

P24 INTP1/TO80/TO20

P25

I/O Port 2

6-bit input / output port

Input/output can be s pecified i n 1-bi t units

When used as an input port, an on-c hi p pul l -up resistor can be

specified by means of sof t ware.

Input

INTP2/TI80

P50 to

P53 I/O Port 5

4-bit N-ch open-drai n i nput /output port

Input/output can be s pecified i n 1-bi t units

An on-chip pul l -up res i stor can be specifi ed by the mas k option.

Input –

P60 to

P63 Input Port 6

4-bit input -onl y port Input ANI0 to A NI3

Data Sheet U14590EJ1V0DS00

10

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

3.2 Non-Port Pins

Pin Name I/O Function After Reset Alternat e Function

INTP0 P23/CPT20/SS20

INTP1 P24/TO80/TO20

INTP2

Input External interrupt request input f or whi ch the val i d edge

(rising edge, f alling edge, or both rising and falling edges ) can

be specified

Input

P25/TI80

SI20 Input Serial int erface seri al data input Input P22/RxD20

SO20 Output Serial int erface seri al data output Input P21/TxD20

SCK20 I/O Serial int erface seri al clock i nput/output Input P20/AS CK20

ASCK20 Input Serial c l oc k input f or asynchronous serial int erf ace Input P20/ SCK20

SS20 Input Chip selec t input for serial int erf ace Input P23/CPT20/INTP0

RxD20 Input Seri al data input for asynchronous serial int erface Input P22/SI20

TxD20 Output Serial data output for as ynchronous serial int erf ace Input P21/SO20

TI80 Input External count cl ock input to 8-bit ti m er/event c ounter 80 Input P25/INTP2

TO80 Output 8-bit ti m er/ event counter 80 output Input P24/INTP 1/TO20

TO20 Output 16-bit timer 20 out put Input P24/INTP1/TO80

CPT20 Input Capture edge input Input P23/INTP 0/SS20

ANI0 to A NI3 Input A/D c onverter analog input Input P60 to P63

AVDD - A/D converter analog power suppl y – –

AVSS - A/D converter ground potent i al – –

X1 Input ––

X2 -

Connecting cryst al resonator for mai n system clock oscillation

––

RESET Input Sy s tem reset input Input –

VDD - Posit i ve power supply – –

VSS - Ground potential – –

IC0 - Internall y connected. Connect directly t o V SS.––

Data Sheet U14590EJ1V0DS00 11

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits

Pin Name Input/Output

Circuit Type I/O Recommended Connection of Unused Pins

P00 to P03

P10, P11

5-A

P20/SCK20/ASCK20

P21/SO20/TXD20

P22/SI20/RXD20

Input: Independently c onnect to V DD or VSS via a resistor.

Output: Leave open

P23/INTP0/CPT20/SS20

P24/INTP1/TO80/TO20

P25/INTP2/TI80

8-A

Input: Independently c onnect to V SS via a resistor.

Output: Leave open

P50 to P53 13-W

I/O

Input: Independently c onnect to V DD via a resistor.

Output: Leave open

P60/ANI 0 to P63/A NI 3 9-C Input Connect directl y to VDD or VSS.

AVDD Connect to VDD.

AVSS

––

Connect to VSS.

RESET 2 Input –

IC0 – – Connect direc tly t o V SS.

Data Sheet U14590EJ1V0DS00

12

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Figure 3-1. Pin Input/Output Circuits

Schmitt-triggered input with hysteresis characteristics

Type 2

IN

Type 5-A

Pull-up

enable

Data

Output

disable

Input

enable

V

DD

P-ch

V

DD

P-ch

IN/OUT

N-ch

Type 13-W

V

SS

V

SS

Type 8-A

Pull-up

enable

Data

Output

disable

V

DD

P-ch

V

DD

P-ch

IN/OUT

N-ch

V

SS

Type 9-C

IN Comparator

+

–

V

REF

(Threshold voltage)

AV

SS

P-ch

N-ch

Input

enable

Output data

Output disable

IN/OUT

V

DD

N-ch

Middle-voltage input buffer

Input enable

Pull-up resistor

(mask option)

Data Sheet U14590EJ1V0DS00 13

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

4. MEMORY SPACE

Figure 4-1 shows the memory map of the

µ

PD78910xA, 78911xA, 78910xA(A), and 78911xA(A).

Figure 4-1. Memory Map

Special function registers

256 × 8 bits

Internal high-speed RAM

256 × 8 bits

Reserved

Program memory

space

Data memory space

Program area

Program area

CALLT table area

Vector table area

Internal ROM

Note

FFFFH

FF00H

FEFFH

FE00H

FDFFH

nnnnH

0080H

007FH

0040H

003FH

0016H

0015H

0000H

0000H

nnnnH

nnnnH+1

Note The internal ROM capacity depends on the product. (See the following table).

Part Number Last Address of I nternal ROM

nnnnH

µ

PD789101A, 789111A , 789101A(A), 789111A (A) 07FFH

µ

PD789102A, 789112A , 789102A(A), 789112A (A) 0FFFH

µ

PD789104A, 789114A , 789104A(A), 789114A (A) 1FFFH

Data Sheet U14590EJ1V0DS00

14

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

The following three types of I/O ports are available:

•CMOS Input (port 6): 4

•CMOS input/output (ports 0 to 2): 12

•N-ch open-drain input/output (port 5): 4

Total: 20

Table 5-1. Port Functions

Port Name Pin Name Function

Port 0 P00 to P03 Input/output port. Input/out put can be speci fied in 1-bit uni ts.

When used as an input port, an on-c hi p pul l -up resistor can be speci f i ed by means of software.

Port 1 P10, P11 Input/output port. Input/out put can be speci fied in 1-bit uni ts.

When used as an input port, an on-c hi p pul l -up resistor can be speci f i ed by means of software.

Port 2 P20 to P25 Input/output port. Input/out put can be speci fied in 1-bit uni ts.

An on-chip pul l -up res i stor can be specifi ed by means of software.

Port 5 P50 to P53 N-channel open-drain input /output port . Input/ output can be s pecified i n 1-bi t uni ts.

An on-chip pul l -up res i stor can be specifi ed by the mas k option.

Port 6 P60 to P63 Input-only port

5.2 Clock Generator

An on-chip system clock generator is provided.

The minimum instruction execution time can be changed.

•0.4

µ

s/1.6

µ

s (@ 5.0-MHz operation with system clock)

Figure 5-1. Clock Generator Block Diagram

X1

X2

STOP

f

X

Prescaler

f

X

2

2

Prescaler

Clock to

peripheral hardware

CPU clock (f

CPU

)

Standby

control

circuit

Wait

control

circuit

Selector

System

clock

oscillator

Data Sheet U14590EJ1V0DS00 15

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

5.3 Timer

Three on-chip timers are provided.

•16-bit timer 20: 1 channel

•8-bit timer/event counter 80: 1 channel

•Watchdog timer: 1 channel

Table 5-2. Timer Operation

16-Bit Timer 20 8-Bit Timer/Event Counter 80 Watchdog Timer

Interval timer – 1 channel 1 channelOperation mode

External event count er – 1 channel –

Timer output 1 output 1 output –

PWM output – 1 output –

Square wave output – 1 output –

Capture 1 input – –

Function

Interrupt request 1 1 1

Figure 5-2. Block Diagram of 16-Bit Timer 20 (TM20)

CPT20/P23

/INTP0/SS20

Internal bus

Internal bus

Selector

f

X

/2

2

f

X

/2

6

Edge detection

circuit

16-bit capture register

20 (TCP20)

16-bit counter

read buffer

Output

control

circuit

16-bit timer counter 20

(TM20)

16-bit compare register 20

(CR20)

Match

OVF

TO20/P24/

INTP1/TO80

INTTM20

Data Sheet U14590EJ1V0DS00

16

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 80 (TM80)

Internal bus

8-bit compare register 80

(CR80)

Match

Selector

INTTM80

OVF TO80/P24/

INTP1/TO20

Clear

f

X

f

X

/2

3

TI80/P25/

INTP2

8-bit timer counter 80

(TM80) Output

control circuit

Internal bus

Figure 5-4. Watchdog Timer Block Diagram

Prescaler

f

X

2

6

f

X

2

8

f

X

2

10

Selector

7-bit counter

INTWDT

maskable

interrupt request

RESET

INTWDT

non-maskable

interrupt request

Control

circuit

f

X

2

4

Data Sheet U14590EJ1V0DS00 17

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

5.4 A/D Converter

The conversion resolution of the A/D converter differs depending on the product as shown below.

•8-bit A/D converter × 4 channels....

µ

PD789101A, 789102A, 789104A, 789101A(A), 789102A(A), 789104A(A)

•10-bit A/D converter × 4 channels..

µ

PD789111A, 789112A, 789114A, 789111A(A), 789112A(A), 789114A(A)

A/D conversion can be only started by software.

Figure 5-5. A/D Converter Block Diagram

Selector

Sample&

hold circuit

INTAD0

Internal bus

A/D converter

(8-/10-bits) A/D conversion

result register

(ADCR0)

ANI0/P60

ANI1/P61

ANI2/P62

ANI3/P63

Data Sheet U14590EJ1V0DS00

18

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

5.5 Serial Interface 20

A one-channel serial interface is incorporated.

Serial interface 20 has following three modes:

•Operation stop mode: Power consumption can be reduced.

•Asynchronous serial interface (UART) mode: A dedicated baud rate generator is incorporated.

•3-wire serial I/O mode: A function to select the clock phase or data phase is incorporated.

Figure 5-6. Block Diagram of Serial Interface 20

SI20/P22/RXD20

SO20/P21/TXD20

SS20/P23

/CPT20/INTP0

INTST20

fX/2 to fX/28

INTSR20/INTCSI20

SCK20/P20

/ASCK20

Internal bus

Reception buffer

register 20

(RXB20/SIO20)

Transmission shift

register 20

(TXS20/SIO20)

Reception shift register 20

(RXS20)

Data phase

control

Clock phase

control

Transmission

data counter

Reception

data counter

Selector

Baud rate generator

Data Sheet U14590EJ1V0DS00 19

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

5.6 Multiplier

The calculation of 8 bits × 8 bits = 16 bits can be performed.

Figure 5-7. Multiplier Block Diagram

Internal bus

Internal bus

Multiplier

Multiplication data

register A0

(MRA0)

Multiplication data

register B0

(MRB0)

16-bit multiplication result

storing register (MUL0)

Data Sheet U14590EJ1V0DS00

20

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

6. INTERRUPT FUNCTION

A total of 10 interrupt sources are provided, divided into the following two types.

•Non-maskable interrupts: 1 source

•Maskable interrupts: 9 sources

Table 6-1. Interrupt Source List

Interrupt Source

Interrupt Type PriorityNote 1

Name Trigger Internal/External Vector

Table

Address

Basic

Configuration

TypeNote 2

Non-maskable −INTWDT Watchdog timer overflow

(with watc hdog timer mode 1

selected)

(A)

0 INTWDT Wat chdog timer ov erflow

(with the i nt erval tim er m ode

selected)

Internal 0004H

(B)

1 INTP0 0006H

2 INTP1 0008H

3INTP2

Pin input edge detecti on External

000AH

(C)

INTSR20 End of seri al i nterface 20 UA RT

reception

4

INTCSI20 E nd of serial i nt erface 20 3-wire

SIO transfer recept i on

000CH

5 INTST20 End of s eri al i nterface 20 UA RT

transmission 000EH

6 INTTM80 Generation of matc hi ng signal of

8-bit ti m er/ event counter 80 0010H

7 INTTM20 Generation of matc hi ng signal of

16-bit ti m er 20 0012H

Maskable

8 INTAD0 A/D conv ersion compl etion

signal

Internal

0014H

(B)

Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 0

is the highest order and 8 is the lowest order.

2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1.

Remark As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable

interrupt (internal) can be selected.

Data Sheet U14590EJ1V0DS00 21

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Figure 6-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Interrupt request Vector table address

generator

Standby release signal

(B) Internal maskable interrupt

Internal bus

MK

IF

Interrupt request

IE

Vector table address

generator

Standby release signal

(C) External maskable interrupt

Internal bus

External interrupt mode

register (INTM0) MK

IF

IE

Vector table address

generator

Standby release

signal

Edge detection

circuit

Interrupt

request

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

Data Sheet U14590EJ1V0DS00

22

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

7. STANDBY FUNCTION

The following two standby functions are available for further reduction of system current consumption.

•HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be

reduced by intermittent operation by combining this mode with the normal operation mode.

•STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the

system clock are suspended, resulting in extremely small power consumption.

Figure 7-1. Standby Function

System clock operation

STOP mode

System clock

oscillation stopped

HALT mode

Clock supply to CPU

halted, oscillation

maintained

(

(

(

(

STOP

instruction HALT instruction

Interrupt

request

Interrupt

request

8. RESET FUNCTION

The following two reset methods are available.

•External reset by RESET signal input

•Internal reset by watchdog timer runaway time detection

Data Sheet U14590EJ1V0DS00 23

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

9. INSTRUCTION SET OVERVIEW

The instruction set for the

µ

PD78910xA, 78911xA, 78910xA(A), 78911xA(A) is listed later.

9.1 Conventions

9.1.1 Operand identifiers and description methods

Operands are described in the “Operand” column of each instruction in accordance with the description method of

the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more

description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords

and must be described as they are. Each symbol has the following meaning.

•#: Immediate data specification •$: Relative address specification

•!: Absolute address specification •[ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #,!, $, or [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 9-1. Operand Identifiers and Description Methods

Identif i er Descript i on M ethod

r

rp

sfr

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special f unction register sy m bol

saddr

saddrp FE20H to FF1FH i m m ediate data or label

FE20H to FF1FH im m edi at e data or label (even address only )

addr16

addr5

0000H to FFFFH immediate data or label

(Only even addresses f or 16-bi t data trans fer instructions )

0040H to 007FH immedi ate data or label (even address only)

word

byte

bit

16-bit imm edi ate data or label

8-bit imm edi ate data or label

3-bit imm edi ate data or label

Data Sheet U14590EJ1V0DS00

24

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

9.1.2 Descriptions of the operation field

A: A register; 8-bit accumulator

X: X register

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

AX: AX register pair; 16-bit accumulator

BC: BC register pair

DE: DE register pair

HL: HL register pair

PC: Program counter

SP: Stack pointer

PSW: Program status word

CY: Carry flag

AC: Auxiliary carry flag

Z: Zero flag

IE: Interrupt request enable flag

NMIS: Non-maskable interrupt servicing flag

( ): Memory contents indicated by address or register contents in parentheses

XH, XL: Higher 8 bits and lower 8 bits of 16-bit register

∧: Logical product (AND)

∨: Logical sum (OR)

∨: Exclusive OR

: Inverted data

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

9.1.3 Description of the flag operation field

(Blank): Not affected

0: Cleared to 0

1: Set to 1

×: Set/cleared according to the result

R: Previously saved value is restored

Data Sheet U14590EJ1V0DS00 25

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

9.2 Operations

FlagMnemonic Operand Byte Clock Operation

ZACCY

r, #byt e 3 6 r ← byte

saddr , #by t e 3 6 (addr) ← byte

sfr, #byte 3 6 sfr ← byte

A, r Note 1 24A

← r

r, A Note 1 24r

← A

A, saddr 2 4 A ← (saddr)

saddr, A 2 4 (saddr) ← A

A, sfr 2 4 A ← sfr

sfr, A 2 4 sfr ← A

A, !addr16 3 8 A ← (addr16)

!addr16, A 3 8 (addr16) ← A

PSW, #byte 3 6 PSW ← byte × × ×

A, PSW 2 4 A ← PSW

PSW, A 2 4 PSW ← A × × ×

A, [DE] 1 6 A ← (DE)

[DE], A 1 6 (DE) ← A

A, [HL] 1 6 A ← (HL)

[HL], A 1 6 (HL) ← A

A, [HL + byte] 2 6 A ← (HL + byte)

MOV

[HL + byte], A 2 6 (HL + byte) ← A

A, X 1 4 A ↔ X

A, r Note 2 26A

↔ r

A, saddr 2 6 A ↔ (saddr)

A, sfr 2 6 A ↔ (sfr)

A, [DE] 1 8 A ↔ (DE)

A, [HL] 1 8 A ↔ (HL)

XCH

A, [HL + byte] 2 8 A ↔ (HL + by te)

rp, #word 3 6 rp ← word

AX, saddrp 2 6 AX ← (s addrp)

saddrp, AX 2 8 (saddrp) ← AX

AX, rp Note 3 1 4 AX ← rp

MOVW

rp, AX Note 3 14rp

← AX

XCHW AX, rp Note 3 1 8 AX ↔ rp

Notes 1. Except r = A

2. Except r = A or X

3. Only when rp = BC, DE, HL

Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control

register (PCC).

Data Sheet U14590EJ1V0DS00

26

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

FlagMnemonic Operand Byte Clock Operation

ZACCY

A, #byte 2 4 A, CY ← A + byte × × ×

saddr, #by te 3 6 (saddr), CY ← (s addr) + byte × × ×

A, r 2 4 A ,CY ← A + r × × ×

A, s addr 2 4 A, CY ← A + (saddr) × × ×

A, ! addr16 3 8 A, CY ← A + (addr16) × × ×

A, [HL] 1 6 A, CY ← A + (HL) × × ×

ADD

A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × ×

A, #byte 2 4 A, CY ← A + byte + CY × × ×

saddr, #by te 3 6 (saddr), CY ← (s addr) + byte + CY × × ×

A, r 2 4 A, CY ← A + r + CY × × ×

A, s addr 2 4 A, CY ← A + (saddr) + CY × × ×

A, ! addr16 3 8 A, CY ← A + (addr16) + CY × × ×

A, [HL] 1 6 A, CY ← A + (HL) + CY × × ×

ADDC

A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × ×

A, #byte 2 4 A, CY ← A – byte × × ×

saddr, #by te 3 6 (saddr), CY ← (s addr) – byte × × ×

A, r 2 4 A, CY ← A – r × × ×

A, s addr 2 4 A, CY ← A – (saddr) × × ×

A, ! addr16 3 8 A, CY ← A – (addr16) × × ×

A, [HL] 1 6 A, CY ← A – (HL) × × ×

SUB

A, [HL + byte] 2 6 A, CY ← A – (HL + byte) × × ×

A, #byte 2 4 A, CY ← A – byt e – CY × × ×

saddr, #by te 3 6 (saddr), CY ← (saddr) – byte – CY × × ×

A, r 2 4 A, CY ← A – r – CY × × ×

A, s addr 2 4 A, CY ← A – (saddr) – CY × × ×

A, ! addr16 3 8 A, CY ← A – (addr16) – CY × × ×

A, [HL] 1 6 A, CY ← A – (HL) – CY × × ×

SUBC

A, [HL + byte] 2 6 A, CY ← A – (HL + byte) – CY × × ×

A, #byte 2 4 A ← A ∧ byte ×

saddr, #by t e 3 6 (saddr) ← (s addr) ∧ byte ×

A, r 2 4 A ← A ∧ r×

A, saddr 2 4 A ← A ∧ (saddr) ×

A, !addr16 3 8 A ← A ∧ (addr16) ×

A, [HL] 1 6 A ← A ∧ (HL) ×

AND

A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×

Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control

register (PCC).

Data Sheet U14590EJ1V0DS00 27

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

FlagMnemonic Operand Byte Clock Operation

ZACCY

A, #byte 2 4 A ← A ∨ byte ×

saddr, #by t e 3 6 (saddr) ← (s addr) ∨ byte ×

A, r 2 4 A ← A ∨ r×

A, saddr 2 4 A ← A ∨ (saddr) ×

A, !addr16 3 8 A ← A ∨ (addr16) ×

A, [HL] 1 6 A ← A ∨ (HL) ×

OR

A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×

A, #byte 2 4 A ← A ∨ byte ×

saddr, #by t e 3 6 (saddr) ← (s addr) ∨ byte ×

A, r 2 4 A ← A ∨ r×

A, saddr 2 4 A ← A ∨ (saddr) ×

A, !addr16 3 8 A ← A ∨ (addr16) ×

A, [HL] 1 6 A ← A ∨ (HL) ×

XOR

A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×

A, #byte 2 4 A – byte × × ×

saddr, #by t e 3 6 (saddr) – by te × × ×

A, r 2 4 A – r × × ×

A, saddr 2 4 A – (s addr) × × ×

A, !addr16 3 8 A – (addr16) × × ×

A, [HL] 1 6 A – (HL) × × ×

CMP

A, [HL + byte] 2 6 A – (HL + byte) × × ×

ADDW AX, #word 3 6 AX, CY ← AX + word × × ×

SUBW AX, #word 3 6 AX, CY ← AX – word × × ×

CMPW AX, #word 3 6 AX – word × × ×

r24r

← r + 1 × ×INC

saddr 2 4 (saddr) ← (s addr) + 1 × ×

r24r

← r – 1 × ×DEC

saddr 2 4 (saddr) ← (s addr) – 1 × ×

INCW rp 1 4 rp ← rp + 1

DECW rp 1 4 rp ← rp – 1

ROR A, 1 1 2 (CY, A7 ← A0, Am – 1 ← Am) × 1×

ROL A, 1 1 2 (CY, A0 ← A7, Am + 1 ← Am) × 1×

RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am – 1 ← Am) × 1×

ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1×

Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control

register (PCC).

Data Sheet U14590EJ1V0DS00

28

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

FlagMnemonic Operand Byte Clock Operation

ZACCY

saddr. bit 3 6 (saddr. bit ) ← 1

sfr. bit 3 6 sfr. bit ← 1

A. bit 2 4 A. bit ← 1

PSW. bit 3 6 PSW. bit ← 1×××

SET1

[HL]. bit 2 10 (HL) . bit ← 1

saddr. bit 3 6 (saddr. bit ) ← 0

sfr. bit 3 6 sfr. bit ← 0

A. bit 2 4 A. bit ← 0

PSW. bit 3 6 PSW. bit ← 0×××

CLR1

[HL]. bit 2 10 (HL) . bit ← 0

SET1 CY 1 2 CY ← 11

CLR1 CY 1 2 CY ← 00

NOT1 CY 1 2 CY ← CY ×

CALL !addr16 3 6 (SP – 1) ← (P C + 3)H,(S P – 2) ← (PC + 3)L,

PC ← addr16, SP ← SP – 2

CALLT [addr5] 1 8 (SP – 1) ← (PC + 1)H, (S P – 2) ← (P C + 1)L,

PCH ← (00000000, addr5 + 1),

PCL ← (00000000, addr5),

SP ← SP – 2

RET 1 6 PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI 1 8 PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0

RRR

PSW 1 2 (SP – 1) ← PSW, SP ← SP – 1PUSH

rp 1 4 (SP – 1) ← rpH, (S P – 2) ← rpL,

SP ← SP – 2

PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP

rp 1 6 rpH ← (SP + 1), rpL ← (SP),

SP ← SP + 2

SP, AX 2 8 SP ← AXMOVW

AX, SP 2 6 AX ← SP

!addr16 3 6 PC ← addr16

$addr16 2 6 PC ← PC + 2 + jdisp8

BR

AX 1 6 PCH ← A, PCL ← X

Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control

register (PCC).

Data Sheet U14590EJ1V0DS00 29

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

FlagMnemonic Operand Byte Clock Operation

ZACCY

BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1

BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0

BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1

BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0

saddr. bit , $addr16 4 10 P C ← PC + 4 + jdis p8

if (saddr. bi t) = 1

sfr. bi t, $addr16 4 10 PC ← PC + 4 + jdi sp8 if sf r. bit = 1

A. bit , $addr16 3 8 PC ← PC + 3 + jdi s p8 i f A. bit = 1

BT

PSW. bi t, $addr16 4 10 P C ← PC + 4 + j disp8 if PS W. bit = 1

saddr. bit , $addr16 4 10 P C ← PC + 4 + jdis p8

if (saddr. bi t) = 0

sfr. bi t, $addr16 4 10 PC ← PC + 4 + jdi sp8 if sf r. bit = 0

A. bit , $addr16 3 8 PC ← PC + 3 + j disp8 if A. bi t = 0

BF

PSW. bi t, $addr16 4 10 P C ← PC + 4 + jdisp8 if PSW. bit = 0

B, $addr16 2 6 B ← B – 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16 2 6 C ← C – 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

DBNZ

saddr, $addr16 3 8 (saddr) ← (saddr) – 1, then

PC ← PC + 3 + jdisp8 if(s addr) ≠ 0

NOP 1 2 No Operation

EI 3 6 IE ← 1(Enable Interrupt)

DI 3 6 IE ← 0(Dis abl e Interrupt)

HALT 1 2 Set HALT Mode

STOP 1 2 Set STOP Mode

Remark One instruction clock cycle is one cycle of the CPU clock (fCPU), selected by the processor clock control

register (PCC).

Data Sheet U14590EJ1V0DS00

30

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°

°°

°C)

Parameter Symbol Conditions Ratings Unit

Supply v ol tage VDD, AVDD VDD = A V DD –0.3 to +6.5 V

VI1 Pins ot her than P50 to P 53 –0.3 to VDD + 0. 3 V

With N-ch open drai n –0.3 to +13 V

Input vol tage

VI2 P50 to P53

With an on-chip pull-up resistor –0.3 to VDD + 0.3 V

Output vol tage VO–0.3 t o V DD + 0. 3 V

Per pin –10 mA

Total for all pins

µ

PD78910xA, 78911xA

–30 mA

Per pin –7 mA

Output current, high IOH

Total for all pins

µ

PD78910xA(A),

78911xA(A) –22 mA

Per pin 30 mA

Total for all pins

µ

PD78910xA, 78911xA

160 mA

Per pin 10 mA

Output current, low IOL

Total for all pins

µ

PD78910xA(A),

78911xA(A) 120 mA

Operating ambient temperature TA–40 to +85 °C

Storage tem perature Tstg –65 to +150 °C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14590EJ1V0DS00 31

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

System Clock Oscillator Characteristics

(TA = –40 to +85 °

°°

°C, VDD = 1.8 to 5.5 V)

Resonator Recommended

Circuit Parameter Conditions MIN. TYP. MAX. Unit

Oscillati on f requency (fX)Note 1 VDD = oscillation voltage

range 1.0 5.0 MHzCeramic

resonator

X2X1IC0

C2C1

Oscillation stabilization

timeNote 2 After VDD reaches

oscillation voltage range

MIN.

4ms

Oscillati on f requency (fX)Note 1 1.0 5.0 MHz

VDD = 4.5 to 5.5 V 10 ms

Crystal

resonator

X2X1IC0

C2C1

Oscillation stabilization

timeNote 2 30

X1 input f requency (fX)Note 1 1.0 5.0 MHz

X1 X2

X1 input high-/low-level

width (tXH, tXL)85 500 ns

X1 input f requency (fX)Note 1 VDD = 2.7 to 5. 5 V 1.0 5.0 MHz

External

clock

X1 X2

OPEN

X1 input high-/low-level

width (tXH, tXL)85 500 ns

Notes 1. Indicates only oscillator characteristics. Refer to AC characteristics for instruction execution time.

2. Time required to stabilize oscillation after a reset or STOP mode release. Use the resonator that

stabilizes oscillation during the oscillation wait time.

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines

in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as VSS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14590EJ1V0DS00

32

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Per pin –1 mA

Total for all pins

µ

PD78910xA, 78911xA

–15 mA

Per pin –1 mA

Output current, high IOH

Total for all pins

µ

PD78910xA(A ), 78911xA(A)

–11 mA

Per pin 10 mA

Total for all pins

µ

PD78910xA, 78911xA

80 mA

Per pin 3 mA

Output current, low IOL

Total for all pins

µ

PD78910xA(A ), 78911xA(A)

60 mA

VDD = 2.7 to 5.5 V 0. 7 V DD VDD VVIH1 Pins other than descri bed

below 0.9 VDD VDD V

VDD = 2.7 to 5.5 V 0.7 VDD 12 VWith N-ch open

drain 0.9 VDD VDD V

VDD = 2.7 to 5.5 V 0.7 VDD VDD V

VIH2 P50 to P53

With on-chi p

pull-up resistor 0.9 VDD VDD V

VDD = 2.7 to 5.5 V 0.8 VDD VDD VVIH3 RESET, P20 to P25

0.9 VDD VDD V

VDD = 4.5 to 5.5 V VDD–0.5 VDD V

Input vol tage, high

VIH4 X1, X2

VDD–0.1 VDD V

VDD = 2.7 to 5.5 V 0 0.3 VDD VVIL1 Pins other than descri bed

below 0 0.1 VDD V

VDD = 2.7 to 5.5 V 0 0.3 VDD VVIL2 P50 to P53

0 0.1 VDD V

VDD = 2.7 to 5.5 V 0 0.2 VDD VVIL3 RESET, P20 to P25

0 0.1 VDD V

VDD = 4.5 to 5.5 V 0 0.4 V

Input vol tage, low

VIL4 X1, X2

00.1V

VOH1 VDD = 4.5 to 5.5 V, IOH = –1 mA VDD–1.0 VOutput voltage, hi gh

VOH2 VDD = 1.8 to 5.5 V, IOH = –100

µ

AV

DD–0.5 V

VDD = 4.5 to 5.5 V, IOL = 10 mA

(

µ

PD78910xA, 78911xA) 1.0 V

VDD = 4.5 to 5.5 V, IOL = 3 mA

(

µ

PD78910xA(A ), 78911xA(A)) 1.0 V

VOL1 Pins other

than P50 to

P53

VDD = 1.8 to 5.5 V, IOL = 400

µ

A0.5V

VDD = 4.5 to 5.5 V, IOL = 10 mA

(

µ

PD78910xA, 78911xA) 1.0 V

VDD = 4.5 to 5.5 V, IOL = 3 mA

(

µ

PD78910xA(A ), 78911xA(A)) 1.0 V

Output vol tage, low

VOL2 P50 to P53

VDD = 1.8 to 5.5 V, IOL = 1.6 mA 0.4 V

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14590EJ1V0DS00 33

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

DC Characteristics (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

ILIH1 Pins other than X1, X 2,

or P50 to P53 3

µ

A

ILIH2 X1, X2

VIN = VDD

20

µ

A

Input leak age current,

high

ILIH3 P50 to P53 (N-ch open

drain) VIN = 12 V 20

µ

A

ILIL1 Pins other than X1, X 2,

or P50 to P53 –3

µ

A

ILIL2 X1, X2 –20

µ

A

Input leak age current,

low

ILIL3 P50 to P53 (N-ch open

drain)

VIN = 0 V

–3Note 1

µ

A

Output leak age

current, hi gh ILOH VOUT = VDD 3

µ

A

Output leak age

current, low ILOL VOUT = 0 V –3

µ

A

Software pul l -up

resistor R1VIN = 0 V, for pins other than P 50 to P53 50 100 200 kΩ

Mask option pull-up

resistor R2VIN = 0 V, P50 to P 53 10 30 60 kΩ

VDD = 5.0 V±10%Note 4 1.8 3.2 mA

VDD = 3.0 V±10%Note 5 0.45 0.9 mA

IDD1Note 2 5.0-MHz crystal

oscillati on operat ing

mode (C1 = C2 = 22pF) VDD = 2.0 V±10%Note 5 0.25 0.45 mA

VDD = 5.0 V±10%Note 4 0.8 1.6 mA

VDD = 3.0 V±10%Note 5 0.3 0.6 mA

IDD2Note 2 5.0-MHz crystal

oscillation HALT mode

(C1 = C2 = 22pF) VDD = 2.0 V±10%Note 5 0.15 0.3 mA

VDD = 5.0 V±10% 0.1 10

µ

A

VDD = 3.0 V±10% 0.05 5.0

µ

A

IDD3Note 2 STOP m ode

VDD = 2.0 V±10% 0.05 5.0

µ

A

VDD = 5.0 V±10%Note 4 3.0 5.5 mA

VDD = 3.0 V±10%Note 5 1.65 3.2 mA

Power supply

current

IDD4Note 3 5.0-MHz crystal

oscillati on A /D operating

mode (C1 = C2 = 22pF) VDD = 2.0 V±10%Note 5 1.25 2.7 mA

Notes 1. When pull-up resistors are not connected to P50 to P53 (specified by the mask option) and when port 5

is in input mode, a low-level input leakage current of –30

µ

A (MAX.) flows only for 1 cycle time after a

read instruction has been executed to port 5.

2. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and

AVDD current are not included.

3. The current flowing to the ports (including the current flowing through an on-chip pull-up resistor) is not

included.

4. High-speed mode operation (when processor clock control register (PCC) is set to 00H.)

5. Low-speed mode operation (when PCC is set to 02H).

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14590EJ1V0DS00

34

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

AC Characteristics

(1) Basic operation (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 0.4 8

µ

sCycle time

(minimum instruction

execut i on t i m e)

TCY

1.6 8

µ

s

VDD = 2.7 to 5.5 V 0.1

µ

sTI80 input hi gh-/ l ow-

level width tTIH,

tTIL 1.8

µ

s

VDD = 2.7 to 5.5 V 0 4 MHz

TI80 input f requenc y f TI

0 275 kHz

Interrupt i nput high-

/low-lev el width tINTH,

tINTL

INTP0 to INTP2 10

µ

s

RESET low-level

width tRSL 10

µ

s

CPT20 input high-

/low-lev el width tCPH,

tCPL

10

µ

s

TCY vs VDD

Supply voltage V

DD

[V]

123456

0.1

0.4

0.5

1.0

2.0

10

60

Cycle time T

CY

[ s]

Guaranteed

operation range

µ

Data Sheet U14590EJ1V0DS00 35

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

(2) Serial interface (TA = –40 to +85°

°°

°C, VDD = 1.8 to 5.5 V)

(i) 3-wire serial I/O mode (SCK20...Internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsSCK20 cycle time tKCY1

3200 ns

VDD = 2.7 to 5.5 V tKCY1/2 – 50 nsSCK20 high-/low-

level width tKH1,

tKL1 tKCY1/2 – 150 ns

VDD = 2.7 to 5.5 V 150 nsSI20 setup time

(to SCK20↑)tSIK1

500 ns

VDD = 2.7 to 5.5 V 400 nsSI20 hold t i m e

(from SCK20↑)tKSI1

600 ns

VDD = 2.7 to 5.5 V 0 250 nsSO20 output delay

time from SCK20↓tKSO1 R = 1 k Ω,

C = 100 pFNote 0 1000 ns

Note R and C are the load resistance and load capacitance of the SO output line.

(ii) 3-wire serial I/O mode (SCK20...External clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsSCK20 cycle time tKCY2

3200 ns

VDD = 2.7 to 5.5 V 400 nsSCK20 high-/ l ow-

level width tKH2,

tKL2 1600 ns

VDD = 2.7 to 5.5 V 100 nsSI20 setup time

(to SCK20↑)tSIK2

150 ns

VDD = 2.7 to 5.5 V 400 nsSI20 hold t i m e

(from SCK20↑)tKSI2

600 ns

VDD = 2.7 to 5.5 V 0 300 nsSO20 output delay

time from SCK20↓tKSO2 R = 1 kΩ,

C = 100 pFNote 0 1000 ns

VDD = 2.7 to 5.5 V 120 nsSO20 setup time

(for SS20↓ when

SS20 is used)

tKAS2

400 ns

VDD = 2.7 to 5.5 V 240 nsSO20 disabl e t i m e

(for SS20↑ when

SS20 is used)

tKDS2

800 ns

Note R and C are the load resistance and load capacitance of the SO output line.

(iii) UART mode (Dedicated baud rate generator output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 78125 bpsTransfer rate

19531 bps

Data Sheet U14590EJ1V0DS00

36

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

(iv) UART mode (external clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 800 nsASCK20 cycle time tKCY3

3200 ns

VDD = 2.7 to 5.5 V 400 nsASCK20 high-/low-

level width tKH3,

tKL3 1600 ns

VDD = 2.7 to 5.5 V 39063 bpsTransfer rate

9766 bps

ASCK20 rise/fall time tR,

tF

1

µ

s

Data Sheet U14590EJ1V0DS00 37

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

AC Timing Test Points (excluding X1 input)

0.8V

DD

0.2V

DD

0.8V

DD

0.2V

DD

Test points

Clock Timing

1/f

X

t

XL

t

XH

X1 input V

IH4

(MIN.)

V

IL4

(MAX.)

TI Timing

TI80

t

TIL

t

TIH

1/f

TI

Interrupt Input Timing

INTP0 to INTP2

t

INTL

t

INTH

RESET Input Timing

RESET

t

RSL

Data Sheet U14590EJ1V0DS00

38

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Serial Transfer Timing

3-wire serial I/O mode:

SCK20

t

KLm

t

KCYm

t

KHm

SI20 Input data

t

KSIm

t

SIKm

Output data

t

KSOm

SO20

m = 1, 2

3-wire serial I/O mode (when SS20 is used):

t

KAS2

SO20

SS20

Output data

t

KDS2

UART mode (external clock input):

ASCK20

t

R

t

F

t

KL3

t

KCY3

t

KH3

Data Sheet U14590EJ1V0DS00 39

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

8-Bit A/D Converter Characteristics (

µ

µµ

µ

PD78910xA, 78910xA(A))

(TA = −

−−

−40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 888bit

VDD = 2.7 to 5.5 V ±0.4 ±0.6 %FSR

Overall errorNote1,2

±0.8 ±1.2 %FSR

VDD = 2.7 to 5.5 V 14 100

µ

sConversion time tCONV

28 100

µ

s

Analog input

voltage VIAN 0AV

DD V

Notes 1. Excludes quantization error (±0.2%).

2. It is indicated as a ratio to the full-scale value (%FSR).

10-Bit A/D Converter Characteristics (

µ

µµ

µ

PD78911xA, 78911xA(A))

(TA = −

−−

−40 to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 10 10 10 bit

4.5 V ≤ VDD ≤ 5.5 V ±0.2 ±0.4 %FSR

2.7 V ≤ VDD < 4.5 V ±0.4 ±0.6 %FSR

Overall errorNote1,2

1.8 V ≤ VDD < 2.7 V ±0.8 ±1.2 %FSR

2.7 V ≤ VDD ≤ 5.5 V 14 100

µ

sConversion time tCONV

1.8 V ≤ VDD < 2.7 V 28 100

µ

s

4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR

2.7 V ≤ VDD < 4.5 V ±0.6 %FSR

Zero-sca l e error Note1,2

1.8 V ≤ VDD < 2.7 V ±1.2 %FSR

4.5 V ≤ VDD ≤ 5.5 V ±0.4 %FSR

2.7 V ≤ VDD < 4.5 V ±0.6 %FSR

Full-scale errorNote1,2

1.8 V ≤ VDD < 2.7 V ±1.2 %FSR

4.5 V ≤ VDD ≤ 5.5 V ±2.5 LSB

2.7 V ≤ VDD < 4.5 V ±4.5 LSB

Non-integral li neari ty

errorNote1 INL

1.8 V ≤ VDD < 2.7 V ±8.5 LSB

4.5 V ≤ VDD ≤ 5.5 V ±1.5 LSB

2.7 V ≤ VDD < 4.5 V ±2.0 LSB

Non-differential

linearity errorNote1 DNL

1.8 V ≤ VDD < 2.7 V ±3.5 LSB

Analog input voltage VIAN 0AV

DD V

Notes 1. Excludes quantization error (±0.05%).

2. It is indicated as a ratio to the full-scale value (%FSR).

Data Sheet U14590EJ1V0DS00

40

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°

°°

°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention

supply voltage VDDDR 1.8 5.5 V

Release si gnal

set time tSREL 0

µ

s

Release by RESET 215/fXmsOscillation

stabilization wait

timeNote 1

tWAIT

Release by i nterrupt request Note 2 ms

Notes 1. The oscillation stabilization wait time is the period during which the CPU operation is stopped to avoid

unstable operation at the beginning of oscillation.

2. Selection of 212/fX, 215/fX, or 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time select register.

Remark fX: System clock oscillation frequency

Data Retention Timing (STOP mode release by RESET)

VDD

Data retention mode

STOP mode

HALT mode

Internal reset operation

Operating mode

tSREL

tWAIT

STOP instruction execution

VDDDR

RESET

Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)

V

DD

Data retention mode

STOP mode

HALT mode

Operating mode

t

SREL

t

WAIT

STOP instruction execution

V

DDDR

Standby release signal

(interrupt request)

Data Sheet U14590EJ1V0DS00 41

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

11. CHARACTERISTICS CURVES (REFERENCE VALUES)

IDD vs VDD (System clock: 5.0-MHz crystal resonator)

01 2345678

0.001

0.005

0.01

0.05

0.1

0.5

1.0

5.0

10

PCC = 00H

PCC = 02H

PCC = 00H (HALT mode)

PCC = 02H (HALT mode)

X2

X1

Crystal resonator

5.0 MHz

22 pF 22 pF

(T

A

= 25 ˚C)

Power supply voltage V

DD

(V)

Power Supply Current I

DD

(mA)

Data Sheet U14590EJ1V0DS00

42

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

IDD vs VDD (System clock: 4.0-MHz crystal resonator)

01 2345678

0.001

0.005

0.01

0.05

0.1

0.5

1.0

5.0

10

PCC = 00H

PCC = 02H

PCC = 00H (HALT mode)

PCC = 02H (HALT mode)

X2

X1

Crystal resonator

4.0 MHz

22 pF 22 pF

(TA = 25 ˚C)

Power supply voltage V

DD

(V)

Power Supply Current I

DD

(mA)

Data Sheet U14590EJ1V0DS00 43

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

IDD vs VDD (System clock: 2.0-MHz crystal resonator)

01 2345678

0.001

0.005

0.01

0.05

0.1

0.5

1.0

5.0

10

PCC = 00H

PCC = 02H

PCC = 00H (HALT mode)

PCC = 02H (HALT mode)

X2

X1

Crystal resonator

2.0 MHz

47 pF 47 pF

(T

A

= 25 ˚C)

Power Supply Current I

DD

(mA)

Power supply voltage V

DD

(V)

Data Sheet U14590EJ1V0DS00

44

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

12. PACKAGE DRAWING

S

S

H

J

T

I

G

D

E

F

CB

K

PL

U

N

ITEM

B

C

I

L

M

N

30-PIN PLASTIC SSOP (7.62 mm (300))

A

K

D

E

F

G

H

J

P

30 16

115

A

detail of lead end

M

M

T

MILLIMETERS

0.65 (T.P.)

0.45 MAX.

0.13

0.5

6.1±0.2

0.10

9.85±0.15

0.17±0.03

0.1±0.05

0.24

1.3±0.1

8.1±0.2

1.2

+0.08

−0.07

1.0±0.2

3°+5°

−3°

0.25

0.6±0.15U

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

S30MC-65-5A4-2

Data Sheet U14590EJ1V0DS00 45

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

13. RECOMMENDED SOLDERING CONDITIONS

The

µ

PD78910xA, 78911xA, 78910xA(A), and 78911xA(A) should be soldered and mounted under the following

recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended

below, contact your NEC sales representative.

Table 13-1. Surface Mounting Type Soldering Conditions

µ

PD789101AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789102AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789104AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789111AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789112AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789114AMC-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789101AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789102AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789104AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789111AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789112AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

µ

PD789114AMC(A)-xxx-5A4: 30-pin plastic SSOP (7.62 mm (300))

Soldering Method Soldering Condit i ons Recommended

Condition Symbol

Infrared refl ow Package peak t em perature: 235°C, Ti me: 30 sec . Max. (at 210°C or higher),

Count: three times or l ess IR35-00-3

VPS Pack age peak temperature: 215°C, Tim e: 40 sec. M ax. (at 200° C or hi gher),

Count: three times or l ess VP15-00-3

Wave solderi ng Solder bath tem perature: 260°C Max., Tim e: 10 sec. M ax., Count : once,

Preheating t em perature: 120°C Max. (pack age surface t em perature) WS60-00-1

Partial heating Pin temperature: 300° C M ax., Tim e: 3 sec. Max. (per pi n row) –

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14590EJ1V0DS00

46

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the

µ

PD78910xA,

µ

PD78911xA,

µ

PD78910xA(A), and

µ

PD78911xA(A).

Language Processing Software

RA78K0SNotes 1, 2, 3 Assembler package common to 78K/0S S eri es

CC78K0SNotes 1, 2, 3 C compiler package com m on to 78K/0S S eri es

DF789136Notes 1, 2, 3 Device file for

µ

PD789104A, 789114A Subseries

Flash Memory Writing Tools

Flashpro lIl

(Model number: FL-PR3Note 4,

PG-FP3)

Dedicated f l ash programmer for on-chip flash memory

FA-30MCNote 4 Flash memory wri t i ng adapter

Debugging Tools (1/2)

IE-78K0S-NS

In-circ ui t emulator In-circ ui t emulator serves t o debug hardware and software when dev el opi ng appl i cation systems

using a 78K/ 0S Series product. I t supports the ID78K0S-NS integrated debugger. Used in

combinat i on wi th an AC adapter, em ul ation probe, and int erface adapter connecting to the host

machine.

IE-70000-MC-PS-B

AC adapter Adapter us ed t o supply power f rom a power out l et of 100 V A C t o 240 V AC.

IE-70000-98-IF-C

Interface adapter Adapter when PC-9800 series PC (exc ept notebook t ype) is used as the IE -78K0S-NS hos t

machine (C bus supported).

IE-70000-CD-IF-A

PC card interface PC card and int erface cable when notebook PC is used as t he IE-78K0S -NS host mac hi ne

(PCMCIA socket supported).

IE-70000-PC-IF-C

Interface adapter Adapter when using an I B M PC/AT™ or c om pat i bl e as the IE -78K0S-NS hos t m achine.

IE-70000-PCI-IF

Interface adapter Adapter when using PC that incl udes a PCI bus as the IE -78K 0S-NS host m achine.

IE-789136-NS-EM1

Emulat i on board Board f or em ul ation of the peri pheral hardware peculiar to a device. Used in combi nation with

an in-circ ui t emulator.

NP-36GSNote 4 Board used t o connect t he i n-circuit em ul ator to the t arget system. For a 30-pin plastic SSOP

(MC-5A4 ty pe), used in c om bi nation with NGS -30.

NGS-30Note 4

Conversion socket Conversion socket used to c onnect the NP -36GS to the target system board designed to m ount

a 30-pin plast i c SSOP (M C-5A 4 type).

Notes 1. PC-9800 series (Japanese Windows™) based

2. IBM PC/AT or compatibles (Japanese/English Windows) based

3. HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), or NEWS™ (NEWS-OS™)

based.

4. Products made by Naito Densei Machida Mfg. Co., Ltd. (Phone: +81-44-822-3813). Contact an NEC

distributor regarding the purchase of these products.

Remark RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789136.

Data Sheet U14590EJ1V0DS00 47

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Debugging Tools (2/2)

SM78K0SNotes 1, 2 System sim ul ator common to 78K/0S S eri es

ID78K0S-NSNotes 1, 2 Int egrat ed debugger common to 78K/0S Seri es

DF789136Notes 1, 2 Device file for

µ

PD789104A, 789114A Subseries

Real-time OS

MX78K0SNotes 1, 2 OS for 78K/0S Series

Notes 1. PC-9800 series (Japanese Windows) based.

2. IBM PC/AT or compatibles (Japanese/English Windows) based.

Data Sheet U14590EJ1V0DS00

48

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

APPENDIX B RELATED DOCUMENTS

Documents Related to Devices

Document No.

Document Nam e Japanese English

µ

PD789101A, 102A , 104A, 111A , 112A, 114A, 101A (A), 102A(A), 104A(A), 111A (A),

112A(A), 114A (A) Data Sheet U14590J This manual

µ

PD78F9116A Data S heet To be prepared To be prepared

µ

PD789104A, 789114A , 789124A, 789134A S ubseries Us er’ s Manual To be prepared To be prepared

78K/0S S eri es User’s M anual Instruc tion U11047J U11047E

78K/0, 78K/0S Seri es Application Note Fl ash Memory Wri te U14458J U14458E

Documents Related to Development Tools (User’s Manuals)

Document No.

Document Nam e Japanese English

Operation U11622J U11622E

Assembly Language U11599J U11599E

RA78K0S Assembler Pac kage

Structured Ass em bl y

Language U11623J U11623E

Operation U11816J U11816ECC78K0S C Compi l e r

Language U11817J U11817E

SM78K0S S ystem Simulator Wi ndows Based Reference U11489J U11489E

SM78K S eri es Sys tem Sim ul at or External Parts Us er Open

Interface Speci f i cations U10092J U10092E

ID78K0S-NS Integrated Debugger Windows Based Reference U12901J U12901E

IE-78K0S -NS In-ci rc ui t Emulat or U13549J U13549E

IE-789136-NS-E M1 Emulat i on Board U14363J To be prepared

Documents Related to Embedded Software (User’s Manuals)

Document No.

Document Nam e Japanese English

78K/0S S eri es OS MX 78K 0S Fundam ental U12938J U12938E

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14590EJ1V0DS00 49

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Other Related Documents

Document No.

Document Nam e Japanese English

SEMI CONDUCT ORS SELECTI ON GUIDE Products & P ac kages (CD-ROM) X13769X

Semic onductor Device Mounting Technology Manual C10535J C10535E

Quality Grades on NEC Semi conductor Dev i ces C11531J C11531E

NEC Semiconduc tor Device Reliabilit y/Quality Control Sys t em C10983J C10983E

Guide to Prev ent Damage for Sem i conductor Devices by Elec t rostatic Disc harge (E SD) C11892J C11892E

Guide to Microcomput er-Rel at ed Products by Third Party U11416J −

Caution The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14590EJ1V0DS00

50

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

EEPROM is a trademark of NEC Corporation.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or

other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of SONY Corporation.

Data Sheet U14590EJ1V0DS00 51

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Tel: 91-504-2787

Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division

Rodovia Presidente Dutra, Km 214

07210-902-Guarulhos-SP Brasil

Tel: 55-11-6465-6810

Fax: 55-11-6465-6829

J99.1

µ

µµ

µ

PD789101A,102A,104A,111A,112A,114A,101A(A),102A(A),104A(A),111A(A),112A(A),114A(A)

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8