SCLS567A − JANUAR Y 2004 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−40°C to 105°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product-Change Notification
DQualification Pedigree†
D2-V to 5.5-V VCC Operation
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupports Mixed-Mode Voltage Operation on
All Ports
description/ordering information
The SN74LV86A is a quadruple 2-input exclusive-OR gate designed for 2-V to 5.5-V VCC operation.
This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function
Y = A ę B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION
TAPACKAGE‡ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 105°CTSSOP − PW Tape and reel SN74LV86ATPWREP LV86AEP
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
OUTPUT
Y
L L L
LHH
HLH
H H L
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
PW PACKAGE
(TOP VIEW)
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCLS567A − JANUAR Y 2004 − REVISED MAY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
1
1A 2
1B 1Y
3
4
2A 5
2B 2Y
6
9
3A 10
3B 3Y
8
12
4A 13
4B 4Y
11
=1
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
= 1
Exclusive OR
These are five equivalent exclusive-OR symbols valid for an ’LV86A gate in positive logic; negation can be
shown at any two ports.
= 2k 2k + 1
Logic-Identity Element Even-Parity Element Odd-Parity Element
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3) 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS567A − JANUAR Y 2004 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.7
V
VIH High-level input voltage VCC = 3 V to 3.6 V VCC ×0.7 V
VCC = 4.5 V to 5.5 V VCC ×0.7
VCC = 2 V 0.5
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V VCC ×0.3
V
VIL Low-level input voltage VCC = 3 V to 3.6 V VCC ×0.3 V
VCC = 4.5 V to 5.5 V VCC ×0.3
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 2 V −50 µA
IOH
High-level output current
VCC = 2.3 V to 2.7 V −2
IOH High-level output current VCC = 3 V to 3.6 V −6 mA
VCC = 4.5 V to 5.5 V −12
mA
VCC = 2 V 50 µA
IOL
Low-level output current
VCC = 2.3 V to 2.7 V 2
IOL Low-level output current VCC = 3 V to 3.6 V 6mA
VCC = 4.5 V to 5.5 V 12
mA
VCC = 2.3 V to 2.7 V 0 200
∆t/∆vInput transition rise or fall rate VCC = 3 V to 3.6 V 0 100 ns/V
∆t/∆v
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V 0 20
ns/V
TAOperating free-air temperature −40 105 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
IOH = −50 µA2 V to 5.5 V VCC−0.1
VOH
IOH = −2 mA 2.3 V 2
V
VOH IOH = −6 mA 3 V 2.48 V
IOH = −12 mA 4.5 V 3.8
IOL = 50 µA2 V to 5.5 V 0.1
VOL
IOL = 2 mA 2.3 V 0.4
V
VOL IOL = 6 mA 3 V 0.44 V
IOL = 12 mA 4.5 V 0.55
IIVI = 5.5 V or GND 0 to 5.5 V ±1µA
ICC VI = VCC or GND, IO = 0 5.5 V 20 µA
Ioff VI or VO = 0 to 5.5 V 0 5 µA
CiVI = VCC or GND 3.3 V 1.4 pF
SCLS567A − JANUAR Y 2004 − REVISED MAY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX
MIN
MAX
UNIT
tpd A or B Y CL = 50 pF 10.5 22.6 1 26.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX
MIN
MAX
UNIT
tpd A or B Y CL = 50 pF 7.4 14.5 1 16.5 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25°C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX
MIN
MAX
UNIT
tpd A or B Y CL = 50 pF 5.3 8.8 1 10 ns
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.1 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 3.1 V
VIH(D) High-level dynamic input voltage 2.31 V
VIL(D) Low-level dynamic input voltage 0.99 V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
3.3 V 8.4
pF
C
pd
Power dissipation capacitance
C
L
= 50 pF,
f = 10 MHz
5 V 8.8
pF
SCLS567A − JANUAR Y 2004 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. t
PHL
and t
PLH
are the same as t
pd
.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
V
CC
RL = 1 kΩ
GND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LV86ATPWREP ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/04694-01XE ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV86A-EP :
•Catalog: SN74LV86A
•Automotive: SN74LV86A-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LV86ATPWREP TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LV86ATPWREP TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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