A8437
Description
The Allegro® A8437 Xenon photoflash charger IC is designed
to meet the needs of ultra-low power, small form factor cameras,
particularly camera-phones.
The charge current time is adjustable by setting the charge
current limit from 0.4 to 1.2 A maximum. By using primary-
side voltage sensing, the need for a secondary-side resistive
voltage divider is eliminated. This has the additional benefit
of reducing leakage currents on the secondary side of the
transformer. To extend battery life, the A8437 features very
low supply current draw—typically 0.1 A in shutdown mode
and 10 A in standby mode.
The A8437 has a flash dual trigger IGBT driver and flash
interlock to increase the device noise immunity. The IGBT
driver also has separate source and sink connections, for
flexibility in controlling IGBT rise and fall times. The charge
and trigger voltage logic thresholds are set at 1.1 VHI (min)
to support applications implementing low voltage control
logic.
The A8437 is available in a 10-pin, 3 mm × 3 mm DFN/MLP
package with exposed pad for enhanced thermal performance.
For an even smaller PCB footprint, a wafer-level chip scale
package (WLCSP) option is available.
Applications include:
Mobile phone flash
Digital and film camera flash
A8437-DS, Rev. 1
Features and Benefits
▪ Low quiescent current draw (0.1 μA in shutdown mode)
▪ Primary-side output voltage sensing; no resistor divider
required
▪ User-adjustable current limit from 0.4 to 1.2 A
▪ 1.1 V logic (VHI(min)) compatibility
▪ Integrated IGBT driver with separate sink and source (CG
package) or common sink/source (EJ package)
▪ Flash dual trigger with interlock for increased noise
immunity
Optimized for mobile phone, 1-cell Li+ battery applications
No primary-side Schottky diode needed
Zero-voltage switching for lower loss
>75% efficiency
Optional regulation feature to maintain the output voltage
Charge complete indication
Integrated 40 V DMOS switch
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
Packages:
Typical Application
Application 1. Typical application
without output voltage regulation.
Note: Application must
periodically restart the charging
cycle to recover lost charge on
the output capacitor.
+
SW
1 : 10
ISET
VIN
Control
Block
CHARGE
DONE
GND
GSOURCE
TRIGGER1
IGBT Driver
IGBT Gate
GSINK
VPULLUP
REG
Connect
to VIN
VOUT Detect
ISW sense
DONE
RSET
Battery Input
2.3 to 5.5 V
C2 COUT
100 μF
315 V
C1
100 k
TLIM
TRIGGER2
12-ball WLCSP
1.205 mm × 1.635 mm
0.5 nominal overall height
(Package CG)
+
SW
1 : 10
ISET
VIN
Control
Block
CHARGE
DONE
GND
TRIGGER1
VIN
IGBT Driver
IGBT Gate
GATE
VPULLUP
TRIGGER2
REG
Connect
to VIN
VOUT Detect
DONE
RSET
C2 COUT
100 μF
315 V
C1
100 k
ISW sense
Battery Input
2.3 to 5.5 V
CG Package EJ Package
10-contact DFN/MLP
3 mm × 3 mm
0.75 nominal overall height
(Package EJ)
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Package Packing
A8437ECGLT*12-ball WLCSP Tape and reel, 4000 pieces per reel
A8437EEJTR-T 10-contact DFN/MLP Tape and reel, 1500 pieces per reel
*Contact Allegro for additional ordering information.
Thermal Characteristics
Characteristic Symbol Test Conditions1Value Units
Package Thermal Resistance2RJA
CG package, on 4-layer PCB based on JEDEC standard 100 ºC/W
EJ package, on 2-layer PCB with 0.88 in.2 area of 2 oz. copper
each side, based on JEDEC standard 65 ºC/W
EJ package, on 4-layer PCB based on JEDEC standard 45 ºC/W
1Additional thermal information available on Allegro website.
2CG results preliminary.
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
SW Pin VSW
DC voltage.
(VSW is self-clamped by internal active clamp
and is allowed to exceed 40 V during flyback
spike durations. Maximum repetitive energy
during flyback spike: 0.5 J at frequency
400 kHz.)
–0.3 to 40 V
VIN Pin VIN –0.3 to 6.0 V
CHARGE, TRIGGERx, ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Pins Care should be taken to limit the current when
–0.6 V is applied to these pins. –0.6 to VIN + 0.3 V V
Remaining Pins –0.3 to VIN + 0.3 V V
Operating Ambient Temperature TARange E –40 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
VIN SW
GND
OCP
ISET
REG
CHARGE
0.96 V
1.2 V
VDSref
ton(max)
toff(max)
DONE
GATE
EJ Package CG Package
VIN VIN
TRIGGER1
TRIGGER2
DMOS
VSW – VBAT
Q
QS
R
Q
QS
R
DCM
Detector
ISET Buffer
H m L
Triggered Timer
Control Logic
18 s
18 sEnable
GND
GSOURCE
GSINK
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Name Number Function
CG EJ
ISET C4 1 Sets the maximum switch current; connect an external resistor to GND to set the
desired peak current
GATE – 2 IGBT gate drive – sink/source
GSOURCE B3 – IGBT gate drive – source
GSINK C3 – IGBT gate drive – sink
VIN C2 3 Input voltage; connect to a 2.3 to 5.5 V bias supply
GND C1 4 Ground connection
CHARGE B1 5 Pull high to initiate charging; pull low to enter low-power standby mode
TRIGGER2 B2 6 IGBT input trigger 2
SW A1 7 Drain connection of internal power MOSFET switch; connect to transformer
TRIGGER1 A2 8 IGBT input trigger 1
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯ A3 9 Pulls low when output reaches target value and CHARGE pin is high; goes high dur-
ing charging or whenever CHARGE pin is low
TLIM A4 – For production test only; connect to GND on PCB
REG B4 10
Output voltage regulation pin; connect to external resistor and capacitor to regulate
output voltage, or connect to VIN pin to disable regulation (see Output Regulation
section for details)
EP n.a. – Exposed pad for enhanced thermal dissipation; not connected electrically
Terminal List Table
(Contacts Down Views)
10
9
8
7
6
1
2
3
4
5
REG
DONE
TRIGGER1
SW
TRIGGER2
ISET
GATE
VIN
GND
CHARGE
EP
Pin-out Diagrams
CG Package EJ Package
Orientation mark
on ball side
A1
B1
C1
A2
B2
C2
A3
B3
C3
A4
B4
C4
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS typical values valid at VIN = 3.6 V, RSET = 33 k, ISWlim = 1.0 A, and TA=25°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
VIN Voltage Range VIN 2.3 – 5.5 V
UVLO Enable Threshold VINUV VIN rising – 2.05 2.2 V
UVLO Hysteresis VINUVhys – 150 – mV
VIN Supply Current IIN
Shutdown (CHARGE = 0 V,
TRIGGER1 and TRIGGER2 = 0 V) – 0.01 0.5 A
Charging complete, regulation disabled (REG = VIN) – 10 50 A
Charging complete, regulation enabled – 0.5 – mA
Charging (CHARGE = VIN,
TRIGGER1 and TRIGGER2 = 0 V) –2 –mA
Current Limits
Switch Current Limit1ISWlimMAX Maximum, RSET = 26.7 k1.08 1.2 1.32 A
ISWlimMIN Minimum, RSET = 85 k– 0.4 – A
SW / ISET Current Ratio ISW/ISET RSET = 33 k, CHARGE = high – 28 – kA/A
ISET Pin Voltage While Charging VSET RSET = 33 k, CHARGE = high – 1.2 – V
ISET Pin Internal Resistance RSET(INT) – 1000 –
Switch On-Resistance RSWDS(on) VIN = 3.6 V, ID = 800 mA, TA = 25°C – 0.25 –
Switch Leakage Current2ISWlk
VSW = VIN(max), over temperature range – – 2 A
Combined VIN and SW leakage current at TA=25°C
VIN= 5.5 V in Shutdown – – 0.5 A
CHARGE Input Current ICHARGE VCHARGE = VIN – 36 – A
CHARGE Input Voltage2VCHARGE
High, over input supply range 1.1 – – V
Low, over input supply range – – 0.4 V
CHARGE Pull-Down Resistor Value RCHPD – 100 – k
CHARGE ON/OFF Delay tCH – 20 – us
Maximum Switch-Off Timeout toffMAX – 18 – s
Maximum Switch-On Timeout tonMAX – 18 – s
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Output Leakage Current2IDONElk ––1A
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
Output Low Voltage2VDONEL 32 A into ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
pin – – 100 mV
Output Comparator Trip Voltage2VOUTTRIP Measured as VSW – VIN 31 31.5 32 V
Output Comparator Overdrive VOUTOV Pulse width = 200 ns (90% to 90%) – 200 400 mV
Minimum dV/dt for ZVS Comparator dV/dt Measured at SW pin – 20 – V/s
Regulation
REG Voltage When Charging Completes VREG(H) CHARGE = high, at ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
low transition 1.15 1.2 1.25 V
REG Voltage Threshold for Regulation VREG(L) CHARGE = high, at ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
= low – 0.96 – V
REG Output Current Drive Capability IREG CHARGE = high, at ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
= high, VSW – VIN = 30 V,
VREG = 1.0 V – 50 – A
REG Leakage Current While Not Charging IREGlk CHARGE = high, at ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
= low, VREG = 1.2 V – 0.1 – A
IGBT Driver
TRIGGER, TRIGGER2 Input Voltage2VTRIG(H) Input = logic high, over input supply range 1.1 – – V
VTRIG(L) Input = logic low, over input supply range – – 0.4 V
TRIGGER, TRIGGER2 Pull-Down Resistor RTRIGPD – 100 – k
GSOURCE Resistance to VIN3 R
SrcDS(on) VIN = 3.6 V, VGSOURCE =1.8 V – 5 –
GSINK Resistance to GND3RSnkDS(on) VIN = 3.6 V, VGSINK = 1.8 V – 6 –
Propagation Delay (Rising) tDr
GSOURCE and GSINK tied together, measurement
taken at pin; RGATE = 12 , CL= 6500 pF, VIN
= 3.6 V
–30–ns
Propagation Delay (Falling) tDf –30–ns
Output Rise Time tr–70–ns
Output Fall Time tf–70–ns
1Current limit guaranteed by design and correlation to static test. Refer to application section for peak current in actual circuits.
2Specifications over the range TA= –40°C to 85°C; guaranteed by design and characterization.
3GSOURCE and GSINK tied together (GATE pin) in EJ package.
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The two TRIGGER signals are internally ANDed together. As
shown in the timing diagram, below, triggering is prohibited dur-
ing the initial charging process. This prevents premature firing
of the flash before the output capacitor has been charged to its
target voltage. Refer to the section IGBT Gate Driver Interlock
for details.
Timing and IGBT Interlock Function
VOUT
CHARGE
VIN
TRIGGER
IGBTDRV
SW
DONE ABCD
Case Description
ATRIGGER pulse arrives before first charging process is finished (CHARGE and
¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯
pins are both high). IGBTDRV is disabled in this case.
BArrives during regulation mode, while not refreshing. IGBTDRV is enabled.
Charging resumes once TRIGGER is low again.
C
Arrives during regulation mode, while refreshing. Charging is stopped after
present cycle. IGBTDRV is enabled. Charging resumes after TRIGGER is low
again.
DArrives while IC is in low-power Standby mode (CHARGE pin is low).
IGBTDRV is always enabled in this case.
IGBT Drive Timing Definition
GSOURCE,
GSINK,
or GATE
TRIGGER
tDr trtDf tf
50%
10%
90%
50%
10%
90%
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Symbol Parameter Units/Division
C1 VOUT 50 V
C2 VBAT 1 V
C3 IIN 100 mA
t time 200 ms
Conditions Parameter Value
VBATT 3.6 V
COUT 20 F
t
C1
C2
C3
Conditions Parameter Value
RSET 39 k
ISWlim 0.9 A
IIN
VOUT
VBAT
t
Conditions Parameter Value
RSET 33.2 k
ISWlim 1.0 A
IIN
VOUT
VBAT
C1
C2
C3
t
IIN
VOUT
Conditions Parameter Value
RSET 26.7 k
ISWlim 1.2 A
VBAT
C1
C2
C3
C1
C2
C3
C1
C2
C3
C1
C2
C3
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Charge Time versus Battery Voltage
Transformer L
p
= 8 H, N = 10.2; C
OUT
= 20 F / 330 V UCC; T
A
=25°
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
BAT
(V)
Time (s)
55 0.65
45 0.8
39 0.9
33.2 1.0
26.7 1.2
R
SET
(k)
I
P
(A)
COUT= 20 F. For larger or smaller capacitances, charging time
scales proportionally.
Efficiency versus Battery Voltage
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
2.02.53.03.54.04.55.05.56.0
V
BAT
(V)
Efficiency (%)
Transformer Lp= 8 H, N = 10.2; COUT= 20 F / 330 V UCC; TA=25°
55 0.65
45 0.8
39 0.9
33.2 1.0
26.7 1.2
RSET
(k)
IP
(A)
Special low-profile transformer with relatively low inductance
(Lp= 8 H) and high winding resistance (Rp = 0.37 ). Higher efficien-
cy can be achieved by using transformers with higher Lp, which reduces
switching frequency and therefore switching loses, and lower resistance,
which reduces conduction losses.
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VBAT (V)
IIN (A)
Average Input Current versus Battery Voltage
XFM L
p
= 8 H, N = 10.2, C
OUT
= 20 F 330 V UCC, T
A
=25°
55 0.65
R
SET
(k)
I
P
(A)
45 0.8
39 0.9
33.2 1.0
26.7 1.2
An increase in ISWlim with respect to VBAT actually keeps the average input current
roughly constant throughout the battery voltage range. Normally, if ISWlim is kept
constant, the average current will drop as VBAT goes higher.
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
General Operation Overview
The CHARGE pin enables the part and starts charging.
The D
¯¯
¯
¯
¯
O
¯
¯
¯
N
¯
¯
E
¯
open-drain indicator is pulled low when
CHARGE is high and target output voltage is reached.
Charging is reinitiated when the REG pin voltage falls
below the regulation threshold. Pulling the CHARGE
pin low stops charging and forces the chip into low-
power standby mode.
Output Voltage Regulation
When the REG pin is connected to VIN, the A8437
stops charging the output voltage after the reflected
voltage (VSW – VIN) reaches 31.5 V. In this mode,
charging can be reinitiated by cycling the CHARGE
signal through a low to high transition.
The A8437 can also be used to regulate output voltage
within a predetermined window. In this mode, con-
nect a capacitor, CREG, and resistor, RREG, from the
REG pin to GND (refer to the figure Application 3).
When CHARGE is held high, the voltage monitoring
circuit of the A8437 is always active, irrespective of
the REG pin voltage level.
Voltage Regulation Using Predicitive Droop The A8437
uses a technique called Predictive Droop for regulat-
ing the output capacitor voltage after the completion
of a charging cycle. When the target output voltage
is reached, the converter stops charging and output
capacitor voltage droops due to leakage current. An
external resistor and capacitor connected from the
REG pin to ground will provide an RC discharge time
constant. This time constant can be selected to mirror
the droop rate of the output capacitor. When voltage at
the REG pin drops to 80% of the reference value, the
converter starts charging again and brings the output
capacitor back to target voltage again.
The time required for an RC network to discharge
from V0 to VT is given by:
T = R × C × ln (V0
/ VT) . (1)
For example, if C = 10 F, R = 10 M and V0
/ VT =
1.25, then T = 22 seconds. Assuming that the RC-dis-
charge characteristic of the output capacitor matches
that at the REG pin, we can predict that the output
voltage has drooped 20%, and therefore it is time to
recharge the output capacitor.
By implementing a Predictive Droop technique, no
additional leakage paths are introduced on the second-
ary side, which helps to keep power losses to a mini-
mum. By intentionally making the RC discharge time
constant of the REG pin shorter than that of the output
capacitor, we can regulate the output voltage to a win-
dow tighter than the default 20% hysteresis.
Voltage Regulation Using Direct Sensing If direct sens-
ing from the secondary side is desired, connect the
REG pin to a resistor divider network across the out-
put capacitor to enable output regulation. In this case,
the charging cut-off is still controlled by primary side
sensing (charging stops when reflected voltage reaches
31.5 V), but the regulation threshold is controlled by
the secondary side sensing. When the CHARGE pin
is high, and the sensed output voltage falls below the
lower VREG threshold, the flyback converter charges
the output capacitor again until the primary side sens-
ing stops further charging. This cycle repeats till the
CHARGE pin is pulled low.
The benefit of this method is that a lower output volt-
age can be selected independently, simply by chang-
ing the resistor divider ratio. For example, given
R1=10 M, R2= 33.2 k, and VREG(L)= 0.96 V, then:
VOUT(Low) = VREG(L) × ( R1/ R2 + 1) = 290 V . (2)
Selection of Switching Current Limit
The A8437 features continuously adjustable peak
switching current between 0.4 and 1.2A. This is done
Application Information
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
by selecting the value of an external resistor RSET,
connected from the ISET pin to GND, which deter-
mines the ISET bias current, and therefore the switch-
ing current limit, ISWlim.
To the first order approximation, ISWlim is related to
ISET and RSET according to the following equations:
ISWlim = ISET × K = VSET / RSET × K , (3)
where K = 28000 when battery voltage is 3.6 V.
In real applications, the actual switching current
limit is affected by input battery voltage, and also the
transformer primary inductance, Lp. If necessary, the
following expressions can be used to determine ISWlim
more accurately:
ISET = VSET / (RSET + RSET(INT) – K × RGND(INT)
), (4)
where:
R
SET(INT) is the internal resistance of the ISET pin
(1 k typical),
R
GND(INT) is the internal resistance of the bonding
wire for the GND pin (27 m typical), and
K = (K + VIN × K), with K = 24350 and K
1040 at TA = 25°C. Then,
ISWlim = ISET × K + VBAT / LP × tD , (5)
where tD is the delay in SW turn-off (0.1 s typical).
The chart at the bottom of the page can be used to
determine the relationship between RSET and ISWlim at
various battery voltages.
Peak Current Limit versus ISET Resistance
VIN = VBAT, XFM Lp = 8 H, TA=25°C
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
25 30 35 40 45 50 55 60 65 70 75 80 85 90
R
SET
(k)
I
SWlim
(A)
V
IN
= 5.5 V
V
IN
= 4.5 V
V
IN
= 3.6 V
V
IN
= 3.0 V
V
IN
= 2.3 V
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Smart Current Limit (Optional)
With the help of some simple external logic, the
user can change the charging current according to
the battery voltage. For example, assume that ISET is
normally 36 A (for ISWlim = 1.0 A). Referring to the
following illustration, when the battery voltage drops
RSET
ISET
BL RBL
below 2.5 V, the signal at BL (battery-low) goes high.
The resistor RBL, connecting BL to the ISET pin,
then injects 10 A into RSET. This effectively reduces
ISET current to 26 A (for ISWLIM = 0.73 A). A disad-
vantage of the above method is that the 10 A current
is always flowing whenever the BL signal goes high.
Timer Mode and Fast Charging Mode
The A8437 achieves fast charging times and high effi-
ciency by operating in discontinuous conduction mode
(DCM) through most of the charging process. The
relationship of Timer Mode and Fast Charging Mode
is shown in the following figure.
Timer Mode
Fast Charging Mode
I
IN
V
BAT
V
OUT
t =200 ms/div; VOUT =50 V/div; VBAT =1 V/div.; IIN =100 mA/div.
VBAT =3.6 V; COUT =20 μF/330 V; RSET=46 kΩ (ISWlim≈0.75 A)
The IC operates in Timer Mode when beginning to
charge a completely discharged photoflash capaci-
tor, usually when the output voltage, VOUT, is less
than approximately 15 to 20 V. Timer Mode is a fixed
period, 18 s, off-time control. One advantage of
having Timer Mode is that it limits the initial battery
current surge and thus acts as a “soft-start.” A time-
expanded view of a Timer Mode interval is shown in
the following figure.
ISW
VBAT
VOUT
VSW
VOUT≤ 14 V; t =2 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
As soon as a sufficient voltage has built up at the
output capacitor, the IC enters Fast-Charging Mode.
In this mode, the next switching cycle starts after the
secondary side current has stopped flowing, and the
switch voltage has dropped to a minimum value. A
proprietary circuit is used to allow minimum-voltage
switching, even if the SW pin voltage does not drop to
0 V. This enables Fast-Charging Mode to start earlier
than previously possible, thereby reducing the overall
charging time. Minimum-voltage switching is shown
in the following figure.
ISW
VBAT
VOUT
VSW
VOUT ≥ 15 V; t =1 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
During Fast-Charging Mode, when VOUT is high
enough (over 50 V), true zero-voltage switching
Timer Mode
Minimum Voltage
Switching
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
(ZVS) is achieved. This further improves efficiency
as well as reduces switching noise. A ZVS interval is
shown in the following figure.
ISW
VBAT
VOUT
VSW
ISW
VBAT
VOUT
VSW
VOUT = 120 V; t =0.2 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
IGBT Gate Driver Interlock
The TRIGGER1and TRIGGER2 pins are ANDed
together inside the IC to control the IGBT gate driver.
If only one trigger signal is needed, tie both trigger
pins together and use as a single input.
Triggering is disabled (locked) during charging. This
is to prevent switching noise from interfering with the
IGBT driver. After the CHARGE pin goes high (at the
start of a charging cycle), the IC must wait for comple-
tion of the charging cycle (D
¯¯
¯
¯
¯
O
¯
¯
¯
N
¯
¯
E
¯
goes low) before
triggering can be enabled, according to the following
chart:
Conditions Resulting State
CHARGE ¯
D
¯
¯
O
¯
¯
N
¯
¯
E
¯ IGBT Gate Driver
Low Don’t Care Enabled
High High Disabled
High Low Enabled
After completion of the charging cycle, if the charge
pin is kept high and REG is enabled, the IC will
periodically recharge the output. If a trigger signal
comes in during a recharge cycle, charging will be
halted immediately and the IGBT gate driver will be
allowed to fire after a delay of less than 1 s. Charging
resumes after the trigger signal is removed.
Red Eye Reduction
The IGBT gate driver is always enabled when
CHARGE is low. If the charge pin is disabled before
sufficient voltage has built up on the output capacitor,
the flash may not fire. In the case of red-eye reduction
flashes, it is recommended to keep the CHARGE pin
low until completion of triggering pulses. This ensures
that the IGBT gate driver will remain enabled regard-
less of the D
¯¯
¯
¯
¯
O
¯
¯
¯
N
¯
¯
E
¯
state.
Zero Voltage
Switching
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ambient Light Sensing
Ambient Light Sensing (ALS) can be easily imple-
mented for the A8437 using the TRIGGER2 pin plus
three external components. This configuration is
shown in the figure below.
The phototransistor current is proportional to the
intensity of the light that it receives. When there is
sufficient ambient light (for example, during daylight
outdoor photographing), a current of about 30 A
can flow through the phototransistor. This forces the
voltage at TRIGGER2 pin to fall to 0.8 V or lower,
so it prohibits TRIGGER1 from firing the flash. The
exact threshold of ambient light required to prohibit
flash firing can be adjusted by RTGR1. The smaller this
resistance, the brighter the ambient light must be to
prohibit flash firing.
When ambient conditions are dark, the current flow-
ing through the phototransistor is in less than 1 A.
Because the TRIGGER2 pin is biased at 1.4 V or
+
SW
1 : 10
ISET
VIN
Control
Block
TLIM
CHARGE
DONE
GND
GSOURCE
TRIGGER1
VIN
IGBT Driver
IGBT Gate
GSINK
TRIGGER2
REG
Connect
to VIN
VOUT Detect
ISW sense
DONE
RSET
Battery Input
2.3 to 5.5 V
Bias Voltage
2.5 to 5.5 V
C2 COUT
100 μF
315 V
C1
A
A
RTGR1
100 k
PNZ121S
Phototransistor
It is recommend to use a regulated system voltage for the bias.
If battery voltage is used, the ALS sensitivity will vary with
battery voltage, and there would be a small leakage current
even when the camera is turned off.
CTGR1
1 F
ALS typical application (CG package shown)
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
higher, TRIGGER1 is allowed to activate the IGBT
gate driver (and thereby fire the flash).
The capacitor CTGR1 and resistor RTGR1 form an
integrator for light exposure. When the flash fires,
bright light bounces back from subject and enters the
phototransistor. In example A below, the flash termi-
nates after just 30 s, without fully discharging the
photoflash capacitor.
If the subject is far away, the reflected light intensity
is lower, so the phototransistor current is also lower.
In example B below, the flash stays on for longer time
(60 s) and discharges more energy from the photo-
flash capacitor.
Using a larger CTGR1 causes the time constant of the
integrator to increase, so a longer pulse is required
before the flash is terminated.
Example A
Example B
Common Parameters
Symbol Parameter Units/Division
C1 VOUT 50 V
C2 VTRIGGER2 1 V
C3 VTRIGGER1 5 V
C4 VGATE 5 V
t time 20 s
C1
C4 C4
C2
C3
C1
t
VGATE
VOUT
VTRIGGER2
VTRIGGER1
C2
C3
C1
C4 C4
C2
C3
C1
t
VGATE
VOUT
VTRIGGER2
VTRIGGER1
C2
C3
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Transformer Selection
1. The transformer turns ratio, N, determines the out-
put voltage:
N = NS / NP
V
OUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP , and Vd is
the forward drop of the output diode.
2. The primary inductance, LP , determines the on-time
of the switch:
ton = (–LP / R ) × ln (1 – ISWlim × R / VIN) ,
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
If VIN is much larger than ISWlim × R, then ton can be
approximated by:
t
on = ISWlim × LP /VIN .
3. The secondary inductance, LS, determines the off-
time of the switch. Given:
L
S
/ LP = N × N , then
t
off = (ISWlim / N) × LS / VOUT
= (ISWlim × LP × N) /VOUT .
The minimum pulse width for toff determines what
is the minimum LP required for the transformer. For
example, if ISWlim = 0.7 A, N = 10, and VOUT = 315 V,
then LP must be at least 9 H in order to keep toff at
200 ns or longer. These relationships are illustrated in
the figure at the bottom of the page.
In general, choosing a transformer with a larger LP
results in higher efficiency (because a larger LP means
lower switch frequency and hence lower switching
loss). But transformers with a larger LP also require
more windings and larger magnetic cores. Therefore, a
trade-off must be made between transformer size and
efficiency.
Component Selection
Selection of the flyback transformer should be based
on the peak current, according to the following table:
IPeak Range
(A) Supplier Part Number
LP
(H)
0.4 to 1.0 TDK LDT565630T-002 14.5
0.6 to 1.2 TDK LDT565630T-003 10.5
0.75 to 1.0 TDK LDT565620ST-203 8.2
VSW
VSW
VIN VIN
ISW
ISW
ton toff
Vrtf
tneg
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application 2. Maintaining output target voltage by directly
monitoring the output voltage (REG pin connected to a
secondary-side resistor divider). CG package shown.
+
SW
Battery Input
2.3 to 5.5 V
C2 COUT
100 μF
315 V
1 : 10
C1
ISET
VIN
Control
Block
TLIM
CHARGE
DONE
GND
100 k
GSOURCE
TRIGGER1
VIN
IGBT Driver
IGBT Gate
GSINK
VPULLUP
TRIGGER2
REG
VOUT Detect
ISW sense
DONE
RSET
10 M
38.3 k
Application 3. Maintaining output voltage by predicting the output
voltage droop (REG pin connected to primary-side RC network).
CG package shown.
+
SW
Battery Input
2.3 to 5.5 V
C2 COUT
100 μF
315 V
1 : 10
C1
CREG RREG
10 MF
ISET
VIN
Control
Block
TLIM
CHARGE
DONE
GND
100 k
GSOURCE
TRIGGER1
VIN
IGBT Driver
IGBT Gate
GSINK
VPULLUP
TRIGGER2
REG
VOUT Detect
ISW sense
DONE
RSET 10 M
C
R
E
G
R
RE
G
10
M
F
1
0
M
10
M
3
8
.3
k
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package CG, 12-Ball WLCSP
0.19
0.2225
0.208
X.17
1.215
1.645
0.550 MAX
0.400
1.200
0.40
0.800
1234
0.40
A
B
C
C
B
A
1234
A
B
C
1234
A
All dimensions nominal, not for tooling use
Dimensions in millimeters
Dimensions exclusive of burrs
Exact configuration at supplier discretion within limits shown
A
Terminal #A1 mark area
B
B
Reference pad layout; all pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application
process requirements and PCB layout tolerances
PCB Layout Reference View
SEATING
PLANE
CDie orientation mark
C0.05
12X C
C
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EJ, 3 mm x 3 mm 10-Contact DFN/MLP
2.38
10
10
2
1
2
1
A
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
B
PCB Layout Reference View
1.64
2.38
0.30
1
10 0.50
0.85
3.10
C
1.64
C0.08
11X C
SEATING
PLANE
D
0.25 +0.05
–0.07 0.50 0.75 ±0.05
3.00 ±0.15
3.00 ±0.15
0.40 ±0.10
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
19
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
CG Package Marking
Line 1:
Bump A1 mark
NN – last two digits of the device number (37)
N N
Y W W
Line 2: Date code
Y – last digit of year of manufacture
WW – week of manufacture
(Marks on substrate side, exact
appearance at supplier discretion)
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
20
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Reflow Profile per J-STD-020D
IPC-020d-5-1
JSTD020D-01, Figure 5-1 Classification Profile (Not to scale)
Tc -5°C
t
Max. Ramp Up Rate = 3°C/s
Max. Ramp Down Rate = 6°C/s
Preheat Area
Tsmax
Tsmin
ts
Tp
TL
Temperature
Time
25 Time 25°C to Peak
Supplier Tp>Tc
-
Supplier tp
Tc
User Tp< Tc
-
User tp
Tc-5°C
tp
L
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
21
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2006-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Typical Reflow Profile per J-STD-020D
JSTD020D-01 Table 5-2 Classification Reflow Profiles
ylbmessAeerF-bPylbmessAcitcetuEbP-nSerutaeFelfiorP
Preheat/Soak
Temperature Min (T
smin
)
Temperature Max (T
smax
)
Time (t
s
)from(T
smin
to T
smax
)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Ramp-up rate (T
L
to T
p
.xamdnoces/C°3.xamdnoces/C°3)
Liquidous temperature (T
L
)
Time (t
L
) maintained above T
L
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body temperature (T
p
)
For users T
p
must not exceed the
Classification temp in Table 4-1.
For suppliers T
p
must equal or exceed
the Classification temp in Table 4-1.
For users T
p
must not exceed the
Classification temp in Table 4-2.
For suppliers T
p
must equal or exceed
the Classification temp in Table 4-2.
Time (t
p
)* within 5 °C of the specified
classification temperature (T
c
), see
Figure 5-1.
sdnoces*03sdnoces*02
Ramp-down rate (T
p
to T
L
.xamdnoces/C°6.xamdnoces/C°6)
.xamsetunim8.xamsetunim6erutarepmetkaepotC°52emiT
* Tolerance for peak profile temperature (T
p
)isdefined as a supplier minimum and a user maximum.
Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug). If
parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), T
p
shall be within ± 2 °C of the live-bug T
p
and still
meet the T
c
requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body temperatures
refer to JEP140 for recommended thermocouple use.
Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table 5-2.
For example, if T
c
is 260 °C and time t
p
is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260 °C. The time above 255 °C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260 °C. The time above 255 °C must not exceed 30 seconds.
Note 3: All components in the test load shall meet the classification profile requirements.
Note 4: SMD packages classified to a given moisture sensitivity level by using Procedures or Criteria defined within any previous version of J-STD-020,
JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or a
higher peak classification temperature is desired.
