VNQ7E100AJ Datasheet Quad channel high-side driver with CurrentSense analog feedback for automotive applications Features PowerSSO-16 Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 100 m Current limitation (typ) ILIMH 15 A Stand-by current (max) ISTBY 0.5 A Minimum cranking supply Voltage (VCC decreasing) VUSD_cranking 2.85 V * * * * Product status VNQ7E100AJ Product summary Order code VNQ7E100AJTR Package PowerSSO-16 Packing Tape and reel * AEC-Q100 qualified Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013) General - Quad channel smart high-side driver with CurrentSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs CurrentSense diagnostic functions - Analog feedback of load current with high precision proportional current mirror - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/disable Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation - Loss of ground and loss of VCC - - Reverse battery with external components Electrostatic discharge protection Applications * * * Automotive resistive, inductive and capacitive loads Protected supply for ADAS systems: radars and sensors Automotive lamps DS12570 - Rev 3 - February 2019 For further information contact your local STMicroelectronics sales office. www.st.com VNQ7E100AJ Description The device is a quad channel high-side driver manufactured using ST proprietary VIPower(R) M0-7 technology and housed in a PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOScompatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A multiplexed current sense pin delivers high precision proportional load current sense in addition to the detection of overload and short circuit to ground, short to VCC and off-state openload. A sense enable pin allows OFF-state diagnosis to be disabled during the module lowpower mode as well as external sense resistor sharing among similar devices. DS12570 - Rev 3 page 2/45 VNQ7E100AJ Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC - GND Clamp Internal supply Undervoltage shut-down Channel 3 Channel 2 CH 3 Channel 1 CH 2 Control & Diagnostic Channel 0 CH 1 FaultRST INPUT3 VCC - OUT Clamp INPUT2 CH 0 INPUT1 OUTPUT3 OUTPUT2 INPUT0 Gate Driver T SEL1 SEL0 OUTPUT1 Current Limitation SEn Power Limitation Overtemperature MUX CS 0 Short to VCC Open-Load in OFF Fault Current Sense VSENSEH GND OUTPUT0 GADG1003171112PS Table 1. Pin functions Name VCC Function Battery connection. OUTPUT0,1,2,3 Power output. DS12570 - Rev 3 GND Ground connection. Must be reverse battery protected by an external diode / resistor network. INPUT0,1,2,3 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. They control output switch state. CS Analog current sense output pin delivers a current proportional to the load current. SEn Active high, compatible with 3 V and 5 V CMOS outputs input pin; it enables the CS diagnostic pin. SEL0,1 Active high, compatible with 3 V and 5 V CMOS outputs input pin; They address the CS multiplexer. FaultRST Active low, compatible with 3 V and 5 V CMOS outputs input pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. page 3/45 VNQ7E100AJ Block diagram and pin description Figure 2. Configuration diagram (top view) PowerSSO-16 OUTPUT0 1 16 OUTPUT3 SEn 2 15 SEL1 INPUT0 3 14 INPUT3 GND 4 13 CS FaultRST 5 12 SEL0 INPUT1 6 11 INPUT2 N.C. 7 10 OUTPUT1 8 9 N.C. OUTPUT2 TAB = V CC GAPGCFT00632 Table 2. Suggested connections for unused and not connected pins Connection / pin CS N.C. Output Input SEn, SELx, FaultRST Floating Not allowed X (1) X X X To ground Through 1 k resistor X Not allowed Through 15 k resistor Through 15 k resistor 1. X: do not care. DS12570 - Rev 3 page 4/45 VNQ7E100AJ Electrical specification 2 Electrical specification Figure 3. Current and voltage conventions IS VCC FaultRST I SEn I OUT OUTPUT 0,1,2,3 CS SEL 0,1 VSEn V OUT I SENSE SE n I SEL VFR VCC VFn I FR VSENSE I IN VSEL INPUT 0,1,2,3 VIN I GND GADG0704171646PS Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3. Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in the table below for extended periods may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT0,1,2,3 DC output current -IOUT Reverse DC output current IIN ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current ISENSE V Internally limited 7.5 A INPUT0,1,2,3 DC input current CS pin DC output current (VGND = VCC and VSENSE < 0 V) CS pin DC output current in reverse (VCC < 0 V) DS12570 - Rev 3 Value -1 to 10 mA -1 to 1.5 mA 10 mA -20 page 5/45 VNQ7E100AJ Thermal data Symbol Parameter EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150C) JEDEC standard (Electrostatic discharge) VESD VESD Tj Tstg 2.2 Value Unit 10 mJ JEDEC 22A-114F INPUT0,1,2,3 4000 CS, SEn 2000 SEL0,1, FaultRST 4000 OUTPUT0,1,2,3 4000 VCC 4000 Charge device model (CDM-AEC-Q100-011) 750 Junction operating temperature -40 to 150 Storage temperature -55 to 150 V V C Thermal data Table 4. Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5) (1)(3) 60.3 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7) (1)(2) 27.1 Rthj-top Thermal resistance junction-top (JEDEC JESD 51-7)(1)(2) 13.5 (1)(2) Unit 7.7 C/W 1. One channel ON. 2. Device mounted on four-layers 2s2p PCB. 3. Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace. DS12570 - Rev 3 page 6/45 VNQ7E100AJ Main electrical characteristics 2.3 Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5. Electrical characteristics during cranking Symbol VUSD_Cranking RON TTSD (2) Parameter Test conditions Min. Typ. Minimum cranking supply voltage (VCC decreasing) On-state resistance (1) IOUT = 0.2 A; VCC = 2.85 V; VCC decreasing Shutdown temperature (VCC decreasing) VCC =2.85 V Max. Unit 2.85 V 300 m 140 C 1. For each channel. 2. Parameter guaranteed by design and characterization; not subject to production test. Table 6. Power section Symbol Parameter VCC Operating supply voltage VUSD Undervoltage shutdown VUSDReset VUSDhyst Test conditions Min. Typ. Max. 4 13 28 2.85 Undervoltage shutdown reset 5 Undervoltage shutdown hysteresis Vclamp ISTBY tD_STBY IS(ON) IGND(ON) DS12570 - Rev 3 On-state resistance (1) Clamp voltage Supply current in Standby at VCC = 13 V (3) V 0.3 IOUT = 1 A; Tj = 25C RON Unit 100 IOUT = 1 A; Tj = 150C 210 IOUT = 1 A; VCC = 4 V; Tj = 25C (2) 160 IS = 20 mA; 25C < Tj < 150C 41 IS = 20 mA; Tj = -40C 38 46 52 m V VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25C 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85C (4) 0.5 A VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125C 3 A 300 550 s 10 16 mA 20 mA Standby mode blanking time VCC = 13 V VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V to 0 V Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 1 A 60 page 7/45 VNQ7E100AJ Main electrical characteristics Symbol Parameter Test conditions Off-state output current at VCC = 13 V (1) IL(off) Output - VCC diode voltage at Tj = 150C VF Min. Typ. Max. VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 0.01 0.5 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 3 IOUT = -1 A; Tj = 150C 0.7 Unit A V 1. For each channel. 2. Parameter guaranteed only at Vcc = 4 V and Tj = 25 C 3. PowerMOS leakage included. 4. Parameter specified by design; not subject to production test. Table 7. Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Parameter td(on) (1) Turn-on delay time at Tj = 25C Test conditions Turn-on voltage slope at Tj = 25C (dVOUT/dt)on (1) Max. 10 50 120 10 35 100 0.1 0.3 0.7 Unit s RL = 13 Turn-off voltage slope at Tj = 25C (dVOUT/dt)off (1) Typ. RL = 13 Turn-off delay time at Tj = 25C td(off) (1) Min. V/s 0.1 0.4 0.7 WON Switching energy losses at turn-on (twon) RL = 13 -- 0.15 0.5 (2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 13 -- 0.1 0.5(2) mJ RL = 13 -65 -15 35 s Max. Unit 0.9 V Differential Pulse skew tSKEW (1) (tPHL - tPLH) 1. See Figure 6. Switching times and Pulse skew. 2. Parameter guaranteed by design and characterization, not subject to production test Table 8. Logic Inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. INPUT0,1,2,3 characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA A V 5.3 7.2 -0.7 V FaultRST characteristics VFRL DS12570 - Rev 3 Input low level voltage 0.9 V page 8/45 VNQ7E100AJ Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions IFRL Low level input current VIN = 0.9 V VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL Input clamp voltage Min. Typ. Max. 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Unit V 5.3 IIN = -1 mA A 7.5 -0.7 V SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V V 5.3 IIN = -1 mA A 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA V V 5.3 IIN = -1 mA A 7.2 -0.7 V Table 9. Protections 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature TR Reset TRS Thermal reset of fault diagnostic indication VCC = 13 V 4 V < VCC < 18 V Thermal hysteresis (TTSD TR)(1) TJ_SD Dynamic temperature Min. Typ. Max. 11 15 22 (1) 22 VCC = 13 V; TR < Tj < TTSD temperature(1) THYST DS12570 - Rev 3 Test conditions VFR = 0 V; VSEn = 5 V; Unit A 6 150 175 TRS + 1 TRS + 7 200 C 135 7 Tj = -40C; VCC = 13 V 60 K page 9/45 VNQ7E100AJ Main electrical characteristics 7 V < VCC < 28 V; -40C < Tj < 150C Symbol tLATCH_RST VDEMAG Parameter Test conditions Fault reset time for output unlatch(1) * Turn-off output voltage clamp Min. Typ. Max. Unit 3 10 20 s VFR = 5 V to 0 V; VSEn = 5 V E.g. Ch0 VIN0 = 5 V; VSEL0,1 = 0 V IOUT= 1 A; L = 6 mH; Tj = -40C VCC - 38 IOUT= 1 A; L = 6 mH; Tj = 25C to 150C VCC - 41 V VCC - 46 VCC - 52 V Max. Unit 1. Parameter guaranteed by design and characterization; not subject to production test. Table 10. CurrentSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol VSENSE_CL Parameter Current sense clamp voltage Test conditions Min. VSEn = 0 V; ISENSE = 1 mA -17 VSEn = 0 V; ISENSE = -1 mA Typ. -12 7 V Current Sense characteristics K0 dK0/K0 (1) (2) K1 dK1/K1 (1) (2) K2 dK2/K2 (1) (2) K3 dK3/K3 (1) (2) ISENSE_OL IOUT/ISENSE IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V -30% Current sense ratio drift IOUT = 0.025 A; VSENSE = 0.5 V; VSEn = 5 V -20 IOUT/ISENSE IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V -15% Current sense ratio drift IOUT = 0.15 A; VSENSE = 4 V; VSEn = 5 V -10 IOUT/ISENSE IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V -7% Current sense ratio drift IOUT = 0.7 A; VSENSE = 4 V; VSEn = 5 V -6 IOUT/ISENSE IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -7% Current sense ratio drift IOUT = 2 A; VSENSE = 4 V; VSEn = 5 V -6 CS current for OL detection IOUT = 0.01 A; VSENSE = 4 V; VSEn = 5 V Current sense disabled: VSEn = 0 V; Current sense disabled: -1 V < VSENSE < 5 V(1) 710 +30% +20 710 +15% +10 710 % +7% +6 710 % % +7% +6 % 24 A 0 0.5 -0.5 0.5 0 10 Current sense enabled: VSEn = 5 V All channels ON; IOUTX = 0 A; ChX diagnostic selected: ISENSE0 Current sense leakage current * E.g. Ch0: VIN0,1,2,3 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; IOUT1,2,3 = 1 A A Current sense enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected: * DS12570 - Rev 3 E.g. Ch0: VIN0 = 0 V; VIN1,2,3 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT1,2,3 = 1 A 0 2 page 10/45 VNQ7E100AJ Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit VSEn = 5 V; RSENSE = 2.7 k VOUT_MSD (1) VSENSE_SAT Output Voltage for Current sense shutdown CS saturation voltage * E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 1 A VCC = 7 V; RSENSE = 2.7 k; VSEn = 5 V; VIN0 = 5 V; VSEL0,1 = 0 V; IOUT0 = 2 A; 5 V 4.8 V Tj = -40 C ISENSE_SAT (1) IOUT_SAT (1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150 C 4 mA Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150 C 3.1 A OFF-state diagnostic VSEn = 5 V; ChX OFF; ChX diagnostic selected VOL OFF-state open-load voltage detection threshold IL(off2) (3) OFF-state output sink current tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 8. TDSKON ) * tD_OL_V Settling time for valid OFFstate open-load diagnostic indication from rising edge of SEn VIN0,1,2,3 = 0 V; VFR = 0 V; VSEL0,1 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V * E.g: Ch0 VIN0 = 0 V; VSEL0,1 = 0 V VIN = 0 V; VOUT = VOL; Tj = -40C to 125C 2 3 -100 4 V -15 A 700 s 60 s 30 s 6.6 V 30 mA 60 s 20 s VSEn = 5 V; ChX ON to OFF transition; ChX diagnostic selected: E.g: Ch0 VIN0 = 5 V to 0 V; VSEL0,1 = 0 V; VOUT0 = 4 V; IOUT0 = 0 A 100 350 VSEn = 5 V; ChX OFF; tD_VOL OFF-state diagnostic delay time from rising edge of VOUT ChX diagnostic selected: * 5 E.g: Ch0 VIN0 = 0 V; VSEL0,1 = 0 V; VOUT0 = 0 V to 4 V Fault diagnostic feedback (see Table 11. Truth table) VCC = 13 V; RSENSE = 1 k VSENSEH Current sense output voltage in fault condition ISENSEH Current sense output current in fault condition * E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0,1 = 0 V; IOUT0 = 0 A; VOUT0 = 4 V VCC = 13 V; VSENSE = 5 V 5 7 20 Current sense timings (current sense mode - see Figure 7. Current sense timings (current sense mode))(4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 k; RL = 6.5 tDSENSE1L Current sense disable delay time from falling edge of SEn VSEn = 5 V to 0 V; RSENSE = 1 k; RL = 6.5 DS12570 - Rev 3 5 page 11/45 VNQ7E100AJ Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C Symbol tDSENSE2H Parameter Test conditions Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 k; RL = 6.5 tDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) tDSENSE2L Current sense turn-off delay time from falling edge of INPUT Min. Typ. Max. Unit 100 250 s 100 s 250 s VIN = 5 V; VSEn = 5 V; RSENSE = 1 k; ISENSE = 90 % of ISENSEMAX; RL = 6.5 VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 k; RL = 6.5 50 Current sense timings (Multiplexer transition times) (4) tD_XtoY VIN0 = 5 V; VIN1 = 5 V; VSEn = 5 V; VSEL1 Current sense transition delay = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 0 A; from ChX to ChY IOUT1 = 1 A; RSENSE = 1 k 20 s tD_CStoVSENSEH Current sense transition delay VIN0 = 5 V; VIN1 = 0 V; VSEn = 5 V; VSEL1 from stable current sense on = 0 V; VSEL0 = 0 V to 5 V; IOUT0 = 1 A; ChX to VSENSEH on ChY VOUT1 = 4 V; RSENSE = 1 k 20 s 1. Parameter defined by design. Not subject to production test. 2. All values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. 3. Parameter granted at -40 C < Tj < 125 C" 4. Transition delay are measured up to +/- 10% of final conditions. Figure 4. IOUT/ISENSE versus IOUT 1200 Max Min 1000 Typ K-factor 800 600 400 200 0 0 1 IOUT[A] 2 3 GADG0903171157PS DS12570 - Rev 3 page 12/45 VNQ7E100AJ Main electrical characteristics Figure 5. Current sense accuracy versus IOUT 50 45 40 35 30 Current sense uncalibrated precision Current sense calibrated precision % 25 20 15 10 5 0 0 1 2 I OUT [A] 3 GADG0903171216PS Figure 6. Switching times and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t GAPGCFT00797 DS12570 - Rev 3 page 13/45 VNQ7E100AJ Main electrical characteristics Figure 7. Current sense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 Current Sense tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L GADG0704171311PS Figure 8. TDSKON VINPUT VOUT VOUT > VOL MultiSense TDSTKON GAPG2609141140CFT DS12570 - Rev 3 page 14/45 VNQ7E100AJ Main electrical characteristics Table 11. Truth table Mode Conditions Standby All logic inputs low INX FR SEn SELX OUTX Current sense Nominal load connected; Tj < 150C Normal Overload or short to GND causing: Overload Tj > TTSD or Tj > Tj_SD L L L X H L H Hi-Z L See (1) H See (1) Outputs configured for auto-restart H H See (1) Outputs configured for Latch-off L X L See (1) H L H See (1) Output cycles with temperature hysteresis H H L See (1) Output latches-off L Hi-Z Re-start when VCC > VUSD + L Hi-Z VCC < VUSD (falling) OFF-state diagnostics Short to VCC L X Open-load L X Inductive loads turn-off L X Negative output voltage X X L Low quiescent current consumption L Under-voltage L Comments See (1) See (1) X X H See H See (1) <0V See (1) See (1) See (1) VUSDhyst (rising) (1) External pull-up 1. Refer to Table 12. Current sense multiplexer addressing Table 12. Current sense multiplexer addressing SEn SEL1 SEL0 Current sense output MUX channel Nomal mode Overload OFF-state diag. (1) (2) (3) Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/ K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel 1 diagnostic ISENSE = 1/ K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L Channel 2 diagnostic ISENSE = 1/ K * IOUT2 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H H Channel 3 diagnostic ISENSE = 1/ K * IOUT3 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z 1. In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, CS pin delivers feedback according to OFF-State diagnostic. 2. Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; CS = 0 3. Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH DS12570 - Rev 3 page 15/45 VNQ7E100AJ Waveforms 2.4 Waveforms Figure 9. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) Logic high Sense enable Logic high Input Logic high t t > t latch RST I limH Fault Reset Output current Junction temperature << TTDS Tj 60 Logic high Hard short circuit Internal fault detection Vout <5V Vout <5V VsenseH Output Voltage Multisense voltage GADG1703171451PS Figure 10. Latch functionality - behavior in hard short-circuit condition Logic high Sense enable Logic high Input Logic high t t > t latch RST I lim H Fault Reset Output current I lim L TTSD TR TAMB Junction temperature Thermal shut down cycling in AutoRestart mode Logic high Hard short circuit VsenseH DS12570 - Rev 3 Internal fault detection Vout <5V Vout <5V Output Voltage Multisense voltage page 16/45 VNQ7E100AJ Waveforms Figure 11. Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) Logic high Sense enable Logic high Input Logic high Fault Reset I lim H Output current I lim L TTSD Junction temperature Chip temperature 60 TAMB Logic high Hard short circuit Internal fault detection Vout <5V Vout <5V VsenseH Output Voltage Multisense voltage GADG2103171742PS Figure 12. Standby mode activation DS12570 - Rev 3 page 17/45 VNQ7E100AJ Waveforms Figure 13. Standby state diagram Normal Operation t > t D_STBY INx = Low AND FaultRST = Low AND SEn = Low AND SELx = Low INx = High OR FaultRST = High OR SEn = High OR SELx = High Stand-by Mode GAPGCFT00598 DS12570 - Rev 3 page 18/45 VNQ7E100AJ Electrical characteristics curves 2.5 Electrical characteristics curves Figure 14. OFF-state output current Iloff [nA] GADG071220181211OSOC Figure 15. Standby current ISTBY [A] GADG071220181212STBC 1.8 300 250 200 VCC = 13 V 1.6 Vin = Vout = 0 1.4 Off state 1.2 VCC = 13 V 1 150 0.8 0.6 100 0.4 50 0.2 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 16. IGND(ON) vs. Iout IGND(ON) [mA] GADG071220181212IGIO 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 17. Logic input high level voltage ViIH ,VFRH ,VSELH ,VSEnH [V] GADG071220181214LILV 1.8 10 1.6 1.4 8 VCC = 13 V 1.2 IOUT = 1 A 6 1 0.8 4 0.6 0.4 2 0.2 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 18. Logic input low level voltage ViIL ,VFRL ,VSELL ,VSEnL [V] GADG071220181214LILLV 1.8 0 -50 -25 50 75 100 125 150 175 T [C] Figure 19. High level logic input current IiH ,IFRH ,ISELH ,ISEnH [A] GADG101220181119HLLIC 3 1.4 1.2 2.5 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 DS12570 - Rev 3 25 3.5 1.6 0 -50 -25 0 0 25 50 75 100 125 150 175 T [C] 0 -50 -25 0 25 50 75 100 125 150 175 T [C] page 19/45 VNQ7E100AJ Electrical characteristics curves Figure 20. Low level logic input current IiL ,IFRL ,ISELL ,ISEnL [A] GADG071220181216LLLIC Figure 21. Logic input hysteresis voltage Vi(hyst) ,VFR(hyst) ,VSEL(hyst) ,VSEn(hyst) [V] GADG071220181216LIHV 0.9 3 0.8 2.5 0.7 0.6 2 0.5 1.5 0.4 0.3 1 0.2 0.5 0 -50 -25 0.1 0 25 50 75 100 125 150 175 T [C] Figure 22. FaultRST Input clamp voltage VFRCL(hyst) [V] GADG071220181217FICV 7 0 -50 -25 IIN = 1 mA 5 75 100 125 150 175 T [C] VUSD [V] GADG071220181217UNSH 6 5 3 4 2 3 1 IIN = -1 mA 0 2 1 -1 0 25 50 75 100 125 150 175 T [C] Figure 24. On-state resistance vs. Tcase RDS(on) [m] GADG071220181217OSRT 180 IOUT = 1 A 160 VCC = 13 V 140 0 -50 -25 0 25 50 75 100 125 150 175 T [C] Figure 25. On-state resistance vs. VCC RDS(on) [m] GADG071220181218ONRV T = 150 C 200 180 160 T = 125 C 140 120 120 100 T = 25 C 100 80 80 60 60 40 40 20 20 0 0 DS12570 - Rev 3 50 Figure 23. Undervoltage shutdown 4 0 -50 -25 25 7 6 -2 -50 -25 0 0 25 50 75 100 125 150 175 T [C] T = -40 C 5 10 15 20 25 V [V] 30 35 40 page 20/45 VNQ7E100AJ Electrical characteristics curves Figure 26. Turn-on voltage slope (dVout /dt)on [V/s] GADG071220181218ONVS 0.9 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 25 50 VCC = 13 V RL = 13 0.7 0.6 0 -50 -25 75 100 125 150 175 T [C] 0 -50 -25 Figure 28. Won vs. Tcase Won [m/J] GADG071220181220WONT 0.9 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 25 50 75 100 125 150 175 T [C] 25 50 75 100 125 150 175 T [C] Woff [m/J] 0.8 0 0 Figure 29. Woff vs. Tcase 0.9 0 -50 -25 GADG071220181219OFVS 0.8 RL = 13 0.7 (dVout /dt)off [V/s] 0.9 VCC = 13 V 0.8 Figure 27. Turn-off voltage slope 0 -50 -25 Figure 30. OFF-state open-load voltage detection threshold GADG071220181220WOFFT 0 25 50 75 100 125 150 175 T [C] Figure 31. VSENSE clamp vs. Tcase VSENSE_CL [V] IOL [A] GADG071220181222VCT GADG071220181221OFFOL 3.5 5 Iin = -1 mA 3 0 2.5 -5 2 1.5 -10 1 -15 Iin = 1 mA 0.5 0 -50 -25 DS12570 - Rev 3 0 25 50 75 100 125 150 175 T [C] -20 -50 -25 0 25 50 75 100 125 150 175 T [C] page 21/45 VNQ7E100AJ Electrical characteristics curves Figure 32. VSENSEH vs. Tcase VSENSEH [V] GADG071220181222VST 9 8 7 6 5 4 3 2 1 0 -50 -25 DS12570 - Rev 3 0 25 50 75 100 125 150 175 T [C] page 22/45 VNQ7E100AJ Protections 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermomechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. DS12570 - Rev 3 page 23/45 VNQ7E100AJ Application information 4 Application information Figure 33. Application diagram +5V VDD OUT VCC Rprot OUT FaultRST INPUT Rprot OUT Logic OUT Rprot SEn Rprot SEL Dld OUTPUT Rprot ADC in CS Current mirror GND Cext Rsense OUT R GND GND D GND GND GND GND GND GND DS12570 - Rev 3 page 24/45 VNQ7E100AJ GND protection network against reverse battery 4.1 GND protection network against reverse battery Figure 34. Simplified internal structure 5V Vcc Rprot Rprot INPUT SEn MCU Dld Rprot FaultRST OUTPUT Rprot CS GND Rsense D GND R GND GND 4.1.1 GAPGCFT00830 Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 13. ISO 7637-2 - electrical transient conduction along supply line. Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". DS12570 - Rev 3 page 25/45 VNQ7E100AJ MCU I/Os protection Table 13. ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US (1) 1 III -112 V 500 pulses 0.5 s 2a(3) III +55 V 500 pulses 0.2 s 5s 50 s, 2 3a IV -220 V 1h 90 ms 100 ms 0.1 s, 50 3b IV +150 V 1h 90 ms 100 ms 0.1 s, 50 IV -7 V 1 pulse 4 (2) min max 2 ms, 10 100 ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40 V 5 pulse 1 min 400 ms, 2 1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40C < Tj < 150 C). 4.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 CS - analog current sense Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals: * Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. DS12570 - Rev 3 page 26/45 VNQ7E100AJ CS - analog current sense Figure 35. CurrentSense and diagnostic - block diagram VCC VCC - GND Clamp Internal Supply Undervoltage shut-down Control & Diagnostic FaultRST VCC - OUT Clamp INPUT Gate Driver T SEL1 SEL 0 SE n RPROT Current Limitation I SENSE CS Fault Diagnostic MUX Short to VCC Open-Load in OFF To C ADC R SENSE CURRENT MONITOR GND Power Limitation Overtemperature K factor Current Sense Fault IOUT OUT VSENSEH GADG2004171456PS DS12570 - Rev 3 page 27/45 VNQ7E100AJ CS - analog current sense 4.4.1 Principle of CurrentSense signal generation Figure 36. CurrentSense block diagram Vcc INPUT Sense MOS Main MOS OUT Current sense Current sense Switch Block Fault CS To uC ADC RPROT RSENSE GAPG2307131200CFT Current sense The output is able to provide: * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K * Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by CS output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * VSENSE is the voltage measurable on RSENSE resistor DS12570 - Rev 3 page 28/45 VNQ7E100AJ CS - analog current sense * ISENSE is the current provided from CS pin in current output mode * IOUT is the current flowing through output * K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry, specifying the ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the CS in this condition is limited to ISENSEH. Figure 37. Analog HSD - open-load detection in off-state +5V Vbat Vbat 100nF/ 50V 100nF Rpull-up GND Microcontroller GND VDD V CC OUT FaultRST 15k INPUT External Pull -Up switch OUT Logic 15k SEn OUT SEL 15k OUT OUTPUT OUTPUT CS Cu rrent mirror 15k GND ADC in 15k Rsense R GN D 4.7k DGN D 10nF /100V OUT 15k GND GND CEXT GND GND GND GND GAPG1201151432CFT DS12570 - Rev 3 page 29/45 VNQ7E100AJ CS - analog current sense Figure 38. Open-load / short to VCC condition VIN VSENSE VSENSEH Pull-up connected Open-load VSENSE = 0 VSENSE Pull-up disconnected tDSTKON Short to VCC VSENSEH Table 14. CurrentSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL CS SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short-circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: DS12570 - Rev 3 page 30/45 VNQ7E100AJ CS - analog current sense Equation RPU < DS12570 - Rev 3 VPU - 4 IL(off2)min @ 4V page 31/45 VNQ7E100AJ Maximum demagnetization energy (Vcc = 16 V) 5 Maximum demagnetization energy (Vcc = 16 V) Figure 40. Maximum turn off current versus inductance I [A] GADG101220181148MTOC 100 10-1 10-1 Single pulse Repetitive pulse Tjstart = 100C Repetitive pulse Tjstart = 125C 100 101 L [mH] 102 103 Figure 41. Maximum turn off energy versus inductance EI [mJ] GADG101220181149MTOE 102 101 100 10-1 Note: Single pulse Repetitive pulse Tjstart = 100C Repetitive pulse Tjstart = 125C 100 101 L [mH] 102 103 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. DS12570 - Rev 3 page 32/45 VNQ7E100AJ Package and PCB thermal data 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 42. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 43. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 15. PCB properties Dimension Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation Thermal via diameter Copper thickness on vias Footprint dimension (top layer) DS12570 - Rev 3 Value 1.2 mm 0.3 mm +/- 0.08 mm 0.025 mm 2.2 mm x 3.9 mm page 33/45 VNQ7E100AJ PowerSSO-16 thermal data Dimension Value Footprint, 2 cm2 or 8 cm2 Heatsink copper area dimension (bottom layer) Figure 44. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 2 4 6 8 10 GAPG2307131254CFT Figure 45. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) 100 ZTH (C/W) 10 1 Cu=footprint Cu=2 cm2 Cu=8 cm2 4 Layer 0.1 0.0001 0.001 0.01 0.1 Time (s) 1 10 100 1000 GAPG2307131257CFT Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T DS12570 - Rev 3 page 34/45 VNQ7E100AJ PowerSSO-16 thermal data Figure 46. Thermal fitting model of a double-channel HSD in PowerSSO-16 C1 C2 Tj R1 C7 PdCh1 R2 C8 Tj R7 C3 R8 C4 C5 C6 PdCh2 C9 C10 R3 R4 R5 R6 Tj R9 R10 PdCh3 C11 C12 T_amb Tj R11 R12 PdCh4 GADG2203171318PS Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 16. Thermal parameters DS12570 - Rev 3 Area/island (cm) Footprint R1, R7 (C/W) 1.75 2 8 4L R2, R8 (C/W) 6 R3 (C/W) 6.6 6.6 6.6 5.4 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1, C7 (W.s/C) 0.0002 C2, C8 (W.s/C) 0.0009 C3 (W.s/C) 0.023 C4 (W.s/C) 0.2 0.3 0.3 0.4 C5 (W.s/C) 0.4 1 1 4 C6 (W.s/C) 3 5 7 18 page 35/45 VNQ7E100AJ Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 47. PowerSSO-16 package dimensions ggg D2 D3 Bottom view C A-B D ggg C A-B D minimum solderable area Section A-A E3 E2 h 2 h 1 R1 H B for dual gauge only eee C GAUGE PLANE S A2 A R B L 3 ccc C e L1 SEATING PLANE A1 b ddd C CD 2x f f f C A-B D A N Section B-B D A b WITH PLATING 1.2 for dual gauge only c c1 E1 E index area (0.25D x 0.75E1) b1 2x BASE METAL aaa C D Top view 2x N/2 TIPS bbb C 1 2 3 A N/2 B 8017965_Rev_9 DS12570 - Rev 3 GAPG1605141159CFT page 36/45 VNQ7E100AJ PowerSSO-16 package information Table 17. PowerSSO-16 mechanical data Symbol Millimeters Min. Typ. Max. 0 8 1 0 2 5 15 3 5 15 A 1.70 A1 0.00 0.10 A2 1.10 1.60 b 0.20 0.30 b1 0.20 c 0.19 c1 0.19 D 0.25 0.28 0.25 0.20 0.23 4.90 BSC D2 3.31 D3 2.61 3.91 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 2.20 E3 1.49 h 0.25 L 0.40 2.80 0.50 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 0.85 Tolerance of form and position DS12570 - Rev 3 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 page 37/45 VNQ7E100AJ PowerSSO-16 packing information 7.2 PowerSSO-16 packing information Figure 48. PowerSSO-16 reel 13" Access Hole at Slot Location ( 40 mm min.) W2 N D A C W1 B If present, tape slot in core for tape start: 2.5 mm min. width x 10.0 mm min. depth TAPG2004151655CFT Table 18. Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 1. All dimensions are in mm. DS12570 - Rev 3 page 38/45 VNQ7E100AJ PowerSSO-16 packing information Figure 49. PowerSSO-16 carrier tape P0 P2 4.0 0.1 2.0 0.1 0.30 0.05 X 1.55 0.05 1.75 0.1 1.6 0.1 F W B0 R 0.5 Typical Y K1 Y X K0 P1 A0 SECTION X - X REF 4.18 REF 0.6 REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 19. PowerSSO-16 carrier tape dimensions Value(1) Description A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 1. All dimensions are in mm. Figure 50. PowerSSO-16 schematic drawing of leader and trailer tape Embossed carrier Punched carrier 8 mm & 12 mm only END Carrier tape Round sprocket holes START Top cover tape Elongated sprocket holes (32 mm tape and wider) Trailer 160 mm minimum Top cover tape Components 100 mm min. Leader 400 mm minimum User direction feed GAPG2004151511CFT DS12570 - Rev 3 page 39/45 VNQ7E100AJ PowerSSO-16 marking information 7.3 PowerSSO-16 marking information Figure 51. PowerSSO-16 marking information Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not to scale) GADG0310161234SMD Parts marked as '&' are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12570 - Rev 3 page 40/45 VNQ7E100AJ Revision history Table 20. Document revision history Date 08-June-2018 Version Changes 1 Initial release. Updated features and application in cover page. 08-Jan-2019 2 Updated Table 4. Thermal data, Section 2.3 Main electrical characteristics, Figure 12. Standby mode activation. Inserted Section 2.5 Electrical characteristics curves, Section 5 Maximum demagnetization energy (Vcc = 16 V) and Section 6 Package and PCB thermal data. Minor text changes. 18-Feb-2019 DS12570 - Rev 3 3 Updated Figure 44 and Figure 45. page 41/45 VNQ7E100AJ Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 2.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.1 Power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 Negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.1 GND protection network against reverse battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 Diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 CS - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.1 Principle of CurrentSense signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.2 Short to VCC and OFF-state open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Maximum demagnetization energy (VCC = 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 6 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.1 7 PowerSSO-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.1 PowerSSO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 PowerSSO-16 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 PowerSSO-16 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DS12570 - Rev 3 page 42/45 VNQ7E100AJ List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested connections for unused and not connected pins . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics during cranking . . . . . . . . . . . . . . . Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense multiplexer addressing . . . . . . . . . . . . . . . . . ISO 7637-2 - electrical transient conduction along supply line CurrentSense pin levels in off-state . . . . . . . . . . . . . . . . . . PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 mechanical data . . . . . . . . . . . . . . . . . . . . . Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape dimensions . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . DS12570 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 . 6 . 7 . 7 . 8 . 8 . 9 10 15 15 26 30 33 35 37 38 39 41 page 43/45 VNQ7E100AJ List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. DS12570 - Rev 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching times and Pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current sense timings (current sense mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TDSKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition. . . . . . . . . . . . . . . . . . . . . . Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) . Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGND(ON) vs. Iout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FaultRST Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF-state open-load voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSENSE clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSENSEH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense and diagnostic - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CurrentSense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog HSD - open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off current versus inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum turn off energy versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) . . . . . Thermal fitting model of a double-channel HSD in PowerSSO-16 . . . . . . . . . . . . . . . . . PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 reel 13" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 schematic drawing of leader and trailer tape . . . . . . . . . . . . . . . . . . . . . PowerSSO-16 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 5 12 13 13 14 14 16 16 17 17 18 19 19 19 19 19 19 20 20 20 20 20 20 21 21 21 21 21 21 22 24 25 27 28 29 30 32 32 33 33 34 34 35 36 38 39 39 40 page 44/45 VNQ7E100AJ IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS12570 - Rev 3 page 45/45