ADVANCE INFORMATION MX29VW160T/B 16M-BIT [2M x 8-BIT/1M x16-BIT] SIMULTANEOUSREAD/WRITE - SINGLE 2.5V OPERATION FLASH MEMORY FEATURES * Two Memory Banks for Simultaneous Read/Write op- erations - Host system can program or erase in one bank and simultaneously read from the other bank - Zero latency between simultaneous Read/Write op- erations -Read-While-Erase/Program Extended Single-supply voltage range from 2.25V to 3. OV for read, erase and write operations + JEDEC-standard EEPROM commands * Minimum 100,000 write/erase cycles * Fast Access time: 120ns * Optimized block architecture: - Bank A - Eight 8K Byte (4K Word) blocks - Three 64K Byte (32K Word) blocks - Bank B - Twenty-eight 64K Byte (32K Word) blocks + Data polting and toggle bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY): Hardware method for detection of program or erase cycle completion * Automatic standby mode: When addresses remain stable,automatically switch themseives to low power mode(1uA Typical) * Auto erase operation - Automatically erases any combination of the blocks or the whole chip - Fast erase time: 20ms typical for single block erase and 50ms typical for chip erase and multi-block erase Auto page program operation - Automatically programs and verifies data at specified addresses - Internal address and data latches for 128 Bytes (64 Word) per page in each bank - Fast program time: 4ms typical for page program * Built-in 128 Bytes/64 Words page buffer in each bank - Work as SRAM for temporary data storage - Fast access to temporary data * Low power dissipation (typical values at 8MHz) - 40mA typical for Read While Write - 20mA typical for Read - 1uA typical for standby * Hardware reset pin (RP) - Reset internal state machine and put the device into standby mode * Hardware write protect pin (WP) - Allows protection of the first two 8K Byte blocks, regardless of their orginal protect status. * Group Protection - Hardware method of locking groups to prevent any program or erase operation within that group - Any group can be locked in-system or via program- ming equipment - Temporary group unprotect feature allows code change in any previously locked group * Erase Suspend/Erase Resume - Suspends or resumes erasing blocks to allow reading and programming in other blocks. - Itis not necessary to do erase suspend if reading or programming blocks in the other bank * Low Vec write inhibit is equal to or less than 1.6V * Compatible with JEDEC-standard pinouts - 48-pin TSOP (I) - 48-ball CSP P/N:PM0567 35-1 REV. 0.7, EFB. 12, 1999GENERAL DESCRIPTION The MX29VW160T/B is a 16Mbit Flash memory organized as either 2M-byte by 8-bit or 1M-word by 16-bit. To provide simultaneous operation which can read a data while pro- gram/erase,the 16Mbits of data is divided into two banks of bank A ( 2M bit) and bank B(14M bit). Bank A is orga- nized by eight 8K-byte blocks and three 64k-byte blocks. Bank Bis organized by twenty-eight 64K-byte blocks. To allow for simple in-system operation with very low op- eration voltage, MX29VW160T/B can be operated with a single 2.25V to 3.0V supply voltage.Manufactured with MXICs advanced nonvolatile memory technology, the device offers access times of 120ns, and a low 1uA typi- cal standby current. The MX29VW160T/B command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard micro-pro- cessor write timings. MXICs flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device RY/ BY pin provides a convenient way to monitor when a pro- gram or erase cycle is complete. Programming the MX29VW160T/B is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Pro- gram time is 4ms. The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar to reading from an EPROM or other flash. Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase algorithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MXICs advance design technology, no preprogram is required (internally or externally). As a result, the whole chip can be typically erased and verified in as fast as 50ms. MX29VW160T/B Acombined feature of Reset Pin (RP), a hardware lockout bit, and software command sequences provide complete data protection. First, software data protection protects the device from inadvertent program or erase. Two "unlock" write cycles must be presented to the device before the program or erase command can be accepted by the device. For hardware data protection, the RP pin provide protec- tion against unwanted command writes due to invalid sys- tem bus condition that may occur during system reset and power up/down sequence. Finally, with a hardware lockout bit feature, the device provides complete core security for the kernal code required for system initialization. MXICs flash technology reliably stores memory contents after 100,000 erase and program cycles. The MXICs cell is designed to optimize the erase and program mechanism. |n addition, the combination of ad- vanced tunnel oxide processing and low internal electric fields for erase and program operations produce reliable cycling. The highest degree of latch-up protection is achieved with MXICs proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to Vec+1V. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-2=I, PINOUT 48-PIN TSOP(I) 12mm x 20mm ag 54 48] ate Ata 2 47) BYTE aig 19 46 GND aes 45) arsat a 44} a7 aio 8 aa} ats Ag 7 42 8 ae a ay} ais ag (9 4} Os NG 0 ag an We ou ze [| Qa AB 2 Mx2evW 16078 a7} Vee NC 13 a6} Ott we is as| ag AYIBY 115 3%] ato a8 16 a3} OR ar a7 go} as a 8 auf oat ae | 19 30 | aa AS | 20 29| oo Abia ze} OE a | 2 2 | GND a2 26 AL | 2a 25 | Ao MX29VW160T/B PIN DESCRIPTION SYMBOL _ PIN NAME AQ~A19 Address input Q0~Q14 _ Data Input/ Output QI15/A-1 Q15 (word mode)/LSB addr. (byte mode) CE Chip Enable Input OE Output Enable Input WE Write Enable WP Write Protect RP Reset/Deep Power-down RY/BY Ready/Busy Output BYTE Word/Byte Selection Input Vec Power Supply Pin (2.25V ~ 3.0V) GND Ground Pin No Intemal! Connection Pin 48-Ball CSP 8mm x 13mm x 1.2mm(Ball Pitch = 0.8 mm), Top View, Balls Facing Up A B c D E F G -H 1] A3 A4 A2 Al AO CE OE GND | 2| A7 A17 | AG A5 Qo a8 ae Qt 3| RY/BY| WP | A18 | NC ae Qi0 | Qi Q3 4| WE RP NC A195 Qi2 | Veo 14 5 | Ag A8 Aio | Att Q7 Qi4 | Qi3 | a6 6| A13 Ai2 | Al4 A15 Ai6 BYTE} Q15/A-1| GND P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-3MxX29VW160T/B Table 1 Block Architecture (Word Mode Addr. :AO~A19, BYTE Mode Addr.:A-1~A19) Byte Mode (A-1 TO A19) Word Mode (AO TO A19) 1FFFFF~1FE000 FFFFF~FFO0O 8K-Byte Block SA01 GAO1 BANK A 1FDFFF~1FC000 FEFFF~FEO0O 8K-Byte Block SA02 GA02 BANK A 1FBFFF~1FA000 FDFFF~FD000 8K-Byte Block SA03 GA03 BANK A 1FOFFF~1F8000 FCFFF~FCo00 8K-Byte Block SA04 GA04 BANK A 1F7FFF~1F6000 FBFFF~FBOOO 8K-Byte Block SA05 GAO0S BANK A 1F5FFF~1F4000 FAFFF~FAO0O 8K-Byte Block SA06 GA06 BANK A 1F3FFF~1F2000 FOFFF~F9000 8K-Byte Block SA07 GA07 BANK A 1F1FFF~1FO000 F8FFF~F8000 8K-Byte Block SA08 GA08 BANK A 1EFFFF~1E0000 F7FFF~FO000 64K-Byte Block SA09 GAO09 BANK A 1DFFFF~1D0000 EFFFF~E8000 64K-Byte Block SA10 GAO09 BANK A 1CFFFF~1C0000 E7FFF~E0000 64K-Byte Block SA11 GA09 BANK A 1BFFFF~1B0000 DFFFF~D8000 64K-Byte Block SA12 GA10 BANK B 1AFFFF~1A0000 D7FFF~D0000 64K-Byte Block SA13 GA10 BANK B 19FFFF~190000 CFFFF~C8000 64K-Byte Block SA14 GA10 BANK B 18FFFF~180000 C7FFF~C0000 64K-Byte Block SA15 GA10 BANK B 17FFFF~1 70000 BFFFF~B8000 64K-Byte Block SA16 GA11 BANK B 16FFFF~160000 B7FFF~BO000 64K-Byte Block SA17 GA11 BANK B 15FFFF~150000 AFFFF~A8000 64K-Byte Block SA18 GA11 BANK B 14FFFF~140000 A7FFF~A0000 64K-Byte Block SA19 GA11 BANK B 13FFFF~130000 OFFFF~98000 64K-Byte Block SA20 GA12 BANK B 12FFFF~120000 97FFF~90000 64K-Byte Block SA21 GAi2 BANK B 11FFFF~110000 8FFFF~88000 64K-Byte Block SA22 GA12 BANK B 10FFFF~100000 87FFF~80000 64K-Byte Block SA23 GAi2 BANK B OFFFFF~OFO000 7FFFF~78000 64K-Byte Biock SA24 GA13 BANK B OEFFFF~OE0000 77FFF~70000 64K-Byte Block SA25 GA13 BANK B ODFFFF~oD0000 6FFFF~68000 64K-Byte Block SA26 GA13 BANK B OCFFFF~0C0000 67FFF~60000 64K-Byte Block SA27 GA13 BANK B OBFFFF~OB0000 5FFFF~58000 64K-Byte Block SA28 GA14 BANK B OAFFFF~OA0000 57FFF~50000 64K-Byte Block SA29 GA14 BANK B O9FFFF~090000 4FFFF~48000 64K-Byte Block SA30 GA14 BANK B O8FFFF~080000 47FFF~40000 64K-Byte Block SA31 GA14 BANK B 07FFFF~070000 3FFFF~38000 64K-Byte Block SA32 GAI5 BANK B O6FFFF~060000 37FFF~30000 64K-Byte Block SA33 GA15 BANK B O5FFFF~050000 2FFFF~28000 64K-Byte Block SA34 GA15 BANK B O4FFFF~040000 27FFF~20000 64K-Byte Block SA35 GA15 BANK B O38FFFF~030000 1FFFF~18000 64K-Byte Block SA36 GA16 BANK B 02FFFF~020000 17FFF~10000 64K-Byte Block SA37 GA16 BANK B 01FFFF~010000 OFFFF~08000 64K-Byte Block SA38 GAI6 BANK B OOFFFF~000000 07FFF~00000 64K-Byte Block SA39 GA17 BANK B MX29VW160T P/N:PM0567 35-4 REV. 0.7, EFB. 12,1999M=Ic A MxX29VW160T/B Byte Mode (A-1 TO A19) Word Mode (AO TO A19) 1FFFFF~1FO000 FFFFF~F8000 64K-Byte Block SA01 GA01 BANK A 1EFFFF~1E0000 F7FFF~FO000 64K-Byte Block SA02 GA02 BANK A 1DFFFF~1D0000 EFFFF~E8000 64K-Byte Block SA03 GA02 BANK A 1CFFFF~1C0000 E7FFF~E0000 64K-Byte Block SA04 GA02 BANK A 1BFFFF~1Bo000 DFFFF~D8000 64K-Byte Block SA05 GA0S3 BANK A 1AFFFF~1A0000 D7FFF~DO000 64K-Byte Block SA06 GA0S BANK A 19FFFF~190000 CFFFF~C8000 64K-Byte Block SA07 GA03 BANK A 18FFFF~180000 C7FFF~C0000 64K-Byte Block SA08 GA03 BANK A 17FFFF~170000 BFFFF~B8000 64K-Byte Block SA09 GA04 BANK A 16FFFF~160000 B7FFF~B0000 64K-Byte Block SA10 GA04 BANK A 15FFFF~150000 AFFFF~A8000 64K-Byte Block SA11 GA04 BANK A 14FFFF~140000 A7FFF~A0000 64K-Byte Block SA12 GA04 BANK A 13FFFF~130000 QFFFF~98000 64K-Byte Block SA13 GA0S5 BANK A 12FFFF~120000 97FFF~80000 64K-Byte Block SA14 GA05 BANK A 11FFFF~110000 8FFFF~88000 64K-Byte Block SA15 GA05 BANK A 10FFFF~100000 87FFF~80000 64K-Byte Block SA16 GAQ5 BANK A OFFFFF~OFO000 7FFFF~78000 64K-Byte Block SA17 GAO6 BANK A OEFFFF~OE0000 77FFF~70000 64K-Byte Block SA18 GAQ6 BANK A ODFFFF~OD0000 6FFFF~68000 64K-Byte Block SA19 GA06 BANK A OCFFFF~OC0000 67FFF~60000 64K-Byte Block SA20 GA06 BANK A OBFFFF~OBO000 5FFFF~58000 64K-Byte Block SA21 GA07 BANK A OAFFFF~OA0000 57FFF~50000 64K-Byte Block SA22 GA07 BANK A O9FFFF~090000 4FFFF~48000 64K-Byte Block SA23 GAO7 BANK A O8FFFF~080000 47FFF~40000 64K-Byte Block SA24 GA07 BANK A 07FFFF~070000 SFFFF~38000 64K-Byte Block SA25 GAQ8 BANK A O6FFFF~060000 37FFF~30000 64K-Byte Block SA26 GA08 BANK A O5FFFF~050000 2FFFF~28000 64K-Byte Block SA27 GA08 BANK A OQ4FFFF~040000 27FFF~20000 64K-Byte Block SA28 GA08 BANK A OSFFFF~030000 1FFFF~18000 64K-Byte Block SA29 GAO0S BANK B O2FFFF~020000 17FFF~10000 64K-Byte Block SA30 GAOS BANK B 01FFFF~010000 OFFFF~08000 64K-Byte Block SA31 GA0S BANK B OOFFFF~OOE000 07FFF~07000 8K-Byte Block SA32 GAI0 BANK B OODFFF~00C000 O6FFF~06000 8K-Byte Block SA33 GAT1 BANK B OOBFFF~00A000 O5FFF~05000 8K-Byte Block SA34 GA12 BANK B OOSFFF~008000 04FFF~04000 8K-Byte Block SA385 GA13 BANK B 007FFF~006000 O3FFF~03000 8K-Byte Block SA36 GA14 BANK B 0O5FFF~004000 02FFF~02000 8K-Byte Block SA37 GA15 BANK B O03FFF~002000 01FFF~01000 8K-Byte Block SA388 GA16 BANK B 001FFF ~000000 OOFFF~00000 8K-Byte Block SA39 GA17 BANK B MX29VW160B P/N:PM0567 35-5 REV. 0.7, EFB. 12, 1999M=I MxX29VW160T/B Block Diagram CE+ __ OE+| Control RYIBY WE+_ Input Wwpes Logic }/_______ RP Write State Command Interface Machine (WSM) Register (CIR) x it oO Bank A Command Data 8 4KWISKB x 8 Latch R S2KW/G4KB x 3 < o Page Buffer rc MUX 8 & Y-Pass Gate Program/ = Address 6 Cc > Erase Latch & . sg: D Q0~Q15/A-1 ~ . h AQ~A19 Butter | Act aan Sense Ampliier) MUX c age i Th WSM * 0 -Pass Gate [bn MUX | 8 i o Page Buffer WSM x o Bank B 8 (32KW/64KB x28) oO P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-6NM=Ic . MxX29VW160T/B BUS OPERATIONS Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized below. Table 2.1 MX29VW160T/B Bus Operations for Byte-Wide Mode (Byte = VIL) MODE CE OF WE RP WP AO At A6 AS Q0-07 Q8~Q14 Q15/A-1__Notes Read LoL H H L/H AQ A1_ A6 AQ DOUT _ HighZ A-1 1,2,7,9 Output Disable L H H H xX xX X X XxX HighZ _ HighZ x 1,6,7 Standby H xX xX HX X X X X HighZ __ HighZ Xx 1,6,7 Hardware Standby X X Xx L X X % X X HighZ _ HighZ x 1,3 Manufacturer ID L L H HH WH LoL X VID C2H HighZ x 4,8 Device ID boot H H UH H LL X VID 67/68H_ HighZ xX 4,8 Block Protect Verify * Lt 4H H =H tL H X VID C2H HighZ x Write LH OL H LWHNVID AO Ai A6 AQ __ DIN High Z A-1 1,5,6,10 Table 2.2 MX29VW160T/B Bus Operations for Word-Wide Mode (Byte = VIH) MODE CE OE WE RP WP AO A1 A6_ AQ Q0-Q7 Q8-Q14_ QI15/A-1_ Notes Read LoL oH HLA AO Ai A6 AQ DOUT DOUT DOUT 1,27 Output Disable LH HH xX X xX X X HighZ HighZ ss HighZ 16,7 Standby H X XH xX X =X X X HighZ HighZ HighZ_1,6,7 Hardware Standby X xX xX LX X xX X X HighZ HighZ ~~ HighZ_1,3 Manufacturer ID L L H H L/H L L xX VID C2H OOH 0B 4,8 Device ID LL eH HUH H LX VID 67/68H OOH 0B 48 Block Protect Verify" LoL oH =H =H LH X VID C2H OOH 0B Write LH -~ _H__UHWID_AO_ Ai AG AQ DIN DIN DIN 1,5,6,10 *: Valid Sector Address must be provided when doing block protect Verify mode. Legend : L = Logic Low = VIL, H = Logic High = VIH ,X = VIL or VIH, VID = 8.5~10.5V ,Refer to DC Characteristics for Voltage loads. Notes: 1. X can be VIH or VIL for address or control pins except for RY/BY which is either VOL or VOH. __ 2. RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH, if it is tied to Vec through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3. RP< GND+0.2V ensures the lowest consumption current. 4. AO and Ai at VIL provide manufacturer ID code. AO at VIH and At at VIL provide !D code. AO at VIL, A1 at VIH and with appropriate block address provide Block Protect Code.(Refer to Table 4) 5.Command or different Erase operations, Data program operations or Group protect operation can only be successfully com- pleted through proper command sequence. 6. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7.RY/BY may be at VOL while the WSM is busy performing various operations. 8.VID = 8.5V-10.5V 9. Q15/A-1 = VIL, Q0-Q7 = DO-D7 out. Q15/A-1 = VIH, Q0-Q7 = D8-D15 out. 10. When WP=VIL, the two outer most 8K-Byte blocks be protected. When WP=VIH, all blocks remain orginal protect status. When WP=VID, all blocks be unprotected. P/N:PM0567 REV.0.7, EFB. 12, 1999 35-7M=I MxX29VW160T/B COMMAND DEFINITIONS Table 3 Command Definitions Bus Cycles First Second Third Fourth Fifth Sixth Addr | Data| Addr | Data/Addr | Data! Addr | Data Addr |DatajAddr |Data Read 1) RA RD Reset 1| XXXH | FOH Manufacturer ID | Word} 4;/555H ; AAH | 2AAH| 55H |555H | 90H | XOOH | 00C2H Byte AAAH 555H AAAH XO0H | C2H Device ID Word] 41555H | AAH | 2AAH | 55H |555H | 90H | X01H | 0067H/0068H* Byte AAAH 555H AAAH X02H | 67H/68H* Block Protect Word! 4|/555H | AAH | 2AAH| 55H |555H | 90H | X02H | XX01H/XX00H" Verify Byte AAAH 555H AAAH X04H | 01H/00H* Group Protect Word} 6]/555H | AAH | 2AAH| 55H |555H | 60H | 555H | AAH 2AAH|55H |GA_ {20H Byte AAAH 555H AAAH AAAH 555H Group Unprotect| Word| 6] 555H | AAH | 2AAH| 55H 1555H | 60H | 555H | AAH 2AAH| 55H |555H |40H Byte AAAH 555H AAAH AAAH 555H AAAH Page/Byte Word 555H | AAH | 2AAH/ 55H 1555H | AOH| PA PD Program Byte AAAH 555H AAAH Single Block Word] 6] 555H | AAH | 2AAH | 55H /555H | 80H | 555H | AAH 2AAH|55H |SA = |20H Erase Byte AAAH 555H AAAH AAAH 555H Multi Biock Word| 6] 555H | AAH | 2AAH| 55H |555H | 80H | 555H | AAH 2AAH/55H |SA [30H Erase Byte AAAH 555H AAAH AAAH 555H Chip Erase Word| 6] 555H | AAH | 2AAH/ 55H /555H | 80H | 555H | AAH 2AAH! 55H |555H |10H Byte AAAH 555H AAAH AAAH 555H AAAH Erase Suspend 1| XXXH | BOH Erase Resume 1| XXXH | 30H Notes: 1. OOH Represents unprotect block & *01H represents protect block in the 4th Bus cycle data of "Block Protect Verity. 2. Address bit A11-A19 = X = "Don't care" for all address commands except for Program Address (PA) and Block Address (SA). 555H and 2AAH address command codes stand for Hex number starting from AO to A10 in word mode and A-1 to A10 in byte mode. 3.Bus operations are defined in Table 2. 4. RA = Address of the memory location to be read. __ PA = Address of the memory location to be programmed. Address are located on the falling edge of the WE pulse. SA = Address of the block to be erase. The combination of A12-A19 will select any block(Refer to Table 1). GA = Group address to be protect. The combination of A12-A19 will select any group. 5.RD = Data read from location RA during read operation. __ PD = Data to be Programmed at location PA. Data is latched on the rising edge of WE. 6.Only Q0-Q7 command data is taken, Q8 to Q15 = Dont care. *Refer to Table 4. P/N:PMO567 REV. 0.7, EFB. 12, 1999 35-8NM=Iic MxX29VW160T/B FUNCTIONAL DESCRIPTION SIMULTANEOUS OPERATION The MX29VW160T/B provides the simultaneous read/write The MX29VW160T/B contains two data banks which are function. The device is capable of reading data from one bank A (8K-Byte x 8, 64K-Byte x 3} and Bank B (64K- bank and simultaneously erasing (so as, programming, erase- Byte x 28). Following table describes the detail simulta- suspend reading, and erase suspend programming) data neous operation. from the other bank. The bank selection can be selected by bank address (A17 to A19) with zero latency. Simultaneous Operation Table Bank-B |standby| Read! Single! Multiple block|Multiple block |Chip| Erase | Erase | Page | Group | Silicon mode} block erase erase erase|suspend|resume|program| protect/ ID Bank-A erase | (only 1 bank); (2 banks) lunprotect| read Standby oO - - - - - - - - - - Read mode : Xx oO oO X : Oo {e) oO - Single block erase - oO : : - : - - xX xX - Multipie block erase - 0 - - - - x - - (only 1 bank) Multiple block erase Xx - - oO oO O X xX - (2 banks) Chip erase - - - oO - - - - - Erase suspend - O - 0 - - - X 0 Erase resume - 0 : - oO : - - Xx - Page program - (e) X x xX - - - - X - Group protect/ - X X - xX - xX X Xx - unprotect Silicon ID read : : : - : - oO : - Legend : o"=Okay,"X"= Not allow, "-"= Not available. P/N:P 7 REV. 0.7, EFB. 12, 1999 Mose 35-9M=Ic READ ARRAY MODE The MX29VW160T/B must satisfy two control functions to obtain data output. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected.(Figure 11) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from state the falling edge of CE to valid data at the output pins. (Assuming the ad- dresses have been stable for at least tACC - tCE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from "H to "L". READ/RESET COMMAND The Read or Reset operation is initiated by writing the read/ reset command sequence into the command register. Mi- croprocessor read cycles retrieve array data from the memory. The device remains enable for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will re- trieve array data. This default value ensures that no spuri- ous alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms (Figure 12) for the specific timing parameters. MxX29VW160T/B READ ID MODE Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manu- facturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29VW160T/B contains a Silicon-ID-Read Opera- tion to supplement traditional PROM programming method- ology. The operation is initiated by writing the Read Silicon ID command sequence into the command register. Fol- lowing the command write, a read cycle with A1=VIL, AO=VIL retrieves the manufacturer code of C2H. A read cycle with Ai=VIL, AO=VIH returns the device code of 67H for MX29VW160T, 68H for MX29VW160B. The Silicon-ID-Read Operation also covers the block pro- tection verification. A read cycle with A1=VIH, A0= "Dont care returns data of OOH for"unprotected block" and 01H for "protected block". P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-10M=Iic MxX29VW160T/B Tabie 4.1 Read ID Mode Tabie TYPE A12 to A19 A6 At AO A-1 Code (HEX) Manufacturer ID X Xx L L xX C2H MX29VW160T Byte x x L H * ar Device ID MX29VW/160B Byte | X X L H xX 68H Word Xx 6068H Block Protection Verify Block Address | X H Xx xX O01H/O0H* *O1H for "protected block" addresses and 00H for "unprotected block addresses. Table 4.2 Extended Read ID Mode Table TYPE 1 1 MX29VW160T 67H A-1_ | Hi-Z] HI-2Z| HI-Z|HI-Z | HI-Z| HI-Z} HI- ID MxX29VW160B 68H A-1_ | HI-Z] Hi-Z | Hi-Z|HI-Z; HI-Z| HI-Z} HI- Notes: * Manufacture Code = C2 H, Device Code = 67H/68H when BYTE = VIL Manufacture Code = 00C2H,Device Code =0067H/0068H when BYTE = VIH ** Outputs 01H at protected block address ,0OH at unprotected block address. P/N:PM0567 REV.0.7, EFB. 12, 1999 35-11MxX29VW160T/B PROGRAM MODE PAGE PROGRAM The MX29VW160T/B is page programmable with one 128- Byte/ 64-Word page buffer in each bank. To initiate Page program mode, a three-cycle command sequence is required. There are two unlock write cycles. These are followed by writing the page program command AOH. Any attempt to write to the device without the three-cycle com- mand sequence will not start the internal Write State Ma- chine (WSM), no data will be written to the device. After three-cycle command sequence is given, a Byte/ Word load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first ris- ing edge of CE or WE. Maximum of 128-Byte/64-Word of data may be loaded into each page. Data loading activity is terminated by issuing same address load twice. BYTE-WIDE LOAD/WORD-WIDE LOAD Byte (Word) loads are used to enter the 128 bytes (64 words) of a page to be programmed or the software codes for data protection. A byte load (word load) is performed by applying a low pulse on the WE or CE input with CE or WE low respectively, and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Either byte-wide load or word-wide load is determined (Byte = VIL or VIH is latched) on the falling edge of the WE (or CE) during the 3 command write cycle. AUTOMATIC PROGRAM ALGORITHM Any page to be programmed should have the page in the erased state first, i.e. performing block erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of the page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. A6 to A19 specify the page address, i.e., the device is page-aligned on 128-byte boundary. The page addresses must be valid (Page Ad- dress A6-A19 is latched at the 4th bus write-cycle)during each high to low transition of WE or CE. A-1 to AS specify the byte address during the page. The byte may be loaded in any order; sequential loading is not required. The load period will also end if the same address is consecutively loaded twice. For the last two same address, the first ad- dress and data will be treated as normal data to be programmed. The second one must keep the same ad- dress and data as the first one. The status of program cycle can be determined by check- ing the Q7 (Data Polling), Q6 (Toggle Bit), or RY/BY. The automatic programming operation is completed when Q6 stops toggling (See Table 5 of Hardware Sequence Flags.) WRITE OPERATION STATUS Detailed in Table 5 are all the status flags that can deter- mine the status of the bank for the current mode operation. The read operation from the bank where is not operating Automatic algorithm returns a data of memory cell. These bits offer a method for determining whether a Automatic Algorithm is completed properly. The information on Q2 is address sensitive. This means that if an address from an erasing block is consecutively read, then the Q2 bit will toggle. However, Q2 will not toggle if an address from a non-erasing block is consecutively read. This allows the user to determine which blocks are erasing and which are not. The status flag is not output from bank (non-busy bank) not executing Automatic Algorithm. For example, there is bank (busy bank) which is now executing Automatic Algo- rithm. When the read sequence is (a)"busy bank (b)"non- busy bank" and (c )"busy bank" the Q6 is toggling in the case (a) and (c ). In case of (b), the data of memory cell is output. In the erase-suspend read mode with the same read sequence, Q6 will not be toggled in the (a), and (c). In the erase suspend read mode, Q2 is toggled in the (a) and (c ). In case of (b), the data of memory cell is output. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-12M=Ic MxX29VWw1 6O0T/B Table 5. Hardware Sequence Flags Table Automatic In Progress | Suspend Mode Automatic Program Algorithm Toggie Automatic Erase Te Suspend (Non-Erase-Suspend Block) *. Successive reads from the erasing block will cause Q2 to toggle. Reading from non-erase block address will indicate logic "1" at the Q2 bit. . REV. 0.7, EFB. 12, 1999 P/N:PM0587 35-13M=Iic ERASE MODE AUTOMATIC CHIP ERASE The MX29VW160T/B does not require pre-program opera- tion prior to erase operation. Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command (80H). Two more "unlock" write cycles are then followed by the Chip Erase command (10H). The system can determine the status of the erase opera- tion by using Q7 (Data Polling), Q6 (Toggle Bit), or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on Q7 is (See Write Opera- tion Status section.) at which time the device returns to read the mode. AUTOMATIC BLOCK ERASE The MX29VW160T/B does not require pre-program opera- tion prior to erase operation. Block erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command (80H). Two more "unlock" write cycles are then followed by the Block Erase command (20H for single-block erase, 30H for multi-block erase). The system is not required to provide any controls or timings during these operations. When erasing a block or blocks the remaining un-selected blocks are not affected. The block address is latched on the falling edge of CE or WE whichever happens later, while the command (data) is latched on the rising edge of CE or WE whichever hap- pens first.After issue same address (A12-A19) twice ,the device will stop block address loading and start erase op- eration when at multi-block erase mode. Before issued the same address twice to the device, any command other than Erase Suspend (BOH) or multi block Erase (30H) will reset the device to read mode and ignore the previous command string. The system can determine the status of the erase opera- tion by using Q7 (Data Polling), Q6 (Toggle Bit), or RY/BY. MX29VW160T/B ERASE SUSPEND AND RESUME The Erase Suspend command ,BOH allows the user to interrupt a Block Erase operation and then perform data reads from or program to a block not being erased. This commandis applicable ONLY during the Block Erase opera- tion. The Erase Suspend command will be ignored if writ- ten during the Chip Erase operation or Auto Program Algorithm. Writing the Erase Suspend command (BOH) during the multiple block erase operation (before issue same address twice to terminate the block address loading and to start the erase operation) results immediate termination of the address loading and suspension of the erase operation. Writing the Erase Resume command (30H) resumes the erase operation. When the Erase Suspend command is written during the Block Erase operation, the device will take a maximum of 300us to suspend the erase operation. When the devices have entered the erase suspended mode, the RY/BY out- put pin will be at HighZ . The user must use the Q6 (or RY/ BY pin) to determine if the erase operation has been sus- pended. Further writes of the Erase Suspend command are ignored. To resume the operation of Block Erase, the Resume com- mand (30H) should be written . Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. STANDBY MODE MX29VW160T/B can be set into Standby mode with two different approaches. One is using both CE and RP pins and the other one is using RP pin only. When using both pins of CE and RP, a CMOS Standby mode is achieved with both pins held at Vcc + 0.3V. Un- der this condition, the current consumed is less than 1uA (typ.). During Auto Algorithm operation, Vcc active cur- rent (Icc2) is required even CE = "H".The device can be read with standard access time (tCE) from either of these standby modes. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-14When using only RP, a CMOS standby mode is achieved with RP input held at Vss + 0.3V Under this condition the current is consumed less than 1UA (typ.). Once the RP pin is taken high,the device is back to active without recovery delay. In the standby mode the outputs are in the high impedance state, independent of the OE input. AUTOMATIC STANDBY MODE MX29VW160T/B is capable to provide the Automatic Standby Mode to restrain power consumption during read- out of data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To active this mode, MX29VW160T/B automatically switch themselves to low power mode when MX28VW160T/B addresses remain stable during access time of 250ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1uA (CMOS level). During Simultaneous operation, Vcc active current (Icc2) is required.Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and MX29VW160T/B read-out the data for changed addresses. OUTPUT DISABLE With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state. DATA PROTECTION The MX29VW160T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the inter- nal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory con- tents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power- up and power-down transitions or system noise. MX29VW160T/B TEMPORARY GROUP UNPROTECT This feature allows temoprary unprotection of previously protected group to change data in-system. The Temporary Group Unprotect mode is activated by setting the RP pin to VID(8.5V-10.5V). During this mode, formerly protected groups can be programmed or erased as un-protected group. Once VID is remove from the RP pin,all the previ- ously protected group are protected again.Figure 1 shows the algorithm, for this feature. GROUP PROTECTION To activate this mode,a six-bus cycle operation is required. there are two "unlock" write cycle. There are followed by writing the setup command. Two more "unlock" write cycles are then followed by the lock group command-20H. Group address(A12~A19) is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Q6 stops toggling(or RY/BY =1) at which time the device stays at the read array mode. The devcie remains enabled for read array mode until the CIR contents are altered by a valid command sequence (Refer to the table 3 ). GROUP UNPROTECT Itis also possible to unprotect all groups,same as the first five write command cycle in activating group protection mode followed by the unprotect group command -40H, the automatic unprotect operation begins on the rising edge of the last WE pulse in the command sequence and termi- nates when the Q6 stops toggling (or RY/BY =1) at with time the device stays at the read array mode.(Refer to table 3 ).Note that all groups are unprotected after group unprotection completed. The device remains enable for read array mode until the CIR content are altered by a valid command sequence. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-15M=Iic MxX29VW160T/B RP vs WP Truth Table AP} VIL VIH VID WP VIL Hardware Standby | The two outer most 8K-Byte be protected, | The two outer most 8K-Byte blocks be protected, all other blocks remains at original protect | all other blocks be unprotected. status. MIH Hardware Standby } All blocks remain at origined protect status. | All blocks be unprotected. VID Hardware Standby | All blocks be unprotected. All blocks be unprotected. VERIFY BLOCK PROTECT To verify Protect status of the block,operation is initiated by writing Silicon ID read command into the command register. Following the command write ,a read cycle from address XXX2H(A1=VIH) and Group Address (A15~A19) returns data of OOH for unprotected block". A read cycle from XXX2H(A1=VIH) and group address (A15~A19) returns data of 01H for "protected block. Figure 1 Temporary Block Unprotect Operation RP = VID (Note 1) | | | Perform Erase or Program Operation | | Operation Completed | |! [ RP= VIH | | Temporary group Unprotect Completed(Note 2) | Note: 1. All protected groups are temporary unprotected. VID=8.5V~10.5V 2. All previously protected groups are protected again. P/N:PMO567 REV. 0.7, EFB. 12, 1999 35-16= MX29VWw160T/B Figure 2 Group Protection Algorithm (Word Mode) Start PLSCNT =0 Write Data AAH Address 555H increment PLSCNT, To Protect Group Ag: Group Protect Operation Terminated Device Failed No Write Silicon ID Read Command & Read Data with A1=VIH, Data = 01H ? A15-A19=Group Address * Group Address : A12~A19 oo Yes Read RY/BY No Le Yes Group Protected,Operation Done,Device Stays at Read Array Mode Contirm Group Protection Status K REV. 0.7, EFB. 12, 1999 P/N:PM0567 35-17== MxX29VW160T/B Figure 3 Group Unprotection Algorithm (Word Mode) Start PLSCNT =0 Write Data AAH Address 555H Read RY/BY Increment! fo Unprotect PLSCN Group Again PLSCNT = 32? Unprotect Group ration Terminated Device Failed Write Silicon ID Read Command & Read Data with A1=VIH,A12~A19 = Group Address. For avery Group Data = 00H ? Yes RY/BY = 1? Read Data for every Group Contirm Group Unprotection Status . Group Unprotected,Operation Note : *All group are unprotected after group unprotection completed. Done,Device Stays at Read Array Mode P/N:PMO567 REV. 0.7, EFB. 12, 1999 35-18M=ic WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typ.) on CE or WE will not initiate a write cycle. LOGIC INHIBIT Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical "0" while OE is a logical "1". POWER-UP SEQUENCE The MX29VW160T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its Vcc and GND. Q7: Data Poliing The MX29VW160T/B features Data Polling as a method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress or completed. While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to Q7. Upon completion of the Automatic Program algorithm an attempt to read the de- vice will produce the true data last written to Q7. The Data Polling feature is valid after terminating load operation for automatic program. While the Automatic Erase algorithm is in operation, Q7 will read "0" until the erase operation is competed. Upon completion of the erase operation, the data on Q7 will read "1" The Data_Polling feature is valid after the rising edge of the sixth WE pulse of six write pulse sequences for automatic chip/block erase. The Data Polling feature is active during Automatic Pro- gram/Erase algorithm (see section Q3 Block Erase Status Bit ). MX29VW160T/B RY/BY: Ready/Busy The RY/BY is a dedicated, open-drain output pin that indi- cates whether an Automatic Erase/Program algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to Vcc. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 5 shows the outputs for RY/BY. Q6: Toggle Bit! Toggle Bit | on Q6 indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend made. Toggle Bit | may be read at any address, and is valid after the rising edge of the final WE pulse in the command se- quence (prior to the program or erase operation), and dur- ing the block erase time-out period. During an Automatic Program or Erase algorithm operation, successive read cycies to any address cause Q6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6 stops toggling. After an erase command sequence is written, if all blocks selected for erasing are protected, Q6 toggles and returns to reading array data. If not all selected blocks are protected, the Automatic Erase algorithm erases the un-protected blocks, and ignores the selected blocks that are protected. The system can use G6 and Q2 together to determine whether a block is actively erasing (that is, the Automatic Erase algorithm is in progress), Q6 toggling. When the device enters the Erase Suspend mode, Q6 stops toggling. However, the system must also use Q2 to determine which blocks are erasing or erase-suspended. Alternatively, the system can use Q7. P/N:PM0567 REV. 0.7, EFB. 12, 1989 35-19M=Ic If a program address falls within a protected block, Q6 toggles for approximately 1us after the program command sequence is written, then returns to reading ar- ray data. Q6 also toggles during the erase-suspend-program mode, and stops toggling once the Automatic Program algorithm is complete. Table 5 shows the outputs for Toggle Bit | on Q6. Q2: Toggle Bit Il The Toggle Bit Il on Q2, when used with Q6, indicates whether a particular block is actively erasing (that is the Automatic Erase algorithm is in process), or whether that biock is erase-suspended. Toggle Bit Il is valid after the rising edge of the final WE pulse in the command sequence. Q2 toggles when the system reads at addresses within those blocks that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But Q2 cannot distinguish whether the block is actively erasing or is erase-suspended. Q6, by comparison, indi- cates whether the device is actively erasing or is erase- suspended, but cannot distinguish which blocks are se- lected for erasure. Thus, both status bits are required for blocks and mode information. Refer to table 5 to compare outputs for Q2 and Q6. Reading Toggle Bits Q6/Q2 Whenever the system initially begins reading toggle bit status, it must read Q7~Q0 at least twice in a row to deter- mine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would com- pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on Q7~Q0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high (see the section on Q5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as Q5 went high. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset com- mand to return to reading array data. MX29VW160T/B The remaining scenario is that system initially determines that the toggle bit is toggling and Q5 has not gone high. The system may continue to monitor the toggle bit and Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Q5: Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these con- ditions Q5 will produce a "1" This is a time-out condition which indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during block erase opera- tion, it is specifiesd that a particular block is bad and it may not be reused. However, other blocks are still func- tional and may be used for program or erase operation. The device must be reset to use other blocks. Write the Reset command sequence to the device, and then ex- ecute program or erase command sequence. This allows the system to continue to use the other active blocks in the device. If this time-out condition occurs during the chip erase op- eration, it specifies that the entire chip is bad or combina- tion of blocks are bad. If this time-out condition occurs during the byte program- ming operation, it specifies that the entire block containing that byte is bad and this block may not be reused. (Other blocks are still functional and can be reused.) The Q5 time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Auto- matic algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the device has exceeded timing limits, the Q5 bit will indi- cate a logical "1" Please note that this is not a device failure condition since the device was incorrectly used. P/N:PMO0567 REV. 0.7, EFB. 12, 1999 35-20M=Iic MX29VW160T/B Q3: Block Erase Status Bit The MX29VW160T/B provides three difference erase op- eration :(1) chip erase. (2) single block erase,and (3) mutil- block erase. The device will automatically start erase op- eration after erase command completed when doing (1) and (2). For the case of (3), toggling the same address (A12 to A19 ) twice is necessary to terminate the block address loading and start the erase operation . No extra time-out is needed to terminate the block address loading or complete the erase operation . During the period of issuing the erase command,Q3 will remain low until the erase operation starts. Data polling and Toggle Bit are valid after the initial block erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the block address loading window is still open. If Q3 is high (logical "1" the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If Q3 is low (logical "0", the device will be accept additional block erase command. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent block erase command. If Q3 were high on the second status check, the command may not have been accepted.Note that dur- ing the block address loading period,any command other than Multiple Block Erase (30H) or Erase Suspend (BOH) will reset the device to read array mode. WP : Write Protect Pin When system provides VIL to the WP pin, the two outer most 8K-Byte blocks (SA01 and SA02 of MX29VW160T or SA38 and SA39 of MX29VW160B) will be protected from program and erase operations. When WP=VIH, the two outer most 8K-Byte blocks and all other blocks will remain at (or back to) their original protect status. When WP=VID, the whole device will be unprotected. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-21M=Ic MxX29VW160T/B Figure 4 Data Polling Aigorithm Read (Q0 to Q7) Q7 = Data ? No v No Read (Q0 to Q7) Q7 = Data ? I exceeded timing limits NOTE : Q7 is rechecked even if Q5 = "1" because Q7 may change simultaneously with Q5. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-22Mic Figure 5 Toggle Bit Algorithm MxX29VW160T/B START Y Read Q7-Q0 Y NO Read Q7-Q0 Q6 Toggle Bit = Toggle ? YES Y Read Q7-Q0 Twice Toggle bit = NO ~ Toggle? YES Y v Program/Erase operation Not Program/Erase Complete,Write Reset Command operation Complete Note:The system should recheck the toggle bit even if Q5="1" because the toggle bit may stop toggling as Q5 changes to "1".See the subsections on Q6 and Q2 for more information. P/N:PM0567 35-23 REV. 0.7, EFB. 12,1999Mic MxX29VW160T/B Figure 6 Automatic Erase Algorithm (Word Mode) Write erase Command Sequence (See below) ! Data polling Toggle Bit Successfully Command Erase Completed Chip Erase Command Sequence* Single Block Erase Command Sequence Multi Block Erase Command Sequence (Address/Command)}: (Address/Command): (Address/Commana): 555H/AAH 555H/AAH 555H/AAH { ! { 2AAH/55H 2AAH/55H 2AAH/55H { { t SS5H/80H 555H/80H 555H/80H t { ! 555H/AAH 585H/AAH 555H/AAH ! ! ! 2AAH/55H 2AAH/55H 2AAH/55H { { ! SSSH/10H Block Address/20H Block Address/30H + = Operation Start Erase Operation Start Erase Operation P/N:PMO0567 REV. 0.7, EFB. 12, 1999 35-24M=Ic MxX29VW160T/B Figure 7 Automatic Page Program Flow Chart (Word Mode) Write Data AAH Address 555H ' Write Data 55H Address 2AAH t Write Data AOH Address 555H 4 Write Program Data/Address Loading End? Reload the last address to teminate loading operation ! Check Device Status Q6 = Toggle ? No Q7 = Data ? Page Program Completed Operation Done,Device Stays at Read Array Mode Y Program Error Write Reset command P/N:PM0567 35-25 REV. 0.7, EFB. 12, 1999MX29VW160T/B Table 6 DC CHARACTERISTICS SYMBOL DESCRIPTIONS MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load Current 1 uA Vee = Vcc Max VIN = Vec or GND ILO Output Leakage Current 10 uA Vec = Vec Max VIN = Vcc or GND ISB1 Vcc Standby Current (CMOS) 1 10 uA Vee = Vcc Max CE =VIH ISB2 Vcc Standby Current (TTL) 5 mA Vec = Veco Max CE = ViIH ICC1 Vcc Read Current 20 27 mA Vec = Voc Max f = 8MHz, IOUT = OmA icc2 Vcc Erase/ Suspend Current 20 35 mA CE=VIH Block Erase Suspend ICC3 Vec Program Current 20 35 mA Program in Progress Icc4 Vec Erase Current 8 15 mA Erase in Progress ICC5 Vcc Read/Write Current (Note 1) 25 45 mA Read/Write in Progress ICC6 Vcc Read/Erase Current (Note 1) 25 45 mA Read/Erase in Progress VIL Input Low Voltage -0.5 0.8 Vv VIH Input High Voltage 0.7 x Voc Vec+0.3 V VOL Output Low Voltage 0.45 Vv lOL = 2.1mA Vec = Vcc Min VOH Output High Voltage Vec-0.4 Vv IOH = -100uA Vec = Vec Min 0.85Vcc Vv IOH =-2mA Vee = Vec Min VID Voltage for Read ID Mode 8.5 10 10.5 Vv Tabie 7 AC CHARACTERISTICS - READ OPERATIONS SYMBOL DESCRIPTIONS MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 120 ns CE=-OE=VIL tCE CE to Output Delay 120 ns OE=VIL tOE OE to Output Delay 55 ns CE=VIL tDF OE High to Output High Z (Note 1) 40 ns CE=VIL tOH Address to Output Hold 0 ns CE=OE=VIL Note 1: Not 100% Tested. P/N:PM0567 35-26 REV. 0.7, EFB. 12, 1999M=IcC MX29VW160T/B Figure 8 Key to Switching Waveforms WAVEFROM INPUT OUTPUT Must Be Steady Will Be Steady May Be Chang Will be Changing from H to L from H to L May change Will be Changing from L toH from L to H "H" or "L" Any '- Changing Change Permitted State Unknow Center Line is High- FREE Does Not Apply Impedance "Off" Stste Figure 9 Switching Test Circuits DEVICE UNDER 2.7K ohm TEST , Ky : +2.8V cL 6.2K ohm DIODES=!N3064 | OR EQUIVALENT CL=30pF Including jig capacitance Test Specifications Test Condition Unit Output Load 1TTL Output Load Capacitance,CL (in cluding jig capacitance) 30 pF Input rise & fall time 5 ns Input pulse Level 0~-2.5 Vv Input timing measurement reference levels 1.25 Vv Output timing measurement reference levels 1.25 Vv P/N:PMO567 REV. 0.7, EFB. 12, 1999 35-27M=I MxX29VW160T/B Figure 10 Switching Test Waveforms 2.5V i .25V TEST POINTS 125v-X- OV INPUT OUTPUT Figure 11 AC Waveform for Read Operations tRC | Address ) Address Stable y tACC CE ry tOE 10F OE K 7 tOEH tOH |_ WE tCE Output High 2 < Output Valid Hy High Z P/N:PM0567 REV.0.7, EFB. 12, 1999 35-28NM= Its MX29VW160T/B Figure 12 AC Waveform for Hardware Reset/Read Operations tRC Address xX Address Stable x tACC CE , tRP | tRH | tCE RP tOH High Z - Output g K& Output Valid Table 8 AC CHARACTERISTICS-WRITE/ERASE/PROGRAM OPERATION SYMBOL DESCRIPTIONS MIN. MAX. UNIT CONDITIONS iwc Write Cycle Time 120 ns tAS Address Setup Time 0 ns tAH Address Hold Time 65 ns tDS Data Setup Time 65 ns tDH Data Hold Time 0 ns tOES Output Enable Setup Time 0 ns tCES CE Setup Time ) ns tGHWL Read Recover Time Before Write 0 ns tcs CE Setup Time 0 ns tCH CE Hold Time 0 ns twP Write Pulse Width 65 ns tWPH Write Pulse Width High 35 ns tVCS CE setup Before VCC Ready 0 ns tRB RY/BY recovery time 0 ns tRP RP pulse width 50 ns tRH RP high time before read 50 ns tRC Read cycle time 120 ns P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-29M_ic MxX29VW160T/B Figure 13 Automatic Page Program Timing Waveform(Word Mode) Page Program Sequence (Last two cycle) 3rd cycle 4 PA Last PA Last PA Address 55SH (AO~A19) ><_(Ad~A5) (A0~AB) {we tAS at taH ez , SSSI WP wes) heh RyiByY 17 Hi , Program Operation Legend :PA : Program addr. PD : Program data Note: 1.A6~A19 for page addr. 2,It is necessary to write the last PA twice to terminate PD loading operation. Status:Q7: Data Polling,Q6: toggle bit |,Q5:exceeded timing limits,Q3: Block Erase Status bit ,Q2: toggle bit Ii. P/N:PMO567 REV. 0.7, EFB. 12, 1999 : 35-30M=Ic MxX29VW160T/B Figure 14 AC Waveform Chip/Block Erase Operations (Word Mode) Address WP] tWPH 7S ADS: DH Data Va AAH 55H (sor (aH) 3) Gort) WCS Vee Notes: 1. SA is the sector address for sector Erase Address = 555H(Word), AAAH(Byte) for Chip Erase. = A12~A19 for Block Erase. 2.These Waveform are for the word mode.(The address differ from byte mode.) 3.It is necessary to write the last SA twice to terminate SA loading operation for multi-block erase. P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-31MxX29VW160T/B Figure 15 AC Waveforms for Data Polling Automatic Algorithm Operations ce f 1CH __ 10E DF OE \ tOEH N WE / _ tCE or eR Q0 to Q6 tBUSY RY/BY *:Q7 = Valid Data (The device has completed the automatic operation). aX *Q7 = Valid Data Q0 to Q6 = Output Flas 'Q0 to Q6 Walid Data, / P/N:PMO0567 35-32 REV. 0.7, EFB. 12, 1999M=Ii MxX<29vw160T/B Figure 16 AC Waveform for Toggie Bit 1 during Automatic Algorithm Operation Address tAHT| tas tAHTEASO 1 CE x tCEPH Toggle Data WE # tOEPH tOEH tOEH RY/BY / *: Q6 stops toggling (The Device has completed the Automatic operation). SYMBOL DESCRIPTIONS MIN. MAX. UNIT tAHT Address hold time from CE or OE high during toggle bit polling 0 ns tASO Address setup time to OE tow during toggle bit polling 15 ns tCEPH Chip enable high during toggle bit polling tOEPH Output enable high during toggle bit polling 20 ns tOEH Output enable hold time 10 ns tELFL/ELFH GE to BYTE switching low or high 5 ns tFHQV BYTE switching high to output active . 120 ns tFLQZ BYTE switching low to output High-Z 30 ns P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-33M=Ic Mx29VWw160T/B Figure 17 RY/BY Timing Diagram during Program/Erase Operation The rising edge of the last write pulse we \_f \_ So \_f- Entire programming or erase operations RY/BY. {BUSY Figure 18 RP/RY/BY Timing Diagram = mi __} tRP AP \ RY/BY ~(\ tREADY Figure 19 Timing Diagram for Word Mode Configuration ce \ | fo BYTE ff / Data Output Data Outpu Q0 to Q14 Ea on MXXXXX ato Oy tELFH tFHQV Q15/A-1 XXX At X Qi5 - P/N:PMO567 REV. 0.7, EFB. 12, 1999 35-34MxX29VW160T/B Figure 20 Timing Diagram for Byte Mode Configuration CE [. BYTE N tELFL Data Output Data Output Q0 to Q14 - (Q0 to Q14) XK (Q0 to Q7) )>_ orsiat _+ (ais KK mm XXXXXX tFLQZ Figure 21 AC Waveform for Group Protection (Word Mode) Group Protuct Command Sequence (Last two cycles) | 5th cycle | I Address ~< 2AAH 6th cycle | I >< wrtthiy OS cE / \ /\ [\_ fo Data < 55H > 20H C status > GE \_/ RY/BY GA : Group Address P/N:PMO0567 REV. 0.7, EFB. 12, 1999 35-35MxX29VW160T/B Figure 22 AC Waveform For Group Unprotection (Word Mode) Group Un-Protuct Command Sequence (Last two cycles) | 5th cycle | | 6th cycle | I 2AAH >< 555H >< Address =< @ /\___/\ ___/\ WE \/ \Y/ Css > aw, RY/BY \_ P/N:PM0567 REV.0.7, EFB. 12, 1999 35-36Ye | MxX29VW160T/B Figure 23 ID Code Read Timing Waveform Vcc BV VID AQ VIH VIL VK 00 MOO XXXX tAGG tACC VIH Al _ \ Vit oes wu KOA A10-A16 svi cE VIH \ fo VIL (CE WE VIH VIL tOE . -VIH | |/>___ OF iw \ y {DF 10H {OH VIH r aoais VIL _ DATA OUT KXXXXKX DATA OUT } C2H/00C2H 67H/68H(Byte) 0067H/0068H(Word) P/N:PM0567 REV. 0.7, EFB, 12, 1999 35-37Mic i MxX29VW160T/B Figure 24 Back to Back Read/Write Timing Diagram Read Command Read Command Read Read | tRAC tWC tRC \ twe , tRC \ tRC / BA2 BA2 BA2 Address X BAI x Gay 2S X (PA) X BAI X (PA) tAH tacc fas c tAHT | tAS - VSN P\ /\_/\ tOE tCEPH OE DF tGHW twP {OEH | We Vf ff 1DF t0S_|tDH Valid Valid Outpu (Oat) Maat Kate (at) NOTE : This is example of read for Bank 1 and Embedded Alogorithm (Program) for Bank 2. BA1 :Address of Bank 1. BA2 : Address of Bank 2. PIN-P 7 REV. 0.7, EFB. 12, 1999 IN:PMOSE 35-38MES: i i @ &}3}3mx29vw160T/B Figure 25 Q2 Vs Q6 Enter Enter Embedded Erase Suspend Erase Erasing Suspend Program Resume WE | | | | | Erase Erase Suspend | | Erase Erase | Erase Erase Read Suspend Suspend Complete Program Read LP Ur Lut e UAL Toggle Q2 and Q6 with OE or CE NOTE : Q2 toggles onty when read at an address within an erasing or erase-suspended block. . REV. 0.7, EFB. 12, 1999 P/N:PM0567 35-39M=_i MxX29VW160T/B Table 9 ERASE AND PROGRAMMING PERFORMANCE (1) (2) LIMITS PARAMETER MIN. TYP.(3) MAX. UNITS Single/Block Erase Time 20 160 ms Multi Block Erase Time 50 400 ms Chip Erase Time 50 400 ms Page Programming Time 4 120 ms Chip Programming Time 64 192 sec. Byte Programming Time (Avg.) 32 960 us Erase/Program Cycles 100,000 Cycle Note: 1.Sampled, not 100% tested. 2.Excludes external system level over head 3.Typical values measured at 25 C, nominal voltage. Table 10 LATCHUP CHARACTERISTICS MIN. MAX. UNITS Input Voltage with respect to GND on ail pins except I/O pins -1.0 10.5 Vv Input Voltage with respect to GND on I/O pins -1.0 Vec+1.0 V Current -100 +100 mA Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. Table 11 ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature -40C to 85C Storage Temperature 65C to 125C Applied Input Voltage -0.5V to Vec + 4.5 Applied Output Voltage -0.5V to Voc +0.6 Vec to Ground Potential -0.5V to 4.5V AQ, RP,WP -0.5V to 12.5V Table 12 OPERATING RANGES RATING VALUE Ambient Temperature 0C to 70C (Comm.) -40C to 85C (Ind.) Vcc Supply Voltage 2.25V to 3.0V P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-40=IG MxX29VW160T/B Ordering Information Part No. Access Temperature Package Time(ns) Range Type Ball Type Ball Pitch MX29VW160TTC-12 120 Comm. 48 Pin TSOP MX29VW160TTI-12 120 Ind. 48 Pin TSOP MXxX29VW160TXBC-12 120 Comm. 48 Ball CSP BGA 0.80mm MX2SVW160TXBI-12 120 Ind. 48 Ball CSP BGA 0.80mm Note: 1. Top Boot Block as an sample.For Bottom Boot Block ones, MX29VW160TXXxX will be changed to MX29VW1 6OBXXxX) PIN: 7 REV. 0.7, EFB. 12, 1999 /N:PMOS6 35-41a= MX29VW160T/B REVISION HISTORY Revision Description Page Date 0.3 CSP package size:7mmx12mm ---> 8mmx13mmx1.2mm P3 NOV/04/1998 Add in ICC6:Vcc Read/Erase Current P25 Remove tBACC & tBHZ P25 Remove LGA Package P41 0.4 Change Sector structure of the 2Mb-Bank from 16KBx4+ P1,4,5,8 NOVA 9/1998 8KBx8+32KBx4 to 8KBx8+64KBx1 Add in WP pin P1, 3, 5, 6, 14, 20 Change VIP range from 9.5V~10.5V to 8.5V~10.5V P6, 14, 15, 25 0.5 Vcc range change to 2.25V~3.0V Pt, 2,3, 40 NOV/27/1998 0.6 Change Group Addr.: A12~A19 P8, 15,17,18,35 DEC/03/1998 Correct ID data P11 0.7 Block architecture description correction P2 FEB/12/1999 0.8 Modify typing P4,5,9,11,13,16 MAY/17/1999 Modify AC Characteristic description P28,29,32,33,37 Modify Erase/Program Performance P40 Modify Absolute Maximun Rating P40 Remove MX29VW160TXAC-12/TXAI-12 P41 P/N:PM0567 REV. 0.7, EFB. 12, 1999 35-42