Product Specification PE43501 50 RF Digital Attenuator 5-bit, 7.75 dB, 9 kHz - 6.0 GHz Features * HaRPTM-enhanced UltraCMOSTM device * Attenuation: 0.25 dB steps to 7.75 dB * High Linearity: Typical +58 dBm IP3 * Excellent low-frequency performance * 3.3 V or 5.0 V Power Supply Voltage * Fast switch settling time si The PE43501 is a HaRPTM-enhanced, high linearity, 5-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 7.75 dB attenuation range in 0.25 dB steps. The Peregrine 50 RF DSA provides a serial-addressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with VDD due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. gn Product Description * Programming Modes: The PE43501 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Direct Parallel Latched Parallel Serial-Addressable: Program up to eight addresses 000 - 111 de * * * ew * High-attenuation state @ power-up (PUP) Figure 1. Package Type * No DC blocking capacitors required * Packaged in a 32-lead 5x5x0.85 mm QFN fo rn 32-lead 5x5x0.85 mm QFN Package * CMOS Compatible Figure 2. Functional Schematic Diagram ot Switched Attenuator Array RF Output N RF Input Parallel Control 5 Serial In Control Logic Interface CLK LE A0 A1 Document No. 70-0251-05 www.psemi.com A2 P/S (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 PE43501 Product Specification Table 1. Electrical Specifications @ +25C, VDD = 3.3 V or 5.0 V Parameter Test Conditions Frequency Range Attenuation Range Insertion Loss Frequency Min Typical Max 9 kHz 0.25 dB Step 0 - 7.75 2.3 Return Loss Relative Phase P1dB (note 1) IIP3 Typical Spurious Value Video Feed Through Switching Time RF Trise/Tfall All States Input Two tones at +18 dBm, 20 MHz spacing 9 kHz - 6 GHz 9 kHz - 6 GHz 20 MHz - 6 GHz 20 MHz - 6 GHz 1 MHz 30 (0.15+4%) +0.2+4% +0.3+4% -0.2 - 4% dB dB dB dB 18 9 32 58 -110 10 650 400 dB deg dBm dBm dBm mVpp ns ns 4 s de 50% CTRL to 10% / 90% RF 10% / 90% RF RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. Settling Time dB dB si Attenuation Error 9 kHz < 4 GHz 4 GHz 6 GHz 4 GHz 6 GHz 4 GHz 6 GHz 2.8 gn 9 kHz 6 GHz 0 dB - 7.75 dB Attenuation settings 0dB to 3.5 dB Attenuation Settings 3.75 dB to 7.75 dB Attenuation Settings 0dB to 7.75dB Attenuation Settings Units 6 GHz Note: 1. Please note Maximum Operating Pin (50) of +23dBm as shown in Table 3. Performance Plots 200 MHz 3000 MHz 900 MHz 4000 MHz Figure 4. 0.25dB Attenuation vs. Attenuation State Attenuation ew Figure 3. 0.25 dB Step Error vs. Frequency* 1800 MHz 5000 MHz 2200 MHz 6000 MHz 1.00 8 900 MHz 1800 MHz 2200 MHz 3000 MHz 5400 MHz 5800 MHz 7 0.50 0.25 -0.25 0 1 2 3 fo 0.00 4 5 6 Attenuation dB rn Step Error (dB) 0.75 5 4 3 2 1 0 6 7 8 0 Attenuation Setting (dB) 1 2 ot 0.5dB State 1dB State 2dB State 4dB State 7.75dB State N 0.25dB State 6 7 8 200 MHz 3000 MHz 900 MHz 4000 MHz 1800 MHz 5000 MHz 2200 MHZ 6000 MHz 1.5 1.0 Attenuation Error (dB) Bit Error (dB) 5 Figure 6. 0.25 dB Attenuation Error vs. Frequency Figure 5. 0.25 dB Major State Bit Error 1.0 4 Attenuation State *Monotonicity is held so long as Step-Error does not cross below -0.25 1.5 3 0.5 0.0 -0.5 -1.0 0.5 0.0 -0.5 -1.0 -1.5 -1.5 0 1000 2000 3000 4000 5000 Frequency (MHz) (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 13 6000 0 1 2 3 4 5 6 7 Attenuation Setting (dB) Document No. 70-0251-05 UltraCMOSTM RFIC Solutions 8 PE43501 Product Specification Figure 7. Insertion Loss vs. Temperature -40C +25C Figure 8. Input Return Loss vs. Attenuation: T = +25C -0.5 -5 -1 -10 -1.5 -15 -2 -2.5 -3 -3.5 -25 -30 -35 -40 -4.5 -45 3 4 5 Frequency (GHz) 6 7 8 0dB 2dB 1 2 3 4 0.5dB 7.75dB -40C -60 1 2 3 4 5 6 fo 0 7 8 Return Loss (dB) rn -40 -50 25C 9 85C -20 -30 -40 -50 -60 9 0 1 2 3 4 Frequency (GHz) ot -40C 25C 6 7 8 9 Figure 12. Relative Phase vs. Frequency 0dB 2dB 85C 16 0.25dB 4dB 0.5dB 7.75dB 1dB 14 Relative Phase Error (Deg) N 0 5 Frequency (GHz) Figure 11. Output Return Loss vs. Temperature: 7.75 dB State Return Loss (dB) 8 -10 -30 -30 7 0 -20 -20 6 Figure 10. Input Return Loss vs. Temperature: 7.75 dB State 1dB -10 -10 5 ew 0.25dB 4dB 1dB Frequency (GHz) Figure 9. Output Return Loss vs. Attenuation: T = +25C 0 0 9 de 2 si -50 1 0.5dB 7.75dB -20 -4 0 0.25dB 4dB gn Return Loss (dB) Insertion Loss (dBm) 0 -5 Return Loss (dB) 0dB 2dB +85C 0 -40 -50 -60 12 10 8 6 4 2 0 -70 0 1 2 3 4 5 Frequency (GHz) Document No. 70-0251-05 www.psemi.com 6 7 8 9 0 1 2 3 4 5 6 7 Frequency (GHz) (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 13 8 PE43501 Product Specification Figure 13. Relative Phase vs. Temperature: 7.75 dB State 900 MHz 1800 MHz Figure 14. Attenuation Error vs. Attenuation Setting: 900 MHz 3000 MHz +25 C 4.5 -40C +85C 1.5 4.0 1.0 Phase (Deg) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 gn Attenuation Error (dB) 3.5 -0.5 -1.0 0.5 -40 -20 0 20 40 60 0 80 si -1.5 0.0 1 2 -40C 5 6 7 +25C -40C +85C ew 1.5 1.0 rn 0.0 -0.5 -1.5 0 1 2 3 fo -1.0 4 5 6 7 8 ot Attenuation Setting (dB) Attenuation Error (dB) 1.0 0.5 0.5 0.0 -0.5 -1.0 -1.5 0 1 2 3 4 5 6 7 Attenuation Setting (dB) Figure 17. Input IP3 vs. Frequency 0dB 0.25dB 0.5dB 1dB 2dB 4dB N 70 65 60 Input IP3 (dBm) 8 de +85C 1.5 Attenuation Error (dB) 4 Figure 16. Attenuation Error vs. Attenuation Setting: 3000 MHz Figure 15. Attenuation Error vs. Attenuation Setting: 1800 MHz +25C 3 Attenuation Setting (dB) Temperature (Deg. C) 55 50 45 40 35 30 0 1000 2000 3000 4000 5000 6000 7000 Frequency (MHz) (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 13 Document No. 70-0251-05 UltraCMOSTM RFIC Solutions 8 PE43501 Product Specification C0.5 C1 C2 C4 GND GND SI 32 31 30 29 28 27 26 25 1 24 CLK 2 23 LE P/S 3 22 A1 A0 4 21 A2 GND 5 20 GND GND 6 19 GND RF1 7 18 RF2 GND 8 17 GND 10 11 12 13 14 15 16 GND GND GND GND GND GND GND Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE43501 in the 32-lead 5x5 QFN package is MSL1. de 9 GND Exposed Solder pad When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. si NC VDD Electrostatic Discharge (ESD) Precautions gn C0.25 Figure 18. Pin Configuration (Top View) Switching Frequency The PE43501 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Table 2. Pin Descriptions Pin No. Pin Name Description 1 N/C No Connect 2 VDD Power supply pin 3 P/S Serial/Parallel mode select Address bit A0 connection A0 GND Ground 7 RF1 RF1 port 18 RF2 21 A2 22 A1 23 LE Serial interface Latch Enable input Address bit A2 connection Address bit A1 connection CLK Serial interface Clock input SI Serial interface Data input N 25 RF2 port ot 24 The exposed solder pad on the bottom of the package must be grounded for proper device operation. rn 4 5, 6, 8-17, 19, 20, 26, 27 fo ew Exposed Solder Pad Connection 28 C4 (D4) Parallel control bit, 4 dB 29 C2 (D3) Parallel control bit, 2 dB 30 C1 (D2) Parallel control bit, 1 dB 31 C0.5 (D1) Parallel control bit, 0.5 dB 32 C0.25 (D0) Parallel control bit, 0.25 dB Paddle GND Ground for proper operation Note: Ground C0.25, C0.5, C1 C2, C4, if not in use. Document No. 70-0251-05 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 13 PE43501 Product Specification Table 3. Operating Ranges VDD Power Supply Voltage Min Typ 3.0 3.3 Max Units Symbol V VDD VDD Power Supply Voltage 5.0 5.5 V IDD Power Supply Current 70 350 A Digital Input High 2.6 PIN Input power (50): 9 kHz 20 MHz 20 MHz 6 GHz TOP Operating temperature range -40 25 5.5 V See fig. 19 +23 dBm dBm 85 C 1 V 15 A Parameter/Conditions Min Max Units Power supply voltage -0.3 6.0 V VI Voltage on any Digital input -0.3 5.8 V PIN Input power (50) 9 kHz 20 MHz 20 MHz 6 GHz See fig. 19 +23 dBm dBm TST Storage temperature range VESD ESD voltage (HBM)1 ESD voltage (Machine Model) gn Parameter Table 4. Absolute Maximum Ratings -65 150 C 500 100 V V Digital Input Leakage1 Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. de 0 si Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Digital Input Low Note 1. Input leakage current per Control pin ew Figure 19. Maximum Power Handling Capability: Z0 = 50 30 rn 25 15 fo Pin dBm 20 10 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 Hz N 0 1.0E+03 ot 5 (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 13 Document No. 70-0251-05 UltraCMOSTM RFIC Solutions PE43501 Product Specification Table 5. Control Voltage State Table 8. Address Word Truth Table Bias Condition Address Word A0 Address Setting L L 000 L H 001 H L 010 L H H 011 H L L 100 Low 0 to +1.0 Vdc at 2 A (typ) A7 (MSB) High +2.6 to +5 Vdc at 10 A (typ) X X X X X L X X X X X L X X X X X L X X X X X X X X X X X X X X X X X X X X X X Shift Clock Function X Shift Register Clocked X Contents of shift register transferred to attenuator core A4 A3 A2 A1 X H L H 101 X X H H H H L H 110 111 si Latch Enable A5 gn Table 6. Latch and Clock Specifications A6 Table 7. Parallel Truth Table Table 9. Serial Attenuation Word Truth Table Attenuation Word D1 D0 (LSB) Attenuation Setting RF1-RF2 L L L Reference I.L. D4 D3 D2 D1 D0 Attenuation Setting RF1-RF2 L L L L L Reference I.L. L L L L H 0.25 dB de Parallel Control Setting L L L L L L L H 0.25 dB L L L H L 0.5 dB L L L L L L H L 0.5 dB L L H L L 1 dB L L L L L H L L 1 dB L H L L L 2 dB L L L L H L L L 2 dB H L L L L 4 dB L L L H L L L L 4 dB H H H H H 7.75 dB L L L H H H H H 7.75 dB D6 D5 D4 D3 D2 L L L L L fo rn ew D7 Table 10. Serial-Addressable Register Map Q14 A7 A6 LSB (first in) D5, D6 and D7 must be set to logic low Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 N Q15 ot Bits can either be set to logic high or logic low MSB (last in) Address Word Attenuation Word Attenuation Word is derived directly from the attenuation value. For example, to program the 3.75 dB state at address 3: Address Word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary 4 * 3.75 dB 15 00001111 Serial Input: XXXXX01100001111 Document No. 70-0251-05 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 13 PE43501 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial-addressable interface can be used to control the PE43501. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serialaddressable interface. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the serial-addressable register is illustrated in Table 10. The serial-addressable timing diagram is illustrated in Fig. 20. The PE43501 will always initialize to the maximum attenuation setting (7.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In directparallel mode, the DSA can be preset to any state within the 7.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-s delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (7.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). ew For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 21) to latch new attenuation state into device. Power-up Control Settings de The parallel interface timing requirements are defined by Fig. 21 (Parallel Interface Timing Diagram), Table 12 (Parallel Interface AC Characteristics), and switching speed (Table 1). si gn Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 7. shift register. Serial data is clocked in LSB first, beginning with the Attenuation Word. rn For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). N ot fo Serial-Addressable Interface The serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 20 illustrates an example timing diagram for programming a state. It is required that all parallel control inputs be grounded when the DSA is used in serialaddressable mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 13 Dynamic operation between serial-addressable and parallel programming modes is possible. If the DSA powers up in serial-addressable mode (P/ S = HIGH), all the parallel control inputs DI[4:0] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or directparallel mode, all parallel pins DI[4:0] must be set to logic low prior to toggling to serial-addressable mode (P/S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on powerup. Once completed, the DSA may be toggled between serial-addressable and parallel programming modes at will. Document No. 70-0251-05 UltraCMOSTM RFIC Solutions PE43501 Product Specification Figure 20. Serial-Addressable Timing Diagram Bits can either be set to logic high or logic low D[5], D[6] and D[7] must be set to logic low DI[4:0] TDISU ADD[2:0] TDIH VALID TASU TAIH P/S TPSSU TPSIH TSISU D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] gn D[0] SI TSIH CLK TCLKL TCLKH TLESU LE TLEPW de Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram P/S TPSSU DI[4:0] TPSH VALID TDISU ew TDIH LE TLEPW DO[4:0] VALID TPD rn TDIPD TPD VALID si DO[6:0] Table 12. Parallel and Direct Interface AC Characteristics VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified VDD = 3.3 or 5.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol fo Table 11. Serial-Addressable Interface AC Characteristics Parameter Min Max Unit FCLK Serial clock frequency - 10 MHz TCLKH Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 TLEPW Latch Enable min. pulse width TSISU Symbol Parameter Min Max Unit Latch Enable minimum pulse width 30 - ns ns TDISU Parallel data setup time 100 - ns - ns TDIH Parallel data hold time 100 - ns 100 - ns - ns TPSSU Parallel/Serial setup time 30 Serial data setup time 10 - ns TPSIH Parallel/Serial hold time 100 - ns TSIH Serial data hold time 10 - ns TPD - 10 ns TDISU Parallel data setup time 100 - ns Digital register delay (internal) TDIH Parallel data hold time 100 - ns Digital register delay (internal, direct mode only) - 5 ns TASU Address setup time 100 - ns TAH ns N ot TLEPW Address hold time 100 - TPSSU Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Document No. 70-0251-05 www.psemi.com TDIPD (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 PE43501 Product Specification Figure 22. Evaluation Board Layout gn Note: Reference Fig. 23 for Evaluation Board Schematic the LE pin on the Serial header must be logic low as the parallel bits are applied. The user must then pulse LE from 0V to VDD and back to 0V to latch the programming word into the DSA. LE must be logic low prior to programming the next word. ew Direct-Parallel Programming Procedure For automated direct-parallel programming, connect the test harness provided with the EVK from the parallel port of the PC to the J1 & Serial header pin and set the D0-D4 SP3T switches to the `MIDDLE' toggle position. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Direct-Parallel mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Peregrine Specification 101-0312 si The Digital Attenuator Evaluation Kit board was designed to ease customer evaluation of the PE43501 Digital Step Attenuator. de Evaluation Kit ot fo rn For manual direct-parallel programming, disconnect the test harness provided with the EVK from the J1 and Serial header pins. Position the Parallel/Serial (P/S) select switch to the Parallel (or left) position. The LE pin on the Serial header must be tied to logic high. Switches D0-D4 are SP3T switches which enable the user to manually program the parallel bits. When any input D0-D4 is toggled `UP', logic high is presented to the parallel input. When toggled `DOWN', logic low is presented to the parallel input. Setting D0-D4 to the `MIDDLE' toggle position presents an OPEN, which forces an on-chip logic low. Table 7 depicts the parallel programming truth table and Fig. 21 illustrates the parallel programming timing diagram. N Latched-Parallel Programming Procedure For automated latched-parallel programming, the procedure is identical to the direct-parallel method. The user only must ensure that LatchedParallel is selected in the software. Serial-Addressable Programming Procedure Position the Parallel/Serial (P/S) select switch to the Serial (or right) position. Prior to programming, the user must define an address setting using the ADD header pin. Jump the middle pins on the ADD header A0-A2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. If the ADD pins are left open, then 000 become the default address. The evaluation software is written to operate the DSA in either Parallel or Serial-Addressable Mode. Ensure that the software is set to program in Serial-Addressable mode. Using the software, enable or disable each setting to the desired attenuation state. The software automatically programs the DSA each time an attenuation state is enabled or disabled. For manual latched-parallel programming, the procedure is identical to direct-parallel except now (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 13 Document No. 70-0251-05 UltraCMOSTM RFIC Solutions PE43501 Product Specification Figure 23. Evaluation Board Schematic Peregrine Specification 102-0381 4 2 1 4 2 2 4 6 8 10 12 14 1 3 5 7 9 11 13 3 D6 D0 1 3 5 7 9 11 13 D1 D2 D3 D4 D5 D6 SERIAL HEADER 4 CLK 1 2 3 4 SI LE CLOCK SI LE GND VDD 2 VDD P/S 3 PS 4 A0 5 GND 6 7 8 GND SMA 1 25 D5 D6 26 C16 D4 27 28 C4 C8 D3 D2 30 29 C2 C1 SI A1 A2 20 GND GND 19 RF1 RF2 18 GND 17 J2 VSS R1 0 OHM R2 J5 Z=50 Ohm C11 0.1uF C12 1 2 CON2 100pf 0 OHM SMA 1 ew 2 2 22 21 9 1 2 J7 Z=50 Ohm SMA 23 GND De-embeding trace J6 A2_1 A1_1 A0_1 16 1 LE A1 A2 GND Z=50 Ohm SMA 24 VSS 15 J4 U1 A0 VDD A1 VDD A2 VDD HEADER3X3 CLK PE43XOX DSA 50 OHM 5X5 MLPQ32 GND A0 GND C14 100pF 14 C13 100pF 13 C8 100pF GND 100pF GND 0.1F C10 A0_2 A1_2 A2_2 de VDD _ C9 12 1 2 GND 11 1 31 100pF CP5 100pF GND 100pF VDD J3 CON2 10 C0 D1 D0 C2 32 C4 CP25 100pF ADD 100pF 100pF 100pF C6 C1 si C3 GND C5 gn 3 D5 J1 HEADER 14 2 4 6 8 10 12 14 2 1 4 3 D4 3 D2 D6 3 3 2 1 4 2 1 4 2 1 4 2 1 4 D1 D5 D4 D3 D2 3 5 P/S _ D1 D0 D0 P/S D3 _ 2 1 6 4 VDD Note: Capacitors C1-C8, C13, & C14 may be omitted. Pin 26 & 27 are ground. On the PE43501 pin 20 (shown as VSS) must also be grounded. N ot fo rn Figure 24. Package Drawing QFN 5x5 mm MAX A 0.900 NOM 0.850 MIN 0.800 Document No. 70-0251-05 www.psemi.com (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 13 PE43501 Product Specification de si gn Figure 24. Tape and Reel Drawing rn ew Tape Feed Direction Pin 1 Top of Device Device Orientation in Tape fo Figure 25. Marking Specifications ot 43501 YYWW ZZZZZ N YYWW = Date Code ZZZZZ = Last five digits of Lot Number Table 13. Ordering Information Order Code Part Marking Description Package Shipping Method 43501 PE43501 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel PE43501MLI-Z 43501 PE43501 G - 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R EK43501-01 43501 PE43501 - 32QFN 5x5mm-EK Evaluation Kit 1 / Box PE43501MLI (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 13 Document No. 70-0251-05 UltraCMOSTM RFIC Solutions PE43501 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 gn Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Europe Peregrine Semiconductor Europe si Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Peregrine Semiconductor K.K., Japan de Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 High-Reliability and Defense Products ew Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 rn Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Advance Information fo Data Sheet Identification ot The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. N Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Document No. 70-0251-05 www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 13