Winbond Clock Generator W83195BR-118/W83195BG-118 For Intel 915/945 Chipsets Date: May/02/2006 Revision: 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS W83195BR-118 Datasheet Revision History PAGES DATES VERSION WEB VERSION n.a. 07/22/2004 0.5 n.a. All of the versions before 0.50 are for internal use. 8,13 11/24/2004 0.6 n.a. Correction IC version, add register default value and correction some description and default value 3 11,13 01/05/2005 0.7 n.a Add spread spectrum function control bit, and correction some description and default value 4 19 01/17/2005 0.71 n.a Add Pb-free part number 5 1-4,1012,14-16 3/25/2005 0.8 n.a Refine the description and register value 6 All 05/02/2006 0.81 n.a. Change the part no from W83195BR119 to W83195BR-118 1 2 MAIN CONTENTS 7 8 9 -I- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Tables of Contents1. GENERAL DESCRIPTION......................................................................................................... 1 2. PRODUCT FEATURES.............................................................................................................. 1 3. PIN CONFIGURATION .............................................................................................................. 2 4. BLOCK DIAGRAM...................................................................................................................... 3 5. PIN DESCRIPTION .................................................................................................................... 3 5.1 Crystal I/O .....................................................................................................................................4 5.2 CPU and PCIE, PCI, Clock Outputs ............................................................................................4 5.3 Fixed Frequency Outputs .............................................................................................................4 5.4 I2C Control Interface .....................................................................................................................5 5.5 Power Management Pins .............................................................................................................5 5.6 Power Pins....................................................................................................................................6 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE................................................ 7 7. I2C CONTROL AND STATUS REGISTERS .............................................................................. 8 7.1 Register 0: Frequency Select Register (Default = 10h)...............................................................8 7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h) .................................8 7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ...................................9 7.4 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ...................................9 7.5 Register 4: 24_48MHz, 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh) 9 7.6 Register 5: Watchdog Control (Default: 02h).............................................................................10 7.7 Register 6: SRC, PCIE Control (1 = Enable, 0 = Stopped) (Default: FEh)...............................10 7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only) .........................................................11 7.9 Register 8: M/N Program (Default: 90h) ....................................................................................11 7.10 Register 9: M/N Program Register (Default: BBh).....................................................................11 7.11 Register 10: Reserved (Default: 3Bh) ........................................................................................12 7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)....................................................12 7.13 Register 12: Divisor Control (Default: 08h) ................................................................................12 7.14 Register 13: Step-less Enable Control (Default: 0Ah) ...............................................................13 7.15 Register 14: Control (Default: 10h) ............................................................................................14 7.16 Register 15: SST Control (Default: ECh) ...................................................................................14 7.17 Register 16: Skew Control (Default: E4h)..................................................................................15 7.18 Register 17: Slew rate Control (Default: 00h) ............................................................................15 7.19 Register 18: Reserved (Default: 00h) ........................................................................................15 7.20 Register 19: Skew Control (Default: DAh) .................................................................................15 7.21 Register 20: Watch dog timer (Default: 88h) .............................................................................16 - II - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.22 Register 21: Asynchronous Control (Default: 4Bh) ...................................................................16 8. ACCESS INTERFACE ............................................................................................................. 17 8.1 Block Write protocol....................................................................................................................17 8.2 Block Read protocol....................................................................................................................17 8.3 Byte Write protocol......................................................................................................................17 8.4 Byte Read protocol .....................................................................................................................17 9. SPECIFICATIONS.................................................................................................................... 18 9.1 ABSOLUTE MAXIMUM RATINGS............................................................................................18 9.2 General Operating Characteristics.............................................................................................18 9.3 Skew Group timing clock............................................................................................................19 9.4 CPU 0.7V Electrical Characteristics...........................................................................................19 9.5 SRC 0.7V Electrical Characteristics...........................................................................................19 9.6 PCIE 0.7V Electrical Characteristics..........................................................................................20 9.7 PCI Electrical Characteristics .....................................................................................................20 9.8 24M, 48M Electrical Characteristics...........................................................................................20 9.9 REF Electrical Characteristics....................................................................................................21 9.10 DOT 0.7V Electrical Characteristics...........................................................................................21 10. ORDERING INFORMATION .................................................................................................... 22 11. HOW TO READ THE TOP MARKING ..................................................................................... 22 12. PACKAGE DRAWING AND DIMENSIONS ............................................................................. 23 - III - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 1. GENERAL DESCRIPTION The W83195BR-118 is a Clock Synthesizer for Intel P4 processors and Intel Grandsdale chipsets. W83195BR-118 provides all clocks required for high-speed microprocessor and provides step-less frequency programming, 32 different frequencies of CPU, PCI, PCI-Express clocks setting. Simultaneously W83195BR-118 supports SRC 100MHz for SATA and DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195BR-118 programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% down type spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195BR-118 also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83195BR-118 is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply. 2. PRODUCT FEATURES * * * * * * * * * * * * * * * * 2 pair 0.7 V current mode Differential clock outputs for CPU 1 pair 0.7V current mode Differential 100 MHz clock outputs for SRC. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 5 pair 0.7V current mode Differential clock outputs for PCI-Express 6 PCI clock outputs for PCI 3 PCI clock free running outputs for PCI 1 24_48Mhz clock output for super I/O. 1 48 MHz clock output for USB. 2 14.318MHz REF clock outputs. Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% down type spread spectrum in H/W and software select mode Programmable spread spectrum scale to reduce EMI in M/N mode Programmable registers to enable/stop each output. Programmable clock outputs to control slew rate and skew. Watch Dog Timer and RESET# output pins * 56 pin SSOP package -1- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 3. PIN CONFIGURATION 56 VDDP 55 PCI2 54 PCI1 53 PCI0 52 RESET# 51 REF0/& FS2 50 REF1 49 GND 48 XIN 47 XOUT 46 VDDR 45 *SCLK 44 *SDATA 43 CPUT0 42 CPUC0 41 VDDC 40 CPUT1 39 CPUC1 38 GND 37 IREF 36 GNDA 35 VDDA 34 VDDPE 33 PCIET4 32 PCIEC4 31 PCIET3 30 PCIEC3 29 GND GND 1 PCI3 2 PCI4 3 PCI5 4 GND 5 VDDP 6 PCI_F0 7 & FS0/PCI_F1 8 * FS1/PCI_F2 9 VDD48 10 & SEL24_48#/24_48MHz 11 48MHz 12 GND 13 DOTT 14 DOTC 15 VTT_PWRGD#/PD 16 PCIET0 17 PCIEC0 18 VDDPE 19 GND 20 PCIET1 21 PCIEC1 22 PCIET2 23 PCIEC2 24 GND 25 SRCT 26 SRCC 27 VDDS 28 #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND -2- W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 4. BLOCK DIAGRAM 48M H z PLL2 24_48M H z D iv id e r DO TT DOTC X IN XOUT 2 XTAL OSC 2 PLL1 S p re a d S p e c tru m 2 VCO C LK SRCT SRCC 5 M /N /R a t io ROM D iv id e r 5 3 F S (0 :2 ) VTT_PW R G D # &SEL24_48# L a tc h &POR C o n tr o l L o g ic & C o n f ig R e g is t e r *S D A T A *S C L K I2 C In te r f a c e 6 P C IE T 0 : 4 P C IE C 0 : 4 P C I_ F 0 :2 P C I 0 :5 RESET# IREF PD R E F 0 :1 C P U T 0 :1 C P U C 0 :1 475 5. PIN DESCRIPTION BUFFER TYPE SYMBOL IN DESCRIPTION Input INtp120k Latched input at power up, internal 120k pull up. INtd120k Latched input at power up, internal 120k pull down. OUT Output OD Open Drain I/OD Bi-directional Pin, Open Drain. # Active Low * Internal 120k pull-up & Internal 120 k pull-down -3- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 5.1 Crystal I/O PIN 5.2 PIN NAME 48 XIN 47 XOUT IN OUT DESCRIPTION Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF). CPU and PCIE, PCI, Clock Outputs PIN PIN NAME 43,42,40,39 CPUT [0:1] CPUC [0:1] 17,18,21,22 PCIET [0:4] ,23,24,31,3 PCIEC [0:4] 0,33,32 7 PCI_F0 8 PCI_F1 & FS0 9 PCI_F2 * FS1 53,54,55,2, PCI [0:5] 3,4 5.3 TYPE TYPE OUT OUT DESCRIPTION Low skew (< 125ps) 0.7V Current mode differential clock outputs for host frequencies of CPU Low skew (<125ps) 0.7V Current mode differential clock outputs for PCI-Express OUT 3.3V free running PCI clock output. OUT 3.3V free running PCI clock output. INtd120k Latched input for FS0 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. OUT 3.3V free running PCI clock output. INtp120k Latched input for FS1 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. OUT Low skew (< 500ps) 3.3V PCI clock outputs Fixed Frequency Outputs PIN 51 50 11 PIN NAME REF0 & FS2 REF1 24_48MHz & SEL24_48# TYPE OUT INtd120k OUT OUT INtd120k DESCRIPTION 3.3V REF 14.318Mhz clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency, Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. 3.3V REF 14.318Mhz clock output. 24MHz or 48MHz (default) clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 5 bit 7. Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 48MHz. In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 5 bit 7. -4- W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Fixed Frequency Outputs, continued. PIN PIN NAME TYPE DESCRIPTION 48MHz clock output for USB. 0.7V current mode 100MHz differential clock outputs for SATA 12 48MHz OUT 26,27 SRCT OUT SRCC 14,15 5.4 DOTT/C 0.7V current mode 96MHz differential clock outputs for DOT I2C Control Interface PIN 5.5 OUT PIN NAME 44 *SDATA 45 *SCLK TYPE DESCRIPTION 2 I/OD Serial data of I C 2-wire control interface with internal pullup resistor. IN Serial clock of I2C 2-wire control interface with internal pullup resistor. Power Management Pins PIN PIN NAME TYPE DESCRIPTION Deciding the reference current for the differential pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. 37 IREF OUT 52 RESET# OD 16 VTT_PWRGD# IN PD Power good is a low active input signal used to determine when FS [2:0] are valid to be sample. INtd120k Power Down Function. This is power down pin, high active (PD). Internal 120K pull down -5- Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 5.6 Power Pins PIN PIN NAME TYPE DESCRIPTION 35 VDDA PWR 3.3V power supply for PLL core. 6,56 VDDP PWR 3.3V power supply for PCI. 19,34 VDDPE PWR 3.3V power supply for PCI express pair. 28 VDDS PWR 3.3V power supply for SRC pair. 10 VDD48 PWR 3.3V power supply for 48MHz. 41 VDDC PWR 3.3V power supply for CPU. 46 VDDR PWR 3.3V power supply for REF. 36 GNDA PWR Ground pin for PLL core. PWR Ground pin 1,5,13,20,25,29, GND 38,49 -6- W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE This frequency table is used at power on latched FS [2:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 171.66 279.99 140.00 210.00 174.99 287.99 144.00 216.00 179.99 -7- PCIE (MHZ) SRC (MHZ) 100.00 100.00 100.00 111.11 111.11 100.00 100.00 100.00 133.33 133.33 133.33 111.11 111.11 133.33 133.33 100.00 101.00 101.00 101.00 112.22 103.00 103.00 103.00 114.44 105.00 105.00 105.00 116.66 108.00 108.00 108.00 120.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI (MHZ) 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 36.00 36.00 36.00 36.00 Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7. I2C CONTROL AND STATUS REGISTERS 7.1 BIT Register 0: Frequency Select Register (Default = 10h) NAME PWD 2 TYPE Frequency selection by software via I C R/W 0 Enable software frequency table selection SSEL [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 3. R/W SPSPEN 0 Enable Spread Spectrum 0 = Normal 1 = Spread Spectrum enabled R/W EN_SAFE_FREQ 0 R/W Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [2:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. 7 SSEL [4] 0 6 SSEL [3] 0 5 SSEL [2] 0 4 SSEL [1] 1 3 SSEL [0] 0 2 EN_SSEL 1 0 7.2 DESCRIPTION Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h) BIT PIN NO PWD DESCRIPTION 7 Reserve 1 Reserved R/W 6 40,39 1 CPUT1 / C1 output control R/W 5 43,42 1 CPUT0 / C0 output control R/W 4 Reserved 0 Reserved (Read only) R 3 Reserved 0 Reserved (Read only) R 2 - X Power on latched value of FS2 pin, Default: 0 (Read only). R 1 - X Power on latched value of FS1 pin, Default: 1 (Read only). R 0 - X Power on latched value of FS0 pin, Default: 0 (Read only). R -8- TYPE W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD 7 9 1 PCI_F2 output control R/W 6 8 1 PCI_F1 output control R/W 5 7 1 PCI_F0 output control R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 4 1 PCI5 output control R/W 1 2,3 1 PCI3, PCI4 output control R/W 0 Reserved 1 Reserved R/W 7.4 DESCRIPTION TYPE Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD 7 54,55 1 PCI1, PCI2 output control R/W 6 Reserved 1 Reserved R/W 5 53 1 PCI0 output control R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 Reserved 1 Reserved R/W 1 Reserved 1 Reserved R/W 0 Reserved 1 Reserved R/W 7.5 DESCRIPTION TYPE Register 4: 24_48MHz, 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh) BIT PIN NO PWD DESCRIPTION 7 11 1 24_48MHz output control R/W 6 14,15 1 DOT_T/C output control R/W 5 12 1 48MHz output control R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 50,51 1 REF1, REF0 output control R/W 1 Reserved 1 Reserved R/W 0 Reserved 1 Reserved R/W -9- TYPE Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.6 Register 5: Watchdog Control (Default: 02h) BIT NAME PWD 7 SEL24_48 X DESCRIPTION 24_ 48 MHz output selection, 1: 24 MHz, 0: 48 MHz (Default). TYPE R/W Default value follow hardware trapping data on SEL24_48# pin. 6 EN_WD 0 Program this bit => R/W 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. 5 WD_TIMEOUT 0 Read Back only. Timeout Flag. This bit is Read Only. R 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting. 4 SAF_FREQ [4] 0 3 SAF_FREQ [3] 0 2 SAF_FREQ [2] 0 1 SAF_FREQ [1] 1 0 SAF_FREQ [0] 0 7.7 R/W These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1. Register 6: SRC, PCIE Control (1 = Enable, 0 = Stopped) (Default: FEh) BIT NAME PWD DESCRIPTION 7 26,27 1 SRCT/C output control R/W 6 Reserved 1 Reserved R/W 5 33,32 1 PCIET4/C4 output control R/W 4 31,30 1 PCIET3/C3 output control R/W 3 23,24 1 PCIET2/C2 output control R/W 2 21,22 1 PCIET1/C1 output control R/W 1 17,18 1 PCIET0/C0 output control R/W 0 Reserved 0 Reserved R/W - 10 - TYPE W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only) BIT NAME PWD 7 CHPI_ID [7] 0 Winbond Chip ID. W83195BR-118 R 6 CHPI_ID [6] 0 Winbond Chip ID. R 5 CHPI_ID [5] 1 Winbond Chip ID. R 4 CHPI_ID [4] 0 Winbond Chip ID. R 3 CHPI_ID [3] 0 Winbond Chip ID. R 2 CHPI_ID [2] 0 Winbond Chip ID. R 1 CHPI_ID [1] 1 Winbond Chip ID. R 0 CHPI_ID [0] 0 Winbond Chip ID. R 7.9 DESCRIPTION TYPE Register 8: M/N Program (Default: 90h) BIT NAME PWD 7 N_DIV [8] 1 6 N_DIV [9] 0 5 4 3 2 1 0 M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0] 0 1 0 0 0 0 DESCRIPTION TYPE Programmable N divisor value. Bit7~0 are defined in the Register R/W 9 Programmable N divisor value. Bit7~0 are defined in the Register R/W 9 Programmable M divisor value. R/W R/W R/W R/W R/W R/W 7.10 Register 9: M/N Program Register (Default: BBh) BIT NAME PWD 7 N_DIV [7] 1 DESCRIPTION R/W 6 N_DIV [6] 0 R/W 5 N_DIV [5] 1 R/W 4 N_DIV [4] 1 3 N_DIV [3] 1 Programmable N divisor value bit 7 ~0. The bit 8 is defined in R/W Register 8. R/W 2 N_DIV [2] 0 R/W 1 N_DIV [1] 1 R/W 0 N_DIV [0] 1 R/W - 11 - TYPE Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.11 Register 10: Reserved (Default: 3Bh) BIT NAME PWD 7 SRC_SPSPEN 0 DESCRIPTION TYPE Enable SRC spread spectrum feature R/W R/W 6 Reserved 0 1: Enable 0: Disable Reserved 5 Reserved 1 Reserved R/W 4 Reserved 1 Reserved R/W 3 Reserved 1 Reserved R/W 2 Reserved 0 Reserved R/W 1 Reserved 1 Reserved R/W 0 Reserved 1 Reserved R/W 7.12 Register 11: Spread Spectrum Programming (Default: 0Eh) BIT NAME PWD DESCRIPTION 7 SP_UP [3] 0 6 SP_UP [2] 0 R/W 5 SP_UP [1] 0 R/W 4 SP_UP [0] 0 R/W 3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 ~ bit 0 R/W 2 SP_DOWN [2] 1 2's complement representation. R/W 1 SP_DOWN [1] 1 Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 R/W 0 SP_DOWN [0] 0 Spread Spectrum Up Counter bit 3 ~ bit 0. TYPE R/W R/W 7.13 Register 12: Divisor Control (Default: 08h) BIT NAME PWD 7 6 Reserved KVAL6 0 X 5 KVAL5 X 4 KVAL4 X 3 KVAL3 X 2 KVAL2 X 1 KVAL1 X 0 KVAL0 X DESCRIPTION TYPE Reserved Define the PCI divider ratio Table-2 integrate the all divider configuration R/W R/W Define the PCIE divider ratio Refer to Table-2 R/W Define the CPU divider ratio Refer to Table-2 R/W R/W R/W R/W R/W - 12 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Table-2 CPU, PCIE, PCI divider ratio selection Table LSB MSB PCI PCIE CPU Bit5 Bit3 Bit1, 0 0 1 0 1 00 01 10 11 Bit2/ 0 Div12 Div16 Div3 Div4 Div2 Div3 Div4 Div6 Bit4/ 1 Div20 Div24 Div8 Div6 Div8 Div8 Div8 Div8 Bit6 7.14 Register 13: Step-less Enable Control (Default: 0Ah) BIT NAME PWD 7 EN_MN_PROG 0 DESCRIPTION 0: Output frequency depend on frequency table TYPE R/W 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<2:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). 6 N<10> 0 Programmable N divisor bit 10. R/W 5 Reserved 0 Reserved R/W 4 Reserved 0 Reserved R/W 3 IVAL<3> 1 Charge pump current selection R/W 2 IVAL<2> 0 R/W 1 IVAL<1> 1 R/W 0 IVAL<0> 0 R/W - 13 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.15 Register 14: Control (Default: 10h) BIT NAME PWD 7 DRI_CONT 0 DESCRIPTION TYPE CPUT / SRCT / PCIE_T / DOT_T output state in during POWER R/W DOWN assertion. 1: Driven (2*Iref), 0: Tristate (Floating) CPUT / SRCT / PCIE_T / DOT_T output state in during STOP Mode assertion. 1: Driven (6*Iref), 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. Reserved R/W 6 Reserved 0 5 SPCNT [5] 0 4 SPCNT [4] 1 Spread Spectrum Programmable time, the resolution is 280ns. R/W Default period is 11.8us R/W 3 SPCNT [3] 0 R/W 2 SPCNT [2] 0 R/W 1 SPCNT [1] 0 R/W 0 SPCNT [0] 0 R/W 7.16 Register 15: SST Control (Default: ECh) BIT NAME PWD DESCRIPTION TYPE 7 INV_CPU 1 Invert the CPU phase, 1: Default, 0: Inverse R/W 6 Reserved 1 Reserved R/W 5 SPSP_TYPE 1 Spread spectrum implementation method R/W 1 : Pendulum type 0 : Original Reserved R/W 4 Reserved 0 3 2 Reserved Reserved 1 1 Reserved R/W Reserved R/W 1 Reserved 0 Reserved R/W 0 Reserved 0 Reserved R/W - 14 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.17 Register 16: Skew Control (Default: E4h) BIT NAME PWD 7 INV_PCIE 1 Invert the PCIE phase, 1: Default, 0: Inverse R/W 6 INV_PCI 1 Invert the PCI phase, 1: Default, 0: Inverse R/W 5 CSKEW [2] 1 CPU1 to CPU0 skew control, Skew resolution is 300ps The decision of skew direction is same as CSKEW<2:0> setting R/W 4 CSKEW [1] 0 3 CSKEW [0] 0 2 PSKEW [2] 1 1 PSKEW [1] 0 0 PSKEW [0] 0 DESCRIPTION TYPE R/W R/W CPU1 to PCI skew control, Skew resolution is 300ps The decision of skew direction is same as PSKEW [2:0] setting R/W R/W R/W 7.18 Register 17: Slew rate Control (Default: 00h) BIT NAME PWD 7 Reserved X Reserved DESCRIPTION TYPE R/W 6 INV_48MHz 0 Invert the 48MHz phase, 0: In phase with 24_48MHz 1: 180 degrees out of phase R/W 5 PCI_F0_S2 0 4 PCI_F0_S1 0 PCI_F0 slew rate control 11 : Strong , 00 : Weak , 3 Reserved 0 Reserved R/W 2 Reserved 0 Reserved R/W 1 Reserved 0 Reserved R/W 0 Reserved 0 Reserved R/W R/W 10/01 : Normal R/W 7.19 Register 18: Reserved (Default: 00h) 7.20 Register 19: Skew Control (Default: DAh) BIT NAME PWD DESCRIPTION 7 Reserved 1 Reserved R/W 6 Reserved 1 Reserved R/W 5 PCIESKEW<2> 0 4 PCIESKEW<1> 1 3 PCIESKEW<0> 1 R/W CPU1 to PCIE skew control Skew resolution is 300ps R/W The decision of skew direction is same as PCIESKEW<2:0> R/W setting 2 Reserved 0 Reserved R/W 1 Reserved 1 Reserved R/W 0 Reserved 0 Reserved R/W - 15 - TYPE Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 7.21 Register 20: Watch dog timer (Default: 88h) BIT NAME PWD DESCRIPTION TYPE 7 Reserved 1 Reserved 6 WD_TIME [6] 0 5 WD_TIME [5] 0 4 WD_TIME [4] 0 Setting the down count depth (Failure decision). One bit R/W resolution represents 250ms. Default time depth is 8*250ms = R/W 2.0 second. If the watchdog timer is counting, this register will R/W return present down count value. 3 WD_TIME [3] 1 R/W 2 WD_TIME [2] 0 R/W 1 WD_TIME [1] 0 R/W 0 WD_TIME [0] 0 R/W R/W 7.22 Register 21: Asynchronous Control (Default: 4Bh) BIT NAME PWD DESCRIPTION TYPE 7 6 Tri-state Reserved 0 1 Tri-state all output if set 1 Reserved R/W 5 Reserved 0 Reserved R/W 4 Reserved 0 Reserved R/W 3 Reserved 1 Reserved R/W 2 SRC_BASE3 0 1: Asynchronous PCIE / PCI always at 100MHz / 33MHz R/W R/W 0: PCIE / PCI frequency are follow Bit1, 0 setting 1 FIX_ADDR<1> 1 Asynchronous PCIE / PCI frequency table selection R/W FIX_ADDR<1:0> => 0 FIX_ADDR<0> 1 00: 96 / 36MHz R/W 01 : 96 / 32MHz 10: 128 / 38.4MHz 11 : Output from PLL1 - 16 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 8. ACCESS INTERFACE The W83195BR-118 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR-118 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. The register number is increased by one if using byte data read/write protocol. Example: In block mode, byte number of program register is 1 In byte mode, byte number of program register is 2 (Byte number of block mode +1) Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8'h00 8.3 Byte Write protocol 8.4 Byte Read protocol - 17 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9. SPECIFICATIONS 9.1 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). 9.2 PARAMETER RATING Absolute 3.3V Core Supply Voltage -0.5V to +4.6V Absolute 3.3V I/O Supple Voltage - 0.5V to + 4.6V Operating 3.3V Core Supply Voltage 3.135V to 3.465V Operating 3.3V I/O Supple Voltage 3.135V to 3.465V Storage Temperature - 65C to + 150C Ambient Temperature - 55C to + 125C Operating Temperature 0C to + 70C Input ESD protection (Human body model) 2000V General Operating Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, PARAMETER SYMBOL Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Operating Supply Current Idd MIN MAX UNITS 0.8 Vdc 2.0 TEST CONDITIONS Vdc 0.4 2.4 Vdc Vdc 350 mA CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Input pin capacitance Output pin capacitance Input pin inductance Cin 5 pF Cout 6 pF Lin 7 nH - 18 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.3 Skew Group timing clock VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF PARAMETER MAX UNITS CPU pair to CPU pair Skew 125 ps Measure Crossing point PCIE pair to PCIE pair Skew 125 ps Measure Crossing point PCI to PCI Skew 500 ps Measured at 1.5V 48MHz to 48MHz Skew 1000 ps Measured at 1.5V 9.4 MIN TEST CONDITIONS CPU 0.7V Electrical Characteristics VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 100 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 9.5 45 TEST CONDITIONS SRC 0.7V Electrical Characteristics VDDS= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 100 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 45 - 19 - TEST CONDITIONS Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.6 PCIE 0.7V Electrical Characteristics VDDPE= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 100 ps Measure Differential waveform 55 % Measure Differential waveform Absolute Voltages crossing point Cycle to Cycle jitter Duty Cycle 9.7 45 TEST CONDITIONS PCI Electrical Characteristics VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 250 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min -33 30 Pull-Down Current Max 9.8 38 TEST CONDITIONS mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V 24M, 48M Electrical Characteristics VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS TEST CONDITIONS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 500 ps Measured at 1.5V 55 % Measured at 1.5V Long term jitter Duty Cycle 45 Pull-Up Current Min -33 Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max mA -33 30 38 - 20 - Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 9.9 REF Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, PARAMETER MIN MAX UNITS Rise Time 500 2000 ps Vol=0.4V, Voh=2.4V Fall Time 500 2000 ps Voh=2.4V, Vol=0.4V 1000 ps Measured at 1.5V 55 % Measured at 1.5V Cycle to Cycle jitter Duty Cycle 45 Pull-Up Current Min -29 Pull-Up Current Max Pull-Down Current Min -23 29 Pull-Down Current Max 27 TEST CONDITIONS mA Vout=1.0V mA Vout=3.135V mA Vout=1.95V mA Vout=0.4V 9.10 DOT 0.7V Electrical Characteristics VDD= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER MIN MAX UNITS Rise Time 175 700 ps Measure Single Ended waveform Fall Time 175 700 ps Measure Single Ended waveform Absolute crossing point Voltages 250 550 mV Measure Single Ended waveform Voltage High 660 850 mV Measure Single Ended waveform Voltage Low -150 mV Measure Single Ended waveform 250 ps Measure Differential waveform 55 % Measure Differential waveform Cycle to Cycle jitter Duty Cycle 45 - 21 - TEST CONDITIONS Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 10. ORDERING INFORMATION PART NUMBER PACKAGE TYPE PRODUCTION FLOW W83195BR-118 56 PIN SSOP Commercial, 0C to +70C W83195BG-118 56 PIN SSOP Commercial, 0C to +70C 11. HOW TO READ THE TOP MARKING W83195BR-118 28051234 520GCASA W83195BG-118 28051234 520GCASA Left line: Winbond logo 1st line: the part number: W83195BR-118, the Pb-free part number W83195BG-118 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 520 G C A SA 520: packages made in '2005, week 20 G: assembly house ID; O means OSE, G means GR C: Internal use code A: IC revision SA: Internal use code All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. - 22 - W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS 12. PACKAGE DRAWING AND DIMENSIONS 56 PIN SSOP-300mil .035 .045 SYMBOL .045 .055 0.40/0.50 DIA E END VIEW HE TOP VIEW SEE DETAIL "A" c D A2 A SEATING PLANE A1 e b SIDE VIEW DIMENSION IN INCH c D HE 18.2 18.42 18.54 910.16 10.31 10.41 E 7.42 0.51 7.52 0.64 7.59 0.76 0.61 0.81 1.40 1.02 A A1 A2 b e L L1 Y DIMENSION IN MM MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 PARTING LINE Y c 0 0.08 8 0.720 0.400 0.292 0.020 0.024 MAX. 0.110 0.016 0.092 0.0135 0.010 0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 0 8 L L1 DETAIL"A" - 23 - Publication Release Date: May 2006 Revision 0.81 W83195BR-118/W83195BG-118 STEPLESS FOR INTEL 915/945 CHIPSETS Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 24 -