Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 7
1Publication Order Number:
NCP1250/D
NCP1250
Current-Mode PWM
Controller for Off-line
Power Supplies
The NCP1250 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
tiny TSOP−6 package. With a supply range up to 28 V, the controller
hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak
current mode control. When the power on the secondary side starts to
decrease, the controller automatically folds back its switching
frequency down to a minimum level of 26 kHz. As the power further
goes down, the part enters skip cycle while limiting the peak current.
Over Power Protection (OPP) is a difficult exercise especially when
no−load standby requirements drive the converter specifications. The
ON proprietary integrated OPP lets you harness the maximum
delivered power without affecting your standby performance simply
via two external resistors. An Over Voltage Protection input is also
combined on the same pin and protects the whole circuitry in case of
optocoupler failure or adverse open loop operation.
Finally, a timer−based short−circuit protection offers the best
protection scheme, letting you precisely select the protection trip point
irrespective of a loose coupling between the auxiliary and the power
windings.
Features
Fixed−Frequency 65 or 100 kHz Current−Mode Control Operation
Internal and Adjustable Over Power Protection (OPP) Circuit
Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load
Conditions
Internal Ramp Compensation
Internal Fixed 4 ms Soft−Start
100 ms Timer−Based Auto−Recovery Short−Circuit Protection
Frequency Jittering in Normal and Frequency Foldback Modes
Option for Auto−Recovery or Latched Short−Circuit Protection
OVP Input for Improved Robustness
Up to 28 V VCC Operation
+300 mA / −500 mA Source/Sink Drive Capability
Less than 100 mW Standby Power at High Line
EPS 2.0 Compliant
These are Pb−Free Devices
Typical Applications
ac−dc Converters for TVs, Set−top Boxes and Printers
Offline Adapters for Notebooks and Netbooks
PIN CONNECTIONS
1
3CS
GND
2
OPP/Latch 4
DRV
6
(Top View)
5VCC
TSOP−6
(SOT23−6)
SN SUFFIX
CASE 318G
STYLE 13
MARKING DIAGRAM
FB
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(Note: Microdot may be in either location)
1
25xAYWG
G
1
25x = Specific Device Code
x = A, 2, C, or D
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
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2
1
2
3
6
4
5
NCP1250
Vbulk
.
.
ramp
comp.
OPP
Vo u t
OVP
.
Figure 1. Typical Application Example
Pin N5Pin Name Function Pin Description
1 GND −The controller ground.
2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.
3 OPP/OVP Adjust the Over Power Protection
Latches off the part
A resistive divider from the auxiliary winding to this pin sets the OPP
compensation level. When brought above 3 V, the part is fully latched
off.
4 CS Current sense + ramp
compensation
This pin monitors the primary peak current but also offers a means to
introduce ramp compensation.
5 VCC Supplies the controller This pin is connected to an external auxiliary voltage and supplies the
controller.
6 DRV Driver output The driver’s output to an external MOSFET gate.
OPTIONS
Controller Frequency OCP Latched OCP Auto−Recovery
NCP1250ASN65T1G 65 kHz Yes No
NCP1250BSN65T1G 65 kHz No Yes
NCP1250ASN100T1G 100 kHz Yes No
NCP1250BSN100T1G 100 kHz No Yes
ORDERING INFORMATION
Device Package Marking OCP Protection Switching Frequency Package Shipping†
NCP1250ASN65T1G 25A Latch 65 kHz
TSOP−6
(Pb−Free)
3000 /
Tape & Reel
NCP1250BSN65T1G 252 Autorecovery 65 kHz
NCP1250ASN100T1G 25C Latch 100 kHz
NCP1250BSN100T1G 25D Autorecovery 100 kHz
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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Figure 2. Internal Circuit Architecture
S
R
Q
Q
65
100 kHz
clock
vdd
Frequency
modulation
Drv
Vcc and logic
management
vdd power
on reset
Rramp
LEB
vdd
RFB
/ 4.2
IpFlag
4 ms
SS
Power on
reset
IpFlag
GND
CS
FB
600−ns time
constant
OPP
Frequency
foldback
Vskip
Vlatch
The soft−start is activated during:
− the startup sequence
− the auto−recovery burst mode
+
Vlimit
VOPP Vlimit + VOPP
Vfold
S
R
Q
Q
Clamp
1−us
blanking
Up counter
4
hiccup
RST
OVP
gone?
250 mV
peak current
freeze
VFB < 1.05 V ? setpoint = 250 mV
UVLO
Rlim
Iscr
Vcc
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MAXIMUM RATINGS TABLE
Symbol Rating Value Unit
VCC Power Supply voltage, VCC pin, continuous voltage 28 V
VDRVtran Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1) VCC + 0.3 V
Maximum voltage on low power pins CS, FB and OPP −0.3 to 10 V
IOPP Maximum injected negative current into the OPP pin (pin 3) −2 mA
ISCR Maximum continuous current in to the VCC Pin while in latched mode 3 mA
RqJA Thermal Resistance Junction−to−Air 360 C/W
TJ,max Maximum Junction Temperature 150 C
Storage Temperature Range −60 to +150 C
ESD Capability, Human Body Model (HBM), all pins 2 kV
ESD Capability, Machine Model (MM) 200 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)
Symbol Rating Pin Min Typ Max Unit
SUPPLY SECTION − (For the best efficiency performance, we recommend a VCC below 20 V)
VCCON VCC increasing level at which driving pulses are authorized 5 16 18 20 V
VCC(min) VCC decreasing level at which driving pulses are stopped 5 8.2 8.8 9.4 V
VCCHYST Hysteresis VCCON − VCC(min) 5 6.0 V
VZENER Clamped VCC when latched off / burst mode activation @ ICC = 500 mA5 7.0 V
ICC1 Start−up current 5 15 mA
ICC2 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 0 nF 5 1.4 2.2 mA
ICC3 Internal IC consumption with IFB = 50 mA, FSW = 65 kHz and CL = 1 nF 5 2.1 3.0 mA
ICC2 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 0 nF 5 1.7 2.5 mA
ICC3 Internal IC consumption with IFB = 50 mA, FSW = 100 kHz and CL = 1 nF 5 3.1 4.0 mA
ICCLATCH Current flowing into VCC pin that keeps the controller latched (Note 4)
TJ = −40C to +125C
TJ = 0C to +125C
5
40
32
mA
ICCstby Internal IC consumption while in skip cycle (VCC = 12 V, driving a typical 6 A/600 V
MOSFET)
5 550 mA
Rlim Current−limit resistor in series with the latch SCR 5 4.0 kW
DRIVE OUTPUT
TrOutput voltage rise−time @ CL = 1 nF, 10−90% of output signal 6 40 ns
TfOutput voltage fall−time @ CL = 1 nF, 10−90% of output signal 6 30 ns
ROH Source resistance 6 13 W
ROL Sink resistance 6 6.0 W
Isource Peak source current, VGS = 0 V – (Note 5) 6 300 mA
Isink Peak sink current, VGS = 12 V – (Note 5) 6 500 mA
VDRVlow DRV pin level at VCC close to VCC(min) with a 33 kW resistor to GND 6 8.0 V
VDRVhigh DRV pin level at VCC = 28 V – DRV unloaded 6 10 12 14 V
CURRENT COMPARATOR
IIB Input Bias Current @ 0.8 V input level on pin 4 4 0.02 mA
VLimit1 Maximum internal current setpoint – TJ = 25C – pin 3 grounded 4 0.744 0.8 0.856 V
VLimit2 Maximum internal current setpoint – TJ = −40C to 125C – pin 3 grounded 4 0.72 0.8 0.88 V
Vfold Default internal voltage set point for frequency foldback trip point – 45% of Vlimit 3 357 mV
Vfreeze Internal peak current setpoint freeze ([31% of Vlimit) 3 250 mV
TDEL Propagation delay from current detection to gate off−state 4 100 150 ns
TLEB Leading Edge Blanking Duration 4 300 ns
TSS Internal soft−start duration activated upon startup, auto−recovery −4.0 ms
IOPPo Setpoint decrease for pin 3 biased to –250 mV – (Note 6) 3 31.3 %
IOOPv Voltage setpoint for pin 3 biased to −250 mV – (Note 6), TJ = 25C 3 0.51 0.55 0.60 V
IOOPv Voltage setpoint for pin 3 biased to −250 mV – (Note 6), TJ = −40C to 125C 3 0.50 0.55 0.62 V
IOPPs Setpoint decrease for pin 3 grounded 3 0 %
INTERNAL OSCILLATOR
fOSC Oscillation frequency (65 kHz version) −61 65 71 kHz
fOSC Oscillation frequency (100 kHz version) −92 100 108 kHz
Dmax Maximum duty−cycle −76 80 84 %
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ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)
Symbol UnitMaxTypMinPinRating
INTERNAL OSCILLATOR
fjitter Frequency jittering in percentage of fOSC −5 %
fswing Swing frequency −240 Hz
FEEDBACK SECTION
Rup Internal pull−up resistor 2 20 kW
Req Equivalent ac resistor from FB to GND 2 16 kW
Iratio Pin 2 to current setpoint division ratio −4.2
Vfreeze Feedback voltage below which the peak current is frozen 2 1.05 V
FREQUENCY FOLDBACK
Vfold Frequency folback level on the feedback pin – [45% of maximum peak current −1.5 V
Ftrans Transition frequency below which skip−cycle occurs −22 26 30 kHz
Vfold,end End of frequency foldback feedback leve, Fsw = Fmin 350 mV
Vskip Skip−cycle level voltage on the feedback pin −300 mV
Skip
hysteresis
Hysteresis on the skip comparator – (Note 5) −30 mV
INTERNAL SLOPE COMPENSATION
Vramp Internal ramp level @ 25C – (Note 7) 4 2.5 V
Rramp Internal ramp resistance to CS pin 4 20 kW
PROTECTIONS
Vlatch Latching level input 3 2.7 3.0 3.3 V
Tlatch−blank Blanking time after drive turn off 1 1.0 ms
Tlatch−count Number of clock cycles before latch confirmation −4.0
Tlatch−del OVP detection time constant 1 600 ns
Timer Internal auto−recovery fault timer duration −100 130 160 ms
4. For design robustness, we recommend to inject 60 mA as a minimum at the lowest input line voltage.
5. Guaranteed by design
6. See characterization table for linearity over negative bias voltage
7. A 1 MW resistor is connected from pin 3 to the ground for the measurement.
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TYPICAL CHARACTERISTICS
75
76
77
78
79
80
81
82
83
84
85
−50 −25 0 25 50 75 100 125
Dmax (%)
TEMPERATURE (C)
Figure 3.
60
62
64
66
68
70
72
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 4.
FSW (kHz)
21
22
23
24
25
26
27
28
29
30
31
TEMPERATURE (C)
Figure 5.
−50 −25 0 25 50 75 100 125
Ftrans (kHz)
140
190
240
290
340
390
440
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 6.
F_swing (Hz)
0.71
0.73
0.75
0.77
0.79
0.81
0.83
0.85
0.87
0.89
TEMPERATURE (C)
Figure 7.
Vlimit (mV)
−50 −25 0 25 50 75 100 125
190
240
290
340
390
440
490
140
VLskip (mV)
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 8.
FSW = 65 kHz
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TYPICAL CHARACTERISTICS
19
24
29
34
39
44
IOOPO (%)
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 9.
0.5
0.52
0.54
0.56
0.58
0.6
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 10.
IOOPV (V)
15.9
16.4
16.9
17.4
17.9
18.4
18.9
19.4
19.9
VCC(ON) (V)
TEMPERATURE (C)
Figure 11.
−50 −25 0 25 50 75 100 125
8.1
8.3
8.5
8.7
8.9
9.1
9.3
9.5
VCC(min) (V)
TEMPERATURE (C)
Figure 12.
−50 −25 0 25 50 75 100 125
5
6
7
8
9
10
11
12
13
14
TEMPERATURE (C)
Figure 13.
−50 −25 0 25 50 75 100 125
VCC(Hyst) (V)
0
2
4
6
8
10
12
14
16
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 14.
ICC1 (mA)
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TYPICAL CHARACTERISTICS
0
0.5
1
1.5
2
TEMPERATURE (C)
Figure 15.
ICC2 (mA)
−50 −25 0 25 50 75 100 125
0
0.5
1
1.5
2
2.5
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 16.
0
2
4
6
8
10
ICC3 (mA)
Vzener (V)
TEMPERATURE (C)
Figure 17.
−50 −25 0 25 50 75 100 125
0
5
10
15
20
25
30
TEMPERATURE (C)
Figure 18.
−50 −25 0 25 50 75 100 125
ICCLatch (mA)
90
140
190
240
290
340
390
Tleb (V)
TEMPERATURE (C)
Figure 19.
−50 −25 0 25 50 75 100 125
0
20
40
60
80
100
120
140
160
TEMPERATURE (C)
Figure 20.
−50 −25 0 25 50 75 100 125
Req (kW)
FSW = 65 kHz FSW = 65 kHz
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TYPICAL CHARACTERISTICS
3.6
3.8
4
4.2
4.4
4.6
4.8
Iratio (−)
TEMPERATURE (C)
Figure 21.
−50 −25 0 25 50 75 100 125 2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 22.
Vlatch (V)
0
20
40
60
80
100
trise (ns)
TEMPERATURE (C)
Figure 23.
−50 −25 0 25 50 75 100 125 0
20
40
60
80
100
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 24.
tfall (ns)
2
3
4
5
6
7
8
9
10
11
Rol (W)
TEMPERATURE (C)
Figure 25.
−50 −25 0 25 50 75 100 125
5
10
15
20
25
30
35
Roh (W)
TEMPERATURE (C)
Figure 26.
−50 −25 0 25 50 75 100 125
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TYPICAL CHARACTERISTICS
0
20
40
60
80
100
Vovp_del (ms)
TEMPERATURE (C)
Figure 27.
−50 −25 0 25 50 75 100 125 7
8
9
10
11
12
13
14
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 28.
Vdrv_low (V)
8.9
9.4
9.9
10.4
10.9
11.4
11.9
12.4
12.9
Vdrv_high (V)
TEMPERATURE (C)
Figure 29.
−50 −25 0 25 50 75 100 125 2.9
3.4
3.9
4.4
4.9
TSS (ms)
TEMPERATURE (C)
Figure 30.
−50 −25 0 25 50 75 100 125
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Vfold(FB) (V)
TEMPERATURE (C)
Figure 31.
−50 −25 0 25 50 75 100 125 350
352
354
356
358
360
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 32.
Vfold(CS) (mV)
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TYPICAL CHARACTERISTICS
0.29
0.31
0.33
0.35
0.37
0.39
0.41
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 33.
Vfold_end (V)
190
240
290
340
390
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 34.
Vskip (mV)
190
240
290
340
390
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 35.
Vfreeze (mV)
0.7
0.9
1.1
1.3
1.5
1.7
Vfreeze(FB) (V)
TEMPERATURE (C)
Figure 36.
−50 −25 0 25 50 75 100 125
90
100
110
120
130
140
150
160
−50 −25 0 25 50 75 100 125
TEMPERATURE (C)
Figure 37.
TIMER (ms)
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
ICC (mA)
ADAPTER OUTPUT CURRENT (A)
Figure 38. Controller Consumption vs.
Adapter Output Current
FSW = 65 kHz
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APPLICATION INFORMATION
Introduction
The NCP1250 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current setpoint. This component represents the ideal
candidate where low part−count and cost effectiveness are
the key parameters, particularly in low−cost ac−dc adapters,
open−frame power supplies etc. Capitalizing on the
NCP120X series success, the NCP1250 packs all the
necessary components normally needed in today modern
power supply designs, bringing several enhancements such
as a non−dissipative OPP.
Current−mode operation with internal ramp
compensation: Implementing peak current mode
control at a fixed 65 kHz or 100 kHz, the NCP1250
offers an internal ramp compensation signal that can
easily by summed with the sensed current. Sub
harmonic oscillations are eliminated via the inclusion of
a single resistor in series with the current−sense
information.
Internal OPP: By routing a portion of the negative
voltage present during the on−time on the auxiliary
winding to the dedicated OPP pin (pin 3), the user has a
simple and non−dissipative means to alter the
maximum peak current setpoint as the bulk voltage
increases. If the pin is grounded, no OPP compensation
occurs. If the pin receives a negative voltage down to
–250 mV, then a peak current reduction down to 31.3%
typical can be achieved. For an improved performance,
the maximum voltage excursion on the sense resistor is
limited to 0.8 V.
Low startup current: Achieving a low no−load
standby power always represents a difficult exercise
when the controller draws a significant amount of
current during start−up. Due to its proprietary
architecture, the NCP1250 is guaranteed to draw less
than 15 mA typical, easing the design of low standby
power adapters.
EMI jittering: An internal low−frequency modulation
signal varies the pace at which the oscillator frequency
is modulated. This helps by spreading out energy in
conducted noise analysis. To improve the EMI
signature at low power levels, the jittering remains
active in frequency foldback mode.
Frequency foldback capability: A continuous flow of
pulses is not compatible with no−load/light−load
standby power requirements. To excel in this domain,
the controller observes the feedback pin and when it
reaches a level of 1.5 V, the oscillator then starts to
reduce its switching frequency as the feedback level
continues to decrease. When the feedback pin reaches
1.05 V, the peak current setpoint is internally frozen and
the frequency continues to decrease. It can go down to
26 kHz (typical) reached for a feedback level of
roughly 350 mV. At this point, if the power continues to
drop, the controller enters classical skip−cycle mode.
Internal soft−start: A soft−start precludes the main
power switch from being stressed upon start−up. In this
controller, the soft−start is internally fixed to 4 ms. The
soft−start is activated when a new startup sequence
occurs or during an auto−recovery hiccup.
OVP input: The NCP1250 includes a latch input
(pin 3) that can be used to sense an overvoltage
condition on the adapter. If this pin is brought higher
than the internal reference voltage Vlatch, then the
circuit permanently latches off. The VCC pin is pulled
down to a fixed level, keeping the controller latched.
The latch reset occurs when the user disconnects the
adapter from the mains and lets the VCC falls below the
VCC reset.
Short−circuit protection: Short−circuit and especially
over−load protections are difficult to implement for
transformers with high leakage inductance between
auxiliary and power windings (the aux winding level
does not properly collapse in presence of an output
short). Here, every time the internal 0.8 V maximum
peak current limit is activated (or less when OPP is
used), an error flag is asserted and a time period starts,
thanks to an internal timer. If the timer reaches
completion while the error flag is still present, the
controller stops the pulses and goes into a latch−off
phase, operating in a low−frequency burst−mode. When
the fault is cleared, the SMPS resumes operation.
Please note that some versions offer an auto−recovery
mode as described and some latch off in case of a short
circuit.
Start−up Sequence
The NCP1250 start−up voltage is made purposely high to
permit a large energy storage in a small VCC capacitor value.
This helps to operate with a small start−up current which,
together with a small VCC capacitor, will not hamper the
start−up time. To further reduce the standby power, the
start−up current of the controller is extremely low, below
15 mA maximum. The start−up resistor can therefore be
connected to the bulk capacitor or directly to the mains input
voltage to further reduce the power dissipation.
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11
1
R1
200k
10
R2
200k
3
R3
200k
5
D1
1N4007
12
D2
1N4007
Cbulk
22uF
C1
4.7uF
D3
1N4007
D4
1N4007
input
mains
42
D5
1N4935
C3
47uF
D6
1N4148
VCC
aux.
Figure 39. The Startup Resistor Can Be Connected to the Input Mains for Further Power Dissipation Reduction
The first step starts with the calculation of the VCC
capacitor which will supply the controller when it operates
until the auxiliary winding takes over. Experience shows
that this time t1 can be between 5 ms and 20 ms. If we
consider we need at least an energy reservoir for a t1 time of
10 ms, the VCC capacitor must be larger than:
CVCC w
ICCt1
VCCon *VCC
min
w3m 10m
9w3.3 mF(eq. 1)
Let us select a 4.7 mF capacitor at first and experiments in
the laboratory will let us know if we were too optimistic for
the time t1. The VCC capacitor being known, we can now
evaluate the charging current we need to bring the VCC
voltage from 0 to the VCCon of the IC, 18 V typical. This
current has to be selected to ensure a start−up at the lowest
mains (85 V rms) to be less than 3 s (2.5 s for design margin):
Icharge w
VCConCVCC
2.5 w18 4.7m
2.5 w34 mA(eq. 2)
If we account for the 15 mA that will flow inside the
controller, then the total charging current delivered by the
start−up resistor must be 49 mA. If we connect the start−up
network to the mains (half−wave connection then), we know
that the average current flowing into this start−up resistor
will be the smallest when VCC reaches the VCCon of the
controller:
ICVCC,min +
Vac,rms 2
Ǹ
p*VCCon
Rstart*up
(eq. 3)
To make sure this current is always greater than 49 mA,
then the minimum value for Rstart−up can be extracted:
Rstart*up v
Vac,rms 2
Ǹ
p*VCCon
ICVCC,min
v
85 1.414
p*18
49mv413.5 k
W
(eq. 4)
This calculation is purely theoretical, and assumes a
constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
VCC capacitor. Hence, a decrease in charging current and an
increase of the start−up resistor, thus reducing the standby
power. Laboratory experiments on the prototype are thus
mandatory to fine tune the converter. If we chose the 413 kW
resistor as suggested by Equation 4, the dissipated power at
high line amounts to:
PRstart*up +
Vac,peak 2
4Rstart*up
+ǒ230 2
ǸǓ2
4 413k (eq. 5)
+2302
0.827Meg +64 mW
Now that the first VCC capacitor has been selected, we
must ensure that the self−supply does not disappear when in
no−load conditions. In this mode, the skip−cycle can be so
deep that refreshing pulses are likely to be widely spaced,
inducing a large ripple on the VCC capacitor. If this ripple is
too large, chances exist to touch the VCCmin and reset the
controller into a new start−up sequence. A solution is to
grow this capacitor but it will obviously be detrimental to the
start−up time. The option offered in Figure 39 elegantly
solves this potential issue by adding an extra capacitor on the
auxiliary winding. However, this component is separated
from the VCC pin via a simple diode. You therefore have the
ability to grow this capacitor as you need to ensure the
self−supply of the controller without jeopardizing the
start−up time and standby power. A capacitor ranging from
22 to 47 mF is the typical value for this device.
One note on the start-up current. If reducing it helps to
improve the standby power, its value cannot fall below a
certain level at the minimum input voltage. Failure to inject
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15
enough current (30 mA) at low line will turn a converter in
fault into an auto-recovery mode since the SCR won’t
remain latched. To build a sufficient design margin, we
recommend to keep at least 60 mA flowing at the lowest input
line (80 V rms for 85 V minimum for instance). An excellent
solution is to actually combine X2 discharge and start-up
networks as proposed in Figure 13 of application note
AND8488/D.
Internal Over Power Protection
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
swing present on the auxiliary diode anode. During the
power switch on−time, this point dips to −NVin, N being the
turns ratio between the primary winding and the auxiliary
winding. The negative plateau observed on Figure 41 will
have an amplitude dependant on the input voltage. The idea
implemented in this chip is to sum a portion of this negative
swing with the 0.8 V internal reference level. For instance,
if the voltage swings down to −150 mV during the on time,
then the internal peak current set point will be fixed to 0.8 −
0.150 = 650 mV. The adopted principle appears in Figure 41
and shows how the final peak current set point is
constructed.
1v(24)
464u 472u 480u 488u 496u
time (s)
−40.0
−20.0
0
20.0
40.0
v(24) (V)
1
on−time
1v(24)
−40.0
−20.0
0
20.0
40.0
1
off−time
Figure 40. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time
N1(Vout +Vf)
−N2Vbulk
Let’s assume we need to reduce the peak current from
2.5 A at low line, to 2 A at high line. This corresponds to a
20% reduction or a set point voltage of 640 mV. To reach this
level, then the negative voltage developed on the OPP pin
must reach:
VOPP +640m *800m +−160 mV (eq. 6)
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VDD
re f
OPP
+
−
from FB reset
CS
VCC
aux
RoppU
swings to:
Vout during toff
−N V in during ton
Iopp
R oppL
SUM2
K1
K2
0.8 V
$5%
ref = 0.8 V + VOPP
(V O P P is negativ e)
This p oin t will
be adjusted to
reduce the ref
at hi line to the
desired level.
Figure 41. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to the
Internal Voltage Reference
Let us assume that we have the following converter
characteristics:
Vout = 19 V
Vin = 85 to 265 Vrms
N1 = Np:Ns = 1:0.25
N2 = Np:Naux = 1:0.18
Given the turns ratio between the primary and the auxiliary
windings, the on−time voltage at high line (265 Vac) on the
auxiliary winding swings down to:
Vaux +−N2Vin,max +−0.18 375 +−67.5 V (eq. 7)
To obtain a level as imposed by Equation 6, we need to
install a divider featuring the following ratio:
Div +0.16
67.5 [2.4m (eq. 8)
If we arbitrarily fix the pull−down resistor ROPPL to 1 kW,
then the upper resistor can be obtained by:
ROPPU +67.5 *0.16
0.16ń1k [421 kW(eq. 9)
If we now plot the peak current set point obtained by
implementing the recommended resistor values, we obtain
the following curve (Figure 42):
80%
Peak current
setpoint
Vbulk
375
100%
Figure 42. The Peak Current Regularly Reduces Down to 20% at 375 Vdc
The OPP pin is surrounded by Zener diodes stacked to
protect the pin against ESD pulses. These diodes accept
some peak current in the avalanche mode and are designed
to sustain a certain amount of energy. On the other side,
negative injection into these diodes (or forward bias) can
cause substrate injection which can lead to an erratic circuit
behavior. To avoid this problem, the pin is internally
clamped slightly below –300 mV which means that if more
current is injected before reaching the ESD forward drop,
then the maximum peak reduction is kept to 40%. If the
voltage finally forward biases the internal zener diode, then
care must be taken to avoid injecting a current beyond
–2 mA. Given the value of ROPPU, there is no risk in the
present example.
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Finally, please note that another comparator internally
fixes the maximum peak current set point to 0.8 V even if the
OPP pin is inadvertently biased above 0 V.
Frequency Foldback
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change to
the traditional fixed−frequency type of operation. This
controller implements a switching frequency foldback when
the feedback voltage passes below a certain level, Vfold, set
around 1.5 V. At this point, the oscillator enters frequency
foldback and reduces its switching frequency. The peak
current setpoint follows the feedback pin until its level
reaches 1.05 V. Below this value, the peak current freezes to
Vfold/4.2 (250 mV or 31% of the maximum 0.8 V setpoint)
and the only way to further reduce the transmitted power is
to reduce the operating frequency down to 26 kHz. This
value is reached at a voltage feedback level of 350 mV
typically. Below this point, if the output power continues to
decrease, the part enters skip cycle for the best noise−free
performance in no−load conditions. Figure 43 depicts the
adopted scheme for the part.
Fsw
VFB
VCS
VFB
65 kHz
26 kHz
350 mV Vfold
3.4 V Vfold 3.4 V
0.8 V
0.36 V
FB
Vfreeze
[0.25 V
1.05 V 1.5 V
1.5 V
max
min
max
min
Vfold,end
Frequency Peak current setpoint
VFB
min
Figure 43. By Observing the Voltage on the Feedback Pin, the Controller Reduces its Switching Frequency for an
Improved Performance at Light Load
[
Auto−Recovery Short−Circuit Protection
In case of output short−circuit or if the power supply
experiences a severe overloading situation, an internal error
flag is raised and starts a countdown timer. If the flag is
asserted longer than 100 ms, the driving pulses are stopped
and the VCC pin slowly goes down to around 7 V. At this
point, the controller wakes−up and the VCC builds up again
due to the resistive starting network. When VCC reaches
VCCON, the controller attempts to re−start, checking for the
absence of the fault. If the fault is still there, the supply enters
another cycle of so−called hiccup mode. If the fault has
cleared, the power supply resumes normal operation. Please
note that the soft−start is activated during each of the re−start
sequence.
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1vcc 2vdrv 3ilprim
500u 1.50m 2.50m 3.50m 4.50m
time in seconds
445m
1.41
2.38
3.35
4.32
ilprim in amperes
−8.13
−2.12
3.89
9.90
15.9
vcc in volts
−11.5
−2.72
6.05
14.8
23.6
vdrv in volts
Plot1
2
1
3
cc
V (t)
DRV
V
p
L
I
SS
1vcc 2vdrv 3ilprim
500u 1.50m 2.50m 3.50m 4.50m
time in seconds
445m
1.41
2.38
3.35
4.32
ilprim in amperes
−8.13
−2.12
3.89
9.90
15.9
vcc in volts
−11.5
−2.72
6.05
14.8
23.6
vdrv in volts
Plot1
2
1
3
cc
V
DRV
V
p
L
I
SS
Figure 44. An Auto−Recovery Hiccup Mode is Activated for Faults Longer than 100 ms
(t)
(t)
Slope Compensation
The NCP1250 includes an internal ramp compensation
signal. This is the buffered oscillator clock delivered only
during the on time. Its amplitude is around 2.5 V at the
maximum duty−cycle. Ramp compensation is a known
means used to cure sub harmonic oscillations in Continuous
Conduction Mode (CCM) operated current−mode
converters. These oscillations take place at half the
switching frequency and occur only during CCM with a
duty−cycle greater than 50%. To lower the current loop gain,
one usually injects between 50% and 100% of the inductor
downslope. Figure 45 depicts how internally the ramp is
generated. Please note that the ramp signal will be
disconnected from the CS pin, during the off time.
Rsense
Rcomp
20k
0V
2.5 V
CS
+
−
LEB
from FB
setpoint
latch
reset
ON
Figure 45. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and
Stabilizes the Converter in CCM Operation.
In the NCP1250 controller, the oscillator ramp features a
2.5 V swing reached at a 80% duty−ratio. If the clock
operates at a 65 kHz frequency, then the available oscillator
slope corresponds to:
Sramp +
Vramp,peak
DmaxTSW
+2.5
0.8 15m(eq. 10)
+208 kVńsor208mVńms
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19
In our flyback design, let’s assume that our primary
inductance Lp is 770 mH, and the SMPS delivers 19 V with
a Np:Ns ratio of 1:0.25. The off−time primary current slope
Sp is thus given by:
Sp+ǒVout )VfǓNp
Ns
Lp+(19 )0.8) 4
770m+103 kAńs
(eq. 11)
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
Ssense +SpRsense +103k 0.33 (eq. 12)
+34 kVńsor34mVńms
If we select 50% of the downslope as the required amount
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
208 mV/ms, the divider ratio (divratio) between Rcomp and
the internal 20 kW resistor is:
divratio +17m
208m +0.082 (eq. 13)
The series compensation resistor value is thus:
(eq. 14)
Rcomp +Rramp @divratio +20k 0.082 [1.6 kW
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small capacitor of 100 pF, from the current sense
pin to the controller ground for an improved immunity to the
noise. Please make sure both components are located very
close to the controller.
Latching Off the Controller
The OPP pin not only allows a reduction of the peak
current set point in relationship to the line voltage, it also
offers a means to permanently latch−off the part. When the
part is latched−off, the VCC pin is internally pulled down to
around 7 V and the part stays in this state until the user cycles
the VCC down and up again, e.g. by un−plugging the
converter from the mains outlet. It is important to note that
the SCR maintains its latched state as long as the injected
current stays above the minimum value of 30 mA. As the
SCR delatches for an injected current below this value, it is
the designer duty to make sure the injected current is high
enough at the lowest input voltage. Failure to maintain a
sufficiently high current would make the device auto
recover. A good design practice is to ensure at least 60 mA
at the lowest input voltage. The latch detection is made by
observing the OPP pin by a comparator featuring a 3 V
reference voltage. However, for noise reasons and in
particular to avoid the leakage inductance contribution at
turn off, a 1 ms blanking delay is introduced before the
output of the OVP comparator is checked. Then, the OVP
comparator output is validated only if its high−state duration
lasts a minimum of 600 ns. Below this value, the event is
ignored. Then, a counter ensures that 4 successive OVP
events have occurred before actually latching the part. There
are several possible implementations, depending on the
needed precision and the parameters you want to control.
The first and easiest solution is the additional resistive
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on time.
D2
1N4148
4
5
1
OP P
Vlatch
10
8
9
VCC
aux.
winding
OPP
ROPPL
1k
RoppU
421k
11
R3
5k
C1
100p
OVP
Figure 46. A Simple Resistive Divider Brings the OPP Pin Above 3 V in Case of a VCC Voltage Runaway above
18 V
First, calculate the OPP network with the above equations.
Then, suppose we want to latch off our controller when Vout
exceeds 25 V. On the auxiliary winding, the plateau reflects
the output voltage by the turns ratio between the power and
the auxiliary winding. In case of voltage runaway for our
19 V adapter, the plateau will go up to:
Vaux,OVP +25 0.18
0.25 +18 V (eq. 15)
Since our OVP comparator trips at a 3 V level, across the
1 kW selected OPP pulldown resistor, it implies a 3 mA
current. From 3 V to go up to 18 V, we need an additional
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20
15 V. Under 3 mA and neglecting the series diode forward
drop, it requires a series resistor of:
ROVP +
Vlatch *VVOP
VOVPńROPPL
+18 *3
3ń1k +15
3m +5kW(eq. 16)
In nominal conditions, the plateau establishes to around
14 V. Given the divide−by−6 ratio, the OPP pin will swing
to 14/6 = 2.3 V during normal conditions, leaving 700 mV
margin. A 100 pF capacitor can be added between the OPP
pin and GND to improve noise immunity and avoid erratic
trips in presence of external surges. Do not increase this
capacitor too much otherwise the OPP signal will be affected
by the integrating time constant.
A second solution for the OVP detection alone, is to use
a Zener diode wired as recommended by.
D3
15V
4
5
1
OPP
Vlatch
10
8
9
VCC
aux.
winding
OPP
ROPPL
1k
ROPPU
421k
11
D2
1N4148
C1
22pF
OVP
Figure 47. A Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System
For this configuration to maintain an 18 V level, we have
selected a 15 V Zener diode. In nominal conditions, the
voltage on the OPP pin is almost 0 V during the off time as
the Zener is fully blocked. This technique clearly improves
the noise immunity of the system compared to that obtained
from a resistive string as in Figure 46. Please note the
reduction of the capacitor on the OPP pin to 10 pF − 22 pF.
This capacitor is necessary because of the potential spike
coupling through the Zener parasitic capacitance from the
bias winding due to the leakage inductance. Despite the 1 ms
blanking delay at turn off. This spike is energetic enough to
charge the added capacitor C1 and given the time constant,
could make it discharge slower, potentially disturbing the
blanking circuit. When implementing the Zener option, it is
important to carefully observe the OPP pin voltage (short
probe connections!) and check that enough margin exists to
that respect.
Over Temperature Protection
In a lot of designs, the adapter must be protected against
thermal runaways, e.g. when the temperature inside the
adapter box increases above a certain value. Figure 48
shows how to implement a simple OTP using an external
NTC and a series diode. The principle remains the same:
make sure the OPP network is not affected by the additional
NTC hence the presence of this isolation diode. When the
NTC resistance decreases as the temperature increases, the
voltage on the OPP pin during the off time will slowly
increase and, once it passes 3 V for 4 consecutive clock
cycles, the controller will permanently latch off.
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21
OP P
Vlatch
VCC
au x.
winding
OPP
ROPPL
2.5k
NT C
D2
1N4148
ROPPU
841k
full−latch
Figure 48. The Internal Circuitry Hooked to Pin 3 Can Be Used to Implement Over Temperature Protection (OTP)
Back to our 19 V adapter, we have found that the plateau
voltage on the auxiliary diode was 13 V in nominal
conditions. We have selected an NTC which offers a
resistance of 470 kW at 25C and drops to 8.8 kW at 110C.
If our auxiliary winding plateau is 14 V and we consider a
0.6 V forward drop for the diode, then the voltage across the
NTC in fault mode must be:
VNTC +14 *3*0.6 +10.4 V (eq. 17)
Based on the 8.8 kW NTC resistor at 110 C, the current
through the device must be:
INTC +10.4
8.8k [1.2 mA (eq. 18)
As such, the bottom resistor ROPPL, can easily be
calculated:
ROPPL +3
1.2m +2.5 kW(eq. 19)
Now that the pulldown OPP resistor is known, we can
calculate the upper resistor value ROPPU to adjust the power
limit at the chosen output power level. Suppose we need a
200 mV decrease from the 0.8 V set point and the on−time
swing on the auxiliary anode is −67.5 V, then we need to drop
over ROPPU a voltage of:
VROPPU +67.5 *0.2 +67.3 V (eq. 20)
The current flowing in the pulldown resistor ROPPL in this
condition will be:
IROPPU +200m
2.5k +80 mA(eq. 21)
The ROPPU value is therefore easily derived:
ROPPU +67.3
80m+841 kW(eq. 22)
Combining OVP and OTP
The OTP and Zener−based OVP can be combined
together as illustrated by Figure 49.
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22
4
5
1
OPP
Vlatch
10
8
9
VCC
au x.
winding
OPP
ROPPL
2.5k
11
NT C
D2
1N4148
ROPPU
841k
D3
15V
OVP
Figure 49. With the NTC Back in Place, the Circuit Nicely Combines OVP, OTP and OPP on the Same Pin
In nominal VCC / output conditions, when the Zener is not
activated, the NTC can drive the OPP pin and trigger the
adapter in case of an over temperature. During nominal
temperature if the loop is broken, the voltage runaway will
be detected and the controller will shut down the converter.
In case the OPP pin is not used for either OPP or OVP, it
can simply be grounded.
Filtering the Spikes
The auxiliary winding is the seat of spikes that can couple
to the OPP pin via the parasitic capacitances exhibited by the
Zener diode and the series diode. To prevent an adverse
triggering of the Over Voltage Protection circuitry, it is
possible to install a small RC filter before the detection
network. Typical values are those given in Figure 50 and
must be selected to provide the adequate filtering function
without degrading the stand−by power by an excessive
current circulation.
4
5
1
OP P
Vlatch
10
3
9
VCC
aux.
winding
OPP
ROPPL
2.5k
11
NT C
2
D2
1N4148
ROPPU
841k
D3
15V
OVP
R3
220
C1
330pF
ad d ition al fil ter
Figure 50. A Small RC Filter Avoids the Fast Rising Spikes from Reaching the Protection Pin of the NCP1250 in
Presence of Energetic Perturbations Superimposed on the Input Line
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23
PACKAGE DIMENSIONS
ÉÉÉ
ÉÉÉ
TSOP−6
CASE 318G−02
ISSUE U
23
456
D
1
e
b
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
DIM
A
MIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
−
010
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
L
C
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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